| commit | 964f664520a4c6a247e2c9ff8b4481631cf746df | |
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
| Wed, 13 Jul 2011 06:28:19 +0000 (13 16:28 +1000) | ||
| committer | Dave Airlie <airlied@redhat.com> | |
| Mon, 25 Jul 2011 11:42:39 +0000 (25 12:42 +0100) | ||
| tree | 11bbb5e5f82b7ca236c0d40b76fd11f6efed634d | treesnapshot (tar.gz zip) |
| parent | f1bece7fde9820a99c14d4db46ef071000e4ba47 | commitdiff |
drm/radeon: Add a rmb() in IH processing
We should have a read memory barrier between reading the WPTR from
memory and reading ring entries based on that value (ie, we need to
ensure both loads are done in order by the CPU).
It could be argued that the MMIO reads in r600_ack_irq() might be
enough to get that barrier but I prefer keeping an explicit one just
in case.
[airlied: fix evergreen + r/w mixup]
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
We should have a read memory barrier between reading the WPTR from
memory and reading ring entries based on that value (ie, we need to
ensure both loads are done in order by the CPU).
It could be argued that the MMIO reads in r600_ack_irq() might be
enough to get that barrier but I prefer keeping an explicit one just
in case.
[airlied: fix evergreen + r/w mixup]
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
| drivers/gpu/drm/radeon/evergreen.c | diffblobblamehistory | |
| drivers/gpu/drm/radeon/r600.c | diffblobblamehistory |