| commit | 0531e961fc58bd6c3956c300fe71dee7e771953c | |
| author | Bruce Allan <bruce.w.allan@intel.com> | |
| Tue, 27 Jul 2010 12:28:46 +0000 (27 12:28 +0000) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Tue, 10 Aug 2010 17:20:39 +0000 (10 10:20 -0700) | ||
| tree | 00ac59fccb2d8737ec9340beef0cd22bfb16be7f | treesnapshot (tar.gz zip) |
| parent | 8f0857bb563ee091d8c44d1d7a7e4f7696f364e0 | commitdiff |
e1000e: 82577/82578 PHY register access issues
commit ff847ac2d3e90edd94674c28bade25ae1e6a2e49 upstream.
The MAC-PHY interconnect on 82577/82578 uses a power management feature
(called K1) which must be disabled when in 1Gbps due to a hardware issue on
these parts. The #define bit setting used to enable/disable K1 is
incorrect and can cause PHY register accesses to stop working altogether
until the next device reset. This patch sets the register correctly.
This issue is present in kernels since 2.6.32.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit ff847ac2d3e90edd94674c28bade25ae1e6a2e49 upstream.
The MAC-PHY interconnect on 82577/82578 uses a power management feature
(called K1) which must be disabled when in 1Gbps due to a hardware issue on
these parts. The #define bit setting used to enable/disable K1 is
incorrect and can cause PHY register accesses to stop working altogether
until the next device reset. This patch sets the register correctly.
This issue is present in kernels since 2.6.32.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| drivers/net/e1000e/hw.h | diffblobblamehistory |