| commit | ff847ac2d3e90edd94674c28bade25ae1e6a2e49 | |
| author | Bruce Allan <bruce.w.allan@intel.com> | |
| Tue, 27 Jul 2010 12:28:46 +0000 (27 12:28 +0000) | ||
| committer | David S. Miller <davem@davemloft.net> | |
| Wed, 28 Jul 2010 04:06:26 +0000 (27 21:06 -0700) | ||
| tree | 739943e28d858421e40feca4e99eaed10f3c6ebe | treesnapshot (tar.gz zip) |
| parent | 5447080cfa3c77154498dfbf225367ac85b4c2b5 | commitdiff |
e1000e: 82577/82578 PHY register access issues
The MAC-PHY interconnect on 82577/82578 uses a power management feature
(called K1) which must be disabled when in 1Gbps due to a hardware issue on
these parts. The #define bit setting used to enable/disable K1 is
incorrect and can cause PHY register accesses to stop working altogether
until the next device reset. This patch sets the register correctly.
This issue is present in kernels since 2.6.32.
CC: stable@kernel.org
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The MAC-PHY interconnect on 82577/82578 uses a power management feature
(called K1) which must be disabled when in 1Gbps due to a hardware issue on
these parts. The #define bit setting used to enable/disable K1 is
incorrect and can cause PHY register accesses to stop working altogether
until the next device reset. This patch sets the register correctly.
This issue is present in kernels since 2.6.32.
CC: stable@kernel.org
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| drivers/net/e1000e/hw.h | diffblobblamehistory |