2 * SuperH Timer Support - TMU
4 * Copyright (C) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
35 void __iomem
*mapbase
;
37 struct irqaction irqaction
;
38 struct platform_device
*pdev
;
40 unsigned long periodic
;
41 struct clock_event_device ced
;
42 struct clocksource cs
;
45 static DEFINE_SPINLOCK(sh_tmu_lock
);
47 #define TSTR -1 /* shared register */
48 #define TCOR 0 /* channel register */
49 #define TCNT 1 /* channel register */
50 #define TCR 2 /* channel register */
52 static inline unsigned long sh_tmu_read(struct sh_tmu_priv
*p
, int reg_nr
)
54 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
55 void __iomem
*base
= p
->mapbase
;
59 return ioread8(base
- cfg
->channel_offset
);
64 return ioread16(base
+ offs
);
66 return ioread32(base
+ offs
);
69 static inline void sh_tmu_write(struct sh_tmu_priv
*p
, int reg_nr
,
72 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
73 void __iomem
*base
= p
->mapbase
;
77 iowrite8(value
, base
- cfg
->channel_offset
);
84 iowrite16(value
, base
+ offs
);
86 iowrite32(value
, base
+ offs
);
89 static void sh_tmu_start_stop_ch(struct sh_tmu_priv
*p
, int start
)
91 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
92 unsigned long flags
, value
;
94 /* start stop register shared by multiple timer channels */
95 spin_lock_irqsave(&sh_tmu_lock
, flags
);
96 value
= sh_tmu_read(p
, TSTR
);
99 value
|= 1 << cfg
->timer_bit
;
101 value
&= ~(1 << cfg
->timer_bit
);
103 sh_tmu_write(p
, TSTR
, value
);
104 spin_unlock_irqrestore(&sh_tmu_lock
, flags
);
107 static int sh_tmu_enable(struct sh_tmu_priv
*p
)
109 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
113 ret
= clk_enable(p
->clk
);
115 pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg
->clk
);
119 /* make sure channel is disabled */
120 sh_tmu_start_stop_ch(p
, 0);
122 /* maximum timeout */
123 sh_tmu_write(p
, TCOR
, 0xffffffff);
124 sh_tmu_write(p
, TCNT
, 0xffffffff);
126 /* configure channel to parent clock / 4, irq off */
127 p
->rate
= clk_get_rate(p
->clk
) / 4;
128 sh_tmu_write(p
, TCR
, 0x0000);
131 sh_tmu_start_stop_ch(p
, 1);
136 static void sh_tmu_disable(struct sh_tmu_priv
*p
)
138 /* disable channel */
139 sh_tmu_start_stop_ch(p
, 0);
141 /* disable interrupts in TMU block */
142 sh_tmu_write(p
, TCR
, 0x0000);
148 static void sh_tmu_set_next(struct sh_tmu_priv
*p
, unsigned long delta
,
152 sh_tmu_start_stop_ch(p
, 0);
154 /* acknowledge interrupt */
157 /* enable interrupt */
158 sh_tmu_write(p
, TCR
, 0x0020);
160 /* reload delta value in case of periodic timer */
162 sh_tmu_write(p
, TCOR
, delta
);
164 sh_tmu_write(p
, TCOR
, 0xffffffff);
166 sh_tmu_write(p
, TCNT
, delta
);
169 sh_tmu_start_stop_ch(p
, 1);
172 static irqreturn_t
sh_tmu_interrupt(int irq
, void *dev_id
)
174 struct sh_tmu_priv
*p
= dev_id
;
176 /* disable or acknowledge interrupt */
177 if (p
->ced
.mode
== CLOCK_EVT_MODE_ONESHOT
)
178 sh_tmu_write(p
, TCR
, 0x0000);
180 sh_tmu_write(p
, TCR
, 0x0020);
182 /* notify clockevent layer */
183 p
->ced
.event_handler(&p
->ced
);
187 static struct sh_tmu_priv
*cs_to_sh_tmu(struct clocksource
*cs
)
189 return container_of(cs
, struct sh_tmu_priv
, cs
);
192 static cycle_t
sh_tmu_clocksource_read(struct clocksource
*cs
)
194 struct sh_tmu_priv
*p
= cs_to_sh_tmu(cs
);
196 return sh_tmu_read(p
, TCNT
) ^ 0xffffffff;
199 static int sh_tmu_clocksource_enable(struct clocksource
*cs
)
201 struct sh_tmu_priv
*p
= cs_to_sh_tmu(cs
);
203 return sh_tmu_enable(p
);
206 static void sh_tmu_clocksource_disable(struct clocksource
*cs
)
208 sh_tmu_disable(cs_to_sh_tmu(cs
));
211 static int sh_tmu_register_clocksource(struct sh_tmu_priv
*p
,
212 char *name
, unsigned long rating
)
214 struct clocksource
*cs
= &p
->cs
;
218 cs
->read
= sh_tmu_clocksource_read
;
219 cs
->enable
= sh_tmu_clocksource_enable
;
220 cs
->disable
= sh_tmu_clocksource_disable
;
221 cs
->mask
= CLOCKSOURCE_MASK(32);
222 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
224 /* clk_get_rate() needs an enabled clock */
226 /* channel will be configured at parent clock / 4 */
227 p
->rate
= clk_get_rate(p
->clk
) / 4;
229 /* TODO: calculate good shift from rate and counter bit width */
231 cs
->mult
= clocksource_hz2mult(p
->rate
, cs
->shift
);
233 pr_info("sh_tmu: %s used as clock source\n", cs
->name
);
234 clocksource_register(cs
);
238 static struct sh_tmu_priv
*ced_to_sh_tmu(struct clock_event_device
*ced
)
240 return container_of(ced
, struct sh_tmu_priv
, ced
);
243 static void sh_tmu_clock_event_start(struct sh_tmu_priv
*p
, int periodic
)
245 struct clock_event_device
*ced
= &p
->ced
;
249 /* TODO: calculate good shift from rate and counter bit width */
252 ced
->mult
= div_sc(p
->rate
, NSEC_PER_SEC
, ced
->shift
);
253 ced
->max_delta_ns
= clockevent_delta2ns(0xffffffff, ced
);
254 ced
->min_delta_ns
= 5000;
257 p
->periodic
= (p
->rate
+ HZ
/2) / HZ
;
258 sh_tmu_set_next(p
, p
->periodic
, 1);
262 static void sh_tmu_clock_event_mode(enum clock_event_mode mode
,
263 struct clock_event_device
*ced
)
265 struct sh_tmu_priv
*p
= ced_to_sh_tmu(ced
);
268 /* deal with old setting first */
270 case CLOCK_EVT_MODE_PERIODIC
:
271 case CLOCK_EVT_MODE_ONESHOT
:
280 case CLOCK_EVT_MODE_PERIODIC
:
281 pr_info("sh_tmu: %s used for periodic clock events\n",
283 sh_tmu_clock_event_start(p
, 1);
285 case CLOCK_EVT_MODE_ONESHOT
:
286 pr_info("sh_tmu: %s used for oneshot clock events\n",
288 sh_tmu_clock_event_start(p
, 0);
290 case CLOCK_EVT_MODE_UNUSED
:
294 case CLOCK_EVT_MODE_SHUTDOWN
:
300 static int sh_tmu_clock_event_next(unsigned long delta
,
301 struct clock_event_device
*ced
)
303 struct sh_tmu_priv
*p
= ced_to_sh_tmu(ced
);
305 BUG_ON(ced
->mode
!= CLOCK_EVT_MODE_ONESHOT
);
307 /* program new delta value */
308 sh_tmu_set_next(p
, delta
, 0);
312 static void sh_tmu_register_clockevent(struct sh_tmu_priv
*p
,
313 char *name
, unsigned long rating
)
315 struct clock_event_device
*ced
= &p
->ced
;
318 memset(ced
, 0, sizeof(*ced
));
321 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
322 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
323 ced
->rating
= rating
;
324 ced
->cpumask
= cpumask_of(0);
325 ced
->set_next_event
= sh_tmu_clock_event_next
;
326 ced
->set_mode
= sh_tmu_clock_event_mode
;
328 pr_info("sh_tmu: %s used for clock events\n", ced
->name
);
329 clockevents_register_device(ced
);
331 ret
= setup_irq(p
->irqaction
.irq
, &p
->irqaction
);
333 pr_err("sh_tmu: failed to request irq %d\n",
339 static int sh_tmu_register(struct sh_tmu_priv
*p
, char *name
,
340 unsigned long clockevent_rating
,
341 unsigned long clocksource_rating
)
343 if (clockevent_rating
)
344 sh_tmu_register_clockevent(p
, name
, clockevent_rating
);
345 else if (clocksource_rating
)
346 sh_tmu_register_clocksource(p
, name
, clocksource_rating
);
351 static int sh_tmu_setup(struct sh_tmu_priv
*p
, struct platform_device
*pdev
)
353 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
354 struct resource
*res
;
358 memset(p
, 0, sizeof(*p
));
362 dev_err(&p
->pdev
->dev
, "missing platform data\n");
366 platform_set_drvdata(pdev
, p
);
368 res
= platform_get_resource(p
->pdev
, IORESOURCE_MEM
, 0);
370 dev_err(&p
->pdev
->dev
, "failed to get I/O memory\n");
374 irq
= platform_get_irq(p
->pdev
, 0);
376 dev_err(&p
->pdev
->dev
, "failed to get irq\n");
380 /* map memory, let mapbase point to our channel */
381 p
->mapbase
= ioremap_nocache(res
->start
, resource_size(res
));
382 if (p
->mapbase
== NULL
) {
383 pr_err("sh_tmu: failed to remap I/O memory\n");
387 /* setup data for setup_irq() (too early for request_irq()) */
388 p
->irqaction
.name
= cfg
->name
;
389 p
->irqaction
.handler
= sh_tmu_interrupt
;
390 p
->irqaction
.dev_id
= p
;
391 p
->irqaction
.irq
= irq
;
392 p
->irqaction
.flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
;
394 /* get hold of clock */
395 p
->clk
= clk_get(&p
->pdev
->dev
, cfg
->clk
);
396 if (IS_ERR(p
->clk
)) {
397 pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg
->clk
);
398 ret
= PTR_ERR(p
->clk
);
402 return sh_tmu_register(p
, cfg
->name
,
403 cfg
->clockevent_rating
,
404 cfg
->clocksource_rating
);
411 static int __devinit
sh_tmu_probe(struct platform_device
*pdev
)
413 struct sh_tmu_priv
*p
= platform_get_drvdata(pdev
);
414 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
418 pr_info("sh_tmu: %s kept as earlytimer\n", cfg
->name
);
422 p
= kmalloc(sizeof(*p
), GFP_KERNEL
);
424 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
428 ret
= sh_tmu_setup(p
, pdev
);
431 platform_set_drvdata(pdev
, NULL
);
436 static int __devexit
sh_tmu_remove(struct platform_device
*pdev
)
438 return -EBUSY
; /* cannot unregister clockevent and clocksource */
441 static struct platform_driver sh_tmu_device_driver
= {
442 .probe
= sh_tmu_probe
,
443 .remove
= __devexit_p(sh_tmu_remove
),
449 static int __init
sh_tmu_init(void)
451 return platform_driver_register(&sh_tmu_device_driver
);
454 static void __exit
sh_tmu_exit(void)
456 platform_driver_unregister(&sh_tmu_device_driver
);
459 early_platform_init("earlytimer", &sh_tmu_device_driver
);
460 module_init(sh_tmu_init
);
461 module_exit(sh_tmu_exit
);
463 MODULE_AUTHOR("Magnus Damm");
464 MODULE_DESCRIPTION("SuperH TMU Timer Driver");
465 MODULE_LICENSE("GPL v2");