2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
26 #include <linux/clk.h>
27 #include <linux/irq.h>
28 #include <linux/err.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/sh_timer.h>
34 void __iomem
*mapbase
;
36 unsigned long width
; /* 16 or 32 bit version of hardware block */
37 unsigned long overflow_bit
;
38 unsigned long clear_bits
;
39 struct irqaction irqaction
;
40 struct platform_device
*pdev
;
43 unsigned long flags_suspend
;
44 unsigned long match_value
;
45 unsigned long next_match_value
;
46 unsigned long max_match_value
;
49 struct clock_event_device ced
;
50 struct clocksource cs
;
51 unsigned long total_cycles
;
54 static DEFINE_SPINLOCK(sh_cmt_lock
);
56 #define CMSTR -1 /* shared register */
57 #define CMCSR 0 /* channel register */
58 #define CMCNT 1 /* channel register */
59 #define CMCOR 2 /* channel register */
61 static inline unsigned long sh_cmt_read(struct sh_cmt_priv
*p
, int reg_nr
)
63 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
64 void __iomem
*base
= p
->mapbase
;
67 if (reg_nr
== CMSTR
) {
69 base
-= cfg
->channel_offset
;
77 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
))
78 return ioread32(base
+ offs
);
81 return ioread16(base
+ offs
);
84 static inline void sh_cmt_write(struct sh_cmt_priv
*p
, int reg_nr
,
87 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
88 void __iomem
*base
= p
->mapbase
;
91 if (reg_nr
== CMSTR
) {
93 base
-= cfg
->channel_offset
;
101 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
)) {
102 iowrite32(value
, base
+ offs
);
107 iowrite16(value
, base
+ offs
);
110 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv
*p
,
113 unsigned long v1
, v2
, v3
;
116 o1
= sh_cmt_read(p
, CMCSR
) & p
->overflow_bit
;
118 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
121 v1
= sh_cmt_read(p
, CMCNT
);
122 v2
= sh_cmt_read(p
, CMCNT
);
123 v3
= sh_cmt_read(p
, CMCNT
);
124 o1
= sh_cmt_read(p
, CMCSR
) & p
->overflow_bit
;
125 } while (unlikely((o1
!= o2
) || (v1
> v2
&& v1
< v3
)
126 || (v2
> v3
&& v2
< v1
) || (v3
> v1
&& v3
< v2
)));
133 static void sh_cmt_start_stop_ch(struct sh_cmt_priv
*p
, int start
)
135 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
136 unsigned long flags
, value
;
138 /* start stop register shared by multiple timer channels */
139 spin_lock_irqsave(&sh_cmt_lock
, flags
);
140 value
= sh_cmt_read(p
, CMSTR
);
143 value
|= 1 << cfg
->timer_bit
;
145 value
&= ~(1 << cfg
->timer_bit
);
147 sh_cmt_write(p
, CMSTR
, value
);
148 spin_unlock_irqrestore(&sh_cmt_lock
, flags
);
151 static int sh_cmt_enable(struct sh_cmt_priv
*p
, unsigned long *rate
)
153 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
157 ret
= clk_enable(p
->clk
);
159 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg
->clk
);
163 /* make sure channel is disabled */
164 sh_cmt_start_stop_ch(p
, 0);
166 /* configure channel, periodic mode and maximum timeout */
167 if (p
->width
== 16) {
168 *rate
= clk_get_rate(p
->clk
) / 512;
169 sh_cmt_write(p
, CMCSR
, 0x43);
171 *rate
= clk_get_rate(p
->clk
) / 8;
172 sh_cmt_write(p
, CMCSR
, 0x01a4);
175 sh_cmt_write(p
, CMCOR
, 0xffffffff);
176 sh_cmt_write(p
, CMCNT
, 0);
179 sh_cmt_start_stop_ch(p
, 1);
183 static void sh_cmt_disable(struct sh_cmt_priv
*p
)
185 /* disable channel */
186 sh_cmt_start_stop_ch(p
, 0);
188 /* disable interrupts in CMT block */
189 sh_cmt_write(p
, CMCSR
, 0);
196 #define FLAG_CLOCKEVENT (1 << 0)
197 #define FLAG_CLOCKSOURCE (1 << 1)
198 #define FLAG_REPROGRAM (1 << 2)
199 #define FLAG_SKIPEVENT (1 << 3)
200 #define FLAG_IRQCONTEXT (1 << 4)
202 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv
*p
,
205 unsigned long new_match
;
206 unsigned long value
= p
->next_match_value
;
207 unsigned long delay
= 0;
208 unsigned long now
= 0;
211 now
= sh_cmt_get_counter(p
, &has_wrapped
);
212 p
->flags
|= FLAG_REPROGRAM
; /* force reprogram */
215 /* we're competing with the interrupt handler.
216 * -> let the interrupt handler reprogram the timer.
217 * -> interrupt number two handles the event.
219 p
->flags
|= FLAG_SKIPEVENT
;
227 /* reprogram the timer hardware,
228 * but don't save the new match value yet.
230 new_match
= now
+ value
+ delay
;
231 if (new_match
> p
->max_match_value
)
232 new_match
= p
->max_match_value
;
234 sh_cmt_write(p
, CMCOR
, new_match
);
236 now
= sh_cmt_get_counter(p
, &has_wrapped
);
237 if (has_wrapped
&& (new_match
> p
->match_value
)) {
238 /* we are changing to a greater match value,
239 * so this wrap must be caused by the counter
240 * matching the old value.
241 * -> first interrupt reprograms the timer.
242 * -> interrupt number two handles the event.
244 p
->flags
|= FLAG_SKIPEVENT
;
249 /* we are changing to a smaller match value,
250 * so the wrap must be caused by the counter
251 * matching the new value.
252 * -> save programmed match value.
253 * -> let isr handle the event.
255 p
->match_value
= new_match
;
259 /* be safe: verify hardware settings */
260 if (now
< new_match
) {
261 /* timer value is below match value, all good.
262 * this makes sure we won't miss any match events.
263 * -> save programmed match value.
264 * -> let isr handle the event.
266 p
->match_value
= new_match
;
270 /* the counter has reached a value greater
271 * than our new match value. and since the
272 * has_wrapped flag isn't set we must have
273 * programmed a too close event.
274 * -> increase delay and retry.
282 pr_warning("sh_cmt: too long delay\n");
287 static void sh_cmt_set_next(struct sh_cmt_priv
*p
, unsigned long delta
)
291 if (delta
> p
->max_match_value
)
292 pr_warning("sh_cmt: delta out of range\n");
294 spin_lock_irqsave(&p
->lock
, flags
);
295 p
->next_match_value
= delta
;
296 sh_cmt_clock_event_program_verify(p
, 0);
297 spin_unlock_irqrestore(&p
->lock
, flags
);
300 static irqreturn_t
sh_cmt_interrupt(int irq
, void *dev_id
)
302 struct sh_cmt_priv
*p
= dev_id
;
305 sh_cmt_write(p
, CMCSR
, sh_cmt_read(p
, CMCSR
) & p
->clear_bits
);
307 /* update clock source counter to begin with if enabled
308 * the wrap flag should be cleared by the timer specific
309 * isr before we end up here.
311 if (p
->flags
& FLAG_CLOCKSOURCE
)
312 p
->total_cycles
+= p
->match_value
;
314 if (!(p
->flags
& FLAG_REPROGRAM
))
315 p
->next_match_value
= p
->max_match_value
;
317 p
->flags
|= FLAG_IRQCONTEXT
;
319 if (p
->flags
& FLAG_CLOCKEVENT
) {
320 if (!(p
->flags
& FLAG_SKIPEVENT
)) {
321 if (p
->ced
.mode
== CLOCK_EVT_MODE_ONESHOT
) {
322 p
->next_match_value
= p
->max_match_value
;
323 p
->flags
|= FLAG_REPROGRAM
;
326 p
->ced
.event_handler(&p
->ced
);
330 p
->flags
&= ~FLAG_SKIPEVENT
;
332 if (p
->flags
& FLAG_REPROGRAM
) {
333 p
->flags
&= ~FLAG_REPROGRAM
;
334 sh_cmt_clock_event_program_verify(p
, 1);
336 if (p
->flags
& FLAG_CLOCKEVENT
)
337 if ((p
->ced
.mode
== CLOCK_EVT_MODE_SHUTDOWN
)
338 || (p
->match_value
== p
->next_match_value
))
339 p
->flags
&= ~FLAG_REPROGRAM
;
342 p
->flags
&= ~FLAG_IRQCONTEXT
;
347 static int sh_cmt_start(struct sh_cmt_priv
*p
, unsigned long flag
)
352 spin_lock_irqsave(&p
->lock
, flags
);
354 if (!(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
355 ret
= sh_cmt_enable(p
, &p
->rate
);
361 /* setup timeout if no clockevent */
362 if ((flag
== FLAG_CLOCKSOURCE
) && (!(p
->flags
& FLAG_CLOCKEVENT
)))
363 sh_cmt_set_next(p
, p
->max_match_value
);
365 spin_unlock_irqrestore(&p
->lock
, flags
);
370 static void sh_cmt_stop(struct sh_cmt_priv
*p
, unsigned long flag
)
375 spin_lock_irqsave(&p
->lock
, flags
);
377 f
= p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
);
380 if (f
&& !(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
383 /* adjust the timeout to maximum if only clocksource left */
384 if ((flag
== FLAG_CLOCKEVENT
) && (p
->flags
& FLAG_CLOCKSOURCE
))
385 sh_cmt_set_next(p
, p
->max_match_value
);
387 spin_unlock_irqrestore(&p
->lock
, flags
);
390 static struct sh_cmt_priv
*cs_to_sh_cmt(struct clocksource
*cs
)
392 return container_of(cs
, struct sh_cmt_priv
, cs
);
395 static cycle_t
sh_cmt_clocksource_read(struct clocksource
*cs
)
397 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
398 unsigned long flags
, raw
;
402 spin_lock_irqsave(&p
->lock
, flags
);
403 value
= p
->total_cycles
;
404 raw
= sh_cmt_get_counter(p
, &has_wrapped
);
406 if (unlikely(has_wrapped
))
407 raw
+= p
->match_value
;
408 spin_unlock_irqrestore(&p
->lock
, flags
);
413 static int sh_cmt_clocksource_enable(struct clocksource
*cs
)
415 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
419 return sh_cmt_start(p
, FLAG_CLOCKSOURCE
);
422 static void sh_cmt_clocksource_disable(struct clocksource
*cs
)
424 sh_cmt_stop(cs_to_sh_cmt(cs
), FLAG_CLOCKSOURCE
);
427 static int sh_cmt_register_clocksource(struct sh_cmt_priv
*p
,
428 char *name
, unsigned long rating
)
430 struct clocksource
*cs
= &p
->cs
;
434 cs
->read
= sh_cmt_clocksource_read
;
435 cs
->enable
= sh_cmt_clocksource_enable
;
436 cs
->disable
= sh_cmt_clocksource_disable
;
437 cs
->mask
= CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
438 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
440 /* clk_get_rate() needs an enabled clock */
442 p
->rate
= clk_get_rate(p
->clk
) / (p
->width
== 16) ? 512 : 8;
445 /* TODO: calculate good shift from rate and counter bit width */
447 cs
->mult
= clocksource_hz2mult(p
->rate
, cs
->shift
);
449 pr_info("sh_cmt: %s used as clock source\n", cs
->name
);
451 clocksource_register(cs
);
455 static struct sh_cmt_priv
*ced_to_sh_cmt(struct clock_event_device
*ced
)
457 return container_of(ced
, struct sh_cmt_priv
, ced
);
460 static void sh_cmt_clock_event_start(struct sh_cmt_priv
*p
, int periodic
)
462 struct clock_event_device
*ced
= &p
->ced
;
464 sh_cmt_start(p
, FLAG_CLOCKEVENT
);
466 /* TODO: calculate good shift from rate and counter bit width */
469 ced
->mult
= div_sc(p
->rate
, NSEC_PER_SEC
, ced
->shift
);
470 ced
->max_delta_ns
= clockevent_delta2ns(p
->max_match_value
, ced
);
471 ced
->min_delta_ns
= clockevent_delta2ns(0x1f, ced
);
474 sh_cmt_set_next(p
, (p
->rate
+ HZ
/2) / HZ
);
476 sh_cmt_set_next(p
, p
->max_match_value
);
479 static void sh_cmt_clock_event_mode(enum clock_event_mode mode
,
480 struct clock_event_device
*ced
)
482 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
484 /* deal with old setting first */
486 case CLOCK_EVT_MODE_PERIODIC
:
487 case CLOCK_EVT_MODE_ONESHOT
:
488 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
495 case CLOCK_EVT_MODE_PERIODIC
:
496 pr_info("sh_cmt: %s used for periodic clock events\n",
498 sh_cmt_clock_event_start(p
, 1);
500 case CLOCK_EVT_MODE_ONESHOT
:
501 pr_info("sh_cmt: %s used for oneshot clock events\n",
503 sh_cmt_clock_event_start(p
, 0);
505 case CLOCK_EVT_MODE_SHUTDOWN
:
506 case CLOCK_EVT_MODE_UNUSED
:
507 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
514 static int sh_cmt_clock_event_next(unsigned long delta
,
515 struct clock_event_device
*ced
)
517 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
519 BUG_ON(ced
->mode
!= CLOCK_EVT_MODE_ONESHOT
);
520 if (likely(p
->flags
& FLAG_IRQCONTEXT
))
521 p
->next_match_value
= delta
;
523 sh_cmt_set_next(p
, delta
);
528 static void sh_cmt_register_clockevent(struct sh_cmt_priv
*p
,
529 char *name
, unsigned long rating
)
531 struct clock_event_device
*ced
= &p
->ced
;
533 memset(ced
, 0, sizeof(*ced
));
536 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
537 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
538 ced
->rating
= rating
;
539 ced
->cpumask
= cpumask_of(0);
540 ced
->set_next_event
= sh_cmt_clock_event_next
;
541 ced
->set_mode
= sh_cmt_clock_event_mode
;
543 pr_info("sh_cmt: %s used for clock events\n", ced
->name
);
544 clockevents_register_device(ced
);
547 static int sh_cmt_register(struct sh_cmt_priv
*p
, char *name
,
548 unsigned long clockevent_rating
,
549 unsigned long clocksource_rating
)
551 if (p
->width
== (sizeof(p
->max_match_value
) * 8))
552 p
->max_match_value
= ~0;
554 p
->max_match_value
= (1 << p
->width
) - 1;
556 p
->match_value
= p
->max_match_value
;
557 spin_lock_init(&p
->lock
);
559 if (clockevent_rating
)
560 sh_cmt_register_clockevent(p
, name
, clockevent_rating
);
562 if (clocksource_rating
)
563 sh_cmt_register_clocksource(p
, name
, clocksource_rating
);
568 static int sh_cmt_setup(struct sh_cmt_priv
*p
, struct platform_device
*pdev
)
570 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
571 struct resource
*res
;
575 memset(p
, 0, sizeof(*p
));
579 dev_err(&p
->pdev
->dev
, "missing platform data\n");
583 platform_set_drvdata(pdev
, p
);
585 res
= platform_get_resource(p
->pdev
, IORESOURCE_MEM
, 0);
587 dev_err(&p
->pdev
->dev
, "failed to get I/O memory\n");
591 irq
= platform_get_irq(p
->pdev
, 0);
593 dev_err(&p
->pdev
->dev
, "failed to get irq\n");
597 /* map memory, let mapbase point to our channel */
598 p
->mapbase
= ioremap_nocache(res
->start
, resource_size(res
));
599 if (p
->mapbase
== NULL
) {
600 pr_err("sh_cmt: failed to remap I/O memory\n");
604 /* request irq using setup_irq() (too early for request_irq()) */
605 p
->irqaction
.name
= cfg
->name
;
606 p
->irqaction
.handler
= sh_cmt_interrupt
;
607 p
->irqaction
.dev_id
= p
;
608 p
->irqaction
.flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
;
610 /* get hold of clock */
611 p
->clk
= clk_get(&p
->pdev
->dev
, cfg
->clk
);
612 if (IS_ERR(p
->clk
)) {
613 pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg
->clk
);
614 ret
= PTR_ERR(p
->clk
);
618 if (resource_size(res
) == 6) {
620 p
->overflow_bit
= 0x80;
621 p
->clear_bits
= ~0x80;
624 p
->overflow_bit
= 0x8000;
625 p
->clear_bits
= ~0xc000;
628 ret
= sh_cmt_register(p
, cfg
->name
,
629 cfg
->clockevent_rating
,
630 cfg
->clocksource_rating
);
632 pr_err("sh_cmt: registration failed\n");
636 ret
= setup_irq(irq
, &p
->irqaction
);
638 pr_err("sh_cmt: failed to request irq %d\n", irq
);
650 static int __devinit
sh_cmt_probe(struct platform_device
*pdev
)
652 struct sh_cmt_priv
*p
= platform_get_drvdata(pdev
);
653 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
657 pr_info("sh_cmt: %s kept as earlytimer\n", cfg
->name
);
661 p
= kmalloc(sizeof(*p
), GFP_KERNEL
);
663 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
667 ret
= sh_cmt_setup(p
, pdev
);
670 platform_set_drvdata(pdev
, NULL
);
675 static int __devexit
sh_cmt_remove(struct platform_device
*pdev
)
677 return -EBUSY
; /* cannot unregister clockevent and clocksource */
680 static int sh_cmt_suspend(struct device
*dev
)
682 struct platform_device
*pdev
= to_platform_device(dev
);
683 struct sh_cmt_priv
*p
= platform_get_drvdata(pdev
);
685 /* save flag state and stop CMT channel */
686 p
->flags_suspend
= p
->flags
;
687 sh_cmt_stop(p
, p
->flags
);
691 static int sh_cmt_resume(struct device
*dev
)
693 struct platform_device
*pdev
= to_platform_device(dev
);
694 struct sh_cmt_priv
*p
= platform_get_drvdata(pdev
);
696 /* start CMT channel from saved state */
697 sh_cmt_start(p
, p
->flags_suspend
);
701 static struct dev_pm_ops sh_cmt_dev_pm_ops
= {
702 .suspend
= sh_cmt_suspend
,
703 .resume
= sh_cmt_resume
,
706 static struct platform_driver sh_cmt_device_driver
= {
707 .probe
= sh_cmt_probe
,
708 .remove
= __devexit_p(sh_cmt_remove
),
711 .pm
= &sh_cmt_dev_pm_ops
,
715 static int __init
sh_cmt_init(void)
717 return platform_driver_register(&sh_cmt_device_driver
);
720 static void __exit
sh_cmt_exit(void)
722 platform_driver_unregister(&sh_cmt_device_driver
);
725 early_platform_init("earlytimer", &sh_cmt_device_driver
);
726 module_init(sh_cmt_init
);
727 module_exit(sh_cmt_exit
);
729 MODULE_AUTHOR("Magnus Damm");
730 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
731 MODULE_LICENSE("GPL v2");