drivers/hwmon/coretemp.c

   1 /*
   2  * coretemp.c - Linux kernel module for hardware monitoring
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * Inspired from many hwmon drivers
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301 USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/slab.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/sysfs.h>
  30 #include <linux/hwmon-sysfs.h>
  31 #include <linux/err.h>
  32 #include <linux/mutex.h>
  33 #include <linux/list.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/cpu.h>
  36 #include <linux/pci.h>
  37 #include <asm/msr.h>
  38 #include <asm/processor.h>
  39 #include <asm/smp.h>
  40
  41 #define DRVNAME "coretemp"
  42
  43 typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
  44                 SHOW_NAME } SHOW;
  45
  46 /*
  47  * Functions declaration
  48  */
  49
  50 static struct coretemp_data *coretemp_update_device(struct device *dev);
  51
  52 struct coretemp_data {
  53         struct device *hwmon_dev;
  54         struct mutex update_lock;
  55         const char *name;
  56         u32 id;
  57         u16 core_id;
  58         char valid;             /* zero until following fields are valid */
  59         unsigned long last_updated;     /* in jiffies */
  60         int temp;
  61         int tjmax;
  62         int ttarget;
  63         u8 alarm;
  64 };
  65
  66 /*
  67  * Sysfs stuff
  68  */
  69
  70 static ssize_t show_name(struct device *dev, struct device_attribute
  71                           *devattr, char *buf)
  72 {
  73         int ret;
  74         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  75         struct coretemp_data *data = dev_get_drvdata(dev);
  76
  77         if (attr->index == SHOW_NAME)
  78                 ret = sprintf(buf, "%s\n", data->name);
  79         else    /* show label */
  80                 ret = sprintf(buf, "Core %d\n", data->core_id);
  81         return ret;
  82 }
  83
  84 static ssize_t show_alarm(struct device *dev, struct device_attribute
  85                           *devattr, char *buf)
  86 {
  87         struct coretemp_data *data = coretemp_update_device(dev);
  88         /* read the Out-of-spec log, never clear */
  89         return sprintf(buf, "%d\n", data->alarm);
  90 }
  91
  92 static ssize_t show_temp(struct device *dev,
  93                          struct device_attribute *devattr, char *buf)
  94 {
  95         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  96         struct coretemp_data *data = coretemp_update_device(dev);
  97         int err;
  98
  99         if (attr->index == SHOW_TEMP)
 100                 err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
 101         else if (attr->index == SHOW_TJMAX)
 102                 err = sprintf(buf, "%d\n", data->tjmax);
 103         else
 104                 err = sprintf(buf, "%d\n", data->ttarget);
 105         return err;
 106 }
 107
 108 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL,
 109                           SHOW_TEMP);
 110 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
 111                           SHOW_TJMAX);
 112 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
 113                           SHOW_TTARGET);
 114 static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
 115 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
 116 static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);
 117
 118 static struct attribute *coretemp_attributes[] = {
 119         &sensor_dev_attr_name.dev_attr.attr,
 120         &sensor_dev_attr_temp1_label.dev_attr.attr,
 121         &dev_attr_temp1_crit_alarm.attr,
 122         &sensor_dev_attr_temp1_input.dev_attr.attr,
 123         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 124         NULL
 125 };
 126
 127 static const struct attribute_group coretemp_group = {
 128         .attrs = coretemp_attributes,
 129 };
 130
 131 static struct coretemp_data *coretemp_update_device(struct device *dev)
 132 {
 133         struct coretemp_data *data = dev_get_drvdata(dev);
 134
 135         mutex_lock(&data->update_lock);
 136
 137         if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
 138                 u32 eax, edx;
 139
 140                 data->valid = 0;
 141                 rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 142                 data->alarm = (eax >> 5) & 1;
 143                 /* update only if data has been valid */
 144                 if (eax & 0x80000000) {
 145                         data->temp = data->tjmax - (((eax >> 16)
 146                                                         & 0x7f) * 1000);
 147                         data->valid = 1;
 148                 } else {
 149                         dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax);
 150                 }
 151                 data->last_updated = jiffies;
 152         }
 153
 154         mutex_unlock(&data->update_lock);
 155         return data;
 156 }
 157
 158 static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
 159 {
 160         /* The 100C is default for both mobile and non mobile CPUs */
 161
 162         int tjmax = 100000;
 163         int tjmax_ee = 85000;
 164         int usemsr_ee = 1;
 165         int err;
 166         u32 eax, edx;
 167         struct pci_dev *host_bridge;
 168
 169         /* Early chips have no MSR for TjMax */
 170
 171         if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
 172                 usemsr_ee = 0;
 173         }
 174
 175         /* Atom CPUs */
 176
 177         if (c->x86_model == 0x1c) {
 178                 usemsr_ee = 0;
 179
 180                 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 181
 182                 if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
 183                     && (host_bridge->device == 0xa000   /* NM10 based nettop */
 184                     || host_bridge->device == 0xa010))  /* NM10 based netbook */
 185                         tjmax = 100000;
 186                 else
 187                         tjmax = 90000;
 188
 189                 pci_dev_put(host_bridge);
 190         }
 191
 192         if ((c->x86_model > 0xe) && (usemsr_ee)) {
 193                 u8 platform_id;
 194
 195                 /* Now we can detect the mobile CPU using Intel provided table
 196                    http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
 197                    For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
 198                 */
 199
 200                 err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
 201                 if (err) {
 202                         dev_warn(dev,
 203                                  "Unable to access MSR 0x17, assuming desktop"
 204                                  " CPU\n");
 205                         usemsr_ee = 0;
 206                 } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
 207                         /* Trust bit 28 up to Penryn, I could not find any
 208                            documentation on that; if you happen to know
 209                            someone at Intel please ask */
 210                         usemsr_ee = 0;
 211                 } else {
 212                         /* Platform ID bits 52:50 (EDX starts at bit 32) */
 213                         platform_id = (edx >> 18) & 0x7;
 214
 215                         /* Mobile Penryn CPU seems to be platform ID 7 or 5
 216                           (guesswork) */
 217                         if ((c->x86_model == 0x17) &&
 218                             ((platform_id == 5) || (platform_id == 7))) {
 219                                 /* If MSR EE bit is set, set it to 90 degrees C,
 220                                    otherwise 105 degrees C */
 221                                 tjmax_ee = 90000;
 222                                 tjmax = 105000;
 223                         }
 224                 }
 225         }
 226
 227         if (usemsr_ee) {
 228
 229                 err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
 230                 if (err) {
 231                         dev_warn(dev,
 232                                  "Unable to access MSR 0xEE, for Tjmax, left"
 233                                  " at default\n");
 234                 } else if (eax & 0x40000000) {
 235                         tjmax = tjmax_ee;
 236                 }
 237         /* if we dont use msr EE it means we are desktop CPU (with exeception
 238            of Atom) */
 239         } else if (tjmax == 100000) {
 240                 dev_warn(dev, "Using relative temperature scale!\n");
 241         }
 242
 243         return tjmax;
 244 }
 245
 246 static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
 247                                struct device *dev)
 248 {
 249         /* The 100C is default for both mobile and non mobile CPUs */
 250         int err;
 251         u32 eax, edx;
 252         u32 val;
 253
 254         /* A new feature of current Intel(R) processors, the
 255            IA32_TEMPERATURE_TARGET contains the TjMax value */
 256         err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
 257         if (err) {
 258                 dev_warn(dev, "Unable to read TjMax from CPU.\n");
 259         } else {
 260                 val = (eax >> 16) & 0xff;
 261                 /*
 262                  * If the TjMax is not plausible, an assumption
 263                  * will be used
 264                  */
 265                 if ((val > 80) && (val < 120)) {
 266                         dev_info(dev, "TjMax is %d C.\n", val);
 267                         return val * 1000;
 268                 }
 269         }
 270
 271         /*
 272          * An assumption is made for early CPUs and unreadable MSR.
 273          * NOTE: the given value may not be correct.
 274          */
 275
 276         switch (c->x86_model) {
 277         case 0xe:
 278         case 0xf:
 279         case 0x16:
 280         case 0x1a:
 281                 dev_warn(dev, "TjMax is assumed as 100 C!\n");
 282                 return 100000;
 283                 break;
 284         case 0x17:
 285         case 0x1c:              /* Atom CPUs */
 286                 return adjust_tjmax(c, id, dev);
 287                 break;
 288         default:
 289                 dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
 290                         " using default TjMax of 100C.\n", c->x86_model);
 291                 return 100000;
 292         }
 293 }
 294
 295 static int __devinit coretemp_probe(struct platform_device *pdev)
 296 {
 297         struct coretemp_data *data;
 298         struct cpuinfo_x86 *c = &cpu_data(pdev->id);
 299         int err;
 300         u32 eax, edx;
 301
 302         if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) {
 303                 err = -ENOMEM;
 304                 dev_err(&pdev->dev, "Out of memory\n");
 305                 goto exit;
 306         }
 307
 308         data->id = pdev->id;
 309 #ifdef CONFIG_SMP
 310         data->core_id = c->cpu_core_id;
 311 #endif
 312         data->name = "coretemp";
 313         mutex_init(&data->update_lock);
 314
 315         /* test if we can access the THERM_STATUS MSR */
 316         err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 317         if (err) {
 318                 dev_err(&pdev->dev,
 319                         "Unable to access THERM_STATUS MSR, giving up\n");
 320                 goto exit_free;
 321         }
 322
 323         /* Check if we have problem with errata AE18 of Core processors:
 324            Readings might stop update when processor visited too deep sleep,
 325            fixed for stepping D0 (6EC).
 326         */
 327
 328         if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
 329                 /* check for microcode update */
 330                 rdmsr_on_cpu(data->id, MSR_IA32_UCODE_REV, &eax, &edx);
 331                 if (edx < 0x39) {
 332                         err = -ENODEV;
 333                         dev_err(&pdev->dev,
 334                                 "Errata AE18 not fixed, update BIOS or "
 335                                 "microcode of the CPU!\n");
 336                         goto exit_free;
 337                 }
 338         }
 339
 340         data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 341         platform_set_drvdata(pdev, data);
 342
 343         /*
 344          * read the still undocumented IA32_TEMPERATURE_TARGET. It exists
 345          * on older CPUs but not in this register,
 346          * Atoms don't have it either.
 347          */
 348
 349         if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
 350                 err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
 351                     &eax, &edx);
 352                 if (err) {
 353                         dev_warn(&pdev->dev, "Unable to read"
 354                                         " IA32_TEMPERATURE_TARGET MSR\n");
 355                 } else {
 356                         data->ttarget = data->tjmax -
 357                                         (((eax >> 8) & 0xff) * 1000);
 358                         err = device_create_file(&pdev->dev,
 359                                         &sensor_dev_attr_temp1_max.dev_attr);
 360                         if (err)
 361                                 goto exit_free;
 362                 }
 363         }
 364
 365         if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
 366                 goto exit_dev;
 367
 368         data->hwmon_dev = hwmon_device_register(&pdev->dev);
 369         if (IS_ERR(data->hwmon_dev)) {
 370                 err = PTR_ERR(data->hwmon_dev);
 371                 dev_err(&pdev->dev, "Class registration failed (%d)\n",
 372                         err);
 373                 goto exit_class;
 374         }
 375
 376         return 0;
 377
 378 exit_class:
 379         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 380 exit_dev:
 381         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 382 exit_free:
 383         kfree(data);
 384 exit:
 385         return err;
 386 }
 387
 388 static int __devexit coretemp_remove(struct platform_device *pdev)
 389 {
 390         struct coretemp_data *data = platform_get_drvdata(pdev);
 391
 392         hwmon_device_unregister(data->hwmon_dev);
 393         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 394         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 395         platform_set_drvdata(pdev, NULL);
 396         kfree(data);
 397         return 0;
 398 }
 399
 400 static struct platform_driver coretemp_driver = {
 401         .driver = {
 402                 .owner = THIS_MODULE,
 403                 .name = DRVNAME,
 404         },
 405         .probe = coretemp_probe,
 406         .remove = __devexit_p(coretemp_remove),
 407 };
 408
 409 struct pdev_entry {
 410         struct list_head list;
 411         struct platform_device *pdev;
 412         unsigned int cpu;
 413 #ifdef CONFIG_SMP
 414         u16 phys_proc_id;
 415         u16 cpu_core_id;
 416 #endif
 417 };
 418
 419 static LIST_HEAD(pdev_list);
 420 static DEFINE_MUTEX(pdev_list_mutex);
 421
 422 static int __cpuinit coretemp_device_add(unsigned int cpu)
 423 {
 424         int err;
 425         struct platform_device *pdev;
 426         struct pdev_entry *pdev_entry;
 427         struct cpuinfo_x86 *c = &cpu_data(cpu);
 428
 429         /*
 430          * CPUID.06H.EAX[0] indicates whether the CPU has thermal
 431          * sensors. We check this bit only, all the early CPUs
 432          * without thermal sensors will be filtered out.
 433          */
 434         if (!cpu_has(c, X86_FEATURE_DTS)) {
 435                 printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
 436                        " has no thermal sensor.\n", c->x86_model);
 437                 return 0;
 438         }
 439
 440         mutex_lock(&pdev_list_mutex);
 441
 442 #ifdef CONFIG_SMP
 443         /* Skip second HT entry of each core */
 444         list_for_each_entry(pdev_entry, &pdev_list, list) {
 445                 if (c->phys_proc_id == pdev_entry->phys_proc_id &&
 446                     c->cpu_core_id == pdev_entry->cpu_core_id) {
 447                         err = 0;        /* Not an error */
 448                         goto exit;
 449                 }
 450         }
 451 #endif
 452
 453         pdev = platform_device_alloc(DRVNAME, cpu);
 454         if (!pdev) {
 455                 err = -ENOMEM;
 456                 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
 457                 goto exit;
 458         }
 459
 460         pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
 461         if (!pdev_entry) {
 462                 err = -ENOMEM;
 463                 goto exit_device_put;
 464         }
 465
 466         err = platform_device_add(pdev);
 467         if (err) {
 468                 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
 469                        err);
 470                 goto exit_device_free;
 471         }
 472
 473         pdev_entry->pdev = pdev;
 474         pdev_entry->cpu = cpu;
 475 #ifdef CONFIG_SMP
 476         pdev_entry->phys_proc_id = c->phys_proc_id;
 477         pdev_entry->cpu_core_id = c->cpu_core_id;
 478 #endif
 479         list_add_tail(&pdev_entry->list, &pdev_list);
 480         mutex_unlock(&pdev_list_mutex);
 481
 482         return 0;
 483
 484 exit_device_free:
 485         kfree(pdev_entry);
 486 exit_device_put:
 487         platform_device_put(pdev);
 488 exit:
 489         mutex_unlock(&pdev_list_mutex);
 490         return err;
 491 }
 492
 493 static void coretemp_device_remove(unsigned int cpu)
 494 {
 495         struct pdev_entry *p;
 496         unsigned int i;
 497
 498         mutex_lock(&pdev_list_mutex);
 499         list_for_each_entry(p, &pdev_list, list) {
 500                 if (p->cpu != cpu)
 501                         continue;
 502
 503                 platform_device_unregister(p->pdev);
 504                 list_del(&p->list);
 505                 mutex_unlock(&pdev_list_mutex);
 506                 kfree(p);
 507                 for_each_cpu(i, cpu_sibling_mask(cpu))
 508                         if (i != cpu && !coretemp_device_add(i))
 509                                 break;
 510                 return;
 511         }
 512         mutex_unlock(&pdev_list_mutex);
 513 }
 514
 515 static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
 516                                  unsigned long action, void *hcpu)
 517 {
 518         unsigned int cpu = (unsigned long) hcpu;
 519
 520         switch (action) {
 521         case CPU_ONLINE:
 522         case CPU_DOWN_FAILED:
 523                 coretemp_device_add(cpu);
 524                 break;
 525         case CPU_DOWN_PREPARE:
 526                 coretemp_device_remove(cpu);
 527                 break;
 528         }
 529         return NOTIFY_OK;
 530 }
 531
 532 static struct notifier_block coretemp_cpu_notifier __refdata = {
 533         .notifier_call = coretemp_cpu_callback,
 534 };
 535
 536 static int __init coretemp_init(void)
 537 {
 538         int i, err = -ENODEV;
 539
 540         /* quick check if we run Intel */
 541         if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
 542                 goto exit;
 543
 544         err = platform_driver_register(&coretemp_driver);
 545         if (err)
 546                 goto exit;
 547
 548         for_each_online_cpu(i)
 549                 coretemp_device_add(i);
 550
 551 #ifndef CONFIG_HOTPLUG_CPU
 552         if (list_empty(&pdev_list)) {
 553                 err = -ENODEV;
 554                 goto exit_driver_unreg;
 555         }
 556 #endif
 557
 558         register_hotcpu_notifier(&coretemp_cpu_notifier);
 559         return 0;
 560
 561 #ifndef CONFIG_HOTPLUG_CPU
 562 exit_driver_unreg:
 563         platform_driver_unregister(&coretemp_driver);
 564 #endif
 565 exit:
 566         return err;
 567 }
 568
 569 static void __exit coretemp_exit(void)
 570 {
 571         struct pdev_entry *p, *n;
 572 #ifdef CONFIG_HOTPLUG_CPU
 573         unregister_hotcpu_notifier(&coretemp_cpu_notifier);
 574 #endif
 575         mutex_lock(&pdev_list_mutex);
 576         list_for_each_entry_safe(p, n, &pdev_list, list) {
 577                 platform_device_unregister(p->pdev);
 578                 list_del(&p->list);
 579                 kfree(p);
 580         }
 581         mutex_unlock(&pdev_list_mutex);
 582         platform_driver_unregister(&coretemp_driver);
 583 }
 584
 585 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
 586 MODULE_DESCRIPTION("Intel Core temperature monitor");
 587 MODULE_LICENSE("GPL");
 588
 589 module_init(coretemp_init)
 590 module_exit(coretemp_exit)