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ACPI: ibm-acpi: rename some identifiers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / forcedeth.c
blobc383dc3b52988ac272bef54c6df3388a70c61800
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,5,6 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Changelog:
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41 * irq mask updated
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56 * open.
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60 * the tx length.
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * on close.
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
82 * capabilities.
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90 * per-packet flags.
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94 * of nv_remove
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
114 *
115 * Known bugs:
116 * We suspect that on some hardware no TX done interrupts are generated.
117 * This means recovery from netif_stop_queue only happens if the hw timer
118 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
119 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
120 * If your hardware reliably generates tx done interrupts, then you can remove
121 * DEV_NEED_TIMERIRQ from the driver_data flags.
122 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
123 * superfluous timer interrupts from the nic.
124 */
125 #ifdef CONFIG_FORCEDETH_NAPI
126 #define DRIVERNAPI "-NAPI"
127 #else
128 #define DRIVERNAPI
129 #endif
130 #define FORCEDETH_VERSION "0.59"
131 #define DRV_NAME "forcedeth"
132
133 #include <linux/module.h>
134 #include <linux/types.h>
135 #include <linux/pci.h>
136 #include <linux/interrupt.h>
137 #include <linux/netdevice.h>
138 #include <linux/etherdevice.h>
139 #include <linux/delay.h>
140 #include <linux/spinlock.h>
141 #include <linux/ethtool.h>
142 #include <linux/timer.h>
143 #include <linux/skbuff.h>
144 #include <linux/mii.h>
145 #include <linux/random.h>
146 #include <linux/init.h>
147 #include <linux/if_vlan.h>
148 #include <linux/dma-mapping.h>
149
150 #include <asm/irq.h>
151 #include <asm/io.h>
152 #include <asm/uaccess.h>
153 #include <asm/system.h>
154
155 #if 0
156 #define dprintk printk
157 #else
158 #define dprintk(x...) do { } while (0)
159 #endif
160
161
162 /*
163 * Hardware access:
164 */
165
166 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
167 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
168 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
169 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
170 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
171 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
172 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
173 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
174 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
175 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
176 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
177 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
178 #define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
179
180 enum {
181 NvRegIrqStatus = 0x000,
182 #define NVREG_IRQSTAT_MIIEVENT 0x040
183 #define NVREG_IRQSTAT_MASK 0x81ff
184 NvRegIrqMask = 0x004,
185 #define NVREG_IRQ_RX_ERROR 0x0001
186 #define NVREG_IRQ_RX 0x0002
187 #define NVREG_IRQ_RX_NOBUF 0x0004
188 #define NVREG_IRQ_TX_ERR 0x0008
189 #define NVREG_IRQ_TX_OK 0x0010
190 #define NVREG_IRQ_TIMER 0x0020
191 #define NVREG_IRQ_LINK 0x0040
192 #define NVREG_IRQ_RX_FORCED 0x0080
193 #define NVREG_IRQ_TX_FORCED 0x0100
194 #define NVREG_IRQ_RECOVER_ERROR 0x8000
195 #define NVREG_IRQMASK_THROUGHPUT 0x00df
196 #define NVREG_IRQMASK_CPU 0x0040
197 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
198 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
199 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
200
201 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
202 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
203 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
204
205 NvRegUnknownSetupReg6 = 0x008,
206 #define NVREG_UNKSETUP6_VAL 3
207
208 /*
209 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
210 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
211 */
212 NvRegPollingInterval = 0x00c,
213 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
214 #define NVREG_POLL_DEFAULT_CPU 13
215 NvRegMSIMap0 = 0x020,
216 NvRegMSIMap1 = 0x024,
217 NvRegMSIIrqMask = 0x030,
218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
219 NvRegMisc1 = 0x080,
220 #define NVREG_MISC1_PAUSE_TX 0x01
221 #define NVREG_MISC1_HD 0x02
222 #define NVREG_MISC1_FORCE 0x3b0f3c
223
224 NvRegMacReset = 0x3c,
225 #define NVREG_MAC_RESET_ASSERT 0x0F3
226 NvRegTransmitterControl = 0x084,
227 #define NVREG_XMITCTL_START 0x01
228 #define NVREG_XMITCTL_MGMT_ST 0x40000000
229 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
230 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
231 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
232 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
233 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
234 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
235 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
236 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
237 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
238 NvRegTransmitterStatus = 0x088,
239 #define NVREG_XMITSTAT_BUSY 0x01
240
241 NvRegPacketFilterFlags = 0x8c,
242 #define NVREG_PFF_PAUSE_RX 0x08
243 #define NVREG_PFF_ALWAYS 0x7F0000
244 #define NVREG_PFF_PROMISC 0x80
245 #define NVREG_PFF_MYADDR 0x20
246 #define NVREG_PFF_LOOPBACK 0x10
247
248 NvRegOffloadConfig = 0x90,
249 #define NVREG_OFFLOAD_HOMEPHY 0x601
250 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
251 NvRegReceiverControl = 0x094,
252 #define NVREG_RCVCTL_START 0x01
253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
254 NvRegReceiverStatus = 0x98,
255 #define NVREG_RCVSTAT_BUSY 0x01
256
257 NvRegRandomSeed = 0x9c,
258 #define NVREG_RNDSEED_MASK 0x00ff
259 #define NVREG_RNDSEED_FORCE 0x7f00
260 #define NVREG_RNDSEED_FORCE2 0x2d00
261 #define NVREG_RNDSEED_FORCE3 0x7400
262
263 NvRegTxDeferral = 0xA0,
264 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
265 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
266 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
267 NvRegRxDeferral = 0xA4,
268 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
269 NvRegMacAddrA = 0xA8,
270 NvRegMacAddrB = 0xAC,
271 NvRegMulticastAddrA = 0xB0,
272 #define NVREG_MCASTADDRA_FORCE 0x01
273 NvRegMulticastAddrB = 0xB4,
274 NvRegMulticastMaskA = 0xB8,
275 NvRegMulticastMaskB = 0xBC,
276
277 NvRegPhyInterface = 0xC0,
278 #define PHY_RGMII 0x10000000
279
280 NvRegTxRingPhysAddr = 0x100,
281 NvRegRxRingPhysAddr = 0x104,
282 NvRegRingSizes = 0x108,
283 #define NVREG_RINGSZ_TXSHIFT 0
284 #define NVREG_RINGSZ_RXSHIFT 16
285 NvRegTransmitPoll = 0x10c,
286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
287 NvRegLinkSpeed = 0x110,
288 #define NVREG_LINKSPEED_FORCE 0x10000
289 #define NVREG_LINKSPEED_10 1000
290 #define NVREG_LINKSPEED_100 100
291 #define NVREG_LINKSPEED_1000 50
292 #define NVREG_LINKSPEED_MASK (0xFFF)
293 NvRegUnknownSetupReg5 = 0x130,
294 #define NVREG_UNKSETUP5_BIT31 (1<<31)
295 NvRegTxWatermark = 0x13c,
296 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
297 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
298 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
299 NvRegTxRxControl = 0x144,
300 #define NVREG_TXRXCTL_KICK 0x0001
301 #define NVREG_TXRXCTL_BIT1 0x0002
302 #define NVREG_TXRXCTL_BIT2 0x0004
303 #define NVREG_TXRXCTL_IDLE 0x0008
304 #define NVREG_TXRXCTL_RESET 0x0010
305 #define NVREG_TXRXCTL_RXCHECK 0x0400
306 #define NVREG_TXRXCTL_DESC_1 0
307 #define NVREG_TXRXCTL_DESC_2 0x02100
308 #define NVREG_TXRXCTL_DESC_3 0x02200
309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
310 #define NVREG_TXRXCTL_VLANINS 0x00080
311 NvRegTxRingPhysAddrHigh = 0x148,
312 NvRegRxRingPhysAddrHigh = 0x14C,
313 NvRegTxPauseFrame = 0x170,
314 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
315 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
316 NvRegMIIStatus = 0x180,
317 #define NVREG_MIISTAT_ERROR 0x0001
318 #define NVREG_MIISTAT_LINKCHANGE 0x0008
319 #define NVREG_MIISTAT_MASK 0x000f
320 #define NVREG_MIISTAT_MASK2 0x000f
321 NvRegMIIMask = 0x184,
322 #define NVREG_MII_LINKCHANGE 0x0008
323
324 NvRegAdapterControl = 0x188,
325 #define NVREG_ADAPTCTL_START 0x02
326 #define NVREG_ADAPTCTL_LINKUP 0x04
327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
328 #define NVREG_ADAPTCTL_RUNNING 0x100000
329 #define NVREG_ADAPTCTL_PHYSHIFT 24
330 NvRegMIISpeed = 0x18c,
331 #define NVREG_MIISPEED_BIT8 (1<<8)
332 #define NVREG_MIIDELAY 5
333 NvRegMIIControl = 0x190,
334 #define NVREG_MIICTL_INUSE 0x08000
335 #define NVREG_MIICTL_WRITE 0x00400
336 #define NVREG_MIICTL_ADDRSHIFT 5
337 NvRegMIIData = 0x194,
338 NvRegWakeUpFlags = 0x200,
339 #define NVREG_WAKEUPFLAGS_VAL 0x7770
340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
342 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
343 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
344 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
345 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
349 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
350
351 NvRegPatternCRC = 0x204,
352 NvRegPatternMask = 0x208,
353 NvRegPowerCap = 0x268,
354 #define NVREG_POWERCAP_D3SUPP (1<<30)
355 #define NVREG_POWERCAP_D2SUPP (1<<26)
356 #define NVREG_POWERCAP_D1SUPP (1<<25)
357 NvRegPowerState = 0x26c,
358 #define NVREG_POWERSTATE_POWEREDUP 0x8000
359 #define NVREG_POWERSTATE_VALID 0x0100
360 #define NVREG_POWERSTATE_MASK 0x0003
361 #define NVREG_POWERSTATE_D0 0x0000
362 #define NVREG_POWERSTATE_D1 0x0001
363 #define NVREG_POWERSTATE_D2 0x0002
364 #define NVREG_POWERSTATE_D3 0x0003
365 NvRegTxCnt = 0x280,
366 NvRegTxZeroReXmt = 0x284,
367 NvRegTxOneReXmt = 0x288,
368 NvRegTxManyReXmt = 0x28c,
369 NvRegTxLateCol = 0x290,
370 NvRegTxUnderflow = 0x294,
371 NvRegTxLossCarrier = 0x298,
372 NvRegTxExcessDef = 0x29c,
373 NvRegTxRetryErr = 0x2a0,
374 NvRegRxFrameErr = 0x2a4,
375 NvRegRxExtraByte = 0x2a8,
376 NvRegRxLateCol = 0x2ac,
377 NvRegRxRunt = 0x2b0,
378 NvRegRxFrameTooLong = 0x2b4,
379 NvRegRxOverflow = 0x2b8,
380 NvRegRxFCSErr = 0x2bc,
381 NvRegRxFrameAlignErr = 0x2c0,
382 NvRegRxLenErr = 0x2c4,
383 NvRegRxUnicast = 0x2c8,
384 NvRegRxMulticast = 0x2cc,
385 NvRegRxBroadcast = 0x2d0,
386 NvRegTxDef = 0x2d4,
387 NvRegTxFrame = 0x2d8,
388 NvRegRxCnt = 0x2dc,
389 NvRegTxPause = 0x2e0,
390 NvRegRxPause = 0x2e4,
391 NvRegRxDropFrame = 0x2e8,
392 NvRegVlanControl = 0x300,
393 #define NVREG_VLANCONTROL_ENABLE 0x2000
394 NvRegMSIXMap0 = 0x3e0,
395 NvRegMSIXMap1 = 0x3e4,
396 NvRegMSIXIrqStatus = 0x3f0,
397
398 NvRegPowerState2 = 0x600,
399 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
400 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
401 };
402
403 /* Big endian: should work, but is untested */
404 struct ring_desc {
405 __le32 buf;
406 __le32 flaglen;
407 };
408
409 struct ring_desc_ex {
410 __le32 bufhigh;
411 __le32 buflow;
412 __le32 txvlan;
413 __le32 flaglen;
414 };
415
416 union ring_type {
417 struct ring_desc* orig;
418 struct ring_desc_ex* ex;
419 };
420
421 #define FLAG_MASK_V1 0xffff0000
422 #define FLAG_MASK_V2 0xffffc000
423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
425
426 #define NV_TX_LASTPACKET (1<<16)
427 #define NV_TX_RETRYERROR (1<<19)
428 #define NV_TX_FORCED_INTERRUPT (1<<24)
429 #define NV_TX_DEFERRED (1<<26)
430 #define NV_TX_CARRIERLOST (1<<27)
431 #define NV_TX_LATECOLLISION (1<<28)
432 #define NV_TX_UNDERFLOW (1<<29)
433 #define NV_TX_ERROR (1<<30)
434 #define NV_TX_VALID (1<<31)
435
436 #define NV_TX2_LASTPACKET (1<<29)
437 #define NV_TX2_RETRYERROR (1<<18)
438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
439 #define NV_TX2_DEFERRED (1<<25)
440 #define NV_TX2_CARRIERLOST (1<<26)
441 #define NV_TX2_LATECOLLISION (1<<27)
442 #define NV_TX2_UNDERFLOW (1<<28)
443 /* error and valid are the same for both */
444 #define NV_TX2_ERROR (1<<30)
445 #define NV_TX2_VALID (1<<31)
446 #define NV_TX2_TSO (1<<28)
447 #define NV_TX2_TSO_SHIFT 14
448 #define NV_TX2_TSO_MAX_SHIFT 14
449 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
450 #define NV_TX2_CHECKSUM_L3 (1<<27)
451 #define NV_TX2_CHECKSUM_L4 (1<<26)
452
453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
454
455 #define NV_RX_DESCRIPTORVALID (1<<16)
456 #define NV_RX_MISSEDFRAME (1<<17)
457 #define NV_RX_SUBSTRACT1 (1<<18)
458 #define NV_RX_ERROR1 (1<<23)
459 #define NV_RX_ERROR2 (1<<24)
460 #define NV_RX_ERROR3 (1<<25)
461 #define NV_RX_ERROR4 (1<<26)
462 #define NV_RX_CRCERR (1<<27)
463 #define NV_RX_OVERFLOW (1<<28)
464 #define NV_RX_FRAMINGERR (1<<29)
465 #define NV_RX_ERROR (1<<30)
466 #define NV_RX_AVAIL (1<<31)
467
468 #define NV_RX2_CHECKSUMMASK (0x1C000000)
469 #define NV_RX2_CHECKSUMOK1 (0x10000000)
470 #define NV_RX2_CHECKSUMOK2 (0x14000000)
471 #define NV_RX2_CHECKSUMOK3 (0x18000000)
472 #define NV_RX2_DESCRIPTORVALID (1<<29)
473 #define NV_RX2_SUBSTRACT1 (1<<25)
474 #define NV_RX2_ERROR1 (1<<18)
475 #define NV_RX2_ERROR2 (1<<19)
476 #define NV_RX2_ERROR3 (1<<20)
477 #define NV_RX2_ERROR4 (1<<21)
478 #define NV_RX2_CRCERR (1<<22)
479 #define NV_RX2_OVERFLOW (1<<23)
480 #define NV_RX2_FRAMINGERR (1<<24)
481 /* error and avail are the same for both */
482 #define NV_RX2_ERROR (1<<30)
483 #define NV_RX2_AVAIL (1<<31)
484
485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
486 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
487
488 /* Miscelaneous hardware related defines: */
489 #define NV_PCI_REGSZ_VER1 0x270
490 #define NV_PCI_REGSZ_VER2 0x604
491
492 /* various timeout delays: all in usec */
493 #define NV_TXRX_RESET_DELAY 4
494 #define NV_TXSTOP_DELAY1 10
495 #define NV_TXSTOP_DELAY1MAX 500000
496 #define NV_TXSTOP_DELAY2 100
497 #define NV_RXSTOP_DELAY1 10
498 #define NV_RXSTOP_DELAY1MAX 500000
499 #define NV_RXSTOP_DELAY2 100
500 #define NV_SETUP5_DELAY 5
501 #define NV_SETUP5_DELAYMAX 50000
502 #define NV_POWERUP_DELAY 5
503 #define NV_POWERUP_DELAYMAX 5000
504 #define NV_MIIBUSY_DELAY 50
505 #define NV_MIIPHY_DELAY 10
506 #define NV_MIIPHY_DELAYMAX 10000
507 #define NV_MAC_RESET_DELAY 64
508
509 #define NV_WAKEUPPATTERNS 5
510 #define NV_WAKEUPMASKENTRIES 4
511
512 /* General driver defaults */
513 #define NV_WATCHDOG_TIMEO (5*HZ)
514
515 #define RX_RING_DEFAULT 128
516 #define TX_RING_DEFAULT 256
517 #define RX_RING_MIN 128
518 #define TX_RING_MIN 64
519 #define RING_MAX_DESC_VER_1 1024
520 #define RING_MAX_DESC_VER_2_3 16384
521 /*
522 * Difference between the get and put pointers for the tx ring.
523 * This is used to throttle the amount of data outstanding in the
524 * tx ring.
525 */
526 #define TX_LIMIT_DIFFERENCE 1
527
528 /* rx/tx mac addr + type + vlan + align + slack*/
529 #define NV_RX_HEADERS (64)
530 /* even more slack. */
531 #define NV_RX_ALLOC_PAD (64)
532
533 /* maximum mtu size */
534 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
535 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
536
537 #define OOM_REFILL (1+HZ/20)
538 #define POLL_WAIT (1+HZ/100)
539 #define LINK_TIMEOUT (3*HZ)
540 #define STATS_INTERVAL (10*HZ)
541
542 /*
543 * desc_ver values:
544 * The nic supports three different descriptor types:
545 * - DESC_VER_1: Original
546 * - DESC_VER_2: support for jumbo frames.
547 * - DESC_VER_3: 64-bit format.
548 */
549 #define DESC_VER_1 1
550 #define DESC_VER_2 2
551 #define DESC_VER_3 3
552
553 /* PHY defines */
554 #define PHY_OUI_MARVELL 0x5043
555 #define PHY_OUI_CICADA 0x03f1
556 #define PHY_OUI_VITESSE 0x01c1
557 #define PHYID1_OUI_MASK 0x03ff
558 #define PHYID1_OUI_SHFT 6
559 #define PHYID2_OUI_MASK 0xfc00
560 #define PHYID2_OUI_SHFT 10
561 #define PHYID2_MODEL_MASK 0x03f0
562 #define PHY_MODEL_MARVELL_E3016 0x220
563 #define PHY_MARVELL_E3016_INITMASK 0x0300
564 #define PHY_CICADA_INIT1 0x0f000
565 #define PHY_CICADA_INIT2 0x0e00
566 #define PHY_CICADA_INIT3 0x01000
567 #define PHY_CICADA_INIT4 0x0200
568 #define PHY_CICADA_INIT5 0x0004
569 #define PHY_CICADA_INIT6 0x02000
570 #define PHY_VITESSE_INIT_REG1 0x1f
571 #define PHY_VITESSE_INIT_REG2 0x10
572 #define PHY_VITESSE_INIT_REG3 0x11
573 #define PHY_VITESSE_INIT_REG4 0x12
574 #define PHY_VITESSE_INIT_MSK1 0xc
575 #define PHY_VITESSE_INIT_MSK2 0x0180
576 #define PHY_VITESSE_INIT1 0x52b5
577 #define PHY_VITESSE_INIT2 0xaf8a
578 #define PHY_VITESSE_INIT3 0x8
579 #define PHY_VITESSE_INIT4 0x8f8a
580 #define PHY_VITESSE_INIT5 0xaf86
581 #define PHY_VITESSE_INIT6 0x8f86
582 #define PHY_VITESSE_INIT7 0xaf82
583 #define PHY_VITESSE_INIT8 0x0100
584 #define PHY_VITESSE_INIT9 0x8f82
585 #define PHY_VITESSE_INIT10 0x0
586
587 #define PHY_GIGABIT 0x0100
588
589 #define PHY_TIMEOUT 0x1
590 #define PHY_ERROR 0x2
591
592 #define PHY_100 0x1
593 #define PHY_1000 0x2
594 #define PHY_HALF 0x100
595
596 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
597 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
598 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
599 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
600 #define NV_PAUSEFRAME_RX_REQ 0x0010
601 #define NV_PAUSEFRAME_TX_REQ 0x0020
602 #define NV_PAUSEFRAME_AUTONEG 0x0040
603
604 /* MSI/MSI-X defines */
605 #define NV_MSI_X_MAX_VECTORS 8
606 #define NV_MSI_X_VECTORS_MASK 0x000f
607 #define NV_MSI_CAPABLE 0x0010
608 #define NV_MSI_X_CAPABLE 0x0020
609 #define NV_MSI_ENABLED 0x0040
610 #define NV_MSI_X_ENABLED 0x0080
611
612 #define NV_MSI_X_VECTOR_ALL 0x0
613 #define NV_MSI_X_VECTOR_RX 0x0
614 #define NV_MSI_X_VECTOR_TX 0x1
615 #define NV_MSI_X_VECTOR_OTHER 0x2
616
617 /* statistics */
618 struct nv_ethtool_str {
619 char name[ETH_GSTRING_LEN];
620 };
621
622 static const struct nv_ethtool_str nv_estats_str[] = {
623 { "tx_bytes" },
624 { "tx_zero_rexmt" },
625 { "tx_one_rexmt" },
626 { "tx_many_rexmt" },
627 { "tx_late_collision" },
628 { "tx_fifo_errors" },
629 { "tx_carrier_errors" },
630 { "tx_excess_deferral" },
631 { "tx_retry_error" },
632 { "tx_deferral" },
633 { "tx_packets" },
634 { "tx_pause" },
635 { "rx_frame_error" },
636 { "rx_extra_byte" },
637 { "rx_late_collision" },
638 { "rx_runt" },
639 { "rx_frame_too_long" },
640 { "rx_over_errors" },
641 { "rx_crc_errors" },
642 { "rx_frame_align_error" },
643 { "rx_length_error" },
644 { "rx_unicast" },
645 { "rx_multicast" },
646 { "rx_broadcast" },
647 { "rx_bytes" },
648 { "rx_pause" },
649 { "rx_drop_frame" },
650 { "rx_packets" },
651 { "rx_errors_total" }
652 };
653
654 struct nv_ethtool_stats {
655 u64 tx_bytes;
656 u64 tx_zero_rexmt;
657 u64 tx_one_rexmt;
658 u64 tx_many_rexmt;
659 u64 tx_late_collision;
660 u64 tx_fifo_errors;
661 u64 tx_carrier_errors;
662 u64 tx_excess_deferral;
663 u64 tx_retry_error;
664 u64 tx_deferral;
665 u64 tx_packets;
666 u64 tx_pause;
667 u64 rx_frame_error;
668 u64 rx_extra_byte;
669 u64 rx_late_collision;
670 u64 rx_runt;
671 u64 rx_frame_too_long;
672 u64 rx_over_errors;
673 u64 rx_crc_errors;
674 u64 rx_frame_align_error;
675 u64 rx_length_error;
676 u64 rx_unicast;
677 u64 rx_multicast;
678 u64 rx_broadcast;
679 u64 rx_bytes;
680 u64 rx_pause;
681 u64 rx_drop_frame;
682 u64 rx_packets;
683 u64 rx_errors_total;
684 };
685
686 /* diagnostics */
687 #define NV_TEST_COUNT_BASE 3
688 #define NV_TEST_COUNT_EXTENDED 4
689
690 static const struct nv_ethtool_str nv_etests_str[] = {
691 { "link (online/offline)" },
692 { "register (offline) " },
693 { "interrupt (offline) " },
694 { "loopback (offline) " }
695 };
696
697 struct register_test {
698 __le32 reg;
699 __le32 mask;
700 };
701
702 static const struct register_test nv_registers_test[] = {
703 { NvRegUnknownSetupReg6, 0x01 },
704 { NvRegMisc1, 0x03c },
705 { NvRegOffloadConfig, 0x03ff },
706 { NvRegMulticastAddrA, 0xffffffff },
707 { NvRegTxWatermark, 0x0ff },
708 { NvRegWakeUpFlags, 0x07777 },
709 { 0,0 }
710 };
711
712 /*
713 * SMP locking:
714 * All hardware access under dev->priv->lock, except the performance
715 * critical parts:
716 * - rx is (pseudo-) lockless: it relies on the single-threading provided
717 * by the arch code for interrupts.
718 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
719 * needs dev->priv->lock :-(
720 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
721 */
722
723 /* in dev: base, irq */
724 struct fe_priv {
725 spinlock_t lock;
726
727 /* General data:
728 * Locking: spin_lock(&np->lock); */
729 struct net_device_stats stats;
730 struct nv_ethtool_stats estats;
731 int in_shutdown;
732 u32 linkspeed;
733 int duplex;
734 int autoneg;
735 int fixed_mode;
736 int phyaddr;
737 int wolenabled;
738 unsigned int phy_oui;
739 unsigned int phy_model;
740 u16 gigabit;
741 int intr_test;
742 int recover_error;
743
744 /* General data: RO fields */
745 dma_addr_t ring_addr;
746 struct pci_dev *pci_dev;
747 u32 orig_mac[2];
748 u32 irqmask;
749 u32 desc_ver;
750 u32 txrxctl_bits;
751 u32 vlanctl_bits;
752 u32 driver_data;
753 u32 register_size;
754 int rx_csum;
755 u32 mac_in_use;
756
757 void __iomem *base;
758
759 /* rx specific fields.
760 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
761 */
762 union ring_type rx_ring;
763 unsigned int cur_rx, refill_rx;
764 struct sk_buff **rx_skbuff;
765 dma_addr_t *rx_dma;
766 unsigned int rx_buf_sz;
767 unsigned int pkt_limit;
768 struct timer_list oom_kick;
769 struct timer_list nic_poll;
770 struct timer_list stats_poll;
771 u32 nic_poll_irq;
772 int rx_ring_size;
773
774 /* media detection workaround.
775 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
776 */
777 int need_linktimer;
778 unsigned long link_timeout;
779 /*
780 * tx specific fields.
781 */
782 union ring_type tx_ring;
783 unsigned int next_tx, nic_tx;
784 struct sk_buff **tx_skbuff;
785 dma_addr_t *tx_dma;
786 unsigned int *tx_dma_len;
787 u32 tx_flags;
788 int tx_ring_size;
789 int tx_limit_start;
790 int tx_limit_stop;
791
792 /* vlan fields */
793 struct vlan_group *vlangrp;
794
795 /* msi/msi-x fields */
796 u32 msi_flags;
797 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
798
799 /* flow control */
800 u32 pause_flags;
801 };
802
803 /*
804 * Maximum number of loops until we assume that a bit in the irq mask
805 * is stuck. Overridable with module param.
806 */
807 static int max_interrupt_work = 5;
808
809 /*
810 * Optimization can be either throuput mode or cpu mode
811 *
812 * Throughput Mode: Every tx and rx packet will generate an interrupt.
813 * CPU Mode: Interrupts are controlled by a timer.
814 */
815 enum {
816 NV_OPTIMIZATION_MODE_THROUGHPUT,
817 NV_OPTIMIZATION_MODE_CPU
818 };
819 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
820
821 /*
822 * Poll interval for timer irq
823 *
824 * This interval determines how frequent an interrupt is generated.
825 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
826 * Min = 0, and Max = 65535
827 */
828 static int poll_interval = -1;
829
830 /*
831 * MSI interrupts
832 */
833 enum {
834 NV_MSI_INT_DISABLED,
835 NV_MSI_INT_ENABLED
836 };
837 static int msi = NV_MSI_INT_ENABLED;
838
839 /*
840 * MSIX interrupts
841 */
842 enum {
843 NV_MSIX_INT_DISABLED,
844 NV_MSIX_INT_ENABLED
845 };
846 static int msix = NV_MSIX_INT_DISABLED;
847
848 /*
849 * DMA 64bit
850 */
851 enum {
852 NV_DMA_64BIT_DISABLED,
853 NV_DMA_64BIT_ENABLED
854 };
855 static int dma_64bit = NV_DMA_64BIT_ENABLED;
856
857 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
858 {
859 return netdev_priv(dev);
860 }
861
862 static inline u8 __iomem *get_hwbase(struct net_device *dev)
863 {
864 return ((struct fe_priv *)netdev_priv(dev))->base;
865 }
866
867 static inline void pci_push(u8 __iomem *base)
868 {
869 /* force out pending posted writes */
870 readl(base);
871 }
872
873 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
874 {
875 return le32_to_cpu(prd->flaglen)
876 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
877 }
878
879 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
880 {
881 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
882 }
883
884 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
885 int delay, int delaymax, const char *msg)
886 {
887 u8 __iomem *base = get_hwbase(dev);
888
889 pci_push(base);
890 do {
891 udelay(delay);
892 delaymax -= delay;
893 if (delaymax < 0) {
894 if (msg)
895 printk(msg);
896 return 1;
897 }
898 } while ((readl(base + offset) & mask) != target);
899 return 0;
900 }
901
902 #define NV_SETUP_RX_RING 0x01
903 #define NV_SETUP_TX_RING 0x02
904
905 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
906 {
907 struct fe_priv *np = get_nvpriv(dev);
908 u8 __iomem *base = get_hwbase(dev);
909
910 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
911 if (rxtx_flags & NV_SETUP_RX_RING) {
912 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
913 }
914 if (rxtx_flags & NV_SETUP_TX_RING) {
915 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
916 }
917 } else {
918 if (rxtx_flags & NV_SETUP_RX_RING) {
919 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
920 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
921 }
922 if (rxtx_flags & NV_SETUP_TX_RING) {
923 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
924 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
925 }
926 }
927 }
928
929 static void free_rings(struct net_device *dev)
930 {
931 struct fe_priv *np = get_nvpriv(dev);
932
933 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
934 if (np->rx_ring.orig)
935 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
936 np->rx_ring.orig, np->ring_addr);
937 } else {
938 if (np->rx_ring.ex)
939 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
940 np->rx_ring.ex, np->ring_addr);
941 }
942 if (np->rx_skbuff)
943 kfree(np->rx_skbuff);
944 if (np->rx_dma)
945 kfree(np->rx_dma);
946 if (np->tx_skbuff)
947 kfree(np->tx_skbuff);
948 if (np->tx_dma)
949 kfree(np->tx_dma);
950 if (np->tx_dma_len)
951 kfree(np->tx_dma_len);
952 }
953
954 static int using_multi_irqs(struct net_device *dev)
955 {
956 struct fe_priv *np = get_nvpriv(dev);
957
958 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
959 ((np->msi_flags & NV_MSI_X_ENABLED) &&
960 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
961 return 0;
962 else
963 return 1;
964 }
965
966 static void nv_enable_irq(struct net_device *dev)
967 {
968 struct fe_priv *np = get_nvpriv(dev);
969
970 if (!using_multi_irqs(dev)) {
971 if (np->msi_flags & NV_MSI_X_ENABLED)
972 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
973 else
974 enable_irq(dev->irq);
975 } else {
976 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
977 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
978 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
979 }
980 }
981
982 static void nv_disable_irq(struct net_device *dev)
983 {
984 struct fe_priv *np = get_nvpriv(dev);
985
986 if (!using_multi_irqs(dev)) {
987 if (np->msi_flags & NV_MSI_X_ENABLED)
988 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
989 else
990 disable_irq(dev->irq);
991 } else {
992 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
993 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
994 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
995 }
996 }
997
998 /* In MSIX mode, a write to irqmask behaves as XOR */
999 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1000 {
1001 u8 __iomem *base = get_hwbase(dev);
1002
1003 writel(mask, base + NvRegIrqMask);
1004 }
1005
1006 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1007 {
1008 struct fe_priv *np = get_nvpriv(dev);
1009 u8 __iomem *base = get_hwbase(dev);
1010
1011 if (np->msi_flags & NV_MSI_X_ENABLED) {
1012 writel(mask, base + NvRegIrqMask);
1013 } else {
1014 if (np->msi_flags & NV_MSI_ENABLED)
1015 writel(0, base + NvRegMSIIrqMask);
1016 writel(0, base + NvRegIrqMask);
1017 }
1018 }
1019
1020 #define MII_READ (-1)
1021 /* mii_rw: read/write a register on the PHY.
1022 *
1023 * Caller must guarantee serialization
1024 */
1025 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1026 {
1027 u8 __iomem *base = get_hwbase(dev);
1028 u32 reg;
1029 int retval;
1030
1031 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1032
1033 reg = readl(base + NvRegMIIControl);
1034 if (reg & NVREG_MIICTL_INUSE) {
1035 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1036 udelay(NV_MIIBUSY_DELAY);
1037 }
1038
1039 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1040 if (value != MII_READ) {
1041 writel(value, base + NvRegMIIData);
1042 reg |= NVREG_MIICTL_WRITE;
1043 }
1044 writel(reg, base + NvRegMIIControl);
1045
1046 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1047 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1048 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1049 dev->name, miireg, addr);
1050 retval = -1;
1051 } else if (value != MII_READ) {
1052 /* it was a write operation - fewer failures are detectable */
1053 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1054 dev->name, value, miireg, addr);
1055 retval = 0;
1056 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1057 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1058 dev->name, miireg, addr);
1059 retval = -1;
1060 } else {
1061 retval = readl(base + NvRegMIIData);
1062 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1063 dev->name, miireg, addr, retval);
1064 }
1065
1066 return retval;
1067 }
1068
1069 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1070 {
1071 struct fe_priv *np = netdev_priv(dev);
1072 u32 miicontrol;
1073 unsigned int tries = 0;
1074
1075 miicontrol = BMCR_RESET | bmcr_setup;
1076 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1077 return -1;
1078 }
1079
1080 /* wait for 500ms */
1081 msleep(500);
1082
1083 /* must wait till reset is deasserted */
1084 while (miicontrol & BMCR_RESET) {
1085 msleep(10);
1086 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1087 /* FIXME: 100 tries seem excessive */
1088 if (tries++ > 100)
1089 return -1;
1090 }
1091 return 0;
1092 }
1093
1094 static int phy_init(struct net_device *dev)
1095 {
1096 struct fe_priv *np = get_nvpriv(dev);
1097 u8 __iomem *base = get_hwbase(dev);
1098 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1099
1100 /* phy errata for E3016 phy */
1101 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1102 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1103 reg &= ~PHY_MARVELL_E3016_INITMASK;
1104 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1105 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1106 return PHY_ERROR;
1107 }
1108 }
1109
1110 /* set advertise register */
1111 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1112 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1113 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1114 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1115 return PHY_ERROR;
1116 }
1117
1118 /* get phy interface type */
1119 phyinterface = readl(base + NvRegPhyInterface);
1120
1121 /* see if gigabit phy */
1122 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1123 if (mii_status & PHY_GIGABIT) {
1124 np->gigabit = PHY_GIGABIT;
1125 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1126 mii_control_1000 &= ~ADVERTISE_1000HALF;
1127 if (phyinterface & PHY_RGMII)
1128 mii_control_1000 |= ADVERTISE_1000FULL;
1129 else
1130 mii_control_1000 &= ~ADVERTISE_1000FULL;
1131
1132 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1133 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1134 return PHY_ERROR;
1135 }
1136 }
1137 else
1138 np->gigabit = 0;
1139
1140 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1141 mii_control |= BMCR_ANENABLE;
1142
1143 /* reset the phy
1144 * (certain phys need bmcr to be setup with reset)
1145 */
1146 if (phy_reset(dev, mii_control)) {
1147 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1148 return PHY_ERROR;
1149 }
1150
1151 /* phy vendor specific configuration */
1152 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1153 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1154 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1155 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1156 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1157 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1158 return PHY_ERROR;
1159 }
1160 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1161 phy_reserved |= PHY_CICADA_INIT5;
1162 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1163 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1164 return PHY_ERROR;
1165 }
1166 }
1167 if (np->phy_oui == PHY_OUI_CICADA) {
1168 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1169 phy_reserved |= PHY_CICADA_INIT6;
1170 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1171 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1172 return PHY_ERROR;
1173 }
1174 }
1175 if (np->phy_oui == PHY_OUI_VITESSE) {
1176 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1177 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1178 return PHY_ERROR;
1179 }
1180 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1181 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1182 return PHY_ERROR;
1183 }
1184 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1185 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1186 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1187 return PHY_ERROR;
1188 }
1189 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1190 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1191 phy_reserved |= PHY_VITESSE_INIT3;
1192 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1193 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1194 return PHY_ERROR;
1195 }
1196 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1197 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1198 return PHY_ERROR;
1199 }
1200 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1201 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1202 return PHY_ERROR;
1203 }
1204 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1205 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1206 phy_reserved |= PHY_VITESSE_INIT3;
1207 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1208 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209 return PHY_ERROR;
1210 }
1211 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1212 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1213 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1214 return PHY_ERROR;
1215 }
1216 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1217 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1218 return PHY_ERROR;
1219 }
1220 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1221 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1222 return PHY_ERROR;
1223 }
1224 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1225 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1226 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1227 return PHY_ERROR;
1228 }
1229 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1230 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1231 phy_reserved |= PHY_VITESSE_INIT8;
1232 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1233 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1234 return PHY_ERROR;
1235 }
1236 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1237 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1238 return PHY_ERROR;
1239 }
1240 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1241 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1242 return PHY_ERROR;
1243 }
1244 }
1245 /* some phys clear out pause advertisment on reset, set it back */
1246 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1247
1248 /* restart auto negotiation */
1249 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1250 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1251 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1252 return PHY_ERROR;
1253 }
1254
1255 return 0;
1256 }
1257
1258 static void nv_start_rx(struct net_device *dev)
1259 {
1260 struct fe_priv *np = netdev_priv(dev);
1261 u8 __iomem *base = get_hwbase(dev);
1262 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1263
1264 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1265 /* Already running? Stop it. */
1266 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1267 rx_ctrl &= ~NVREG_RCVCTL_START;
1268 writel(rx_ctrl, base + NvRegReceiverControl);
1269 pci_push(base);
1270 }
1271 writel(np->linkspeed, base + NvRegLinkSpeed);
1272 pci_push(base);
1273 rx_ctrl |= NVREG_RCVCTL_START;
1274 if (np->mac_in_use)
1275 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1276 writel(rx_ctrl, base + NvRegReceiverControl);
1277 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1278 dev->name, np->duplex, np->linkspeed);
1279 pci_push(base);
1280 }
1281
1282 static void nv_stop_rx(struct net_device *dev)
1283 {
1284 struct fe_priv *np = netdev_priv(dev);
1285 u8 __iomem *base = get_hwbase(dev);
1286 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1287
1288 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1289 if (!np->mac_in_use)
1290 rx_ctrl &= ~NVREG_RCVCTL_START;
1291 else
1292 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1293 writel(rx_ctrl, base + NvRegReceiverControl);
1294 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1295 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1296 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1297
1298 udelay(NV_RXSTOP_DELAY2);
1299 if (!np->mac_in_use)
1300 writel(0, base + NvRegLinkSpeed);
1301 }
1302
1303 static void nv_start_tx(struct net_device *dev)
1304 {
1305 struct fe_priv *np = netdev_priv(dev);
1306 u8 __iomem *base = get_hwbase(dev);
1307 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1308
1309 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1310 tx_ctrl |= NVREG_XMITCTL_START;
1311 if (np->mac_in_use)
1312 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1313 writel(tx_ctrl, base + NvRegTransmitterControl);
1314 pci_push(base);
1315 }
1316
1317 static void nv_stop_tx(struct net_device *dev)
1318 {
1319 struct fe_priv *np = netdev_priv(dev);
1320 u8 __iomem *base = get_hwbase(dev);
1321 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1322
1323 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1324 if (!np->mac_in_use)
1325 tx_ctrl &= ~NVREG_XMITCTL_START;
1326 else
1327 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1328 writel(tx_ctrl, base + NvRegTransmitterControl);
1329 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1330 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1331 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1332
1333 udelay(NV_TXSTOP_DELAY2);
1334 if (!np->mac_in_use)
1335 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1336 base + NvRegTransmitPoll);
1337 }
1338
1339 static void nv_txrx_reset(struct net_device *dev)
1340 {
1341 struct fe_priv *np = netdev_priv(dev);
1342 u8 __iomem *base = get_hwbase(dev);
1343
1344 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1345 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1346 pci_push(base);
1347 udelay(NV_TXRX_RESET_DELAY);
1348 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1349 pci_push(base);
1350 }
1351
1352 static void nv_mac_reset(struct net_device *dev)
1353 {
1354 struct fe_priv *np = netdev_priv(dev);
1355 u8 __iomem *base = get_hwbase(dev);
1356
1357 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1358 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1359 pci_push(base);
1360 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1361 pci_push(base);
1362 udelay(NV_MAC_RESET_DELAY);
1363 writel(0, base + NvRegMacReset);
1364 pci_push(base);
1365 udelay(NV_MAC_RESET_DELAY);
1366 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1367 pci_push(base);
1368 }
1369
1370 /*
1371 * nv_get_stats: dev->get_stats function
1372 * Get latest stats value from the nic.
1373 * Called with read_lock(&dev_base_lock) held for read -
1374 * only synchronized against unregister_netdevice.
1375 */
1376 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1377 {
1378 struct fe_priv *np = netdev_priv(dev);
1379
1380 /* It seems that the nic always generates interrupts and doesn't
1381 * accumulate errors internally. Thus the current values in np->stats
1382 * are already up to date.
1383 */
1384 return &np->stats;
1385 }
1386
1387 /*
1388 * nv_alloc_rx: fill rx ring entries.
1389 * Return 1 if the allocations for the skbs failed and the
1390 * rx engine is without Available descriptors
1391 */
1392 static int nv_alloc_rx(struct net_device *dev)
1393 {
1394 struct fe_priv *np = netdev_priv(dev);
1395 unsigned int refill_rx = np->refill_rx;
1396 int nr;
1397
1398 while (np->cur_rx != refill_rx) {
1399 struct sk_buff *skb;
1400
1401 nr = refill_rx % np->rx_ring_size;
1402 if (np->rx_skbuff[nr] == NULL) {
1403
1404 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1405 if (!skb)
1406 break;
1407
1408 skb->dev = dev;
1409 np->rx_skbuff[nr] = skb;
1410 } else {
1411 skb = np->rx_skbuff[nr];
1412 }
1413 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1414 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1415 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1416 np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]);
1417 wmb();
1418 np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1419 } else {
1420 np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1421 np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1422 wmb();
1423 np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1424 }
1425 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1426 dev->name, refill_rx);
1427 refill_rx++;
1428 }
1429 np->refill_rx = refill_rx;
1430 if (np->cur_rx - refill_rx == np->rx_ring_size)
1431 return 1;
1432 return 0;
1433 }
1434
1435 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1436 #ifdef CONFIG_FORCEDETH_NAPI
1437 static void nv_do_rx_refill(unsigned long data)
1438 {
1439 struct net_device *dev = (struct net_device *) data;
1440
1441 /* Just reschedule NAPI rx processing */
1442 netif_rx_schedule(dev);
1443 }
1444 #else
1445 static void nv_do_rx_refill(unsigned long data)
1446 {
1447 struct net_device *dev = (struct net_device *) data;
1448 struct fe_priv *np = netdev_priv(dev);
1449
1450 if (!using_multi_irqs(dev)) {
1451 if (np->msi_flags & NV_MSI_X_ENABLED)
1452 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1453 else
1454 disable_irq(dev->irq);
1455 } else {
1456 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1457 }
1458 if (nv_alloc_rx(dev)) {
1459 spin_lock_irq(&np->lock);
1460 if (!np->in_shutdown)
1461 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1462 spin_unlock_irq(&np->lock);
1463 }
1464 if (!using_multi_irqs(dev)) {
1465 if (np->msi_flags & NV_MSI_X_ENABLED)
1466 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1467 else
1468 enable_irq(dev->irq);
1469 } else {
1470 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1471 }
1472 }
1473 #endif
1474
1475 static void nv_init_rx(struct net_device *dev)
1476 {
1477 struct fe_priv *np = netdev_priv(dev);
1478 int i;
1479
1480 np->cur_rx = np->rx_ring_size;
1481 np->refill_rx = 0;
1482 for (i = 0; i < np->rx_ring_size; i++)
1483 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1484 np->rx_ring.orig[i].flaglen = 0;
1485 else
1486 np->rx_ring.ex[i].flaglen = 0;
1487 }
1488
1489 static void nv_init_tx(struct net_device *dev)
1490 {
1491 struct fe_priv *np = netdev_priv(dev);
1492 int i;
1493
1494 np->next_tx = np->nic_tx = 0;
1495 for (i = 0; i < np->tx_ring_size; i++) {
1496 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1497 np->tx_ring.orig[i].flaglen = 0;
1498 else
1499 np->tx_ring.ex[i].flaglen = 0;
1500 np->tx_skbuff[i] = NULL;
1501 np->tx_dma[i] = 0;
1502 }
1503 }
1504
1505 static int nv_init_ring(struct net_device *dev)
1506 {
1507 nv_init_tx(dev);
1508 nv_init_rx(dev);
1509 return nv_alloc_rx(dev);
1510 }
1511
1512 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1513 {
1514 struct fe_priv *np = netdev_priv(dev);
1515
1516 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1517 dev->name, skbnr);
1518
1519 if (np->tx_dma[skbnr]) {
1520 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1521 np->tx_dma_len[skbnr],
1522 PCI_DMA_TODEVICE);
1523 np->tx_dma[skbnr] = 0;
1524 }
1525
1526 if (np->tx_skbuff[skbnr]) {
1527 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1528 np->tx_skbuff[skbnr] = NULL;
1529 return 1;
1530 } else {
1531 return 0;
1532 }
1533 }
1534
1535 static void nv_drain_tx(struct net_device *dev)
1536 {
1537 struct fe_priv *np = netdev_priv(dev);
1538 unsigned int i;
1539
1540 for (i = 0; i < np->tx_ring_size; i++) {
1541 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1542 np->tx_ring.orig[i].flaglen = 0;
1543 else
1544 np->tx_ring.ex[i].flaglen = 0;
1545 if (nv_release_txskb(dev, i))
1546 np->stats.tx_dropped++;
1547 }
1548 }
1549
1550 static void nv_drain_rx(struct net_device *dev)
1551 {
1552 struct fe_priv *np = netdev_priv(dev);
1553 int i;
1554 for (i = 0; i < np->rx_ring_size; i++) {
1555 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1556 np->rx_ring.orig[i].flaglen = 0;
1557 else
1558 np->rx_ring.ex[i].flaglen = 0;
1559 wmb();
1560 if (np->rx_skbuff[i]) {
1561 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1562 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1563 PCI_DMA_FROMDEVICE);
1564 dev_kfree_skb(np->rx_skbuff[i]);
1565 np->rx_skbuff[i] = NULL;
1566 }
1567 }
1568 }
1569
1570 static void drain_ring(struct net_device *dev)
1571 {
1572 nv_drain_tx(dev);
1573 nv_drain_rx(dev);
1574 }
1575
1576 /*
1577 * nv_start_xmit: dev->hard_start_xmit function
1578 * Called with netif_tx_lock held.
1579 */
1580 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1581 {
1582 struct fe_priv *np = netdev_priv(dev);
1583 u32 tx_flags = 0;
1584 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1585 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1586 unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1587 unsigned int start_nr = np->next_tx % np->tx_ring_size;
1588 unsigned int i;
1589 u32 offset = 0;
1590 u32 bcnt;
1591 u32 size = skb->len-skb->data_len;
1592 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1593 u32 tx_flags_vlan = 0;
1594
1595 /* add fragments to entries count */
1596 for (i = 0; i < fragments; i++) {
1597 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1598 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1599 }
1600
1601 spin_lock_irq(&np->lock);
1602
1603 if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1604 spin_unlock_irq(&np->lock);
1605 netif_stop_queue(dev);
1606 return NETDEV_TX_BUSY;
1607 }
1608
1609 /* setup the header buffer */
1610 do {
1611 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1612 nr = (nr + 1) % np->tx_ring_size;
1613
1614 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1615 PCI_DMA_TODEVICE);
1616 np->tx_dma_len[nr] = bcnt;
1617
1618 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1619 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1620 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1621 } else {
1622 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1623 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1624 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1625 }
1626 tx_flags = np->tx_flags;
1627 offset += bcnt;
1628 size -= bcnt;
1629 } while (size);
1630
1631 /* setup the fragments */
1632 for (i = 0; i < fragments; i++) {
1633 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1634 u32 size = frag->size;
1635 offset = 0;
1636
1637 do {
1638 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1639 nr = (nr + 1) % np->tx_ring_size;
1640
1641 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1642 PCI_DMA_TODEVICE);
1643 np->tx_dma_len[nr] = bcnt;
1644
1645 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1646 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]);
1647 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1648 } else {
1649 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1650 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1651 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1652 }
1653 offset += bcnt;
1654 size -= bcnt;
1655 } while (size);
1656 }
1657
1658 /* set last fragment flag */
1659 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1660 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1661 } else {
1662 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra);
1663 }
1664
1665 np->tx_skbuff[nr] = skb;
1666
1667 #ifdef NETIF_F_TSO
1668 if (skb_is_gso(skb))
1669 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1670 else
1671 #endif
1672 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1673 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1674
1675 /* vlan tag */
1676 if (np->vlangrp && vlan_tx_tag_present(skb)) {
1677 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1678 }
1679
1680 /* set tx flags */
1681 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1682 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1683 } else {
1684 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan);
1685 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1686 }
1687
1688 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1689 dev->name, np->next_tx, entries, tx_flags_extra);
1690 {
1691 int j;
1692 for (j=0; j<64; j++) {
1693 if ((j%16) == 0)
1694 dprintk("\n%03x:", j);
1695 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1696 }
1697 dprintk("\n");
1698 }
1699
1700 np->next_tx += entries;
1701
1702 dev->trans_start = jiffies;
1703 spin_unlock_irq(&np->lock);
1704 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1705 pci_push(get_hwbase(dev));
1706 return NETDEV_TX_OK;
1707 }
1708
1709 /*
1710 * nv_tx_done: check for completed packets, release the skbs.
1711 *
1712 * Caller must own np->lock.
1713 */
1714 static void nv_tx_done(struct net_device *dev)
1715 {
1716 struct fe_priv *np = netdev_priv(dev);
1717 u32 flags;
1718 unsigned int i;
1719 struct sk_buff *skb;
1720
1721 while (np->nic_tx != np->next_tx) {
1722 i = np->nic_tx % np->tx_ring_size;
1723
1724 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1725 flags = le32_to_cpu(np->tx_ring.orig[i].flaglen);
1726 else
1727 flags = le32_to_cpu(np->tx_ring.ex[i].flaglen);
1728
1729 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1730 dev->name, np->nic_tx, flags);
1731 if (flags & NV_TX_VALID)
1732 break;
1733 if (np->desc_ver == DESC_VER_1) {
1734 if (flags & NV_TX_LASTPACKET) {
1735 skb = np->tx_skbuff[i];
1736 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1737 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1738 if (flags & NV_TX_UNDERFLOW)
1739 np->stats.tx_fifo_errors++;
1740 if (flags & NV_TX_CARRIERLOST)
1741 np->stats.tx_carrier_errors++;
1742 np->stats.tx_errors++;
1743 } else {
1744 np->stats.tx_packets++;
1745 np->stats.tx_bytes += skb->len;
1746 }
1747 }
1748 } else {
1749 if (flags & NV_TX2_LASTPACKET) {
1750 skb = np->tx_skbuff[i];
1751 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1752 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1753 if (flags & NV_TX2_UNDERFLOW)
1754 np->stats.tx_fifo_errors++;
1755 if (flags & NV_TX2_CARRIERLOST)
1756 np->stats.tx_carrier_errors++;
1757 np->stats.tx_errors++;
1758 } else {
1759 np->stats.tx_packets++;
1760 np->stats.tx_bytes += skb->len;
1761 }
1762 }
1763 }
1764 nv_release_txskb(dev, i);
1765 np->nic_tx++;
1766 }
1767 if (np->next_tx - np->nic_tx < np->tx_limit_start)
1768 netif_wake_queue(dev);
1769 }
1770
1771 /*
1772 * nv_tx_timeout: dev->tx_timeout function
1773 * Called with netif_tx_lock held.
1774 */
1775 static void nv_tx_timeout(struct net_device *dev)
1776 {
1777 struct fe_priv *np = netdev_priv(dev);
1778 u8 __iomem *base = get_hwbase(dev);
1779 u32 status;
1780
1781 if (np->msi_flags & NV_MSI_X_ENABLED)
1782 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1783 else
1784 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1785
1786 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1787
1788 {
1789 int i;
1790
1791 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1792 dev->name, (unsigned long)np->ring_addr,
1793 np->next_tx, np->nic_tx);
1794 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1795 for (i=0;i<=np->register_size;i+= 32) {
1796 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1797 i,
1798 readl(base + i + 0), readl(base + i + 4),
1799 readl(base + i + 8), readl(base + i + 12),
1800 readl(base + i + 16), readl(base + i + 20),
1801 readl(base + i + 24), readl(base + i + 28));
1802 }
1803 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1804 for (i=0;i<np->tx_ring_size;i+= 4) {
1805 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1806 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1807 i,
1808 le32_to_cpu(np->tx_ring.orig[i].buf),
1809 le32_to_cpu(np->tx_ring.orig[i].flaglen),
1810 le32_to_cpu(np->tx_ring.orig[i+1].buf),
1811 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1812 le32_to_cpu(np->tx_ring.orig[i+2].buf),
1813 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1814 le32_to_cpu(np->tx_ring.orig[i+3].buf),
1815 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1816 } else {
1817 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1818 i,
1819 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1820 le32_to_cpu(np->tx_ring.ex[i].buflow),
1821 le32_to_cpu(np->tx_ring.ex[i].flaglen),
1822 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1823 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1824 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1825 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1826 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1827 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1828 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1829 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1830 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1831 }
1832 }
1833 }
1834
1835 spin_lock_irq(&np->lock);
1836
1837 /* 1) stop tx engine */
1838 nv_stop_tx(dev);
1839
1840 /* 2) check that the packets were not sent already: */
1841 nv_tx_done(dev);
1842
1843 /* 3) if there are dead entries: clear everything */
1844 if (np->next_tx != np->nic_tx) {
1845 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1846 nv_drain_tx(dev);
1847 np->next_tx = np->nic_tx = 0;
1848 setup_hw_rings(dev, NV_SETUP_TX_RING);
1849 netif_wake_queue(dev);
1850 }
1851
1852 /* 4) restart tx engine */
1853 nv_start_tx(dev);
1854 spin_unlock_irq(&np->lock);
1855 }
1856
1857 /*
1858 * Called when the nic notices a mismatch between the actual data len on the
1859 * wire and the len indicated in the 802 header
1860 */
1861 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1862 {
1863 int hdrlen; /* length of the 802 header */
1864 int protolen; /* length as stored in the proto field */
1865
1866 /* 1) calculate len according to header */
1867 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1868 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1869 hdrlen = VLAN_HLEN;
1870 } else {
1871 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1872 hdrlen = ETH_HLEN;
1873 }
1874 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1875 dev->name, datalen, protolen, hdrlen);
1876 if (protolen > ETH_DATA_LEN)
1877 return datalen; /* Value in proto field not a len, no checks possible */
1878
1879 protolen += hdrlen;
1880 /* consistency checks: */
1881 if (datalen > ETH_ZLEN) {
1882 if (datalen >= protolen) {
1883 /* more data on wire than in 802 header, trim of
1884 * additional data.
1885 */
1886 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1887 dev->name, protolen);
1888 return protolen;
1889 } else {
1890 /* less data on wire than mentioned in header.
1891 * Discard the packet.
1892 */
1893 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1894 dev->name);
1895 return -1;
1896 }
1897 } else {
1898 /* short packet. Accept only if 802 values are also short */
1899 if (protolen > ETH_ZLEN) {
1900 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1901 dev->name);
1902 return -1;
1903 }
1904 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1905 dev->name, datalen);
1906 return datalen;
1907 }
1908 }
1909
1910 static int nv_rx_process(struct net_device *dev, int limit)
1911 {
1912 struct fe_priv *np = netdev_priv(dev);
1913 u32 flags;
1914 u32 vlanflags = 0;
1915 int count;
1916
1917 for (count = 0; count < limit; ++count) {
1918 struct sk_buff *skb;
1919 int len;
1920 int i;
1921 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1922 break; /* we scanned the whole ring - do not continue */
1923
1924 i = np->cur_rx % np->rx_ring_size;
1925 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1926 flags = le32_to_cpu(np->rx_ring.orig[i].flaglen);
1927 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1928 } else {
1929 flags = le32_to_cpu(np->rx_ring.ex[i].flaglen);
1930 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1931 vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow);
1932 }
1933
1934 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1935 dev->name, np->cur_rx, flags);
1936
1937 if (flags & NV_RX_AVAIL)
1938 break; /* still owned by hardware, */
1939
1940 /*
1941 * the packet is for us - immediately tear down the pci mapping.
1942 * TODO: check if a prefetch of the first cacheline improves
1943 * the performance.
1944 */
1945 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1946 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1947 PCI_DMA_FROMDEVICE);
1948
1949 {
1950 int j;
1951 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1952 for (j=0; j<64; j++) {
1953 if ((j%16) == 0)
1954 dprintk("\n%03x:", j);
1955 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1956 }
1957 dprintk("\n");
1958 }
1959 /* look at what we actually got: */
1960 if (np->desc_ver == DESC_VER_1) {
1961 if (!(flags & NV_RX_DESCRIPTORVALID))
1962 goto next_pkt;
1963
1964 if (flags & NV_RX_ERROR) {
1965 if (flags & NV_RX_MISSEDFRAME) {
1966 np->stats.rx_missed_errors++;
1967 np->stats.rx_errors++;
1968 goto next_pkt;
1969 }
1970 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1971 np->stats.rx_errors++;
1972 goto next_pkt;
1973 }
1974 if (flags & NV_RX_CRCERR) {
1975 np->stats.rx_crc_errors++;
1976 np->stats.rx_errors++;
1977 goto next_pkt;
1978 }
1979 if (flags & NV_RX_OVERFLOW) {
1980 np->stats.rx_over_errors++;
1981 np->stats.rx_errors++;
1982 goto next_pkt;
1983 }
1984 if (flags & NV_RX_ERROR4) {
1985 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1986 if (len < 0) {
1987 np->stats.rx_errors++;
1988 goto next_pkt;
1989 }
1990 }
1991 /* framing errors are soft errors. */
1992 if (flags & NV_RX_FRAMINGERR) {
1993 if (flags & NV_RX_SUBSTRACT1) {
1994 len--;
1995 }
1996 }
1997 }
1998 } else {
1999 if (!(flags & NV_RX2_DESCRIPTORVALID))
2000 goto next_pkt;
2001
2002 if (flags & NV_RX2_ERROR) {
2003 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
2004 np->stats.rx_errors++;
2005 goto next_pkt;
2006 }
2007 if (flags & NV_RX2_CRCERR) {
2008 np->stats.rx_crc_errors++;
2009 np->stats.rx_errors++;
2010 goto next_pkt;
2011 }
2012 if (flags & NV_RX2_OVERFLOW) {
2013 np->stats.rx_over_errors++;
2014 np->stats.rx_errors++;
2015 goto next_pkt;
2016 }
2017 if (flags & NV_RX2_ERROR4) {
2018 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
2019 if (len < 0) {
2020 np->stats.rx_errors++;
2021 goto next_pkt;
2022 }
2023 }
2024 /* framing errors are soft errors */
2025 if (flags & NV_RX2_FRAMINGERR) {
2026 if (flags & NV_RX2_SUBSTRACT1) {
2027 len--;
2028 }
2029 }
2030 }
2031 if (np->rx_csum) {
2032 flags &= NV_RX2_CHECKSUMMASK;
2033 if (flags == NV_RX2_CHECKSUMOK1 ||
2034 flags == NV_RX2_CHECKSUMOK2 ||
2035 flags == NV_RX2_CHECKSUMOK3) {
2036 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
2037 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
2038 } else {
2039 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
2040 }
2041 }
2042 }
2043 /* got a valid packet - forward it to the network core */
2044 skb = np->rx_skbuff[i];
2045 np->rx_skbuff[i] = NULL;
2046
2047 skb_put(skb, len);
2048 skb->protocol = eth_type_trans(skb, dev);
2049 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
2050 dev->name, np->cur_rx, len, skb->protocol);
2051 #ifdef CONFIG_FORCEDETH_NAPI
2052 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2053 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2054 vlanflags & NV_RX3_VLAN_TAG_MASK);
2055 else
2056 netif_receive_skb(skb);
2057 #else
2058 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2059 vlan_hwaccel_rx(skb, np->vlangrp,
2060 vlanflags & NV_RX3_VLAN_TAG_MASK);
2061 else
2062 netif_rx(skb);
2063 #endif
2064 dev->last_rx = jiffies;
2065 np->stats.rx_packets++;
2066 np->stats.rx_bytes += len;
2067 next_pkt:
2068 np->cur_rx++;
2069 }
2070
2071 return count;
2072 }
2073
2074 static void set_bufsize(struct net_device *dev)
2075 {
2076 struct fe_priv *np = netdev_priv(dev);
2077
2078 if (dev->mtu <= ETH_DATA_LEN)
2079 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2080 else
2081 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2082 }
2083
2084 /*
2085 * nv_change_mtu: dev->change_mtu function
2086 * Called with dev_base_lock held for read.
2087 */
2088 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2089 {
2090 struct fe_priv *np = netdev_priv(dev);
2091 int old_mtu;
2092
2093 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2094 return -EINVAL;
2095
2096 old_mtu = dev->mtu;
2097 dev->mtu = new_mtu;
2098
2099 /* return early if the buffer sizes will not change */
2100 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2101 return 0;
2102 if (old_mtu == new_mtu)
2103 return 0;
2104
2105 /* synchronized against open : rtnl_lock() held by caller */
2106 if (netif_running(dev)) {
2107 u8 __iomem *base = get_hwbase(dev);
2108 /*
2109 * It seems that the nic preloads valid ring entries into an
2110 * internal buffer. The procedure for flushing everything is
2111 * guessed, there is probably a simpler approach.
2112 * Changing the MTU is a rare event, it shouldn't matter.
2113 */
2114 nv_disable_irq(dev);
2115 netif_tx_lock_bh(dev);
2116 spin_lock(&np->lock);
2117 /* stop engines */
2118 nv_stop_rx(dev);
2119 nv_stop_tx(dev);
2120 nv_txrx_reset(dev);
2121 /* drain rx queue */
2122 nv_drain_rx(dev);
2123 nv_drain_tx(dev);
2124 /* reinit driver view of the rx queue */
2125 set_bufsize(dev);
2126 if (nv_init_ring(dev)) {
2127 if (!np->in_shutdown)
2128 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2129 }
2130 /* reinit nic view of the rx queue */
2131 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2132 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2133 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2134 base + NvRegRingSizes);
2135 pci_push(base);
2136 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2137 pci_push(base);
2138
2139 /* restart rx engine */
2140 nv_start_rx(dev);
2141 nv_start_tx(dev);
2142 spin_unlock(&np->lock);
2143 netif_tx_unlock_bh(dev);
2144 nv_enable_irq(dev);
2145 }
2146 return 0;
2147 }
2148
2149 static void nv_copy_mac_to_hw(struct net_device *dev)
2150 {
2151 u8 __iomem *base = get_hwbase(dev);
2152 u32 mac[2];
2153
2154 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2155 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2156 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2157
2158 writel(mac[0], base + NvRegMacAddrA);
2159 writel(mac[1], base + NvRegMacAddrB);
2160 }
2161
2162 /*
2163 * nv_set_mac_address: dev->set_mac_address function
2164 * Called with rtnl_lock() held.
2165 */
2166 static int nv_set_mac_address(struct net_device *dev, void *addr)
2167 {
2168 struct fe_priv *np = netdev_priv(dev);
2169 struct sockaddr *macaddr = (struct sockaddr*)addr;
2170
2171 if (!is_valid_ether_addr(macaddr->sa_data))
2172 return -EADDRNOTAVAIL;
2173
2174 /* synchronized against open : rtnl_lock() held by caller */
2175 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2176
2177 if (netif_running(dev)) {
2178 netif_tx_lock_bh(dev);
2179 spin_lock_irq(&np->lock);
2180
2181 /* stop rx engine */
2182 nv_stop_rx(dev);
2183
2184 /* set mac address */
2185 nv_copy_mac_to_hw(dev);
2186
2187 /* restart rx engine */
2188 nv_start_rx(dev);
2189 spin_unlock_irq(&np->lock);
2190 netif_tx_unlock_bh(dev);
2191 } else {
2192 nv_copy_mac_to_hw(dev);
2193 }
2194 return 0;
2195 }
2196
2197 /*
2198 * nv_set_multicast: dev->set_multicast function
2199 * Called with netif_tx_lock held.
2200 */
2201 static void nv_set_multicast(struct net_device *dev)
2202 {
2203 struct fe_priv *np = netdev_priv(dev);
2204 u8 __iomem *base = get_hwbase(dev);
2205 u32 addr[2];
2206 u32 mask[2];
2207 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2208
2209 memset(addr, 0, sizeof(addr));
2210 memset(mask, 0, sizeof(mask));
2211
2212 if (dev->flags & IFF_PROMISC) {
2213 pff |= NVREG_PFF_PROMISC;
2214 } else {
2215 pff |= NVREG_PFF_MYADDR;
2216
2217 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2218 u32 alwaysOff[2];
2219 u32 alwaysOn[2];
2220
2221 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2222 if (dev->flags & IFF_ALLMULTI) {
2223 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2224 } else {
2225 struct dev_mc_list *walk;
2226
2227 walk = dev->mc_list;
2228 while (walk != NULL) {
2229 u32 a, b;
2230 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2231 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2232 alwaysOn[0] &= a;
2233 alwaysOff[0] &= ~a;
2234 alwaysOn[1] &= b;
2235 alwaysOff[1] &= ~b;
2236 walk = walk->next;
2237 }
2238 }
2239 addr[0] = alwaysOn[0];
2240 addr[1] = alwaysOn[1];
2241 mask[0] = alwaysOn[0] | alwaysOff[0];
2242 mask[1] = alwaysOn[1] | alwaysOff[1];
2243 }
2244 }
2245 addr[0] |= NVREG_MCASTADDRA_FORCE;
2246 pff |= NVREG_PFF_ALWAYS;
2247 spin_lock_irq(&np->lock);
2248 nv_stop_rx(dev);
2249 writel(addr[0], base + NvRegMulticastAddrA);
2250 writel(addr[1], base + NvRegMulticastAddrB);
2251 writel(mask[0], base + NvRegMulticastMaskA);
2252 writel(mask[1], base + NvRegMulticastMaskB);
2253 writel(pff, base + NvRegPacketFilterFlags);
2254 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2255 dev->name);
2256 nv_start_rx(dev);
2257 spin_unlock_irq(&np->lock);
2258 }
2259
2260 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2261 {
2262 struct fe_priv *np = netdev_priv(dev);
2263 u8 __iomem *base = get_hwbase(dev);
2264
2265 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2266
2267 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2268 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2269 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2270 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2271 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2272 } else {
2273 writel(pff, base + NvRegPacketFilterFlags);
2274 }
2275 }
2276 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2277 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2278 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2279 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2280 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2281 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2282 } else {
2283 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2284 writel(regmisc, base + NvRegMisc1);
2285 }
2286 }
2287 }
2288
2289 /**
2290 * nv_update_linkspeed: Setup the MAC according to the link partner
2291 * @dev: Network device to be configured
2292 *
2293 * The function queries the PHY and checks if there is a link partner.
2294 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2295 * set to 10 MBit HD.
2296 *
2297 * The function returns 0 if there is no link partner and 1 if there is
2298 * a good link partner.
2299 */
2300 static int nv_update_linkspeed(struct net_device *dev)
2301 {
2302 struct fe_priv *np = netdev_priv(dev);
2303 u8 __iomem *base = get_hwbase(dev);
2304 int adv = 0;
2305 int lpa = 0;
2306 int adv_lpa, adv_pause, lpa_pause;
2307 int newls = np->linkspeed;
2308 int newdup = np->duplex;
2309 int mii_status;
2310 int retval = 0;
2311 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2312
2313 /* BMSR_LSTATUS is latched, read it twice:
2314 * we want the current value.
2315 */
2316 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2317 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2318
2319 if (!(mii_status & BMSR_LSTATUS)) {
2320 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2321 dev->name);
2322 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2323 newdup = 0;
2324 retval = 0;
2325 goto set_speed;
2326 }
2327
2328 if (np->autoneg == 0) {
2329 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2330 dev->name, np->fixed_mode);
2331 if (np->fixed_mode & LPA_100FULL) {
2332 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2333 newdup = 1;
2334 } else if (np->fixed_mode & LPA_100HALF) {
2335 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2336 newdup = 0;
2337 } else if (np->fixed_mode & LPA_10FULL) {
2338 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2339 newdup = 1;
2340 } else {
2341 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2342 newdup = 0;
2343 }
2344 retval = 1;
2345 goto set_speed;
2346 }
2347 /* check auto negotiation is complete */
2348 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2349 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2350 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2351 newdup = 0;
2352 retval = 0;
2353 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2354 goto set_speed;
2355 }
2356
2357 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2358 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2359 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2360 dev->name, adv, lpa);
2361
2362 retval = 1;
2363 if (np->gigabit == PHY_GIGABIT) {
2364 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2365 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2366
2367 if ((control_1000 & ADVERTISE_1000FULL) &&
2368 (status_1000 & LPA_1000FULL)) {
2369 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2370 dev->name);
2371 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2372 newdup = 1;
2373 goto set_speed;
2374 }
2375 }
2376
2377 /* FIXME: handle parallel detection properly */
2378 adv_lpa = lpa & adv;
2379 if (adv_lpa & LPA_100FULL) {
2380 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2381 newdup = 1;
2382 } else if (adv_lpa & LPA_100HALF) {
2383 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2384 newdup = 0;
2385 } else if (adv_lpa & LPA_10FULL) {
2386 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2387 newdup = 1;
2388 } else if (adv_lpa & LPA_10HALF) {
2389 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2390 newdup = 0;
2391 } else {
2392 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2393 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2394 newdup = 0;
2395 }
2396
2397 set_speed:
2398 if (np->duplex == newdup && np->linkspeed == newls)
2399 return retval;
2400
2401 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2402 dev->name, np->linkspeed, np->duplex, newls, newdup);
2403
2404 np->duplex = newdup;
2405 np->linkspeed = newls;
2406
2407 if (np->gigabit == PHY_GIGABIT) {
2408 phyreg = readl(base + NvRegRandomSeed);
2409 phyreg &= ~(0x3FF00);
2410 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2411 phyreg |= NVREG_RNDSEED_FORCE3;
2412 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2413 phyreg |= NVREG_RNDSEED_FORCE2;
2414 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2415 phyreg |= NVREG_RNDSEED_FORCE;
2416 writel(phyreg, base + NvRegRandomSeed);
2417 }
2418
2419 phyreg = readl(base + NvRegPhyInterface);
2420 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2421 if (np->duplex == 0)
2422 phyreg |= PHY_HALF;
2423 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2424 phyreg |= PHY_100;
2425 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2426 phyreg |= PHY_1000;
2427 writel(phyreg, base + NvRegPhyInterface);
2428
2429 if (phyreg & PHY_RGMII) {
2430 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2431 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2432 else
2433 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2434 } else {
2435 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2436 }
2437 writel(txreg, base + NvRegTxDeferral);
2438
2439 if (np->desc_ver == DESC_VER_1) {
2440 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2441 } else {
2442 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2443 txreg = NVREG_TX_WM_DESC2_3_1000;
2444 else
2445 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2446 }
2447 writel(txreg, base + NvRegTxWatermark);
2448
2449 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2450 base + NvRegMisc1);
2451 pci_push(base);
2452 writel(np->linkspeed, base + NvRegLinkSpeed);
2453 pci_push(base);
2454
2455 pause_flags = 0;
2456 /* setup pause frame */
2457 if (np->duplex != 0) {
2458 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2459 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2460 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2461
2462 switch (adv_pause) {
2463 case ADVERTISE_PAUSE_CAP:
2464 if (lpa_pause & LPA_PAUSE_CAP) {
2465 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2466 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2467 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2468 }
2469 break;
2470 case ADVERTISE_PAUSE_ASYM:
2471 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2472 {
2473 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2474 }
2475 break;
2476 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2477 if (lpa_pause & LPA_PAUSE_CAP)
2478 {
2479 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2480 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2481 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2482 }
2483 if (lpa_pause == LPA_PAUSE_ASYM)
2484 {
2485 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2486 }
2487 break;
2488 }
2489 } else {
2490 pause_flags = np->pause_flags;
2491 }
2492 }
2493 nv_update_pause(dev, pause_flags);
2494
2495 return retval;
2496 }
2497
2498 static void nv_linkchange(struct net_device *dev)
2499 {
2500 if (nv_update_linkspeed(dev)) {
2501 if (!netif_carrier_ok(dev)) {
2502 netif_carrier_on(dev);
2503 printk(KERN_INFO "%s: link up.\n", dev->name);
2504 nv_start_rx(dev);
2505 }
2506 } else {
2507 if (netif_carrier_ok(dev)) {
2508 netif_carrier_off(dev);
2509 printk(KERN_INFO "%s: link down.\n", dev->name);
2510 nv_stop_rx(dev);
2511 }
2512 }
2513 }
2514
2515 static void nv_link_irq(struct net_device *dev)
2516 {
2517 u8 __iomem *base = get_hwbase(dev);
2518 u32 miistat;
2519
2520 miistat = readl(base + NvRegMIIStatus);
2521 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2522 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2523
2524 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2525 nv_linkchange(dev);
2526 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2527 }
2528
2529 static irqreturn_t nv_nic_irq(int foo, void *data)
2530 {
2531 struct net_device *dev = (struct net_device *) data;
2532 struct fe_priv *np = netdev_priv(dev);
2533 u8 __iomem *base = get_hwbase(dev);
2534 u32 events;
2535 int i;
2536
2537 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2538
2539 for (i=0; ; i++) {
2540 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2541 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2542 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2543 } else {
2544 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2545 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2546 }
2547 pci_push(base);
2548 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2549 if (!(events & np->irqmask))
2550 break;
2551
2552 spin_lock(&np->lock);
2553 nv_tx_done(dev);
2554 spin_unlock(&np->lock);
2555
2556 if (events & NVREG_IRQ_LINK) {
2557 spin_lock(&np->lock);
2558 nv_link_irq(dev);
2559 spin_unlock(&np->lock);
2560 }
2561 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2562 spin_lock(&np->lock);
2563 nv_linkchange(dev);
2564 spin_unlock(&np->lock);
2565 np->link_timeout = jiffies + LINK_TIMEOUT;
2566 }
2567 if (events & (NVREG_IRQ_TX_ERR)) {
2568 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2569 dev->name, events);
2570 }
2571 if (events & (NVREG_IRQ_UNKNOWN)) {
2572 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2573 dev->name, events);
2574 }
2575 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2576 spin_lock(&np->lock);
2577 /* disable interrupts on the nic */
2578 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2579 writel(0, base + NvRegIrqMask);
2580 else
2581 writel(np->irqmask, base + NvRegIrqMask);
2582 pci_push(base);
2583
2584 if (!np->in_shutdown) {
2585 np->nic_poll_irq = np->irqmask;
2586 np->recover_error = 1;
2587 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2588 }
2589 spin_unlock(&np->lock);
2590 break;
2591 }
2592 #ifdef CONFIG_FORCEDETH_NAPI
2593 if (events & NVREG_IRQ_RX_ALL) {
2594 netif_rx_schedule(dev);
2595
2596 /* Disable furthur receive irq's */
2597 spin_lock(&np->lock);
2598 np->irqmask &= ~NVREG_IRQ_RX_ALL;
2599
2600 if (np->msi_flags & NV_MSI_X_ENABLED)
2601 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2602 else
2603 writel(np->irqmask, base + NvRegIrqMask);
2604 spin_unlock(&np->lock);
2605 }
2606 #else
2607 nv_rx_process(dev, dev->weight);
2608 if (nv_alloc_rx(dev)) {
2609 spin_lock(&np->lock);
2610 if (!np->in_shutdown)
2611 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2612 spin_unlock(&np->lock);
2613 }
2614 #endif
2615 if (i > max_interrupt_work) {
2616 spin_lock(&np->lock);
2617 /* disable interrupts on the nic */
2618 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2619 writel(0, base + NvRegIrqMask);
2620 else
2621 writel(np->irqmask, base + NvRegIrqMask);
2622 pci_push(base);
2623
2624 if (!np->in_shutdown) {
2625 np->nic_poll_irq = np->irqmask;
2626 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2627 }
2628 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2629 spin_unlock(&np->lock);
2630 break;
2631 }
2632
2633 }
2634 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2635
2636 return IRQ_RETVAL(i);
2637 }
2638
2639 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2640 {
2641 struct net_device *dev = (struct net_device *) data;
2642 struct fe_priv *np = netdev_priv(dev);
2643 u8 __iomem *base = get_hwbase(dev);
2644 u32 events;
2645 int i;
2646 unsigned long flags;
2647
2648 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2649
2650 for (i=0; ; i++) {
2651 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2652 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2653 pci_push(base);
2654 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2655 if (!(events & np->irqmask))
2656 break;
2657
2658 spin_lock_irqsave(&np->lock, flags);
2659 nv_tx_done(dev);
2660 spin_unlock_irqrestore(&np->lock, flags);
2661
2662 if (events & (NVREG_IRQ_TX_ERR)) {
2663 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2664 dev->name, events);
2665 }
2666 if (i > max_interrupt_work) {
2667 spin_lock_irqsave(&np->lock, flags);
2668 /* disable interrupts on the nic */
2669 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2670 pci_push(base);
2671
2672 if (!np->in_shutdown) {
2673 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2674 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2675 }
2676 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2677 spin_unlock_irqrestore(&np->lock, flags);
2678 break;
2679 }
2680
2681 }
2682 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2683
2684 return IRQ_RETVAL(i);
2685 }
2686
2687 #ifdef CONFIG_FORCEDETH_NAPI
2688 static int nv_napi_poll(struct net_device *dev, int *budget)
2689 {
2690 int pkts, limit = min(*budget, dev->quota);
2691 struct fe_priv *np = netdev_priv(dev);
2692 u8 __iomem *base = get_hwbase(dev);
2693 unsigned long flags;
2694
2695 pkts = nv_rx_process(dev, limit);
2696
2697 if (nv_alloc_rx(dev)) {
2698 spin_lock_irqsave(&np->lock, flags);
2699 if (!np->in_shutdown)
2700 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2701 spin_unlock_irqrestore(&np->lock, flags);
2702 }
2703
2704 if (pkts < limit) {
2705 /* all done, no more packets present */
2706 netif_rx_complete(dev);
2707
2708 /* re-enable receive interrupts */
2709 spin_lock_irqsave(&np->lock, flags);
2710
2711 np->irqmask |= NVREG_IRQ_RX_ALL;
2712 if (np->msi_flags & NV_MSI_X_ENABLED)
2713 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2714 else
2715 writel(np->irqmask, base + NvRegIrqMask);
2716
2717 spin_unlock_irqrestore(&np->lock, flags);
2718 return 0;
2719 } else {
2720 /* used up our quantum, so reschedule */
2721 dev->quota -= pkts;
2722 *budget -= pkts;
2723 return 1;
2724 }
2725 }
2726 #endif
2727
2728 #ifdef CONFIG_FORCEDETH_NAPI
2729 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2730 {
2731 struct net_device *dev = (struct net_device *) data;
2732 u8 __iomem *base = get_hwbase(dev);
2733 u32 events;
2734
2735 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2736 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2737
2738 if (events) {
2739 netif_rx_schedule(dev);
2740 /* disable receive interrupts on the nic */
2741 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2742 pci_push(base);
2743 }
2744 return IRQ_HANDLED;
2745 }
2746 #else
2747 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2748 {
2749 struct net_device *dev = (struct net_device *) data;
2750 struct fe_priv *np = netdev_priv(dev);
2751 u8 __iomem *base = get_hwbase(dev);
2752 u32 events;
2753 int i;
2754 unsigned long flags;
2755
2756 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2757
2758 for (i=0; ; i++) {
2759 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2760 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2761 pci_push(base);
2762 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2763 if (!(events & np->irqmask))
2764 break;
2765
2766 nv_rx_process(dev, dev->weight);
2767 if (nv_alloc_rx(dev)) {
2768 spin_lock_irqsave(&np->lock, flags);
2769 if (!np->in_shutdown)
2770 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2771 spin_unlock_irqrestore(&np->lock, flags);
2772 }
2773
2774 if (i > max_interrupt_work) {
2775 spin_lock_irqsave(&np->lock, flags);
2776 /* disable interrupts on the nic */
2777 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2778 pci_push(base);
2779
2780 if (!np->in_shutdown) {
2781 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2782 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2783 }
2784 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2785 spin_unlock_irqrestore(&np->lock, flags);
2786 break;
2787 }
2788 }
2789 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2790
2791 return IRQ_RETVAL(i);
2792 }
2793 #endif
2794
2795 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2796 {
2797 struct net_device *dev = (struct net_device *) data;
2798 struct fe_priv *np = netdev_priv(dev);
2799 u8 __iomem *base = get_hwbase(dev);
2800 u32 events;
2801 int i;
2802 unsigned long flags;
2803
2804 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2805
2806 for (i=0; ; i++) {
2807 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2808 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2809 pci_push(base);
2810 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2811 if (!(events & np->irqmask))
2812 break;
2813
2814 if (events & NVREG_IRQ_LINK) {
2815 spin_lock_irqsave(&np->lock, flags);
2816 nv_link_irq(dev);
2817 spin_unlock_irqrestore(&np->lock, flags);
2818 }
2819 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2820 spin_lock_irqsave(&np->lock, flags);
2821 nv_linkchange(dev);
2822 spin_unlock_irqrestore(&np->lock, flags);
2823 np->link_timeout = jiffies + LINK_TIMEOUT;
2824 }
2825 if (events & NVREG_IRQ_RECOVER_ERROR) {
2826 spin_lock_irq(&np->lock);
2827 /* disable interrupts on the nic */
2828 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2829 pci_push(base);
2830
2831 if (!np->in_shutdown) {
2832 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2833 np->recover_error = 1;
2834 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2835 }
2836 spin_unlock_irq(&np->lock);
2837 break;
2838 }
2839 if (events & (NVREG_IRQ_UNKNOWN)) {
2840 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2841 dev->name, events);
2842 }
2843 if (i > max_interrupt_work) {
2844 spin_lock_irqsave(&np->lock, flags);
2845 /* disable interrupts on the nic */
2846 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2847 pci_push(base);
2848
2849 if (!np->in_shutdown) {
2850 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2851 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2852 }
2853 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2854 spin_unlock_irqrestore(&np->lock, flags);
2855 break;
2856 }
2857
2858 }
2859 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2860
2861 return IRQ_RETVAL(i);
2862 }
2863
2864 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2865 {
2866 struct net_device *dev = (struct net_device *) data;
2867 struct fe_priv *np = netdev_priv(dev);
2868 u8 __iomem *base = get_hwbase(dev);
2869 u32 events;
2870
2871 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2872
2873 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2874 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2875 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2876 } else {
2877 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2878 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2879 }
2880 pci_push(base);
2881 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2882 if (!(events & NVREG_IRQ_TIMER))
2883 return IRQ_RETVAL(0);
2884
2885 spin_lock(&np->lock);
2886 np->intr_test = 1;
2887 spin_unlock(&np->lock);
2888
2889 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2890
2891 return IRQ_RETVAL(1);
2892 }
2893
2894 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2895 {
2896 u8 __iomem *base = get_hwbase(dev);
2897 int i;
2898 u32 msixmap = 0;
2899
2900 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2901 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2902 * the remaining 8 interrupts.
2903 */
2904 for (i = 0; i < 8; i++) {
2905 if ((irqmask >> i) & 0x1) {
2906 msixmap |= vector << (i << 2);
2907 }
2908 }
2909 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2910
2911 msixmap = 0;
2912 for (i = 0; i < 8; i++) {
2913 if ((irqmask >> (i + 8)) & 0x1) {
2914 msixmap |= vector << (i << 2);
2915 }
2916 }
2917 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2918 }
2919
2920 static int nv_request_irq(struct net_device *dev, int intr_test)
2921 {
2922 struct fe_priv *np = get_nvpriv(dev);
2923 u8 __iomem *base = get_hwbase(dev);
2924 int ret = 1;
2925 int i;
2926
2927 if (np->msi_flags & NV_MSI_X_CAPABLE) {
2928 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2929 np->msi_x_entry[i].entry = i;
2930 }
2931 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2932 np->msi_flags |= NV_MSI_X_ENABLED;
2933 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2934 /* Request irq for rx handling */
2935 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2936 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2937 pci_disable_msix(np->pci_dev);
2938 np->msi_flags &= ~NV_MSI_X_ENABLED;
2939 goto out_err;
2940 }
2941 /* Request irq for tx handling */
2942 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2943 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2944 pci_disable_msix(np->pci_dev);
2945 np->msi_flags &= ~NV_MSI_X_ENABLED;
2946 goto out_free_rx;
2947 }
2948 /* Request irq for link and timer handling */
2949 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2950 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2951 pci_disable_msix(np->pci_dev);
2952 np->msi_flags &= ~NV_MSI_X_ENABLED;
2953 goto out_free_tx;
2954 }
2955 /* map interrupts to their respective vector */
2956 writel(0, base + NvRegMSIXMap0);
2957 writel(0, base + NvRegMSIXMap1);
2958 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2959 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2960 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2961 } else {
2962 /* Request irq for all interrupts */
2963 if ((!intr_test &&
2964 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2965 (intr_test &&
2966 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2967 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2968 pci_disable_msix(np->pci_dev);
2969 np->msi_flags &= ~NV_MSI_X_ENABLED;
2970 goto out_err;
2971 }
2972
2973 /* map interrupts to vector 0 */
2974 writel(0, base + NvRegMSIXMap0);
2975 writel(0, base + NvRegMSIXMap1);
2976 }
2977 }
2978 }
2979 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2980 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2981 np->msi_flags |= NV_MSI_ENABLED;
2982 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2983 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2984 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2985 pci_disable_msi(np->pci_dev);
2986 np->msi_flags &= ~NV_MSI_ENABLED;
2987 goto out_err;
2988 }
2989
2990 /* map interrupts to vector 0 */
2991 writel(0, base + NvRegMSIMap0);
2992 writel(0, base + NvRegMSIMap1);
2993 /* enable msi vector 0 */
2994 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2995 }
2996 }
2997 if (ret != 0) {
2998 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2999 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
3000 goto out_err;
3001
3002 }
3003
3004 return 0;
3005 out_free_tx:
3006 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3007 out_free_rx:
3008 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3009 out_err:
3010 return 1;
3011 }
3012
3013 static void nv_free_irq(struct net_device *dev)
3014 {
3015 struct fe_priv *np = get_nvpriv(dev);
3016 int i;
3017
3018 if (np->msi_flags & NV_MSI_X_ENABLED) {
3019 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3020 free_irq(np->msi_x_entry[i].vector, dev);
3021 }
3022 pci_disable_msix(np->pci_dev);
3023 np->msi_flags &= ~NV_MSI_X_ENABLED;
3024 } else {
3025 free_irq(np->pci_dev->irq, dev);
3026 if (np->msi_flags & NV_MSI_ENABLED) {
3027 pci_disable_msi(np->pci_dev);
3028 np->msi_flags &= ~NV_MSI_ENABLED;
3029 }
3030 }
3031 }
3032
3033 static void nv_do_nic_poll(unsigned long data)
3034 {
3035 struct net_device *dev = (struct net_device *) data;
3036 struct fe_priv *np = netdev_priv(dev);
3037 u8 __iomem *base = get_hwbase(dev);
3038 u32 mask = 0;
3039
3040 /*
3041 * First disable irq(s) and then
3042 * reenable interrupts on the nic, we have to do this before calling
3043 * nv_nic_irq because that may decide to do otherwise
3044 */
3045
3046 if (!using_multi_irqs(dev)) {
3047 if (np->msi_flags & NV_MSI_X_ENABLED)
3048 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3049 else
3050 disable_irq_lockdep(dev->irq);
3051 mask = np->irqmask;
3052 } else {
3053 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3054 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3055 mask |= NVREG_IRQ_RX_ALL;
3056 }
3057 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3058 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3059 mask |= NVREG_IRQ_TX_ALL;
3060 }
3061 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3062 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3063 mask |= NVREG_IRQ_OTHER;
3064 }
3065 }
3066 np->nic_poll_irq = 0;
3067
3068 if (np->recover_error) {
3069 np->recover_error = 0;
3070 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3071 if (netif_running(dev)) {
3072 netif_tx_lock_bh(dev);
3073 spin_lock(&np->lock);
3074 /* stop engines */
3075 nv_stop_rx(dev);
3076 nv_stop_tx(dev);
3077 nv_txrx_reset(dev);
3078 /* drain rx queue */
3079 nv_drain_rx(dev);
3080 nv_drain_tx(dev);
3081 /* reinit driver view of the rx queue */
3082 set_bufsize(dev);
3083 if (nv_init_ring(dev)) {
3084 if (!np->in_shutdown)
3085 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3086 }
3087 /* reinit nic view of the rx queue */
3088 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3089 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3090 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3091 base + NvRegRingSizes);
3092 pci_push(base);
3093 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3094 pci_push(base);
3095
3096 /* restart rx engine */
3097 nv_start_rx(dev);
3098 nv_start_tx(dev);
3099 spin_unlock(&np->lock);
3100 netif_tx_unlock_bh(dev);
3101 }
3102 }
3103
3104 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3105
3106 writel(mask, base + NvRegIrqMask);
3107 pci_push(base);
3108
3109 if (!using_multi_irqs(dev)) {
3110 nv_nic_irq(0, dev);
3111 if (np->msi_flags & NV_MSI_X_ENABLED)
3112 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3113 else
3114 enable_irq_lockdep(dev->irq);
3115 } else {
3116 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3117 nv_nic_irq_rx(0, dev);
3118 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3119 }
3120 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3121 nv_nic_irq_tx(0, dev);
3122 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3123 }
3124 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3125 nv_nic_irq_other(0, dev);
3126 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3127 }
3128 }
3129 }
3130
3131 #ifdef CONFIG_NET_POLL_CONTROLLER
3132 static void nv_poll_controller(struct net_device *dev)
3133 {
3134 nv_do_nic_poll((unsigned long) dev);
3135 }
3136 #endif
3137
3138 static void nv_do_stats_poll(unsigned long data)
3139 {
3140 struct net_device *dev = (struct net_device *) data;
3141 struct fe_priv *np = netdev_priv(dev);
3142 u8 __iomem *base = get_hwbase(dev);
3143
3144 np->estats.tx_bytes += readl(base + NvRegTxCnt);
3145 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
3146 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
3147 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
3148 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
3149 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
3150 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
3151 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
3152 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
3153 np->estats.tx_deferral += readl(base + NvRegTxDef);
3154 np->estats.tx_packets += readl(base + NvRegTxFrame);
3155 np->estats.tx_pause += readl(base + NvRegTxPause);
3156 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
3157 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
3158 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
3159 np->estats.rx_runt += readl(base + NvRegRxRunt);
3160 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
3161 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
3162 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
3163 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
3164 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
3165 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
3166 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
3167 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
3168 np->estats.rx_bytes += readl(base + NvRegRxCnt);
3169 np->estats.rx_pause += readl(base + NvRegRxPause);
3170 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
3171 np->estats.rx_packets =
3172 np->estats.rx_unicast +
3173 np->estats.rx_multicast +
3174 np->estats.rx_broadcast;
3175 np->estats.rx_errors_total =
3176 np->estats.rx_crc_errors +
3177 np->estats.rx_over_errors +
3178 np->estats.rx_frame_error +
3179 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
3180 np->estats.rx_late_collision +
3181 np->estats.rx_runt +
3182 np->estats.rx_frame_too_long;
3183
3184 if (!np->in_shutdown)
3185 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3186 }
3187
3188 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3189 {
3190 struct fe_priv *np = netdev_priv(dev);
3191 strcpy(info->driver, "forcedeth");
3192 strcpy(info->version, FORCEDETH_VERSION);
3193 strcpy(info->bus_info, pci_name(np->pci_dev));
3194 }
3195
3196 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3197 {
3198 struct fe_priv *np = netdev_priv(dev);
3199 wolinfo->supported = WAKE_MAGIC;
3200
3201 spin_lock_irq(&np->lock);
3202 if (np->wolenabled)
3203 wolinfo->wolopts = WAKE_MAGIC;
3204 spin_unlock_irq(&np->lock);
3205 }
3206
3207 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3208 {
3209 struct fe_priv *np = netdev_priv(dev);
3210 u8 __iomem *base = get_hwbase(dev);
3211 u32 flags = 0;
3212
3213 if (wolinfo->wolopts == 0) {
3214 np->wolenabled = 0;
3215 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3216 np->wolenabled = 1;
3217 flags = NVREG_WAKEUPFLAGS_ENABLE;
3218 }
3219 if (netif_running(dev)) {
3220 spin_lock_irq(&np->lock);
3221 writel(flags, base + NvRegWakeUpFlags);
3222 spin_unlock_irq(&np->lock);
3223 }
3224 return 0;
3225 }
3226
3227 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3228 {
3229 struct fe_priv *np = netdev_priv(dev);
3230 int adv;
3231
3232 spin_lock_irq(&np->lock);
3233 ecmd->port = PORT_MII;
3234 if (!netif_running(dev)) {
3235 /* We do not track link speed / duplex setting if the
3236 * interface is disabled. Force a link check */
3237 if (nv_update_linkspeed(dev)) {
3238 if (!netif_carrier_ok(dev))
3239 netif_carrier_on(dev);
3240 } else {
3241 if (netif_carrier_ok(dev))
3242 netif_carrier_off(dev);
3243 }
3244 }
3245
3246 if (netif_carrier_ok(dev)) {
3247 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3248 case NVREG_LINKSPEED_10:
3249 ecmd->speed = SPEED_10;
3250 break;
3251 case NVREG_LINKSPEED_100:
3252 ecmd->speed = SPEED_100;
3253 break;
3254 case NVREG_LINKSPEED_1000:
3255 ecmd->speed = SPEED_1000;
3256 break;
3257 }
3258 ecmd->duplex = DUPLEX_HALF;
3259 if (np->duplex)
3260 ecmd->duplex = DUPLEX_FULL;
3261 } else {
3262 ecmd->speed = -1;
3263 ecmd->duplex = -1;
3264 }
3265
3266 ecmd->autoneg = np->autoneg;
3267
3268 ecmd->advertising = ADVERTISED_MII;
3269 if (np->autoneg) {
3270 ecmd->advertising |= ADVERTISED_Autoneg;
3271 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3272 if (adv & ADVERTISE_10HALF)
3273 ecmd->advertising |= ADVERTISED_10baseT_Half;
3274 if (adv & ADVERTISE_10FULL)
3275 ecmd->advertising |= ADVERTISED_10baseT_Full;
3276 if (adv & ADVERTISE_100HALF)
3277 ecmd->advertising |= ADVERTISED_100baseT_Half;
3278 if (adv & ADVERTISE_100FULL)
3279 ecmd->advertising |= ADVERTISED_100baseT_Full;
3280 if (np->gigabit == PHY_GIGABIT) {
3281 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3282 if (adv & ADVERTISE_1000FULL)
3283 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3284 }
3285 }
3286 ecmd->supported = (SUPPORTED_Autoneg |
3287 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3288 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3289 SUPPORTED_MII);
3290 if (np->gigabit == PHY_GIGABIT)
3291 ecmd->supported |= SUPPORTED_1000baseT_Full;
3292
3293 ecmd->phy_address = np->phyaddr;
3294 ecmd->transceiver = XCVR_EXTERNAL;
3295
3296 /* ignore maxtxpkt, maxrxpkt for now */
3297 spin_unlock_irq(&np->lock);
3298 return 0;
3299 }
3300
3301 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3302 {
3303 struct fe_priv *np = netdev_priv(dev);
3304
3305 if (ecmd->port != PORT_MII)
3306 return -EINVAL;
3307 if (ecmd->transceiver != XCVR_EXTERNAL)
3308 return -EINVAL;
3309 if (ecmd->phy_address != np->phyaddr) {
3310 /* TODO: support switching between multiple phys. Should be
3311 * trivial, but not enabled due to lack of test hardware. */
3312 return -EINVAL;
3313 }
3314 if (ecmd->autoneg == AUTONEG_ENABLE) {
3315 u32 mask;
3316
3317 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3318 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3319 if (np->gigabit == PHY_GIGABIT)
3320 mask |= ADVERTISED_1000baseT_Full;
3321
3322 if ((ecmd->advertising & mask) == 0)
3323 return -EINVAL;
3324
3325 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3326 /* Note: autonegotiation disable, speed 1000 intentionally
3327 * forbidden - noone should need that. */
3328
3329 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3330 return -EINVAL;
3331 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3332 return -EINVAL;
3333 } else {
3334 return -EINVAL;
3335 }
3336
3337 netif_carrier_off(dev);
3338 if (netif_running(dev)) {
3339 nv_disable_irq(dev);
3340 netif_tx_lock_bh(dev);
3341 spin_lock(&np->lock);
3342 /* stop engines */
3343 nv_stop_rx(dev);
3344 nv_stop_tx(dev);
3345 spin_unlock(&np->lock);
3346 netif_tx_unlock_bh(dev);
3347 }
3348
3349 if (ecmd->autoneg == AUTONEG_ENABLE) {
3350 int adv, bmcr;
3351
3352 np->autoneg = 1;
3353
3354 /* advertise only what has been requested */
3355 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3356 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3357 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3358 adv |= ADVERTISE_10HALF;
3359 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3360 adv |= ADVERTISE_10FULL;
3361 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3362 adv |= ADVERTISE_100HALF;
3363 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3364 adv |= ADVERTISE_100FULL;
3365 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3366 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3367 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3368 adv |= ADVERTISE_PAUSE_ASYM;
3369 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3370
3371 if (np->gigabit == PHY_GIGABIT) {
3372 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3373 adv &= ~ADVERTISE_1000FULL;
3374 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3375 adv |= ADVERTISE_1000FULL;
3376 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3377 }
3378
3379 if (netif_running(dev))
3380 printk(KERN_INFO "%s: link down.\n", dev->name);
3381 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3382 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3383 bmcr |= BMCR_ANENABLE;
3384 /* reset the phy in order for settings to stick,
3385 * and cause autoneg to start */
3386 if (phy_reset(dev, bmcr)) {
3387 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3388 return -EINVAL;
3389 }
3390 } else {
3391 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3392 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3393 }
3394 } else {
3395 int adv, bmcr;
3396
3397 np->autoneg = 0;
3398
3399 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3400 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3401 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3402 adv |= ADVERTISE_10HALF;
3403 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3404 adv |= ADVERTISE_10FULL;
3405 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3406 adv |= ADVERTISE_100HALF;
3407 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3408 adv |= ADVERTISE_100FULL;
3409 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3410 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3411 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3412 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3413 }
3414 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3415 adv |= ADVERTISE_PAUSE_ASYM;
3416 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3417 }
3418 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3419 np->fixed_mode = adv;
3420
3421 if (np->gigabit == PHY_GIGABIT) {
3422 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3423 adv &= ~ADVERTISE_1000FULL;
3424 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3425 }
3426
3427 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3428 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3429 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3430 bmcr |= BMCR_FULLDPLX;
3431 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3432 bmcr |= BMCR_SPEED100;
3433 if (np->phy_oui == PHY_OUI_MARVELL) {
3434 /* reset the phy in order for forced mode settings to stick */
3435 if (phy_reset(dev, bmcr)) {
3436 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3437 return -EINVAL;
3438 }
3439 } else {
3440 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3441 if (netif_running(dev)) {
3442 /* Wait a bit and then reconfigure the nic. */
3443 udelay(10);
3444 nv_linkchange(dev);
3445 }
3446 }
3447 }
3448
3449 if (netif_running(dev)) {
3450 nv_start_rx(dev);
3451 nv_start_tx(dev);
3452 nv_enable_irq(dev);
3453 }
3454
3455 return 0;
3456 }
3457
3458 #define FORCEDETH_REGS_VER 1
3459
3460 static int nv_get_regs_len(struct net_device *dev)
3461 {
3462 struct fe_priv *np = netdev_priv(dev);
3463 return np->register_size;
3464 }
3465
3466 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3467 {
3468 struct fe_priv *np = netdev_priv(dev);
3469 u8 __iomem *base = get_hwbase(dev);
3470 u32 *rbuf = buf;
3471 int i;
3472
3473 regs->version = FORCEDETH_REGS_VER;
3474 spin_lock_irq(&np->lock);
3475 for (i = 0;i <= np->register_size/sizeof(u32); i++)
3476 rbuf[i] = readl(base + i*sizeof(u32));
3477 spin_unlock_irq(&np->lock);
3478 }
3479
3480 static int nv_nway_reset(struct net_device *dev)
3481 {
3482 struct fe_priv *np = netdev_priv(dev);
3483 int ret;
3484
3485 if (np->autoneg) {
3486 int bmcr;
3487
3488 netif_carrier_off(dev);
3489 if (netif_running(dev)) {
3490 nv_disable_irq(dev);
3491 netif_tx_lock_bh(dev);
3492 spin_lock(&np->lock);
3493 /* stop engines */
3494 nv_stop_rx(dev);
3495 nv_stop_tx(dev);
3496 spin_unlock(&np->lock);
3497 netif_tx_unlock_bh(dev);
3498 printk(KERN_INFO "%s: link down.\n", dev->name);
3499 }
3500
3501 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3502 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3503 bmcr |= BMCR_ANENABLE;
3504 /* reset the phy in order for settings to stick*/
3505 if (phy_reset(dev, bmcr)) {
3506 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3507 return -EINVAL;
3508 }
3509 } else {
3510 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3511 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3512 }
3513
3514 if (netif_running(dev)) {
3515 nv_start_rx(dev);
3516 nv_start_tx(dev);
3517 nv_enable_irq(dev);
3518 }
3519 ret = 0;
3520 } else {
3521 ret = -EINVAL;
3522 }
3523
3524 return ret;
3525 }
3526
3527 static int nv_set_tso(struct net_device *dev, u32 value)
3528 {
3529 struct fe_priv *np = netdev_priv(dev);
3530
3531 if ((np->driver_data & DEV_HAS_CHECKSUM))
3532 return ethtool_op_set_tso(dev, value);
3533 else
3534 return -EOPNOTSUPP;
3535 }
3536
3537 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3538 {
3539 struct fe_priv *np = netdev_priv(dev);
3540
3541 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3542 ring->rx_mini_max_pending = 0;
3543 ring->rx_jumbo_max_pending = 0;
3544 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3545
3546 ring->rx_pending = np->rx_ring_size;
3547 ring->rx_mini_pending = 0;
3548 ring->rx_jumbo_pending = 0;
3549 ring->tx_pending = np->tx_ring_size;
3550 }
3551
3552 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3553 {
3554 struct fe_priv *np = netdev_priv(dev);
3555 u8 __iomem *base = get_hwbase(dev);
3556 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3557 dma_addr_t ring_addr;
3558
3559 if (ring->rx_pending < RX_RING_MIN ||
3560 ring->tx_pending < TX_RING_MIN ||
3561 ring->rx_mini_pending != 0 ||
3562 ring->rx_jumbo_pending != 0 ||
3563 (np->desc_ver == DESC_VER_1 &&
3564 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3565 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3566 (np->desc_ver != DESC_VER_1 &&
3567 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3568 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3569 return -EINVAL;
3570 }
3571
3572 /* allocate new rings */
3573 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3574 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3575 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3576 &ring_addr);
3577 } else {
3578 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3579 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3580 &ring_addr);
3581 }
3582 rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3583 rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3584 tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3585 tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3586 tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3587 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3588 /* fall back to old rings */
3589 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3590 if (rxtx_ring)
3591 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3592 rxtx_ring, ring_addr);
3593 } else {
3594 if (rxtx_ring)
3595 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3596 rxtx_ring, ring_addr);
3597 }
3598 if (rx_skbuff)
3599 kfree(rx_skbuff);
3600 if (rx_dma)
3601 kfree(rx_dma);
3602 if (tx_skbuff)
3603 kfree(tx_skbuff);
3604 if (tx_dma)
3605 kfree(tx_dma);
3606 if (tx_dma_len)
3607 kfree(tx_dma_len);
3608 goto exit;
3609 }
3610
3611 if (netif_running(dev)) {
3612 nv_disable_irq(dev);
3613 netif_tx_lock_bh(dev);
3614 spin_lock(&np->lock);
3615 /* stop engines */
3616 nv_stop_rx(dev);
3617 nv_stop_tx(dev);
3618 nv_txrx_reset(dev);
3619 /* drain queues */
3620 nv_drain_rx(dev);
3621 nv_drain_tx(dev);
3622 /* delete queues */
3623 free_rings(dev);
3624 }
3625
3626 /* set new values */
3627 np->rx_ring_size = ring->rx_pending;
3628 np->tx_ring_size = ring->tx_pending;
3629 np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3630 np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3631 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3632 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3633 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3634 } else {
3635 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3636 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3637 }
3638 np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3639 np->rx_dma = (dma_addr_t*)rx_dma;
3640 np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3641 np->tx_dma = (dma_addr_t*)tx_dma;
3642 np->tx_dma_len = (unsigned int*)tx_dma_len;
3643 np->ring_addr = ring_addr;
3644
3645 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3646 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3647 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3648 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3649 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3650
3651 if (netif_running(dev)) {
3652 /* reinit driver view of the queues */
3653 set_bufsize(dev);
3654 if (nv_init_ring(dev)) {
3655 if (!np->in_shutdown)
3656 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3657 }
3658
3659 /* reinit nic view of the queues */
3660 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3661 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3662 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3663 base + NvRegRingSizes);
3664 pci_push(base);
3665 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3666 pci_push(base);
3667
3668 /* restart engines */
3669 nv_start_rx(dev);
3670 nv_start_tx(dev);
3671 spin_unlock(&np->lock);
3672 netif_tx_unlock_bh(dev);
3673 nv_enable_irq(dev);
3674 }
3675 return 0;
3676 exit:
3677 return -ENOMEM;
3678 }
3679
3680 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3681 {
3682 struct fe_priv *np = netdev_priv(dev);
3683
3684 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3685 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3686 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3687 }
3688
3689 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3690 {
3691 struct fe_priv *np = netdev_priv(dev);
3692 int adv, bmcr;
3693
3694 if ((!np->autoneg && np->duplex == 0) ||
3695 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3696 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3697 dev->name);
3698 return -EINVAL;
3699 }
3700 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3701 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3702 return -EINVAL;
3703 }
3704
3705 netif_carrier_off(dev);
3706 if (netif_running(dev)) {
3707 nv_disable_irq(dev);
3708 netif_tx_lock_bh(dev);
3709 spin_lock(&np->lock);
3710 /* stop engines */
3711 nv_stop_rx(dev);
3712 nv_stop_tx(dev);
3713 spin_unlock(&np->lock);
3714 netif_tx_unlock_bh(dev);
3715 }
3716
3717 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3718 if (pause->rx_pause)
3719 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3720 if (pause->tx_pause)
3721 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3722
3723 if (np->autoneg && pause->autoneg) {
3724 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3725
3726 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3727 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3728 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3729 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3730 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3731 adv |= ADVERTISE_PAUSE_ASYM;
3732 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3733
3734 if (netif_running(dev))
3735 printk(KERN_INFO "%s: link down.\n", dev->name);
3736 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3737 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3738 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3739 } else {
3740 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3741 if (pause->rx_pause)
3742 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3743 if (pause->tx_pause)
3744 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3745
3746 if (!netif_running(dev))
3747 nv_update_linkspeed(dev);
3748 else
3749 nv_update_pause(dev, np->pause_flags);
3750 }
3751
3752 if (netif_running(dev)) {
3753 nv_start_rx(dev);
3754 nv_start_tx(dev);
3755 nv_enable_irq(dev);
3756 }
3757 return 0;
3758 }
3759
3760 static u32 nv_get_rx_csum(struct net_device *dev)
3761 {
3762 struct fe_priv *np = netdev_priv(dev);
3763 return (np->rx_csum) != 0;
3764 }
3765
3766 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3767 {
3768 struct fe_priv *np = netdev_priv(dev);
3769 u8 __iomem *base = get_hwbase(dev);
3770 int retcode = 0;
3771
3772 if (np->driver_data & DEV_HAS_CHECKSUM) {
3773 if (data) {
3774 np->rx_csum = 1;
3775 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3776 } else {
3777 np->rx_csum = 0;
3778 /* vlan is dependent on rx checksum offload */
3779 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3780 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3781 }
3782 if (netif_running(dev)) {
3783 spin_lock_irq(&np->lock);
3784 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3785 spin_unlock_irq(&np->lock);
3786 }
3787 } else {
3788 return -EINVAL;
3789 }
3790
3791 return retcode;
3792 }
3793
3794 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3795 {
3796 struct fe_priv *np = netdev_priv(dev);
3797
3798 if (np->driver_data & DEV_HAS_CHECKSUM)
3799 return ethtool_op_set_tx_hw_csum(dev, data);
3800 else
3801 return -EOPNOTSUPP;
3802 }
3803
3804 static int nv_set_sg(struct net_device *dev, u32 data)
3805 {
3806 struct fe_priv *np = netdev_priv(dev);
3807
3808 if (np->driver_data & DEV_HAS_CHECKSUM)
3809 return ethtool_op_set_sg(dev, data);
3810 else
3811 return -EOPNOTSUPP;
3812 }
3813
3814 static int nv_get_stats_count(struct net_device *dev)
3815 {
3816 struct fe_priv *np = netdev_priv(dev);
3817
3818 if (np->driver_data & DEV_HAS_STATISTICS)
3819 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3820 else
3821 return 0;
3822 }
3823
3824 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3825 {
3826 struct fe_priv *np = netdev_priv(dev);
3827
3828 /* update stats */
3829 nv_do_stats_poll((unsigned long)dev);
3830
3831 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3832 }
3833
3834 static int nv_self_test_count(struct net_device *dev)
3835 {
3836 struct fe_priv *np = netdev_priv(dev);
3837
3838 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3839 return NV_TEST_COUNT_EXTENDED;
3840 else
3841 return NV_TEST_COUNT_BASE;
3842 }
3843
3844 static int nv_link_test(struct net_device *dev)
3845 {
3846 struct fe_priv *np = netdev_priv(dev);
3847 int mii_status;
3848
3849 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3850 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3851
3852 /* check phy link status */
3853 if (!(mii_status & BMSR_LSTATUS))
3854 return 0;
3855 else
3856 return 1;
3857 }
3858
3859 static int nv_register_test(struct net_device *dev)
3860 {
3861 u8 __iomem *base = get_hwbase(dev);
3862 int i = 0;
3863 u32 orig_read, new_read;
3864
3865 do {
3866 orig_read = readl(base + nv_registers_test[i].reg);
3867
3868 /* xor with mask to toggle bits */
3869 orig_read ^= nv_registers_test[i].mask;
3870
3871 writel(orig_read, base + nv_registers_test[i].reg);
3872
3873 new_read = readl(base + nv_registers_test[i].reg);
3874
3875 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3876 return 0;
3877
3878 /* restore original value */
3879 orig_read ^= nv_registers_test[i].mask;
3880 writel(orig_read, base + nv_registers_test[i].reg);
3881
3882 } while (nv_registers_test[++i].reg != 0);
3883
3884 return 1;
3885 }
3886
3887 static int nv_interrupt_test(struct net_device *dev)
3888 {
3889 struct fe_priv *np = netdev_priv(dev);
3890 u8 __iomem *base = get_hwbase(dev);
3891 int ret = 1;
3892 int testcnt;
3893 u32 save_msi_flags, save_poll_interval = 0;
3894
3895 if (netif_running(dev)) {
3896 /* free current irq */
3897 nv_free_irq(dev);
3898 save_poll_interval = readl(base+NvRegPollingInterval);
3899 }
3900
3901 /* flag to test interrupt handler */
3902 np->intr_test = 0;
3903
3904 /* setup test irq */
3905 save_msi_flags = np->msi_flags;
3906 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3907 np->msi_flags |= 0x001; /* setup 1 vector */
3908 if (nv_request_irq(dev, 1))
3909 return 0;
3910
3911 /* setup timer interrupt */
3912 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3913 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3914
3915 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3916
3917 /* wait for at least one interrupt */
3918 msleep(100);
3919
3920 spin_lock_irq(&np->lock);
3921
3922 /* flag should be set within ISR */
3923 testcnt = np->intr_test;
3924 if (!testcnt)
3925 ret = 2;
3926
3927 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3928 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3929 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3930 else
3931 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3932
3933 spin_unlock_irq(&np->lock);
3934
3935 nv_free_irq(dev);
3936
3937 np->msi_flags = save_msi_flags;
3938
3939 if (netif_running(dev)) {
3940 writel(save_poll_interval, base + NvRegPollingInterval);
3941 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3942 /* restore original irq */
3943 if (nv_request_irq(dev, 0))
3944 return 0;
3945 }
3946
3947 return ret;
3948 }
3949
3950 static int nv_loopback_test(struct net_device *dev)
3951 {
3952 struct fe_priv *np = netdev_priv(dev);
3953 u8 __iomem *base = get_hwbase(dev);
3954 struct sk_buff *tx_skb, *rx_skb;
3955 dma_addr_t test_dma_addr;
3956 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3957 u32 flags;
3958 int len, i, pkt_len;
3959 u8 *pkt_data;
3960 u32 filter_flags = 0;
3961 u32 misc1_flags = 0;
3962 int ret = 1;
3963
3964 if (netif_running(dev)) {
3965 nv_disable_irq(dev);
3966 filter_flags = readl(base + NvRegPacketFilterFlags);
3967 misc1_flags = readl(base + NvRegMisc1);
3968 } else {
3969 nv_txrx_reset(dev);
3970 }
3971
3972 /* reinit driver view of the rx queue */
3973 set_bufsize(dev);
3974 nv_init_ring(dev);
3975
3976 /* setup hardware for loopback */
3977 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3978 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3979
3980 /* reinit nic view of the rx queue */
3981 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3982 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3983 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3984 base + NvRegRingSizes);
3985 pci_push(base);
3986
3987 /* restart rx engine */
3988 nv_start_rx(dev);
3989 nv_start_tx(dev);
3990
3991 /* setup packet for tx */
3992 pkt_len = ETH_DATA_LEN;
3993 tx_skb = dev_alloc_skb(pkt_len);
3994 if (!tx_skb) {
3995 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
3996 " of %s\n", dev->name);
3997 ret = 0;
3998 goto out;
3999 }
4000 pkt_data = skb_put(tx_skb, pkt_len);
4001 for (i = 0; i < pkt_len; i++)
4002 pkt_data[i] = (u8)(i & 0xff);
4003 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4004 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
4005
4006 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4007 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4008 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4009 } else {
4010 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4011 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4012 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4013 }
4014 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4015 pci_push(get_hwbase(dev));
4016
4017 msleep(500);
4018
4019 /* check for rx of the packet */
4020 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4021 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4022 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4023
4024 } else {
4025 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4026 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4027 }
4028
4029 if (flags & NV_RX_AVAIL) {
4030 ret = 0;
4031 } else if (np->desc_ver == DESC_VER_1) {
4032 if (flags & NV_RX_ERROR)
4033 ret = 0;
4034 } else {
4035 if (flags & NV_RX2_ERROR) {
4036 ret = 0;
4037 }
4038 }
4039
4040 if (ret) {
4041 if (len != pkt_len) {
4042 ret = 0;
4043 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4044 dev->name, len, pkt_len);
4045 } else {
4046 rx_skb = np->rx_skbuff[0];
4047 for (i = 0; i < pkt_len; i++) {
4048 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4049 ret = 0;
4050 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4051 dev->name, i);
4052 break;
4053 }
4054 }
4055 }
4056 } else {
4057 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4058 }
4059
4060 pci_unmap_page(np->pci_dev, test_dma_addr,
4061 tx_skb->end-tx_skb->data,
4062 PCI_DMA_TODEVICE);
4063 dev_kfree_skb_any(tx_skb);
4064 out:
4065 /* stop engines */
4066 nv_stop_rx(dev);
4067 nv_stop_tx(dev);
4068 nv_txrx_reset(dev);
4069 /* drain rx queue */
4070 nv_drain_rx(dev);
4071 nv_drain_tx(dev);
4072
4073 if (netif_running(dev)) {
4074 writel(misc1_flags, base + NvRegMisc1);
4075 writel(filter_flags, base + NvRegPacketFilterFlags);
4076 nv_enable_irq(dev);
4077 }
4078
4079 return ret;
4080 }
4081
4082 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4083 {
4084 struct fe_priv *np = netdev_priv(dev);
4085 u8 __iomem *base = get_hwbase(dev);
4086 int result;
4087 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4088
4089 if (!nv_link_test(dev)) {
4090 test->flags |= ETH_TEST_FL_FAILED;
4091 buffer[0] = 1;
4092 }
4093
4094 if (test->flags & ETH_TEST_FL_OFFLINE) {
4095 if (netif_running(dev)) {
4096 netif_stop_queue(dev);
4097 netif_poll_disable(dev);
4098 netif_tx_lock_bh(dev);
4099 spin_lock_irq(&np->lock);
4100 nv_disable_hw_interrupts(dev, np->irqmask);
4101 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4102 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4103 } else {
4104 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4105 }
4106 /* stop engines */
4107 nv_stop_rx(dev);
4108 nv_stop_tx(dev);
4109 nv_txrx_reset(dev);
4110 /* drain rx queue */
4111 nv_drain_rx(dev);
4112 nv_drain_tx(dev);
4113 spin_unlock_irq(&np->lock);
4114 netif_tx_unlock_bh(dev);
4115 }
4116
4117 if (!nv_register_test(dev)) {
4118 test->flags |= ETH_TEST_FL_FAILED;
4119 buffer[1] = 1;
4120 }
4121
4122 result = nv_interrupt_test(dev);
4123 if (result != 1) {
4124 test->flags |= ETH_TEST_FL_FAILED;
4125 buffer[2] = 1;
4126 }
4127 if (result == 0) {
4128 /* bail out */
4129 return;
4130 }
4131
4132 if (!nv_loopback_test(dev)) {
4133 test->flags |= ETH_TEST_FL_FAILED;
4134 buffer[3] = 1;
4135 }
4136
4137 if (netif_running(dev)) {
4138 /* reinit driver view of the rx queue */
4139 set_bufsize(dev);
4140 if (nv_init_ring(dev)) {
4141 if (!np->in_shutdown)
4142 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4143 }
4144 /* reinit nic view of the rx queue */
4145 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4146 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4147 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4148 base + NvRegRingSizes);
4149 pci_push(base);
4150 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4151 pci_push(base);
4152 /* restart rx engine */
4153 nv_start_rx(dev);
4154 nv_start_tx(dev);
4155 netif_start_queue(dev);
4156 netif_poll_enable(dev);
4157 nv_enable_hw_interrupts(dev, np->irqmask);
4158 }
4159 }
4160 }
4161
4162 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4163 {
4164 switch (stringset) {
4165 case ETH_SS_STATS:
4166 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4167 break;
4168 case ETH_SS_TEST:
4169 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4170 break;
4171 }
4172 }
4173
4174 static const struct ethtool_ops ops = {
4175 .get_drvinfo = nv_get_drvinfo,
4176 .get_link = ethtool_op_get_link,
4177 .get_wol = nv_get_wol,
4178 .set_wol = nv_set_wol,
4179 .get_settings = nv_get_settings,
4180 .set_settings = nv_set_settings,
4181 .get_regs_len = nv_get_regs_len,
4182 .get_regs = nv_get_regs,
4183 .nway_reset = nv_nway_reset,
4184 .get_perm_addr = ethtool_op_get_perm_addr,
4185 .get_tso = ethtool_op_get_tso,
4186 .set_tso = nv_set_tso,
4187 .get_ringparam = nv_get_ringparam,
4188 .set_ringparam = nv_set_ringparam,
4189 .get_pauseparam = nv_get_pauseparam,
4190 .set_pauseparam = nv_set_pauseparam,
4191 .get_rx_csum = nv_get_rx_csum,
4192 .set_rx_csum = nv_set_rx_csum,
4193 .get_tx_csum = ethtool_op_get_tx_csum,
4194 .set_tx_csum = nv_set_tx_csum,
4195 .get_sg = ethtool_op_get_sg,
4196 .set_sg = nv_set_sg,
4197 .get_strings = nv_get_strings,
4198 .get_stats_count = nv_get_stats_count,
4199 .get_ethtool_stats = nv_get_ethtool_stats,
4200 .self_test_count = nv_self_test_count,
4201 .self_test = nv_self_test,
4202 };
4203
4204 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4205 {
4206 struct fe_priv *np = get_nvpriv(dev);
4207
4208 spin_lock_irq(&np->lock);
4209
4210 /* save vlan group */
4211 np->vlangrp = grp;
4212
4213 if (grp) {
4214 /* enable vlan on MAC */
4215 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4216 } else {
4217 /* disable vlan on MAC */
4218 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4219 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4220 }
4221
4222 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4223
4224 spin_unlock_irq(&np->lock);
4225 };
4226
4227 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4228 {
4229 /* nothing to do */
4230 };
4231
4232 /* The mgmt unit and driver use a semaphore to access the phy during init */
4233 static int nv_mgmt_acquire_sema(struct net_device *dev)
4234 {
4235 u8 __iomem *base = get_hwbase(dev);
4236 int i;
4237 u32 tx_ctrl, mgmt_sema;
4238
4239 for (i = 0; i < 10; i++) {
4240 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4241 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4242 break;
4243 msleep(500);
4244 }
4245
4246 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4247 return 0;
4248
4249 for (i = 0; i < 2; i++) {
4250 tx_ctrl = readl(base + NvRegTransmitterControl);
4251 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4252 writel(tx_ctrl, base + NvRegTransmitterControl);
4253
4254 /* verify that semaphore was acquired */
4255 tx_ctrl = readl(base + NvRegTransmitterControl);
4256 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4257 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4258 return 1;
4259 else
4260 udelay(50);
4261 }
4262
4263 return 0;
4264 }
4265
4266 static int nv_open(struct net_device *dev)
4267 {
4268 struct fe_priv *np = netdev_priv(dev);
4269 u8 __iomem *base = get_hwbase(dev);
4270 int ret = 1;
4271 int oom, i;
4272
4273 dprintk(KERN_DEBUG "nv_open: begin\n");
4274
4275 /* erase previous misconfiguration */
4276 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4277 nv_mac_reset(dev);
4278 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4279 writel(0, base + NvRegMulticastAddrB);
4280 writel(0, base + NvRegMulticastMaskA);
4281 writel(0, base + NvRegMulticastMaskB);
4282 writel(0, base + NvRegPacketFilterFlags);
4283
4284 writel(0, base + NvRegTransmitterControl);
4285 writel(0, base + NvRegReceiverControl);
4286
4287 writel(0, base + NvRegAdapterControl);
4288
4289 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4290 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4291
4292 /* initialize descriptor rings */
4293 set_bufsize(dev);
4294 oom = nv_init_ring(dev);
4295
4296 writel(0, base + NvRegLinkSpeed);
4297 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4298 nv_txrx_reset(dev);
4299 writel(0, base + NvRegUnknownSetupReg6);
4300
4301 np->in_shutdown = 0;
4302
4303 /* give hw rings */
4304 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4305 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4306 base + NvRegRingSizes);
4307
4308 writel(np->linkspeed, base + NvRegLinkSpeed);
4309 if (np->desc_ver == DESC_VER_1)
4310 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4311 else
4312 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4313 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4314 writel(np->vlanctl_bits, base + NvRegVlanControl);
4315 pci_push(base);
4316 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4317 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4318 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4319 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4320
4321 writel(0, base + NvRegMIIMask);
4322 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4323 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4324
4325 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4326 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4327 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4328 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4329
4330 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4331 get_random_bytes(&i, sizeof(i));
4332 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4333 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4334 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4335 if (poll_interval == -1) {
4336 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4337 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4338 else
4339 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4340 }
4341 else
4342 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4343 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4344 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4345 base + NvRegAdapterControl);
4346 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4347 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4348 if (np->wolenabled)
4349 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4350
4351 i = readl(base + NvRegPowerState);
4352 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4353 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4354
4355 pci_push(base);
4356 udelay(10);
4357 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4358
4359 nv_disable_hw_interrupts(dev, np->irqmask);
4360 pci_push(base);
4361 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4362 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4363 pci_push(base);
4364
4365 if (nv_request_irq(dev, 0)) {
4366 goto out_drain;
4367 }
4368
4369 /* ask for interrupts */
4370 nv_enable_hw_interrupts(dev, np->irqmask);
4371
4372 spin_lock_irq(&np->lock);
4373 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4374 writel(0, base + NvRegMulticastAddrB);
4375 writel(0, base + NvRegMulticastMaskA);
4376 writel(0, base + NvRegMulticastMaskB);
4377 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4378 /* One manual link speed update: Interrupts are enabled, future link
4379 * speed changes cause interrupts and are handled by nv_link_irq().
4380 */
4381 {
4382 u32 miistat;
4383 miistat = readl(base + NvRegMIIStatus);
4384 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4385 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4386 }
4387 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4388 * to init hw */
4389 np->linkspeed = 0;
4390 ret = nv_update_linkspeed(dev);
4391 nv_start_rx(dev);
4392 nv_start_tx(dev);
4393 netif_start_queue(dev);
4394 netif_poll_enable(dev);
4395
4396 if (ret) {
4397 netif_carrier_on(dev);
4398 } else {
4399 printk("%s: no link during initialization.\n", dev->name);
4400 netif_carrier_off(dev);
4401 }
4402 if (oom)
4403 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4404
4405 /* start statistics timer */
4406 if (np->driver_data & DEV_HAS_STATISTICS)
4407 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4408
4409 spin_unlock_irq(&np->lock);
4410
4411 return 0;
4412 out_drain:
4413 drain_ring(dev);
4414 return ret;
4415 }
4416
4417 static int nv_close(struct net_device *dev)
4418 {
4419 struct fe_priv *np = netdev_priv(dev);
4420 u8 __iomem *base;
4421
4422 spin_lock_irq(&np->lock);
4423 np->in_shutdown = 1;
4424 spin_unlock_irq(&np->lock);
4425 netif_poll_disable(dev);
4426 synchronize_irq(dev->irq);
4427
4428 del_timer_sync(&np->oom_kick);
4429 del_timer_sync(&np->nic_poll);
4430 del_timer_sync(&np->stats_poll);
4431
4432 netif_stop_queue(dev);
4433 spin_lock_irq(&np->lock);
4434 nv_stop_tx(dev);
4435 nv_stop_rx(dev);
4436 nv_txrx_reset(dev);
4437
4438 /* disable interrupts on the nic or we will lock up */
4439 base = get_hwbase(dev);
4440 nv_disable_hw_interrupts(dev, np->irqmask);
4441 pci_push(base);
4442 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4443
4444 spin_unlock_irq(&np->lock);
4445
4446 nv_free_irq(dev);
4447
4448 drain_ring(dev);
4449
4450 if (np->wolenabled)
4451 nv_start_rx(dev);
4452
4453 /* FIXME: power down nic */
4454
4455 return 0;
4456 }
4457
4458 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4459 {
4460 struct net_device *dev;
4461 struct fe_priv *np;
4462 unsigned long addr;
4463 u8 __iomem *base;
4464 int err, i;
4465 u32 powerstate, txreg;
4466 u32 phystate_orig = 0, phystate;
4467 int phyinitialized = 0;
4468
4469 dev = alloc_etherdev(sizeof(struct fe_priv));
4470 err = -ENOMEM;
4471 if (!dev)
4472 goto out;
4473
4474 np = netdev_priv(dev);
4475 np->pci_dev = pci_dev;
4476 spin_lock_init(&np->lock);
4477 SET_MODULE_OWNER(dev);
4478 SET_NETDEV_DEV(dev, &pci_dev->dev);
4479
4480 init_timer(&np->oom_kick);
4481 np->oom_kick.data = (unsigned long) dev;
4482 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
4483 init_timer(&np->nic_poll);
4484 np->nic_poll.data = (unsigned long) dev;
4485 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
4486 init_timer(&np->stats_poll);
4487 np->stats_poll.data = (unsigned long) dev;
4488 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
4489
4490 err = pci_enable_device(pci_dev);
4491 if (err) {
4492 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4493 err, pci_name(pci_dev));
4494 goto out_free;
4495 }
4496
4497 pci_set_master(pci_dev);
4498
4499 err = pci_request_regions(pci_dev, DRV_NAME);
4500 if (err < 0)
4501 goto out_disable;
4502
4503 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4504 np->register_size = NV_PCI_REGSZ_VER2;
4505 else
4506 np->register_size = NV_PCI_REGSZ_VER1;
4507
4508 err = -EINVAL;
4509 addr = 0;
4510 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4511 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4512 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4513 pci_resource_len(pci_dev, i),
4514 pci_resource_flags(pci_dev, i));
4515 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4516 pci_resource_len(pci_dev, i) >= np->register_size) {
4517 addr = pci_resource_start(pci_dev, i);
4518 break;
4519 }
4520 }
4521 if (i == DEVICE_COUNT_RESOURCE) {
4522 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4523 pci_name(pci_dev));
4524 goto out_relreg;
4525 }
4526
4527 /* copy of driver data */
4528 np->driver_data = id->driver_data;
4529
4530 /* handle different descriptor versions */
4531 if (id->driver_data & DEV_HAS_HIGH_DMA) {
4532 /* packet format 3: supports 40-bit addressing */
4533 np->desc_ver = DESC_VER_3;
4534 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4535 if (dma_64bit) {
4536 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4537 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4538 pci_name(pci_dev));
4539 } else {
4540 dev->features |= NETIF_F_HIGHDMA;
4541 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4542 }
4543 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4544 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4545 pci_name(pci_dev));
4546 }
4547 }
4548 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4549 /* packet format 2: supports jumbo frames */
4550 np->desc_ver = DESC_VER_2;
4551 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4552 } else {
4553 /* original packet format */
4554 np->desc_ver = DESC_VER_1;
4555 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4556 }
4557
4558 np->pkt_limit = NV_PKTLIMIT_1;
4559 if (id->driver_data & DEV_HAS_LARGEDESC)
4560 np->pkt_limit = NV_PKTLIMIT_2;
4561
4562 if (id->driver_data & DEV_HAS_CHECKSUM) {
4563 np->rx_csum = 1;
4564 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4565 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4566 #ifdef NETIF_F_TSO
4567 dev->features |= NETIF_F_TSO;
4568 #endif
4569 }
4570
4571 np->vlanctl_bits = 0;
4572 if (id->driver_data & DEV_HAS_VLAN) {
4573 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4574 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4575 dev->vlan_rx_register = nv_vlan_rx_register;
4576 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4577 }
4578
4579 np->msi_flags = 0;
4580 if ((id->driver_data & DEV_HAS_MSI) && msi) {
4581 np->msi_flags |= NV_MSI_CAPABLE;
4582 }
4583 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4584 np->msi_flags |= NV_MSI_X_CAPABLE;
4585 }
4586
4587 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4588 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4589 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4590 }
4591
4592
4593 err = -ENOMEM;
4594 np->base = ioremap(addr, np->register_size);
4595 if (!np->base)
4596 goto out_relreg;
4597 dev->base_addr = (unsigned long)np->base;
4598
4599 dev->irq = pci_dev->irq;
4600
4601 np->rx_ring_size = RX_RING_DEFAULT;
4602 np->tx_ring_size = TX_RING_DEFAULT;
4603 np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4604 np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4605
4606 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4607 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4608 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4609 &np->ring_addr);
4610 if (!np->rx_ring.orig)
4611 goto out_unmap;
4612 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4613 } else {
4614 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4615 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4616 &np->ring_addr);
4617 if (!np->rx_ring.ex)
4618 goto out_unmap;
4619 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4620 }
4621 np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4622 np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4623 np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4624 np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4625 np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4626 if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4627 goto out_freering;
4628 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4629 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4630 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4631 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4632 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4633
4634 dev->open = nv_open;
4635 dev->stop = nv_close;
4636 dev->hard_start_xmit = nv_start_xmit;
4637 dev->get_stats = nv_get_stats;
4638 dev->change_mtu = nv_change_mtu;
4639 dev->set_mac_address = nv_set_mac_address;
4640 dev->set_multicast_list = nv_set_multicast;
4641 #ifdef CONFIG_NET_POLL_CONTROLLER
4642 dev->poll_controller = nv_poll_controller;
4643 #endif
4644 dev->weight = 64;
4645 #ifdef CONFIG_FORCEDETH_NAPI
4646 dev->poll = nv_napi_poll;
4647 #endif
4648 SET_ETHTOOL_OPS(dev, &ops);
4649 dev->tx_timeout = nv_tx_timeout;
4650 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4651
4652 pci_set_drvdata(pci_dev, dev);
4653
4654 /* read the mac address */
4655 base = get_hwbase(dev);
4656 np->orig_mac[0] = readl(base + NvRegMacAddrA);
4657 np->orig_mac[1] = readl(base + NvRegMacAddrB);
4658
4659 /* check the workaround bit for correct mac address order */
4660 txreg = readl(base + NvRegTransmitPoll);
4661 if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4662 /* mac address is already in correct order */
4663 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
4664 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
4665 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4666 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4667 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
4668 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
4669 } else {
4670 /* need to reverse mac address to correct order */
4671 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
4672 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
4673 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4674 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4675 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
4676 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
4677 /* set permanent address to be correct aswell */
4678 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4679 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4680 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4681 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4682 }
4683 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4684
4685 if (!is_valid_ether_addr(dev->perm_addr)) {
4686 /*
4687 * Bad mac address. At least one bios sets the mac address
4688 * to 01:23:45:67:89:ab
4689 */
4690 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4691 pci_name(pci_dev),
4692 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4693 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4694 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4695 dev->dev_addr[0] = 0x00;
4696 dev->dev_addr[1] = 0x00;
4697 dev->dev_addr[2] = 0x6c;
4698 get_random_bytes(&dev->dev_addr[3], 3);
4699 }
4700
4701 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4702 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4703 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4704
4705 /* set mac address */
4706 nv_copy_mac_to_hw(dev);
4707
4708 /* disable WOL */
4709 writel(0, base + NvRegWakeUpFlags);
4710 np->wolenabled = 0;
4711
4712 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4713 u8 revision_id;
4714 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4715
4716 /* take phy and nic out of low power mode */
4717 powerstate = readl(base + NvRegPowerState2);
4718 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4719 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4720 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4721 revision_id >= 0xA3)
4722 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4723 writel(powerstate, base + NvRegPowerState2);
4724 }
4725
4726 if (np->desc_ver == DESC_VER_1) {
4727 np->tx_flags = NV_TX_VALID;
4728 } else {
4729 np->tx_flags = NV_TX2_VALID;
4730 }
4731 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4732 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4733 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4734 np->msi_flags |= 0x0003;
4735 } else {
4736 np->irqmask = NVREG_IRQMASK_CPU;
4737 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4738 np->msi_flags |= 0x0001;
4739 }
4740
4741 if (id->driver_data & DEV_NEED_TIMERIRQ)
4742 np->irqmask |= NVREG_IRQ_TIMER;
4743 if (id->driver_data & DEV_NEED_LINKTIMER) {
4744 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4745 np->need_linktimer = 1;
4746 np->link_timeout = jiffies + LINK_TIMEOUT;
4747 } else {
4748 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4749 np->need_linktimer = 0;
4750 }
4751
4752 /* clear phy state and temporarily halt phy interrupts */
4753 writel(0, base + NvRegMIIMask);
4754 phystate = readl(base + NvRegAdapterControl);
4755 if (phystate & NVREG_ADAPTCTL_RUNNING) {
4756 phystate_orig = 1;
4757 phystate &= ~NVREG_ADAPTCTL_RUNNING;
4758 writel(phystate, base + NvRegAdapterControl);
4759 }
4760 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4761
4762 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4763 /* management unit running on the mac? */
4764 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
4765 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
4766 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
4767 for (i = 0; i < 5000; i++) {
4768 msleep(1);
4769 if (nv_mgmt_acquire_sema(dev)) {
4770 /* management unit setup the phy already? */
4771 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
4772 NVREG_XMITCTL_SYNC_PHY_INIT) {
4773 /* phy is inited by mgmt unit */
4774 phyinitialized = 1;
4775 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
4776 } else {
4777 /* we need to init the phy */
4778 }
4779 break;
4780 }
4781 }
4782 }
4783 }
4784
4785 /* find a suitable phy */
4786 for (i = 1; i <= 32; i++) {
4787 int id1, id2;
4788 int phyaddr = i & 0x1F;
4789
4790 spin_lock_irq(&np->lock);
4791 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4792 spin_unlock_irq(&np->lock);
4793 if (id1 < 0 || id1 == 0xffff)
4794 continue;
4795 spin_lock_irq(&np->lock);
4796 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4797 spin_unlock_irq(&np->lock);
4798 if (id2 < 0 || id2 == 0xffff)
4799 continue;
4800
4801 np->phy_model = id2 & PHYID2_MODEL_MASK;
4802 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4803 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4804 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4805 pci_name(pci_dev), id1, id2, phyaddr);
4806 np->phyaddr = phyaddr;
4807 np->phy_oui = id1 | id2;
4808 break;
4809 }
4810 if (i == 33) {
4811 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4812 pci_name(pci_dev));
4813 goto out_error;
4814 }
4815
4816 if (!phyinitialized) {
4817 /* reset it */
4818 phy_init(dev);
4819 } else {
4820 /* see if it is a gigabit phy */
4821 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4822 if (mii_status & PHY_GIGABIT) {
4823 np->gigabit = PHY_GIGABIT;
4824 }
4825 }
4826
4827 /* set default link speed settings */
4828 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4829 np->duplex = 0;
4830 np->autoneg = 1;
4831
4832 err = register_netdev(dev);
4833 if (err) {
4834 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4835 goto out_error;
4836 }
4837 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4838 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4839 pci_name(pci_dev));
4840
4841 return 0;
4842
4843 out_error:
4844 if (phystate_orig)
4845 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
4846 pci_set_drvdata(pci_dev, NULL);
4847 out_freering:
4848 free_rings(dev);
4849 out_unmap:
4850 iounmap(get_hwbase(dev));
4851 out_relreg:
4852 pci_release_regions(pci_dev);
4853 out_disable:
4854 pci_disable_device(pci_dev);
4855 out_free:
4856 free_netdev(dev);
4857 out:
4858 return err;
4859 }
4860
4861 static void __devexit nv_remove(struct pci_dev *pci_dev)
4862 {
4863 struct net_device *dev = pci_get_drvdata(pci_dev);
4864 struct fe_priv *np = netdev_priv(dev);
4865 u8 __iomem *base = get_hwbase(dev);
4866
4867 unregister_netdev(dev);
4868
4869 /* special op: write back the misordered MAC address - otherwise
4870 * the next nv_probe would see a wrong address.
4871 */
4872 writel(np->orig_mac[0], base + NvRegMacAddrA);
4873 writel(np->orig_mac[1], base + NvRegMacAddrB);
4874
4875 /* free all structures */
4876 free_rings(dev);
4877 iounmap(get_hwbase(dev));
4878 pci_release_regions(pci_dev);
4879 pci_disable_device(pci_dev);
4880 free_netdev(dev);
4881 pci_set_drvdata(pci_dev, NULL);
4882 }
4883
4884 #ifdef CONFIG_PM
4885 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4886 {
4887 struct net_device *dev = pci_get_drvdata(pdev);
4888 struct fe_priv *np = netdev_priv(dev);
4889
4890 if (!netif_running(dev))
4891 goto out;
4892
4893 netif_device_detach(dev);
4894
4895 // Gross.
4896 nv_close(dev);
4897
4898 pci_save_state(pdev);
4899 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4900 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4901 out:
4902 return 0;
4903 }
4904
4905 static int nv_resume(struct pci_dev *pdev)
4906 {
4907 struct net_device *dev = pci_get_drvdata(pdev);
4908 int rc = 0;
4909
4910 if (!netif_running(dev))
4911 goto out;
4912
4913 netif_device_attach(dev);
4914
4915 pci_set_power_state(pdev, PCI_D0);
4916 pci_restore_state(pdev);
4917 pci_enable_wake(pdev, PCI_D0, 0);
4918
4919 rc = nv_open(dev);
4920 out:
4921 return rc;
4922 }
4923 #else
4924 #define nv_suspend NULL
4925 #define nv_resume NULL
4926 #endif /* CONFIG_PM */
4927
4928 static struct pci_device_id pci_tbl[] = {
4929 { /* nForce Ethernet Controller */
4930 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4931 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4932 },
4933 { /* nForce2 Ethernet Controller */
4934 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4935 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4936 },
4937 { /* nForce3 Ethernet Controller */
4938 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4939 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4940 },
4941 { /* nForce3 Ethernet Controller */
4942 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4943 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4944 },
4945 { /* nForce3 Ethernet Controller */
4946 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4947 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4948 },
4949 { /* nForce3 Ethernet Controller */
4950 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4951 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4952 },
4953 { /* nForce3 Ethernet Controller */
4954 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4955 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4956 },
4957 { /* CK804 Ethernet Controller */
4958 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4959 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4960 },
4961 { /* CK804 Ethernet Controller */
4962 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4963 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4964 },
4965 { /* MCP04 Ethernet Controller */
4966 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4967 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4968 },
4969 { /* MCP04 Ethernet Controller */
4970 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4971 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4972 },
4973 { /* MCP51 Ethernet Controller */
4974 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4975 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4976 },
4977 { /* MCP51 Ethernet Controller */
4978 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4979 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4980 },
4981 { /* MCP55 Ethernet Controller */
4982 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4983 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4984 },
4985 { /* MCP55 Ethernet Controller */
4986 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4987 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4988 },
4989 { /* MCP61 Ethernet Controller */
4990 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4991 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4992 },
4993 { /* MCP61 Ethernet Controller */
4994 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4995 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4996 },
4997 { /* MCP61 Ethernet Controller */
4998 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4999 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5000 },
5001 { /* MCP61 Ethernet Controller */
5002 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5003 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5004 },
5005 { /* MCP65 Ethernet Controller */
5006 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5007 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5008 },
5009 { /* MCP65 Ethernet Controller */
5010 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5011 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5012 },
5013 { /* MCP65 Ethernet Controller */
5014 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5015 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5016 },
5017 { /* MCP65 Ethernet Controller */
5018 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5019 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5020 },
5021 { /* MCP67 Ethernet Controller */
5022 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5023 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5024 },
5025 { /* MCP67 Ethernet Controller */
5026 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5027 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5028 },
5029 { /* MCP67 Ethernet Controller */
5030 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5031 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5032 },
5033 { /* MCP67 Ethernet Controller */
5034 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5035 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5036 },
5037 {0,},
5038 };
5039
5040 static struct pci_driver driver = {
5041 .name = "forcedeth",
5042 .id_table = pci_tbl,
5043 .probe = nv_probe,
5044 .remove = __devexit_p(nv_remove),
5045 .suspend = nv_suspend,
5046 .resume = nv_resume,
5047 };
5048
5049 static int __init init_nic(void)
5050 {
5051 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5052 return pci_register_driver(&driver);
5053 }
5054
5055 static void __exit exit_nic(void)
5056 {
5057 pci_unregister_driver(&driver);
5058 }
5059
5060 module_param(max_interrupt_work, int, 0);
5061 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5062 module_param(optimization_mode, int, 0);
5063 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5064 module_param(poll_interval, int, 0);
5065 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5066 module_param(msi, int, 0);
5067 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5068 module_param(msix, int, 0);
5069 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5070 module_param(dma_64bit, int, 0);
5071 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5072
5073 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5074 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5075 MODULE_LICENSE("GPL");
5076
5077 MODULE_DEVICE_TABLE(pci, pci_tbl);
5078
5079 module_init(init_nic);
5080 module_exit(exit_nic);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree