2 * TI DaVinci GPIO Support
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
19 #include <mach/gpio.h>
21 #include <asm/mach/irq.h>
23 struct davinci_gpio_regs
{
36 #define chip2controller(chip) \
37 container_of(chip, struct davinci_gpio_controller, chip)
39 static struct davinci_gpio_controller chips
[DIV_ROUND_UP(DAVINCI_N_GPIO
, 32)];
40 static void __iomem
*gpio_base
;
42 static struct davinci_gpio_regs __iomem __init
*gpio2regs(unsigned gpio
)
47 ptr
= gpio_base
+ 0x10;
48 else if (gpio
< 32 * 2)
49 ptr
= gpio_base
+ 0x38;
50 else if (gpio
< 32 * 3)
51 ptr
= gpio_base
+ 0x60;
52 else if (gpio
< 32 * 4)
53 ptr
= gpio_base
+ 0x88;
54 else if (gpio
< 32 * 5)
55 ptr
= gpio_base
+ 0xb0;
61 static inline struct davinci_gpio_regs __iomem
*irq2regs(int irq
)
63 struct davinci_gpio_regs __iomem
*g
;
65 g
= (__force
struct davinci_gpio_regs __iomem
*)get_irq_chip_data(irq
);
70 static int __init
davinci_gpio_irq_setup(void);
72 /*--------------------------------------------------------------------------*/
74 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
75 static inline int __davinci_direction(struct gpio_chip
*chip
,
76 unsigned offset
, bool out
, int value
)
78 struct davinci_gpio_controller
*d
= chip2controller(chip
);
79 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
82 u32 mask
= 1 << offset
;
84 spin_lock_irqsave(&d
->lock
, flags
);
85 temp
= __raw_readl(&g
->dir
);
88 __raw_writel(mask
, value
? &g
->set_data
: &g
->clr_data
);
92 __raw_writel(temp
, &g
->dir
);
93 spin_unlock_irqrestore(&d
->lock
, flags
);
98 static int davinci_direction_in(struct gpio_chip
*chip
, unsigned offset
)
100 return __davinci_direction(chip
, offset
, false, 0);
104 davinci_direction_out(struct gpio_chip
*chip
, unsigned offset
, int value
)
106 return __davinci_direction(chip
, offset
, true, value
);
110 * Read the pin's value (works even if it's set up as output);
111 * returns zero/nonzero.
113 * Note that changes are synched to the GPIO clock, so reading values back
114 * right after you've set them may give old values.
116 static int davinci_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
118 struct davinci_gpio_controller
*d
= chip2controller(chip
);
119 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
121 return (1 << offset
) & __raw_readl(&g
->in_data
);
125 * Assuming the pin is muxed as a gpio output, set its output value.
128 davinci_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
130 struct davinci_gpio_controller
*d
= chip2controller(chip
);
131 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
133 __raw_writel((1 << offset
), value
? &g
->set_data
: &g
->clr_data
);
136 static int __init
davinci_gpio_setup(void)
140 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
141 struct davinci_gpio_regs
*regs
;
143 if (soc_info
->gpio_type
!= GPIO_TYPE_DAVINCI
)
147 * The gpio banks conceptually expose a segmented bitmap,
148 * and "ngpio" is one more than the largest zero-based
149 * bit index that's valid.
151 ngpio
= soc_info
->gpio_num
;
153 pr_err("GPIO setup: how many GPIOs?\n");
157 if (WARN_ON(DAVINCI_N_GPIO
< ngpio
))
158 ngpio
= DAVINCI_N_GPIO
;
160 gpio_base
= ioremap(soc_info
->gpio_base
, SZ_4K
);
161 if (WARN_ON(!gpio_base
))
164 for (i
= 0, base
= 0; base
< ngpio
; i
++, base
+= 32) {
165 chips
[i
].chip
.label
= "DaVinci";
167 chips
[i
].chip
.direction_input
= davinci_direction_in
;
168 chips
[i
].chip
.get
= davinci_gpio_get
;
169 chips
[i
].chip
.direction_output
= davinci_direction_out
;
170 chips
[i
].chip
.set
= davinci_gpio_set
;
172 chips
[i
].chip
.base
= base
;
173 chips
[i
].chip
.ngpio
= ngpio
- base
;
174 if (chips
[i
].chip
.ngpio
> 32)
175 chips
[i
].chip
.ngpio
= 32;
177 spin_lock_init(&chips
[i
].lock
);
179 regs
= gpio2regs(base
);
180 chips
[i
].regs
= regs
;
181 chips
[i
].set_data
= ®s
->set_data
;
182 chips
[i
].clr_data
= ®s
->clr_data
;
183 chips
[i
].in_data
= ®s
->in_data
;
185 gpiochip_add(&chips
[i
].chip
);
188 soc_info
->gpio_ctlrs
= chips
;
189 soc_info
->gpio_ctlrs_num
= DIV_ROUND_UP(ngpio
, 32);
191 davinci_gpio_irq_setup();
194 pure_initcall(davinci_gpio_setup
);
196 /*--------------------------------------------------------------------------*/
198 * We expect irqs will normally be set up as input pins, but they can also be
199 * used as output pins ... which is convenient for testing.
201 * NOTE: The first few GPIOs also have direct INTC hookups in addition
202 * to their GPIOBNK0 irq, with a bit less overhead.
204 * All those INTC hookups (direct, plus several IRQ banks) can also
205 * serve as EDMA event triggers.
208 static void gpio_irq_disable(struct irq_data
*d
)
210 struct davinci_gpio_regs __iomem
*g
= irq2regs(d
->irq
);
211 u32 mask
= (u32
) irq_data_get_irq_data(d
);
213 __raw_writel(mask
, &g
->clr_falling
);
214 __raw_writel(mask
, &g
->clr_rising
);
217 static void gpio_irq_enable(struct irq_data
*d
)
219 struct davinci_gpio_regs __iomem
*g
= irq2regs(d
->irq
);
220 u32 mask
= (u32
) irq_data_get_irq_data(d
);
221 unsigned status
= irq_desc
[d
->irq
].status
;
223 status
&= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
225 status
= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
227 if (status
& IRQ_TYPE_EDGE_FALLING
)
228 __raw_writel(mask
, &g
->set_falling
);
229 if (status
& IRQ_TYPE_EDGE_RISING
)
230 __raw_writel(mask
, &g
->set_rising
);
233 static int gpio_irq_type(struct irq_data
*d
, unsigned trigger
)
235 struct davinci_gpio_regs __iomem
*g
= irq2regs(d
->irq
);
236 u32 mask
= (u32
) irq_data_get_irq_data(d
);
238 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
241 irq_desc
[d
->irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
242 irq_desc
[d
->irq
].status
|= trigger
;
244 /* don't enable the IRQ if it's currently disabled */
245 if (irq_desc
[d
->irq
].depth
== 0) {
246 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_FALLING
)
247 ? &g
->set_falling
: &g
->clr_falling
);
248 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_RISING
)
249 ? &g
->set_rising
: &g
->clr_rising
);
254 static struct irq_chip gpio_irqchip
= {
256 .irq_enable
= gpio_irq_enable
,
257 .irq_disable
= gpio_irq_disable
,
258 .irq_set_type
= gpio_irq_type
,
262 gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
264 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
267 /* we only care about one bank */
271 /* temporarily mask (level sensitive) parent IRQ */
272 desc
->irq_data
.chip
->irq_mask(&desc
->irq_data
);
273 desc
->irq_data
.chip
->irq_ack(&desc
->irq_data
);
280 status
= __raw_readl(&g
->intstat
) & mask
;
283 __raw_writel(status
, &g
->intstat
);
287 /* now demux them to the right lowlevel handler */
288 n
= (int)get_irq_data(irq
);
292 generic_handle_irq(n
- 1);
296 desc
->irq_data
.chip
->irq_unmask(&desc
->irq_data
);
297 /* now it may re-trigger */
300 static int gpio_to_irq_banked(struct gpio_chip
*chip
, unsigned offset
)
302 struct davinci_gpio_controller
*d
= chip2controller(chip
);
304 if (d
->irq_base
>= 0)
305 return d
->irq_base
+ offset
;
310 static int gpio_to_irq_unbanked(struct gpio_chip
*chip
, unsigned offset
)
312 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
314 /* NOTE: we assume for now that only irqs in the first gpio_chip
315 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
317 if (offset
< soc_info
->gpio_unbanked
)
318 return soc_info
->gpio_irq
+ offset
;
323 static int gpio_irq_type_unbanked(struct irq_data
*d
, unsigned trigger
)
325 struct davinci_gpio_regs __iomem
*g
= irq2regs(d
->irq
);
326 u32 mask
= (u32
) irq_data_get_irq_data(d
);
328 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
331 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_FALLING
)
332 ? &g
->set_falling
: &g
->clr_falling
);
333 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_RISING
)
334 ? &g
->set_rising
: &g
->clr_rising
);
340 * NOTE: for suspend/resume, probably best to make a platform_device with
341 * suspend_late/resume_resume calls hooking into results of the set_wake()
342 * calls ... so if no gpios are wakeup events the clock can be disabled,
343 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
344 * (dm6446) can be set appropriately for GPIOV33 pins.
347 static int __init
davinci_gpio_irq_setup(void)
349 unsigned gpio
, irq
, bank
;
352 unsigned ngpio
, bank_irq
;
353 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
354 struct davinci_gpio_regs __iomem
*g
;
356 ngpio
= soc_info
->gpio_num
;
358 bank_irq
= soc_info
->gpio_irq
;
360 printk(KERN_ERR
"Don't know first GPIO bank IRQ.\n");
364 clk
= clk_get(NULL
, "gpio");
366 printk(KERN_ERR
"Error %ld getting gpio clock?\n",
372 /* Arrange gpio_to_irq() support, handling either direct IRQs or
373 * banked IRQs. Having GPIOs in the first GPIO bank use direct
374 * IRQs, while the others use banked IRQs, would need some setup
375 * tweaks to recognize hardware which can do that.
377 for (gpio
= 0, bank
= 0; gpio
< ngpio
; bank
++, gpio
+= 32) {
378 chips
[bank
].chip
.to_irq
= gpio_to_irq_banked
;
379 chips
[bank
].irq_base
= soc_info
->gpio_unbanked
381 : (soc_info
->intc_irq_num
+ gpio
);
385 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
386 * controller only handling trigger modes. We currently assume no
387 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
389 if (soc_info
->gpio_unbanked
) {
390 static struct irq_chip gpio_irqchip_unbanked
;
392 /* pass "bank 0" GPIO IRQs to AINTC */
393 chips
[0].chip
.to_irq
= gpio_to_irq_unbanked
;
396 /* AINTC handles mask/unmask; GPIO handles triggering */
398 gpio_irqchip_unbanked
= *get_irq_desc_chip(irq_to_desc(irq
));
399 gpio_irqchip_unbanked
.name
= "GPIO-AINTC";
400 gpio_irqchip_unbanked
.irq_set_type
= gpio_irq_type_unbanked
;
402 /* default trigger: both edges */
404 __raw_writel(~0, &g
->set_falling
);
405 __raw_writel(~0, &g
->set_rising
);
407 /* set the direct IRQs up to use that irqchip */
408 for (gpio
= 0; gpio
< soc_info
->gpio_unbanked
; gpio
++, irq
++) {
409 set_irq_chip(irq
, &gpio_irqchip_unbanked
);
410 set_irq_data(irq
, (void *) __gpio_mask(gpio
));
411 set_irq_chip_data(irq
, (__force
void *) g
);
412 irq_desc
[irq
].status
|= IRQ_TYPE_EDGE_BOTH
;
419 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
420 * then chain through our own handler.
422 for (gpio
= 0, irq
= gpio_to_irq(0), bank
= 0;
424 bank
++, bank_irq
++) {
427 /* disabled by default, enabled only as needed */
429 __raw_writel(~0, &g
->clr_falling
);
430 __raw_writel(~0, &g
->clr_rising
);
432 /* set up all irqs in this bank */
433 set_irq_chained_handler(bank_irq
, gpio_irq_handler
);
434 set_irq_chip_data(bank_irq
, (__force
void *) g
);
435 set_irq_data(bank_irq
, (void *) irq
);
437 for (i
= 0; i
< 16 && gpio
< ngpio
; i
++, irq
++, gpio
++) {
438 set_irq_chip(irq
, &gpio_irqchip
);
439 set_irq_chip_data(irq
, (__force
void *) g
);
440 set_irq_data(irq
, (void *) __gpio_mask(gpio
));
441 set_irq_handler(irq
, handle_simple_irq
);
442 set_irq_flags(irq
, IRQF_VALID
);
449 /* BINTEN -- per-bank interrupt enable. genirq would also let these
450 * bits be set/cleared dynamically.
452 __raw_writel(binten
, gpio_base
+ 0x08);
454 printk(KERN_INFO
"DaVinci: %d gpio irqs\n", irq
- gpio_to_irq(0));