arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <plat/cpu.h>
  26 #include <plat/usb.h>
  27 #include <plat/clock.h>
  28 #include <plat/sram.h>
  29 #include <plat/clkdev_omap.h>
  30
  31 #include "clock.h"
  32 #include "opp.h"
  33
  34 __u32 arm_idlect1_mask;
  35 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
  36
  37 /*-------------------------------------------------------------------------
  38  * Omap1 specific clock functions
  39  *-------------------------------------------------------------------------*/
  40
  41 unsigned long omap1_uart_recalc(struct clk *clk)
  42 {
  43         unsigned int val = __raw_readl(clk->enable_reg);
  44         return val & clk->enable_bit ? 48000000 : 12000000;
  45 }
  46
  47 unsigned long omap1_sossi_recalc(struct clk *clk)
  48 {
  49         u32 div = omap_readl(MOD_CONF_CTRL_1);
  50
  51         div = (div >> 17) & 0x7;
  52         div++;
  53
  54         return clk->parent->rate / div;
  55 }
  56
  57 static void omap1_clk_allow_idle(struct clk *clk)
  58 {
  59         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
  60
  61         if (!(clk->flags & CLOCK_IDLE_CONTROL))
  62                 return;
  63
  64         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
  65                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
  66 }
  67
  68 static void omap1_clk_deny_idle(struct clk *clk)
  69 {
  70         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
  71
  72         if (!(clk->flags & CLOCK_IDLE_CONTROL))
  73                 return;
  74
  75         if (iclk->no_idle_count++ == 0)
  76                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
  77 }
  78
  79 static __u16 verify_ckctl_value(__u16 newval)
  80 {
  81         /* This function checks for following limitations set
  82          * by the hardware (all conditions must be true):
  83          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
  84          * ARM_CK >= TC_CK
  85          * DSP_CK >= TC_CK
  86          * DSPMMU_CK >= TC_CK
  87          *
  88          * In addition following rules are enforced:
  89          * LCD_CK <= TC_CK
  90          * ARMPER_CK <= TC_CK
  91          *
  92          * However, maximum frequencies are not checked for!
  93          */
  94         __u8 per_exp;
  95         __u8 lcd_exp;
  96         __u8 arm_exp;
  97         __u8 dsp_exp;
  98         __u8 tc_exp;
  99         __u8 dspmmu_exp;
 100
 101         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 102         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 103         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 104         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 105         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 106         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 107
 108         if (dspmmu_exp < dsp_exp)
 109                 dspmmu_exp = dsp_exp;
 110         if (dspmmu_exp > dsp_exp+1)
 111                 dspmmu_exp = dsp_exp+1;
 112         if (tc_exp < arm_exp)
 113                 tc_exp = arm_exp;
 114         if (tc_exp < dspmmu_exp)
 115                 tc_exp = dspmmu_exp;
 116         if (tc_exp > lcd_exp)
 117                 lcd_exp = tc_exp;
 118         if (tc_exp > per_exp)
 119                 per_exp = tc_exp;
 120
 121         newval &= 0xf000;
 122         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 123         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 124         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 125         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 126         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 127         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 128
 129         return newval;
 130 }
 131
 132 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 133 {
 134         /* Note: If target frequency is too low, this function will return 4,
 135          * which is invalid value. Caller must check for this value and act
 136          * accordingly.
 137          *
 138          * Note: This function does not check for following limitations set
 139          * by the hardware (all conditions must be true):
 140          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 141          * ARM_CK >= TC_CK
 142          * DSP_CK >= TC_CK
 143          * DSPMMU_CK >= TC_CK
 144          */
 145         unsigned long realrate;
 146         struct clk * parent;
 147         unsigned  dsor_exp;
 148
 149         parent = clk->parent;
 150         if (unlikely(parent == NULL))
 151                 return -EIO;
 152
 153         realrate = parent->rate;
 154         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 155                 if (realrate <= rate)
 156                         break;
 157
 158                 realrate /= 2;
 159         }
 160
 161         return dsor_exp;
 162 }
 163
 164 unsigned long omap1_ckctl_recalc(struct clk *clk)
 165 {
 166         /* Calculate divisor encoded as 2-bit exponent */
 167         int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 168
 169         return clk->parent->rate / dsor;
 170 }
 171
 172 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
 173 {
 174         int dsor;
 175
 176         /* Calculate divisor encoded as 2-bit exponent
 177          *
 178          * The clock control bits are in DSP domain,
 179          * so api_ck is needed for access.
 180          * Note that DSP_CKCTL virt addr = phys addr, so
 181          * we must use __raw_readw() instead of omap_readw().
 182          */
 183         omap1_clk_enable(api_ck_p);
 184         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 185         omap1_clk_disable(api_ck_p);
 186
 187         return clk->parent->rate / dsor;
 188 }
 189
 190 /* MPU virtual clock functions */
 191 int omap1_select_table_rate(struct clk *clk, unsigned long rate)
 192 {
 193         /* Find the highest supported frequency <= rate and switch to it */
 194         struct mpu_rate * ptr;
 195         unsigned long dpll1_rate, ref_rate;
 196
 197         dpll1_rate = ck_dpll1_p->rate;
 198         ref_rate = ck_ref_p->rate;
 199
 200         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
 201                 if (ptr->xtal != ref_rate)
 202                         continue;
 203
 204                 /* DPLL1 cannot be reprogrammed without risking system crash */
 205                 if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
 206                         continue;
 207
 208                 /* Can check only after xtal frequency check */
 209                 if (ptr->rate <= rate)
 210                         break;
 211         }
 212
 213         if (!ptr->rate)
 214                 return -EINVAL;
 215
 216         /*
 217          * In most cases we should not need to reprogram DPLL.
 218          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 219          * (on 730, bit 13 must always be 1)
 220          */
 221         if (cpu_is_omap7xx())
 222                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 223         else
 224                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 225
 226         /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
 227         ck_dpll1_p->rate = ptr->pll_rate;
 228
 229         return 0;
 230 }
 231
 232 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 233 {
 234         int dsor_exp;
 235         u16 regval;
 236
 237         dsor_exp = calc_dsor_exp(clk, rate);
 238         if (dsor_exp > 3)
 239                 dsor_exp = -EINVAL;
 240         if (dsor_exp < 0)
 241                 return dsor_exp;
 242
 243         regval = __raw_readw(DSP_CKCTL);
 244         regval &= ~(3 << clk->rate_offset);
 245         regval |= dsor_exp << clk->rate_offset;
 246         __raw_writew(regval, DSP_CKCTL);
 247         clk->rate = clk->parent->rate / (1 << dsor_exp);
 248
 249         return 0;
 250 }
 251
 252 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 253 {
 254         int dsor_exp = calc_dsor_exp(clk, rate);
 255         if (dsor_exp < 0)
 256                 return dsor_exp;
 257         if (dsor_exp > 3)
 258                 dsor_exp = 3;
 259         return clk->parent->rate / (1 << dsor_exp);
 260 }
 261
 262 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 263 {
 264         int dsor_exp;
 265         u16 regval;
 266
 267         dsor_exp = calc_dsor_exp(clk, rate);
 268         if (dsor_exp > 3)
 269                 dsor_exp = -EINVAL;
 270         if (dsor_exp < 0)
 271                 return dsor_exp;
 272
 273         regval = omap_readw(ARM_CKCTL);
 274         regval &= ~(3 << clk->rate_offset);
 275         regval |= dsor_exp << clk->rate_offset;
 276         regval = verify_ckctl_value(regval);
 277         omap_writew(regval, ARM_CKCTL);
 278         clk->rate = clk->parent->rate / (1 << dsor_exp);
 279         return 0;
 280 }
 281
 282 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
 283 {
 284         /* Find the highest supported frequency <= rate */
 285         struct mpu_rate * ptr;
 286         long highest_rate;
 287         unsigned long ref_rate;
 288
 289         ref_rate = ck_ref_p->rate;
 290
 291         highest_rate = -EINVAL;
 292
 293         for (ptr = omap1_rate_table; ptr->rate; ptr++) {
 294                 if (ptr->xtal != ref_rate)
 295                         continue;
 296
 297                 highest_rate = ptr->rate;
 298
 299                 /* Can check only after xtal frequency check */
 300                 if (ptr->rate <= rate)
 301                         break;
 302         }
 303
 304         return highest_rate;
 305 }
 306
 307 static unsigned calc_ext_dsor(unsigned long rate)
 308 {
 309         unsigned dsor;
 310
 311         /* MCLK and BCLK divisor selection is not linear:
 312          * freq = 96MHz / dsor
 313          *
 314          * RATIO_SEL range: dsor <-> RATIO_SEL
 315          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 316          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 317          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 318          * can not be used.
 319          */
 320         for (dsor = 2; dsor < 96; ++dsor) {
 321                 if ((dsor & 1) && dsor > 8)
 322                         continue;
 323                 if (rate >= 96000000 / dsor)
 324                         break;
 325         }
 326         return dsor;
 327 }
 328
 329 /* XXX Only needed on 1510 */
 330 int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
 331 {
 332         unsigned int val;
 333
 334         val = __raw_readl(clk->enable_reg);
 335         if (rate == 12000000)
 336                 val &= ~(1 << clk->enable_bit);
 337         else if (rate == 48000000)
 338                 val |= (1 << clk->enable_bit);
 339         else
 340                 return -EINVAL;
 341         __raw_writel(val, clk->enable_reg);
 342         clk->rate = rate;
 343
 344         return 0;
 345 }
 346
 347 /* External clock (MCLK & BCLK) functions */
 348 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
 349 {
 350         unsigned dsor;
 351         __u16 ratio_bits;
 352
 353         dsor = calc_ext_dsor(rate);
 354         clk->rate = 96000000 / dsor;
 355         if (dsor > 8)
 356                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 357         else
 358                 ratio_bits = (dsor - 2) << 2;
 359
 360         ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
 361         __raw_writew(ratio_bits, clk->enable_reg);
 362
 363         return 0;
 364 }
 365
 366 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 367 {
 368         u32 l;
 369         int div;
 370         unsigned long p_rate;
 371
 372         p_rate = clk->parent->rate;
 373         /* Round towards slower frequency */
 374         div = (p_rate + rate - 1) / rate;
 375         div--;
 376         if (div < 0 || div > 7)
 377                 return -EINVAL;
 378
 379         l = omap_readl(MOD_CONF_CTRL_1);
 380         l &= ~(7 << 17);
 381         l |= div << 17;
 382         omap_writel(l, MOD_CONF_CTRL_1);
 383
 384         clk->rate = p_rate / (div + 1);
 385
 386         return 0;
 387 }
 388
 389 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
 390 {
 391         return 96000000 / calc_ext_dsor(rate);
 392 }
 393
 394 void omap1_init_ext_clk(struct clk *clk)
 395 {
 396         unsigned dsor;
 397         __u16 ratio_bits;
 398
 399         /* Determine current rate and ensure clock is based on 96MHz APLL */
 400         ratio_bits = __raw_readw(clk->enable_reg) & ~1;
 401         __raw_writew(ratio_bits, clk->enable_reg);
 402
 403         ratio_bits = (ratio_bits & 0xfc) >> 2;
 404         if (ratio_bits > 6)
 405                 dsor = (ratio_bits - 6) * 2 + 8;
 406         else
 407                 dsor = ratio_bits + 2;
 408
 409         clk-> rate = 96000000 / dsor;
 410 }
 411
 412 int omap1_clk_enable(struct clk *clk)
 413 {
 414         int ret = 0;
 415
 416         if (clk->usecount++ == 0) {
 417                 if (clk->parent) {
 418                         ret = omap1_clk_enable(clk->parent);
 419                         if (ret)
 420                                 goto err;
 421
 422                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 423                                 omap1_clk_deny_idle(clk->parent);
 424                 }
 425
 426                 ret = clk->ops->enable(clk);
 427                 if (ret) {
 428                         if (clk->parent)
 429                                 omap1_clk_disable(clk->parent);
 430                         goto err;
 431                 }
 432         }
 433         return ret;
 434
 435 err:
 436         clk->usecount--;
 437         return ret;
 438 }
 439
 440 void omap1_clk_disable(struct clk *clk)
 441 {
 442         if (clk->usecount > 0 && !(--clk->usecount)) {
 443                 clk->ops->disable(clk);
 444                 if (likely(clk->parent)) {
 445                         omap1_clk_disable(clk->parent);
 446                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 447                                 omap1_clk_allow_idle(clk->parent);
 448                 }
 449         }
 450 }
 451
 452 static int omap1_clk_enable_generic(struct clk *clk)
 453 {
 454         __u16 regval16;
 455         __u32 regval32;
 456
 457         if (unlikely(clk->enable_reg == NULL)) {
 458                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 459                        clk->name);
 460                 return -EINVAL;
 461         }
 462
 463         if (clk->flags & ENABLE_REG_32BIT) {
 464                 regval32 = __raw_readl(clk->enable_reg);
 465                 regval32 |= (1 << clk->enable_bit);
 466                 __raw_writel(regval32, clk->enable_reg);
 467         } else {
 468                 regval16 = __raw_readw(clk->enable_reg);
 469                 regval16 |= (1 << clk->enable_bit);
 470                 __raw_writew(regval16, clk->enable_reg);
 471         }
 472
 473         return 0;
 474 }
 475
 476 static void omap1_clk_disable_generic(struct clk *clk)
 477 {
 478         __u16 regval16;
 479         __u32 regval32;
 480
 481         if (clk->enable_reg == NULL)
 482                 return;
 483
 484         if (clk->flags & ENABLE_REG_32BIT) {
 485                 regval32 = __raw_readl(clk->enable_reg);
 486                 regval32 &= ~(1 << clk->enable_bit);
 487                 __raw_writel(regval32, clk->enable_reg);
 488         } else {
 489                 regval16 = __raw_readw(clk->enable_reg);
 490                 regval16 &= ~(1 << clk->enable_bit);
 491                 __raw_writew(regval16, clk->enable_reg);
 492         }
 493 }
 494
 495 const struct clkops clkops_generic = {
 496         .enable         = omap1_clk_enable_generic,
 497         .disable        = omap1_clk_disable_generic,
 498 };
 499
 500 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 501 {
 502         int retval;
 503
 504         retval = omap1_clk_enable(api_ck_p);
 505         if (!retval) {
 506                 retval = omap1_clk_enable_generic(clk);
 507                 omap1_clk_disable(api_ck_p);
 508         }
 509
 510         return retval;
 511 }
 512
 513 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 514 {
 515         if (omap1_clk_enable(api_ck_p) == 0) {
 516                 omap1_clk_disable_generic(clk);
 517                 omap1_clk_disable(api_ck_p);
 518         }
 519 }
 520
 521 const struct clkops clkops_dspck = {
 522         .enable         = omap1_clk_enable_dsp_domain,
 523         .disable        = omap1_clk_disable_dsp_domain,
 524 };
 525
 526 static int omap1_clk_enable_uart_functional(struct clk *clk)
 527 {
 528         int ret;
 529         struct uart_clk *uclk;
 530
 531         ret = omap1_clk_enable_generic(clk);
 532         if (ret == 0) {
 533                 /* Set smart idle acknowledgement mode */
 534                 uclk = (struct uart_clk *)clk;
 535                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 536                             uclk->sysc_addr);
 537         }
 538
 539         return ret;
 540 }
 541
 542 static void omap1_clk_disable_uart_functional(struct clk *clk)
 543 {
 544         struct uart_clk *uclk;
 545
 546         /* Set force idle acknowledgement mode */
 547         uclk = (struct uart_clk *)clk;
 548         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 549
 550         omap1_clk_disable_generic(clk);
 551 }
 552
 553 const struct clkops clkops_uart = {
 554         .enable         = omap1_clk_enable_uart_functional,
 555         .disable        = omap1_clk_disable_uart_functional,
 556 };
 557
 558 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 559 {
 560         if (clk->round_rate != NULL)
 561                 return clk->round_rate(clk, rate);
 562
 563         return clk->rate;
 564 }
 565
 566 int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 567 {
 568         int  ret = -EINVAL;
 569
 570         if (clk->set_rate)
 571                 ret = clk->set_rate(clk, rate);
 572         return ret;
 573 }
 574
 575 /*-------------------------------------------------------------------------
 576  * Omap1 clock reset and init functions
 577  *-------------------------------------------------------------------------*/
 578
 579 #ifdef CONFIG_OMAP_RESET_CLOCKS
 580
 581 void __init omap1_clk_disable_unused(struct clk *clk)
 582 {
 583         __u32 regval32;
 584
 585         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 586          * has not enabled any DSP clocks */
 587         if (clk->enable_reg == DSP_IDLECT2) {
 588                 printk(KERN_INFO "Skipping reset check for DSP domain "
 589                        "clock \"%s\"\n", clk->name);
 590                 return;
 591         }
 592
 593         /* Is the clock already disabled? */
 594         if (clk->flags & ENABLE_REG_32BIT)
 595                 regval32 = __raw_readl(clk->enable_reg);
 596         else
 597                 regval32 = __raw_readw(clk->enable_reg);
 598
 599         if ((regval32 & (1 << clk->enable_bit)) == 0)
 600                 return;
 601
 602         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 603         clk->ops->disable(clk);
 604         printk(" done\n");
 605 }
 606
 607 #endif