2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
27 #include <linux/types.h>
28 #include <net/mac80211.h>
30 /* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
34 /* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
41 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
42 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
43 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
44 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
45 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
46 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
47 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
48 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
49 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
58 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
64 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
65 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
66 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
67 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
68 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
70 /****************************\
71 GENERIC DRIVER DEFINITIONS
72 \****************************/
74 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
76 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
77 printk(_level "ath5k %s: " _fmt, \
78 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
81 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
82 if (net_ratelimit()) \
83 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
86 #define ATH5K_INFO(_sc, _fmt, ...) \
87 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
89 #define ATH5K_WARN(_sc, _fmt, ...) \
90 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
92 #define ATH5K_ERR(_sc, _fmt, ...) \
93 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
96 * AR5K REGISTER ACCESS
99 /* Some macros to read/write fields */
101 /* First shift, then mask */
102 #define AR5K_REG_SM(_val, _flags) \
103 (((_val) << _flags##_S) & (_flags))
105 /* First mask, then shift */
106 #define AR5K_REG_MS(_val, _flags) \
107 (((_val) & (_flags)) >> _flags##_S)
109 /* Some registers can hold multiple values of interest. For this
110 * reason when we want to write to these registers we must first
111 * retrieve the values which we do not want to clear (lets call this
112 * old_data) and then set the register with this and our new_value:
113 * ( old_data | new_value) */
114 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
115 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
116 (((_val) << _flags##_S) & (_flags)), _reg)
118 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
119 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
120 (_mask)) | (_flags), _reg)
122 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
123 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
125 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
126 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
128 /* Access to PHY registers */
129 #define AR5K_PHY_READ(ah, _reg) \
130 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
132 #define AR5K_PHY_WRITE(ah, _reg, _val) \
133 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
135 /* Access QCU registers per queue */
136 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
137 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
139 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
140 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
142 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
143 _reg |= 1 << _queue; \
146 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
147 _reg &= ~(1 << _queue); \
150 /* Used while writing initvals */
151 #define AR5K_REG_WAIT(_i) do { \
156 /* Register dumps are done per operation mode */
157 #define AR5K_INI_RFGAIN_5GHZ 0
158 #define AR5K_INI_RFGAIN_2GHZ 1
160 /* TODO: Clean this up */
161 #define AR5K_INI_VAL_11A 0
162 #define AR5K_INI_VAL_11A_TURBO 1
163 #define AR5K_INI_VAL_11B 2
164 #define AR5K_INI_VAL_11G 3
165 #define AR5K_INI_VAL_11G_TURBO 4
166 #define AR5K_INI_VAL_XR 0
167 #define AR5K_INI_VAL_MAX 5
170 * Some tuneable values (these should be changeable by the user)
171 * TODO: Make use of them and add more options OR use debug/configfs
173 #define AR5K_TUNE_DMA_BEACON_RESP 2
174 #define AR5K_TUNE_SW_BEACON_RESP 10
175 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
176 #define AR5K_TUNE_RADAR_ALERT false
177 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
178 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
179 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
180 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
181 * be the max value. */
182 #define AR5K_TUNE_RSSI_THRES 129
183 /* This must be set when setting the RSSI threshold otherwise it can
184 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
185 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
186 * track of it. Max value depends on harware. For AR5210 this is just 7.
187 * For AR5211+ this seems to be up to 255. */
188 #define AR5K_TUNE_BMISS_THRES 7
189 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
190 #define AR5K_TUNE_BEACON_INTERVAL 100
191 #define AR5K_TUNE_AIFS 2
192 #define AR5K_TUNE_AIFS_11B 2
193 #define AR5K_TUNE_AIFS_XR 0
194 #define AR5K_TUNE_CWMIN 15
195 #define AR5K_TUNE_CWMIN_11B 31
196 #define AR5K_TUNE_CWMIN_XR 3
197 #define AR5K_TUNE_CWMAX 1023
198 #define AR5K_TUNE_CWMAX_11B 1023
199 #define AR5K_TUNE_CWMAX_XR 7
200 #define AR5K_TUNE_NOISE_FLOOR -72
201 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
202 #define AR5K_TUNE_MAX_TXPOWER 63
203 #define AR5K_TUNE_DEFAULT_TXPOWER 25
204 #define AR5K_TUNE_TPC_TXPOWER false
205 #define AR5K_TUNE_HWTXTRIES 4
207 #define AR5K_INIT_CARR_SENSE_EN 1
209 /*Swap RX/TX Descriptor for big endian archs*/
210 #if defined(__BIG_ENDIAN)
211 #define AR5K_INIT_CFG ( \
212 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
215 #define AR5K_INIT_CFG 0x00000000
219 #define AR5K_INIT_CYCRSSI_THR1 2
220 #define AR5K_INIT_TX_LATENCY 502
221 #define AR5K_INIT_USEC 39
222 #define AR5K_INIT_USEC_TURBO 79
223 #define AR5K_INIT_USEC_32 31
224 #define AR5K_INIT_SLOT_TIME 396
225 #define AR5K_INIT_SLOT_TIME_TURBO 480
226 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
227 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
228 #define AR5K_INIT_PROG_IFS 920
229 #define AR5K_INIT_PROG_IFS_TURBO 960
230 #define AR5K_INIT_EIFS 3440
231 #define AR5K_INIT_EIFS_TURBO 6880
232 #define AR5K_INIT_SIFS 560
233 #define AR5K_INIT_SIFS_TURBO 480
234 #define AR5K_INIT_SH_RETRY 10
235 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
236 #define AR5K_INIT_SSH_RETRY 32
237 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
238 #define AR5K_INIT_TX_RETRY 10
240 #define AR5K_INIT_TRANSMIT_LATENCY ( \
241 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
244 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
245 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
246 (AR5K_INIT_USEC_TURBO) \
248 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
249 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
250 (AR5K_INIT_PROG_IFS) \
252 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
253 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
254 (AR5K_INIT_PROG_IFS_TURBO) \
257 /* token to use for aifs, cwmin, cwmax in MadWiFi */
258 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
260 /* GENERIC CHIPSET DEFINITIONS */
282 * Common silicon revision/version values
285 enum ath5k_srev_type
{
290 struct ath5k_srev_name
{
292 enum ath5k_srev_type sr_type
;
296 #define AR5K_SREV_UNKNOWN 0xffff
298 #define AR5K_SREV_AR5210 0x00 /* Crete */
299 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
300 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
301 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
302 #define AR5K_SREV_AR5211 0x40 /* Oahu */
303 #define AR5K_SREV_AR5212 0x50 /* Venice */
304 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
305 #define AR5K_SREV_AR5213 0x55 /* ??? */
306 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
307 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
308 #define AR5K_SREV_AR2414 0x70 /* Griffin */
309 #define AR5K_SREV_AR5424 0x90 /* Condor */
310 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
311 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
312 #define AR5K_SREV_AR2415 0xb0 /* Talon */
313 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
314 #define AR5K_SREV_AR5418 0xca /* PCI-E */
315 #define AR5K_SREV_AR2425 0xe0 /* Swan */
316 #define AR5K_SREV_AR2417 0xf0 /* Nala */
318 #define AR5K_SREV_RAD_5110 0x00
319 #define AR5K_SREV_RAD_5111 0x10
320 #define AR5K_SREV_RAD_5111A 0x15
321 #define AR5K_SREV_RAD_2111 0x20
322 #define AR5K_SREV_RAD_5112 0x30
323 #define AR5K_SREV_RAD_5112A 0x35
324 #define AR5K_SREV_RAD_5112B 0x36
325 #define AR5K_SREV_RAD_2112 0x40
326 #define AR5K_SREV_RAD_2112A 0x45
327 #define AR5K_SREV_RAD_2112B 0x46
328 #define AR5K_SREV_RAD_2413 0x50
329 #define AR5K_SREV_RAD_5413 0x60
330 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
331 #define AR5K_SREV_RAD_2317 0x80
332 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
333 #define AR5K_SREV_RAD_2425 0xa2
334 #define AR5K_SREV_RAD_5133 0xc0
336 #define AR5K_SREV_PHY_5211 0x30
337 #define AR5K_SREV_PHY_5212 0x41
338 #define AR5K_SREV_PHY_5212A 0x42
339 #define AR5K_SREV_PHY_5212B 0x43
340 #define AR5K_SREV_PHY_2413 0x45
341 #define AR5K_SREV_PHY_5413 0x61
342 #define AR5K_SREV_PHY_2425 0x70
345 #define IEEE80211_MAX_LEN 2500
347 /* TODO add support to mac80211 for vendor-specific rates and modes */
350 * Some of this information is based on Documentation from:
352 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
354 * Modulation for Atheros' eXtended Range - range enhancing extension that is
355 * supposed to double the distance an Atheros client device can keep a
356 * connection with an Atheros access point. This is achieved by increasing
357 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
358 * the 802.11 specifications demand. In addition, new (proprietary) data rates
359 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
361 * Please note that can you either use XR or TURBO but you cannot use both,
362 * they are exclusive.
365 #define MODULATION_XR 0x00000200
367 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
368 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
369 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
370 * channels. To use this feature your Access Point must also suport it.
371 * There is also a distinction between "static" and "dynamic" turbo modes:
373 * - Static: is the dumb version: devices set to this mode stick to it until
374 * the mode is turned off.
375 * - Dynamic: is the intelligent version, the network decides itself if it
376 * is ok to use turbo. As soon as traffic is detected on adjacent channels
377 * (which would get used in turbo mode), or when a non-turbo station joins
378 * the network, turbo mode won't be used until the situation changes again.
379 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
380 * monitors the used radio band in order to decide whether turbo mode may
383 * This article claims Super G sticks to bonding of channels 5 and 6 for
386 * http://www.pcworld.com/article/id,113428-page,1/article.html
388 * The channel bonding seems to be driver specific though. In addition to
389 * deciding what channels will be used, these "Turbo" modes are accomplished
390 * by also enabling the following features:
392 * - Bursting: allows multiple frames to be sent at once, rather than pausing
393 * after each frame. Bursting is a standards-compliant feature that can be
394 * used with any Access Point.
395 * - Fast frames: increases the amount of information that can be sent per
396 * frame, also resulting in a reduction of transmission overhead. It is a
397 * proprietary feature that needs to be supported by the Access Point.
398 * - Compression: data frames are compressed in real time using a Lempel Ziv
399 * algorithm. This is done transparently. Once this feature is enabled,
400 * compression and decompression takes place inside the chipset, without
401 * putting additional load on the host CPU.
404 #define MODULATION_TURBO 0x00000080
406 enum ath5k_driver_mode
{
408 AR5K_MODE_11A_TURBO
= 1,
411 AR5K_MODE_11G_TURBO
= 4,
416 enum ath5k_ant_mode
{
417 AR5K_ANTMODE_DEFAULT
= 0, /* default antenna setup */
418 AR5K_ANTMODE_FIXED_A
= 1, /* only antenna A is present */
419 AR5K_ANTMODE_FIXED_B
= 2, /* only antenna B is present */
420 AR5K_ANTMODE_SINGLE_AP
= 3, /* sta locked on a single ap */
421 AR5K_ANTMODE_SECTOR_AP
= 4, /* AP with tx antenna set on tx desc */
422 AR5K_ANTMODE_SECTOR_STA
= 5, /* STA with tx antenna set on tx desc */
423 AR5K_ANTMODE_DEBUG
= 6, /* Debug mode -A -> Rx, B-> Tx- */
433 * TX Status descriptor
435 struct ath5k_tx_status
{
449 #define AR5K_TXSTAT_ALTRATE 0x80
450 #define AR5K_TXERR_XRETRY 0x01
451 #define AR5K_TXERR_FILT 0x02
452 #define AR5K_TXERR_FIFO 0x04
455 * enum ath5k_tx_queue - Queue types used to classify tx queues.
456 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
457 * @AR5K_TX_QUEUE_DATA: A normal data queue
458 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
459 * @AR5K_TX_QUEUE_BEACON: The beacon queue
460 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
461 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
463 enum ath5k_tx_queue
{
464 AR5K_TX_QUEUE_INACTIVE
= 0,
466 AR5K_TX_QUEUE_XR_DATA
,
467 AR5K_TX_QUEUE_BEACON
,
472 #define AR5K_NUM_TX_QUEUES 10
473 #define AR5K_NUM_TX_QUEUES_NOQCU 2
476 * Queue syb-types to classify normal data queues.
477 * These are the 4 Access Categories as defined in
478 * WME spec. 0 is the lowest priority and 4 is the
479 * highest. Normal data that hasn't been classified
480 * goes to the Best Effort AC.
482 enum ath5k_tx_queue_subtype
{
483 AR5K_WME_AC_BK
= 0, /*Background traffic*/
484 AR5K_WME_AC_BE
, /*Best-effort (normal) traffic)*/
485 AR5K_WME_AC_VI
, /*Video traffic*/
486 AR5K_WME_AC_VO
, /*Voice traffic*/
490 * Queue ID numbers as returned by the hw functions, each number
491 * represents a hw queue. If hw does not support hw queues
492 * (eg 5210) all data goes in one queue. These match
493 * d80211 definitions (net80211/MadWiFi don't use them).
495 enum ath5k_tx_queue_id
{
496 AR5K_TX_QUEUE_ID_NOQCU_DATA
= 0,
497 AR5K_TX_QUEUE_ID_NOQCU_BEACON
= 1,
498 AR5K_TX_QUEUE_ID_DATA_MIN
= 0, /*IEEE80211_TX_QUEUE_DATA0*/
499 AR5K_TX_QUEUE_ID_DATA_MAX
= 4, /*IEEE80211_TX_QUEUE_DATA4*/
500 AR5K_TX_QUEUE_ID_DATA_SVP
= 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
501 AR5K_TX_QUEUE_ID_CAB
= 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
502 AR5K_TX_QUEUE_ID_BEACON
= 7, /*IEEE80211_TX_QUEUE_BEACON*/
503 AR5K_TX_QUEUE_ID_UAPSD
= 8,
504 AR5K_TX_QUEUE_ID_XR_DATA
= 9,
508 * Flags to set hw queue's parameters...
510 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
511 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
512 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
513 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
514 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
515 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
516 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
517 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
518 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
519 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
520 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
521 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
522 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
523 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
526 * A struct to hold tx queue's parameters
528 struct ath5k_txq_info
{
529 enum ath5k_tx_queue tqi_type
;
530 enum ath5k_tx_queue_subtype tqi_subtype
;
531 u16 tqi_flags
; /* Tx queue flags (see above) */
532 u32 tqi_aifs
; /* Arbitrated Interframe Space */
533 s32 tqi_cw_min
; /* Minimum Contention Window */
534 s32 tqi_cw_max
; /* Maximum Contention Window */
535 u32 tqi_cbr_period
; /* Constant bit rate period */
536 u32 tqi_cbr_overflow_limit
;
538 u32 tqi_ready_time
; /* Time queue waits after an event */
542 * Transmit packet types.
543 * used on tx control descriptor
545 enum ath5k_pkt_type
{
546 AR5K_PKT_TYPE_NORMAL
= 0,
547 AR5K_PKT_TYPE_ATIM
= 1,
548 AR5K_PKT_TYPE_PSPOLL
= 2,
549 AR5K_PKT_TYPE_BEACON
= 3,
550 AR5K_PKT_TYPE_PROBE_RESP
= 4,
551 AR5K_PKT_TYPE_PIFS
= 5,
555 * TX power and TPC settings
557 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
558 ((0 & 1) << ((_v) + 6)) | \
559 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
562 #define AR5K_TXPOWER_CCK(_r, _v) ( \
563 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
567 * DMA size definitions (2^n+2)
586 * RX Status descriptor
588 struct ath5k_rx_status
{
600 #define AR5K_RXERR_CRC 0x01
601 #define AR5K_RXERR_PHY 0x02
602 #define AR5K_RXERR_FIFO 0x04
603 #define AR5K_RXERR_DECRYPT 0x08
604 #define AR5K_RXERR_MIC 0x10
605 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
606 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
609 /**************************\
610 BEACON TIMERS DEFINITIONS
611 \**************************/
613 #define AR5K_BEACON_PERIOD 0x0000ffff
614 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
615 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
619 * struct ath5k_beacon_state - Per-station beacon timer state.
620 * @bs_interval: in TU's, can also include the above flags
621 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
622 * Point Coordination Function capable AP
624 struct ath5k_beacon_state
{
630 u16 bs_cfp_max_duration
;
631 u16 bs_cfp_du_remain
;
633 u16 bs_sleep_duration
;
634 u16 bs_bmiss_threshold
;
641 * TSF to TU conversion:
643 * TSF is a 64bit value in usec (microseconds).
644 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
645 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
647 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
650 /*******************************\
651 GAIN OPTIMIZATION DEFINITIONS
652 \*******************************/
655 AR5K_RFGAIN_INACTIVE
= 0,
657 AR5K_RFGAIN_READ_REQUESTED
,
658 AR5K_RFGAIN_NEED_CHANGE
,
671 /********************\
673 \********************/
675 #define AR5K_SLOT_TIME_9 396
676 #define AR5K_SLOT_TIME_20 880
677 #define AR5K_SLOT_TIME_MAX 0xffff
680 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
681 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
682 #define CHANNEL_CCK 0x0020 /* CCK channel */
683 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
684 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
685 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
686 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
687 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
688 #define CHANNEL_XR 0x0800 /* XR channel */
690 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
691 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
692 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
693 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
694 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
695 #define CHANNEL_108A CHANNEL_T
696 #define CHANNEL_108G CHANNEL_TG
697 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
699 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
702 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
703 #define CHANNEL_MODES CHANNEL_ALL
706 * Used internaly for reset_tx_queue).
707 * Also see struct struct ieee80211_channel.
709 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
710 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
713 * The following structure is used to map 2GHz channels to
714 * 5GHz Atheros channels.
717 struct ath5k_athchan_2ghz
{
728 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
730 * The rate code is used to get the RX rate or set the TX rate on the
731 * hardware descriptors. It is also used for internal modulation control
734 * This is the hardware rate map we are aware of:
736 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
737 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
739 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
740 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
742 * rate_code 17 18 19 20 21 22 23 24
743 * rate_kbps ? ? ? ? ? ? ? 11000
745 * rate_code 25 26 27 28 29 30 31 32
746 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
748 * "S" indicates CCK rates with short preamble.
750 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
751 * lowest 4 bits, so they are the same as below with a 0xF mask.
752 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
753 * We handle this in ath5k_setup_bands().
755 #define AR5K_MAX_RATES 32
758 #define ATH5K_RATE_CODE_1M 0x1B
759 #define ATH5K_RATE_CODE_2M 0x1A
760 #define ATH5K_RATE_CODE_5_5M 0x19
761 #define ATH5K_RATE_CODE_11M 0x18
763 #define ATH5K_RATE_CODE_6M 0x0B
764 #define ATH5K_RATE_CODE_9M 0x0F
765 #define ATH5K_RATE_CODE_12M 0x0A
766 #define ATH5K_RATE_CODE_18M 0x0E
767 #define ATH5K_RATE_CODE_24M 0x09
768 #define ATH5K_RATE_CODE_36M 0x0D
769 #define ATH5K_RATE_CODE_48M 0x08
770 #define ATH5K_RATE_CODE_54M 0x0C
772 #define ATH5K_RATE_CODE_XR_500K 0x07
773 #define ATH5K_RATE_CODE_XR_1M 0x02
774 #define ATH5K_RATE_CODE_XR_2M 0x06
775 #define ATH5K_RATE_CODE_XR_3M 0x01
777 /* adding this flag to rate_code enables short preamble */
778 #define AR5K_SET_SHORT_PREAMBLE 0x04
784 #define AR5K_KEYCACHE_SIZE 8
786 /***********************\
787 HW RELATED DEFINITIONS
788 \***********************/
793 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
795 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
801 * Hardware interrupt abstraction
805 * enum ath5k_int - Hardware interrupt masks helpers
807 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
808 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
809 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
810 * @AR5K_INT_RXNOFRM: No frame received (?)
811 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
812 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
813 * LinkPtr is NULL. For more details, refer to:
814 * http://www.freepatentsonline.com/20030225739.html
815 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
816 * Note that Rx overrun is not always fatal, on some chips we can continue
817 * operation without reseting the card, that's why int_fatal is not
818 * common for all chips.
819 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
820 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
821 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
822 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
823 * We currently do increments on interrupt by
824 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
825 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
826 * checked. We should do this with ath5k_hw_update_mib_counters() but
827 * it seems we should also then do some noise immunity work.
828 * @AR5K_INT_RXPHY: RX PHY Error
829 * @AR5K_INT_RXKCM: RX Key cache miss
830 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
831 * beacon that must be handled in software. The alternative is if you
832 * have VEOL support, in that case you let the hardware deal with things.
833 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
834 * beacons from the AP have associated with, we should probably try to
835 * reassociate. When in IBSS mode this might mean we have not received
836 * any beacons from any local stations. Note that every station in an
837 * IBSS schedules to send beacons at the Target Beacon Transmission Time
838 * (TBTT) with a random backoff.
839 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
840 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
841 * until properly handled
842 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
843 * errors. These types of errors we can enable seem to be of type
844 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
845 * @AR5K_INT_GLOBAL: Used to clear and set the IER
846 * @AR5K_INT_NOCARD: signals the card has been removed
847 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
850 * These are mapped to take advantage of some common bits
851 * between the MACs, to be able to set intr properties
852 * easier. Some of them are not used yet inside hw.c. Most map
853 * to the respective hw interrupt value as they are common amogst different
857 AR5K_INT_RXOK
= 0x00000001,
858 AR5K_INT_RXDESC
= 0x00000002,
859 AR5K_INT_RXERR
= 0x00000004,
860 AR5K_INT_RXNOFRM
= 0x00000008,
861 AR5K_INT_RXEOL
= 0x00000010,
862 AR5K_INT_RXORN
= 0x00000020,
863 AR5K_INT_TXOK
= 0x00000040,
864 AR5K_INT_TXDESC
= 0x00000080,
865 AR5K_INT_TXERR
= 0x00000100,
866 AR5K_INT_TXNOFRM
= 0x00000200,
867 AR5K_INT_TXEOL
= 0x00000400,
868 AR5K_INT_TXURN
= 0x00000800,
869 AR5K_INT_MIB
= 0x00001000,
870 AR5K_INT_SWI
= 0x00002000,
871 AR5K_INT_RXPHY
= 0x00004000,
872 AR5K_INT_RXKCM
= 0x00008000,
873 AR5K_INT_SWBA
= 0x00010000,
874 AR5K_INT_BRSSI
= 0x00020000,
875 AR5K_INT_BMISS
= 0x00040000,
876 AR5K_INT_FATAL
= 0x00080000, /* Non common */
877 AR5K_INT_BNR
= 0x00100000, /* Non common */
878 AR5K_INT_TIM
= 0x00200000, /* Non common */
879 AR5K_INT_DTIM
= 0x00400000, /* Non common */
880 AR5K_INT_DTIM_SYNC
= 0x00800000, /* Non common */
881 AR5K_INT_GPIO
= 0x01000000,
882 AR5K_INT_BCN_TIMEOUT
= 0x02000000, /* Non common */
883 AR5K_INT_CAB_TIMEOUT
= 0x04000000, /* Non common */
884 AR5K_INT_RX_DOPPLER
= 0x08000000, /* Non common */
885 AR5K_INT_QCBRORN
= 0x10000000, /* Non common */
886 AR5K_INT_QCBRURN
= 0x20000000, /* Non common */
887 AR5K_INT_QTRIG
= 0x40000000, /* Non common */
888 AR5K_INT_GLOBAL
= 0x80000000,
890 AR5K_INT_COMMON
= AR5K_INT_RXOK
912 AR5K_INT_NOCARD
= 0xffffffff
915 /* Software interrupts used for calibration */
916 enum ath5k_software_interrupt
{
917 AR5K_SWI_FULL_CALIBRATION
= 0x01,
918 AR5K_SWI_SHORT_CALIBRATION
= 0x02,
924 enum ath5k_power_mode
{
925 AR5K_PM_UNDEFINED
= 0,
929 AR5K_PM_NETWORK_SLEEP
,
933 * These match net80211 definitions (not used in
935 * TODO: Clean this up
937 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
938 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
939 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
940 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
941 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
943 /* GPIO-controlled software LED */
944 #define AR5K_SOFTLED_PIN 0
945 #define AR5K_SOFTLED_ON 0
946 #define AR5K_SOFTLED_OFF 1
949 * Chipset capabilities -see ath5k_hw_get_capability-
950 * get_capability function is not yet fully implemented
951 * in ath5k so most of these don't work yet...
952 * TODO: Implement these & merge with _TUNE_ stuff above
954 enum ath5k_capability_type
{
955 AR5K_CAP_REG_DMN
= 0, /* Used to get current reg. domain id */
956 AR5K_CAP_TKIP_MIC
= 2, /* Can handle TKIP MIC in hardware */
957 AR5K_CAP_TKIP_SPLIT
= 3, /* TKIP uses split keys */
958 AR5K_CAP_PHYCOUNTERS
= 4, /* PHY error counters */
959 AR5K_CAP_DIVERSITY
= 5, /* Supports fast diversity */
960 AR5K_CAP_NUM_TXQUEUES
= 6, /* Used to get max number of hw txqueues */
961 AR5K_CAP_VEOL
= 7, /* Supports virtual EOL */
962 AR5K_CAP_COMPRESSION
= 8, /* Supports compression */
963 AR5K_CAP_BURST
= 9, /* Supports packet bursting */
964 AR5K_CAP_FASTFRAME
= 10, /* Supports fast frames */
965 AR5K_CAP_TXPOW
= 11, /* Used to get global tx power limit */
966 AR5K_CAP_TPC
= 12, /* Can do per-packet tx power control (needed for 802.11a) */
967 AR5K_CAP_BSSIDMASK
= 13, /* Supports bssid mask */
968 AR5K_CAP_MCAST_KEYSRCH
= 14, /* Supports multicast key search */
969 AR5K_CAP_TSF_ADJUST
= 15, /* Supports beacon tsf adjust */
970 AR5K_CAP_XR
= 16, /* Supports XR mode */
971 AR5K_CAP_WME_TKIPMIC
= 17, /* Supports TKIP MIC when using WMM */
972 AR5K_CAP_CHAN_HALFRATE
= 18, /* Supports half rate channels */
973 AR5K_CAP_CHAN_QUARTERRATE
= 19, /* Supports quarter rate channels */
974 AR5K_CAP_RFSILENT
= 20, /* Supports RFsilent */
978 /* XXX: we *may* move cap_range stuff to struct wiphy */
979 struct ath5k_capabilities
{
981 * Supported PHY modes
982 * (ie. CHANNEL_A, CHANNEL_B, ...)
984 DECLARE_BITMAP(cap_mode
, AR5K_MODE_MAX
);
987 * Frequency range (without regulation restrictions)
997 * Values stored in the EEPROM (some of them...)
999 struct ath5k_eeprom_info cap_eeprom
;
1009 /* size of noise floor history (keep it a power of two) */
1010 #define ATH5K_NF_CAL_HIST_MAX 8
1011 struct ath5k_nfcal_hist
1013 s16 index
; /* current index into nfval */
1014 s16 nfval
[ATH5K_NF_CAL_HIST_MAX
]; /* last few noise floors */
1018 /***************************************\
1019 HARDWARE ABSTRACTION LAYER STRUCTURE
1020 \***************************************/
1026 #define AR5K_MAX_GPIO 10
1027 #define AR5K_MAX_RF_BANKS 8
1029 /* TODO: Clean up and merge with ath5k_softc */
1031 struct ath_common common
;
1033 struct ath5k_softc
*ah_sc
;
1034 void __iomem
*ah_iobase
;
1036 enum ath5k_int ah_imr
;
1038 struct ieee80211_channel
*ah_current_channel
;
1040 bool ah_calibration
;
1041 bool ah_single_chip
;
1042 bool ah_aes_support
;
1043 bool ah_combined_mic
;
1045 enum ath5k_version ah_version
;
1046 enum ath5k_radio ah_radio
;
1050 u16 ah_mac_revision
;
1051 u16 ah_phy_revision
;
1052 u16 ah_radio_5ghz_revision
;
1053 u16 ah_radio_2ghz_revision
;
1055 #define ah_modes ah_capabilities.cap_mode
1056 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1062 u32 ah_limit_tx_retries
;
1063 u8 ah_coverage_class
;
1065 /* Antenna Control */
1066 u32 ah_ant_ctl
[AR5K_EEPROM_N_MODES
][AR5K_ANT_MAX
];
1070 bool ah_software_retry
;
1074 struct ath5k_capabilities ah_capabilities
;
1076 struct ath5k_txq_info ah_txq
[AR5K_NUM_TX_QUEUES
];
1078 u32 ah_txq_imr_txok
;
1079 u32 ah_txq_imr_txerr
;
1080 u32 ah_txq_imr_txurn
;
1081 u32 ah_txq_imr_txdesc
;
1082 u32 ah_txq_imr_txeol
;
1083 u32 ah_txq_imr_cbrorn
;
1084 u32 ah_txq_imr_cbrurn
;
1085 u32 ah_txq_imr_qtrig
;
1086 u32 ah_txq_imr_nofrm
;
1089 size_t ah_rf_banks_size
;
1090 size_t ah_rf_regs_count
;
1091 struct ath5k_gain ah_gain
;
1092 u8 ah_offset
[AR5K_MAX_RF_BANKS
];
1096 /* Temporary tables used for interpolation */
1097 u8 tmpL
[AR5K_EEPROM_N_PD_GAINS
]
1098 [AR5K_EEPROM_POWER_TABLE_SIZE
];
1099 u8 tmpR
[AR5K_EEPROM_N_PD_GAINS
]
1100 [AR5K_EEPROM_POWER_TABLE_SIZE
];
1101 u8 txp_pd_table
[AR5K_EEPROM_POWER_TABLE_SIZE
* 2];
1102 u16 txp_rates_power_table
[AR5K_MAX_RATES
];
1105 /* Values in 0.25dB units */
1108 /* Values in 0.5dB units */
1111 s16 txp_cck_ofdm_gainf_delta
;
1112 /* Value in dB units */
1113 s16 txp_cck_ofdm_pwr_delta
;
1119 struct ieee80211_channel r_last_channel
;
1122 struct ath5k_nfcal_hist ah_nfcal_hist
;
1124 /* noise floor from last periodic calibration */
1127 /* Calibration timestamp */
1128 unsigned long ah_cal_tstamp
;
1130 /* Calibration interval (secs) */
1133 /* Software interrupt mask */
1139 int (*ah_setup_rx_desc
)(struct ath5k_hw
*ah
, struct ath5k_desc
*desc
,
1140 u32 size
, unsigned int flags
);
1141 int (*ah_setup_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1142 unsigned int, unsigned int, int, enum ath5k_pkt_type
,
1143 unsigned int, unsigned int, unsigned int, unsigned int,
1144 unsigned int, unsigned int, unsigned int, unsigned int);
1145 int (*ah_setup_mrr_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1146 unsigned int, unsigned int, unsigned int, unsigned int,
1147 unsigned int, unsigned int);
1148 int (*ah_proc_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1149 struct ath5k_tx_status
*);
1150 int (*ah_proc_rx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
1151 struct ath5k_rx_status
*);
1158 /* Attach/Detach Functions */
1159 int ath5k_hw_attach(struct ath5k_softc
*sc
);
1160 void ath5k_hw_detach(struct ath5k_hw
*ah
);
1163 int ath5k_init_leds(struct ath5k_softc
*sc
);
1164 void ath5k_led_enable(struct ath5k_softc
*sc
);
1165 void ath5k_led_off(struct ath5k_softc
*sc
);
1166 void ath5k_unregister_leds(struct ath5k_softc
*sc
);
1168 /* Reset Functions */
1169 int ath5k_hw_nic_wakeup(struct ath5k_hw
*ah
, int flags
, bool initial
);
1170 int ath5k_hw_on_hold(struct ath5k_hw
*ah
);
1171 int ath5k_hw_reset(struct ath5k_hw
*ah
, enum nl80211_iftype op_mode
,
1172 struct ieee80211_channel
*channel
, bool change_channel
);
1173 int ath5k_hw_register_timeout(struct ath5k_hw
*ah
, u32 reg
, u32 flag
, u32 val
,
1175 /* Power management functions */
1177 /* DMA Related Functions */
1178 void ath5k_hw_start_rx_dma(struct ath5k_hw
*ah
);
1179 int ath5k_hw_stop_rx_dma(struct ath5k_hw
*ah
);
1180 u32
ath5k_hw_get_rxdp(struct ath5k_hw
*ah
);
1181 void ath5k_hw_set_rxdp(struct ath5k_hw
*ah
, u32 phys_addr
);
1182 int ath5k_hw_start_tx_dma(struct ath5k_hw
*ah
, unsigned int queue
);
1183 int ath5k_hw_stop_tx_dma(struct ath5k_hw
*ah
, unsigned int queue
);
1184 u32
ath5k_hw_get_txdp(struct ath5k_hw
*ah
, unsigned int queue
);
1185 int ath5k_hw_set_txdp(struct ath5k_hw
*ah
, unsigned int queue
,
1187 int ath5k_hw_update_tx_triglevel(struct ath5k_hw
*ah
, bool increase
);
1188 /* Interrupt handling */
1189 bool ath5k_hw_is_intr_pending(struct ath5k_hw
*ah
);
1190 int ath5k_hw_get_isr(struct ath5k_hw
*ah
, enum ath5k_int
*interrupt_mask
);
1191 enum ath5k_int
ath5k_hw_set_imr(struct ath5k_hw
*ah
, enum ath5k_int new_mask
);
1192 void ath5k_hw_update_mib_counters(struct ath5k_hw
*ah
,
1193 struct ieee80211_low_level_stats
*stats
);
1195 /* EEPROM access functions */
1196 int ath5k_eeprom_init(struct ath5k_hw
*ah
);
1197 void ath5k_eeprom_detach(struct ath5k_hw
*ah
);
1198 int ath5k_eeprom_read_mac(struct ath5k_hw
*ah
, u8
*mac
);
1200 /* Protocol Control Unit Functions */
1201 extern int ath5k_hw_set_opmode(struct ath5k_hw
*ah
, enum nl80211_iftype opmode
);
1202 void ath5k_hw_set_coverage_class(struct ath5k_hw
*ah
, u8 coverage_class
);
1203 /* BSSID Functions */
1204 int ath5k_hw_set_lladdr(struct ath5k_hw
*ah
, const u8
*mac
);
1205 void ath5k_hw_set_associd(struct ath5k_hw
*ah
);
1206 void ath5k_hw_set_bssid_mask(struct ath5k_hw
*ah
, const u8
*mask
);
1207 /* Receive start/stop functions */
1208 void ath5k_hw_start_rx_pcu(struct ath5k_hw
*ah
);
1209 void ath5k_hw_stop_rx_pcu(struct ath5k_hw
*ah
);
1210 /* RX Filter functions */
1211 void ath5k_hw_set_mcast_filter(struct ath5k_hw
*ah
, u32 filter0
, u32 filter1
);
1212 u32
ath5k_hw_get_rx_filter(struct ath5k_hw
*ah
);
1213 void ath5k_hw_set_rx_filter(struct ath5k_hw
*ah
, u32 filter
);
1214 /* Beacon control functions */
1215 u64
ath5k_hw_get_tsf64(struct ath5k_hw
*ah
);
1216 void ath5k_hw_set_tsf64(struct ath5k_hw
*ah
, u64 tsf64
);
1217 void ath5k_hw_reset_tsf(struct ath5k_hw
*ah
);
1218 void ath5k_hw_init_beacon(struct ath5k_hw
*ah
, u32 next_beacon
, u32 interval
);
1220 int ath5k_hw_set_beacon_timers(struct ath5k_hw
*ah
,
1221 const struct ath5k_beacon_state
*state
);
1222 void ath5k_hw_reset_beacon(struct ath5k_hw
*ah
);
1223 int ath5k_hw_beaconq_finish(struct ath5k_hw
*ah
, unsigned long phys_addr
);
1226 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw
*ah
, bool high
);
1227 /* Clock rate related functions */
1228 unsigned int ath5k_hw_htoclock(struct ath5k_hw
*ah
, unsigned int usec
);
1229 unsigned int ath5k_hw_clocktoh(struct ath5k_hw
*ah
, unsigned int clock
);
1230 unsigned int ath5k_hw_get_clockrate(struct ath5k_hw
*ah
);
1231 /* Key table (WEP) functions */
1232 int ath5k_hw_reset_key(struct ath5k_hw
*ah
, u16 entry
);
1233 int ath5k_hw_set_key(struct ath5k_hw
*ah
, u16 entry
,
1234 const struct ieee80211_key_conf
*key
, const u8
*mac
);
1235 int ath5k_hw_set_key_lladdr(struct ath5k_hw
*ah
, u16 entry
, const u8
*mac
);
1237 /* Queue Control Unit, DFS Control Unit Functions */
1238 int ath5k_hw_get_tx_queueprops(struct ath5k_hw
*ah
, int queue
,
1239 struct ath5k_txq_info
*queue_info
);
1240 int ath5k_hw_set_tx_queueprops(struct ath5k_hw
*ah
, int queue
,
1241 const struct ath5k_txq_info
*queue_info
);
1242 int ath5k_hw_setup_tx_queue(struct ath5k_hw
*ah
,
1243 enum ath5k_tx_queue queue_type
,
1244 struct ath5k_txq_info
*queue_info
);
1245 u32
ath5k_hw_num_tx_pending(struct ath5k_hw
*ah
, unsigned int queue
);
1246 void ath5k_hw_release_tx_queue(struct ath5k_hw
*ah
, unsigned int queue
);
1247 int ath5k_hw_reset_tx_queue(struct ath5k_hw
*ah
, unsigned int queue
);
1248 int ath5k_hw_set_slot_time(struct ath5k_hw
*ah
, unsigned int slot_time
);
1250 /* Hardware Descriptor Functions */
1251 int ath5k_hw_init_desc_functions(struct ath5k_hw
*ah
);
1253 /* GPIO Functions */
1254 void ath5k_hw_set_ledstate(struct ath5k_hw
*ah
, unsigned int state
);
1255 int ath5k_hw_set_gpio_input(struct ath5k_hw
*ah
, u32 gpio
);
1256 int ath5k_hw_set_gpio_output(struct ath5k_hw
*ah
, u32 gpio
);
1257 u32
ath5k_hw_get_gpio(struct ath5k_hw
*ah
, u32 gpio
);
1258 int ath5k_hw_set_gpio(struct ath5k_hw
*ah
, u32 gpio
, u32 val
);
1259 void ath5k_hw_set_gpio_intr(struct ath5k_hw
*ah
, unsigned int gpio
,
1260 u32 interrupt_level
);
1262 /* rfkill Functions */
1263 void ath5k_rfkill_hw_start(struct ath5k_hw
*ah
);
1264 void ath5k_rfkill_hw_stop(struct ath5k_hw
*ah
);
1266 /* Misc functions */
1267 int ath5k_hw_set_capabilities(struct ath5k_hw
*ah
);
1268 int ath5k_hw_get_capability(struct ath5k_hw
*ah
,
1269 enum ath5k_capability_type cap_type
, u32 capability
,
1271 int ath5k_hw_enable_pspoll(struct ath5k_hw
*ah
, u8
*bssid
, u16 assoc_id
);
1272 int ath5k_hw_disable_pspoll(struct ath5k_hw
*ah
);
1274 /* Initial register settings functions */
1275 int ath5k_hw_write_initvals(struct ath5k_hw
*ah
, u8 mode
, bool change_channel
);
1278 int ath5k_hw_rfregs_init(struct ath5k_hw
*ah
,
1279 struct ieee80211_channel
*channel
,
1281 int ath5k_hw_rfgain_init(struct ath5k_hw
*ah
, unsigned int freq
);
1282 enum ath5k_rfgain
ath5k_hw_gainf_calibrate(struct ath5k_hw
*ah
);
1283 int ath5k_hw_rfgain_opt_init(struct ath5k_hw
*ah
);
1284 /* PHY/RF channel functions */
1285 bool ath5k_channel_ok(struct ath5k_hw
*ah
, u16 freq
, unsigned int flags
);
1286 int ath5k_hw_channel(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
);
1287 /* PHY calibration */
1288 void ath5k_hw_init_nfcal_hist(struct ath5k_hw
*ah
);
1289 int ath5k_hw_phy_calibrate(struct ath5k_hw
*ah
,
1290 struct ieee80211_channel
*channel
);
1291 void ath5k_hw_calibration_poll(struct ath5k_hw
*ah
);
1292 /* Spur mitigation */
1293 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw
*ah
,
1294 struct ieee80211_channel
*channel
);
1295 void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw
*ah
,
1296 struct ieee80211_channel
*channel
);
1297 /* Misc PHY functions */
1298 u16
ath5k_hw_radio_revision(struct ath5k_hw
*ah
, unsigned int chan
);
1299 int ath5k_hw_phy_disable(struct ath5k_hw
*ah
);
1300 /* Antenna control */
1301 void ath5k_hw_set_antenna_mode(struct ath5k_hw
*ah
, u8 ant_mode
);
1302 /* TX power setup */
1303 int ath5k_hw_txpower(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
,
1304 u8 ee_mode
, u8 txpower
);
1305 int ath5k_hw_set_txpower_limit(struct ath5k_hw
*ah
, u8 txpower
);
1308 * Functions used internaly
1311 static inline struct ath_common
*ath5k_hw_common(struct ath5k_hw
*ah
)
1316 static inline struct ath_regulatory
*ath5k_hw_regulatory(struct ath5k_hw
*ah
)
1318 return &(ath5k_hw_common(ah
)->regulatory
);
1321 static inline u32
ath5k_hw_reg_read(struct ath5k_hw
*ah
, u16 reg
)
1323 return ioread32(ah
->ah_iobase
+ reg
);
1326 static inline void ath5k_hw_reg_write(struct ath5k_hw
*ah
, u32 val
, u16 reg
)
1328 iowrite32(val
, ah
->ah_iobase
+ reg
);
1331 static inline u32
ath5k_hw_bitswap(u32 val
, unsigned int bits
)
1333 u32 retval
= 0, bit
, i
;
1335 for (i
= 0; i
< bits
; i
++) {
1336 bit
= (val
>> i
) & 1;
1337 retval
= (retval
<< 1) | bit
;