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staging: rtl8192e: Fix sparse (non-endian) warnings - Part II
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / rtl8192e / r8192E_dev.c
blob899e4e5e98f39eab5b89aa29a68522fae9d09b88
1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * Based on the r8180 driver, which is:
5 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *
19 * The full GNU General Public License is included in this distribution in the
20 * file called LICENSE.
21 *
22 * Contact Information:
23 * wlanfae <wlanfae@realtek.com>
24 ******************************************************************************/
25 #include "rtl_core.h"
26 #include "r8192E_phy.h"
27 #include "r8192E_phyreg.h"
28 #include "r8190P_rtl8256.h"
29 #include "r8192E_cmdpkt.h"
30 #include "rtl_dm.h"
31 #include "rtl_wx.h"
32
33 extern int WDCAPARA_ADD[];
34
35 void rtl8192e_start_beacon(struct net_device *dev)
36 {
37 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
38 struct rtllib_network *net = &priv->rtllib->current_network;
39 u16 BcnTimeCfg = 0;
40 u16 BcnCW = 6;
41 u16 BcnIFS = 0xf;
42
43 DMESG("Enabling beacon TX");
44 rtl8192_irq_disable(dev);
45
46 write_nic_word(dev, ATIMWND, 2);
47
48 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
49 write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
50 write_nic_word(dev, BCN_DMATIME, 256);
51
52 write_nic_byte(dev, BCN_ERR_THRESH, 100);
53
54 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
55 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
56 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
57 rtl8192_irq_enable(dev);
58 }
59
60 static void rtl8192e_update_msr(struct net_device *dev)
61 {
62 struct r8192_priv *priv = rtllib_priv(dev);
63 u8 msr;
64 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
65 msr = read_nic_byte(dev, MSR);
66 msr &= ~MSR_LINK_MASK;
67
68 switch (priv->rtllib->iw_mode) {
69 case IW_MODE_INFRA:
70 if (priv->rtllib->state == RTLLIB_LINKED)
71 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
72 else
73 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
74 LedAction = LED_CTL_LINK;
75 break;
76 case IW_MODE_ADHOC:
77 if (priv->rtllib->state == RTLLIB_LINKED)
78 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
79 else
80 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
81 break;
82 case IW_MODE_MASTER:
83 if (priv->rtllib->state == RTLLIB_LINKED)
84 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
85 else
86 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
87 break;
88 default:
89 break;
90 }
91
92 write_nic_byte(dev, MSR, msr);
93 if (priv->rtllib->LedControlHandler)
94 priv->rtllib->LedControlHandler(dev, LedAction);
95 }
96
97 void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val)
98 {
99 struct r8192_priv *priv = rtllib_priv(dev);
100
101 switch (variable) {
102 case HW_VAR_BSSID:
103 write_nic_dword(dev, BSSIDR, ((u32 *)(val))[0]);
104 write_nic_word(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
105 break;
106
107 case HW_VAR_MEDIA_STATUS:
108 {
109 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
110 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
111 u8 btMsr = read_nic_byte(dev, MSR);
112
113 btMsr &= 0xfc;
114
115 switch (OpMode) {
116 case RT_OP_MODE_INFRASTRUCTURE:
117 btMsr |= MSR_INFRA;
118 LedAction = LED_CTL_LINK;
119 break;
120
121 case RT_OP_MODE_IBSS:
122 btMsr |= MSR_ADHOC;
123 break;
124
125 case RT_OP_MODE_AP:
126 btMsr |= MSR_AP;
127 LedAction = LED_CTL_LINK;
128 break;
129
130 default:
131 btMsr |= MSR_NOLINK;
132 break;
133 }
134
135 write_nic_byte(dev, MSR, btMsr);
136
137 }
138 break;
139
140 case HW_VAR_CECHK_BSSID:
141 {
142 u32 RegRCR, Type;
143
144 Type = ((u8 *)(val))[0];
145 RegRCR = read_nic_dword(dev, RCR);
146 priv->ReceiveConfig = RegRCR;
147
148 if (Type == true)
149 RegRCR |= (RCR_CBSSID);
150 else if (Type == false)
151 RegRCR &= (~RCR_CBSSID);
152
153 write_nic_dword(dev, RCR, RegRCR);
154 priv->ReceiveConfig = RegRCR;
155
156 }
157 break;
158
159 case HW_VAR_SLOT_TIME:
160
161 priv->slot_time = val[0];
162 write_nic_byte(dev, SLOT_TIME, val[0]);
163
164 break;
165
166 case HW_VAR_ACK_PREAMBLE:
167 {
168 u32 regTmp;
169 priv->short_preamble = (bool)(*(u8 *)val);
170 regTmp = priv->basic_rate;
171 if (priv->short_preamble)
172 regTmp |= BRSR_AckShortPmb;
173 write_nic_dword(dev, RRSR, regTmp);
174 break;
175 }
176
177 case HW_VAR_CPU_RST:
178 write_nic_dword(dev, CPU_GEN, ((u32 *)(val))[0]);
179 break;
180
181 case HW_VAR_AC_PARAM:
182 {
183 u8 pAcParam = *((u8 *)val);
184 u32 eACI = pAcParam;
185 u8 u1bAIFS;
186 u32 u4bAcParam;
187 u8 mode = priv->rtllib->mode;
188 struct rtllib_qos_parameters *qos_parameters =
189 &priv->rtllib->current_network.qos_data.parameters;
190
191 u1bAIFS = qos_parameters->aifs[pAcParam] *
192 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
193
194 dm_init_edca_turbo(dev);
195
196 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[pAcParam])) <<
197 AC_PARAM_TXOP_LIMIT_OFFSET) |
198 (((u32)(qos_parameters->cw_max[pAcParam])) <<
199 AC_PARAM_ECW_MAX_OFFSET) |
200 (((u32)(qos_parameters->cw_min[pAcParam])) <<
201 AC_PARAM_ECW_MIN_OFFSET) |
202 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
203
204 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
205 __func__, eACI, u4bAcParam);
206 switch (eACI) {
207 case AC1_BK:
208 write_nic_dword(dev, EDCAPARA_BK, u4bAcParam);
209 break;
210
211 case AC0_BE:
212 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
213 break;
214
215 case AC2_VI:
216 write_nic_dword(dev, EDCAPARA_VI, u4bAcParam);
217 break;
218
219 case AC3_VO:
220 write_nic_dword(dev, EDCAPARA_VO, u4bAcParam);
221 break;
222
223 default:
224 printk(KERN_INFO "SetHwReg8185(): invalid ACI: %d !\n",
225 eACI);
226 break;
227 }
228 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
229 (u8 *)(&pAcParam));
230 break;
231 }
232
233 case HW_VAR_ACM_CTRL:
234 {
235 struct rtllib_qos_parameters *qos_parameters =
236 &priv->rtllib->current_network.qos_data.parameters;
237 u8 pAcParam = *((u8 *)val);
238 u32 eACI = pAcParam;
239 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
240 (qos_parameters->aifs[0]);
241 u8 acm = pAciAifsn->f.acm;
242 u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
243
244 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
245 __func__, eACI);
246 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
247
248 if (acm) {
249 switch (eACI) {
250 case AC0_BE:
251 AcmCtrl |= AcmHw_BeqEn;
252 break;
253
254 case AC2_VI:
255 AcmCtrl |= AcmHw_ViqEn;
256 break;
257
258 case AC3_VO:
259 AcmCtrl |= AcmHw_VoqEn;
260 break;
261
262 default:
263 RT_TRACE(COMP_QOS, "SetHwReg8185(): [HW_VAR_"
264 "ACM_CTRL] acm set failed: eACI is "
265 "%d\n", eACI);
266 break;
267 }
268 } else {
269 switch (eACI) {
270 case AC0_BE:
271 AcmCtrl &= (~AcmHw_BeqEn);
272 break;
273
274 case AC2_VI:
275 AcmCtrl &= (~AcmHw_ViqEn);
276 break;
277
278 case AC3_VO:
279 AcmCtrl &= (~AcmHw_BeqEn);
280 break;
281
282 default:
283 break;
284 }
285 }
286
287 RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write"
288 " 0x%X\n", AcmCtrl);
289 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
290 break;
291 }
292
293 case HW_VAR_SIFS:
294 write_nic_byte(dev, SIFS, val[0]);
295 write_nic_byte(dev, SIFS+1, val[0]);
296 break;
297
298 case HW_VAR_RF_TIMING:
299 {
300 u8 Rf_Timing = *((u8 *)val);
301 write_nic_byte(dev, rFPGA0_RFTiming1, Rf_Timing);
302 break;
303 }
304
305 default:
306 break;
307 }
308
309 }
310
311 static void rtl8192_read_eeprom_info(struct net_device *dev)
312 {
313 struct r8192_priv *priv = rtllib_priv(dev);
314
315 u8 tempval;
316 u8 ICVer8192, ICVer8256;
317 u16 i, usValue, IC_Version;
318 u16 EEPROMId;
319 u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
320 RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
321
322 EEPROMId = eprom_read(dev, 0);
323 if (EEPROMId != RTL8190_EEPROM_ID) {
324 RT_TRACE(COMP_ERR, "EEPROM ID is invalid:%x, %x\n",
325 EEPROMId, RTL8190_EEPROM_ID);
326 priv->AutoloadFailFlag = true;
327 } else {
328 priv->AutoloadFailFlag = false;
329 }
330
331 if (!priv->AutoloadFailFlag) {
332 priv->eeprom_vid = eprom_read(dev, (EEPROM_VID >> 1));
333 priv->eeprom_did = eprom_read(dev, (EEPROM_DID >> 1));
334
335 usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8;
336 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
337 usValue = eprom_read(dev, (EEPROM_ICVersion_ChannelPlan>>1));
338 priv->eeprom_ChannelPlan = usValue&0xff;
339 IC_Version = ((usValue&0xff00)>>8);
340
341 ICVer8192 = (IC_Version&0xf);
342 ICVer8256 = ((IC_Version&0xf0)>>4);
343 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
344 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
345 if (ICVer8192 == 0x2) {
346 if (ICVer8256 == 0x5)
347 priv->card_8192_version = VERSION_8190_BE;
348 }
349 switch (priv->card_8192_version) {
350 case VERSION_8190_BD:
351 case VERSION_8190_BE:
352 break;
353 default:
354 priv->card_8192_version = VERSION_8190_BD;
355 break;
356 }
357 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
358 priv->card_8192_version);
359 } else {
360 priv->card_8192_version = VERSION_8190_BD;
361 priv->eeprom_vid = 0;
362 priv->eeprom_did = 0;
363 priv->eeprom_CustomerID = 0;
364 priv->eeprom_ChannelPlan = 0;
365 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
366 }
367
368 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
369 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
370 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
371 priv->eeprom_CustomerID);
372
373 if (!priv->AutoloadFailFlag) {
374 for (i = 0; i < 6; i += 2) {
375 usValue = eprom_read(dev,
376 (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
377 *(u16 *)(&dev->dev_addr[i]) = usValue;
378 }
379 } else {
380 memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
381 }
382
383 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
384 dev->dev_addr);
385
386 if (priv->card_8192_version > VERSION_8190_BD)
387 priv->bTXPowerDataReadFromEEPORM = true;
388 else
389 priv->bTXPowerDataReadFromEEPORM = false;
390
391 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
392
393 if (priv->card_8192_version > VERSION_8190_BD) {
394 if (!priv->AutoloadFailFlag) {
395 tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff >>
396 1))) & 0xff;
397 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
398
399 if (tempval&0x80)
400 priv->rf_type = RF_1T2R;
401 else
402 priv->rf_type = RF_2T4R;
403 } else {
404 priv->EEPROMLegacyHTTxPowerDiff = 0x04;
405 }
406 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
407 priv->EEPROMLegacyHTTxPowerDiff);
408
409 if (!priv->AutoloadFailFlag)
410 priv->EEPROMThermalMeter = (u8)(((eprom_read(dev,
411 (EEPROM_ThermalMeter>>1))) &
412 0xff00)>>8);
413 else
414 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
415 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
416 priv->EEPROMThermalMeter);
417 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
418
419 if (priv->epromtype == EEPROM_93C46) {
420 if (!priv->AutoloadFailFlag) {
421 usValue = eprom_read(dev,
422 (EEPROM_TxPwDiff_CrystalCap >> 1));
423 priv->EEPROMAntPwDiff = (usValue&0x0fff);
424 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
425 >> 12);
426 } else {
427 priv->EEPROMAntPwDiff =
428 EEPROM_Default_AntTxPowerDiff;
429 priv->EEPROMCrystalCap =
430 EEPROM_Default_TxPwDiff_CrystalCap;
431 }
432 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
433 priv->EEPROMAntPwDiff);
434 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
435 priv->EEPROMCrystalCap);
436
437 for (i = 0; i < 14; i += 2) {
438 if (!priv->AutoloadFailFlag)
439 usValue = eprom_read(dev,
440 (u16)((EEPROM_TxPwIndex_CCK +
441 i) >> 1));
442 else
443 usValue = EEPROM_Default_TxPower;
444 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
445 usValue;
446 RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index"
447 " %d = 0x%02x\n", i,
448 priv->EEPROMTxPowerLevelCCK[i]);
449 RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index"
450 " %d = 0x%02x\n", i+1,
451 priv->EEPROMTxPowerLevelCCK[i+1]);
452 }
453 for (i = 0; i < 14; i += 2) {
454 if (!priv->AutoloadFailFlag)
455 usValue = eprom_read(dev,
456 (u16)((EEPROM_TxPwIndex_OFDM_24G
457 + i) >> 1));
458 else
459 usValue = EEPROM_Default_TxPower;
460 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
461 = usValue;
462 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level,"
463 " Index %d = 0x%02x\n", i,
464 priv->EEPROMTxPowerLevelOFDM24G[i]);
465 RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level,"
466 " Index %d = 0x%02x\n", i + 1,
467 priv->EEPROMTxPowerLevelOFDM24G[i+1]);
468 }
469 }
470 if (priv->epromtype == EEPROM_93C46) {
471 for (i = 0; i < 14; i++) {
472 priv->TxPowerLevelCCK[i] =
473 priv->EEPROMTxPowerLevelCCK[i];
474 priv->TxPowerLevelOFDM24G[i] =
475 priv->EEPROMTxPowerLevelOFDM24G[i];
476 }
477 priv->LegacyHTTxPowerDiff =
478 priv->EEPROMLegacyHTTxPowerDiff;
479 priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
480 0xf);
481 priv->AntennaTxPwDiff[1] = ((priv->EEPROMAntPwDiff &
482 0xf0)>>4);
483 priv->AntennaTxPwDiff[2] = ((priv->EEPROMAntPwDiff &
484 0xf00)>>8);
485 priv->CrystalCap = priv->EEPROMCrystalCap;
486 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
487 0xf);
488 priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter &
489 0xf0)>>4);
490 } else if (priv->epromtype == EEPROM_93C56) {
491
492 for (i = 0; i < 3; i++) {
493 priv->TxPowerLevelCCK_A[i] =
494 priv->EEPROMRfACCKChnl1TxPwLevel[0];
495 priv->TxPowerLevelOFDM24G_A[i] =
496 priv->EEPROMRfAOfdmChnlTxPwLevel[0];
497 priv->TxPowerLevelCCK_C[i] =
498 priv->EEPROMRfCCCKChnl1TxPwLevel[0];
499 priv->TxPowerLevelOFDM24G_C[i] =
500 priv->EEPROMRfCOfdmChnlTxPwLevel[0];
501 }
502 for (i = 3; i < 9; i++) {
503 priv->TxPowerLevelCCK_A[i] =
504 priv->EEPROMRfACCKChnl1TxPwLevel[1];
505 priv->TxPowerLevelOFDM24G_A[i] =
506 priv->EEPROMRfAOfdmChnlTxPwLevel[1];
507 priv->TxPowerLevelCCK_C[i] =
508 priv->EEPROMRfCCCKChnl1TxPwLevel[1];
509 priv->TxPowerLevelOFDM24G_C[i] =
510 priv->EEPROMRfCOfdmChnlTxPwLevel[1];
511 }
512 for (i = 9; i < 14; i++) {
513 priv->TxPowerLevelCCK_A[i] =
514 priv->EEPROMRfACCKChnl1TxPwLevel[2];
515 priv->TxPowerLevelOFDM24G_A[i] =
516 priv->EEPROMRfAOfdmChnlTxPwLevel[2];
517 priv->TxPowerLevelCCK_C[i] =
518 priv->EEPROMRfCCCKChnl1TxPwLevel[2];
519 priv->TxPowerLevelOFDM24G_C[i] =
520 priv->EEPROMRfCOfdmChnlTxPwLevel[2];
521 }
522 for (i = 0; i < 14; i++)
523 RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_A"
524 "[%d] = 0x%x\n", i,
525 priv->TxPowerLevelCCK_A[i]);
526 for (i = 0; i < 14; i++)
527 RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM"
528 "24G_A[%d] = 0x%x\n", i,
529 priv->TxPowerLevelOFDM24G_A[i]);
530 for (i = 0; i < 14; i++)
531 RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_C"
532 "[%d] = 0x%x\n", i,
533 priv->TxPowerLevelCCK_C[i]);
534 for (i = 0; i < 14; i++)
535 RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM"
536 "24G_C[%d] = 0x%x\n", i,
537 priv->TxPowerLevelOFDM24G_C[i]);
538 priv->LegacyHTTxPowerDiff =
539 priv->EEPROMLegacyHTTxPowerDiff;
540 priv->AntennaTxPwDiff[0] = 0;
541 priv->AntennaTxPwDiff[1] = 0;
542 priv->AntennaTxPwDiff[2] = 0;
543 priv->CrystalCap = priv->EEPROMCrystalCap;
544 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
545 0xf);
546 priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter &
547 0xf0)>>4);
548 }
549 }
550
551 if (priv->rf_type == RF_1T2R) {
552 /* no matter what checkpatch says, the braces are needed */
553 RT_TRACE(COMP_INIT, "\n1T2R config\n");
554 } else if (priv->rf_type == RF_2T4R) {
555 RT_TRACE(COMP_INIT, "\n2T4R config\n");
556 }
557
558 init_rate_adaptive(dev);
559
560 priv->rf_chip = RF_8256;
561
562 if (priv->RegChannelPlan == 0xf)
563 priv->ChannelPlan = priv->eeprom_ChannelPlan;
564 else
565 priv->ChannelPlan = priv->RegChannelPlan;
566
567 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
568 priv->CustomerID = RT_CID_DLINK;
569
570 switch (priv->eeprom_CustomerID) {
571 case EEPROM_CID_DEFAULT:
572 priv->CustomerID = RT_CID_DEFAULT;
573 break;
574 case EEPROM_CID_CAMEO:
575 priv->CustomerID = RT_CID_819x_CAMEO;
576 break;
577 case EEPROM_CID_RUNTOP:
578 priv->CustomerID = RT_CID_819x_RUNTOP;
579 break;
580 case EEPROM_CID_NetCore:
581 priv->CustomerID = RT_CID_819x_Netcore;
582 break;
583 case EEPROM_CID_TOSHIBA:
584 priv->CustomerID = RT_CID_TOSHIBA;
585 if (priv->eeprom_ChannelPlan&0x80)
586 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
587 else
588 priv->ChannelPlan = 0x0;
589 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
590 priv->ChannelPlan);
591 break;
592 case EEPROM_CID_Nettronix:
593 priv->ScanDelay = 100;
594 priv->CustomerID = RT_CID_Nettronix;
595 break;
596 case EEPROM_CID_Pronet:
597 priv->CustomerID = RT_CID_PRONET;
598 break;
599 case EEPROM_CID_DLINK:
600 priv->CustomerID = RT_CID_DLINK;
601 break;
602
603 case EEPROM_CID_WHQL:
604 break;
605 default:
606 break;
607 }
608
609 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
610 priv->ChannelPlan = 0;
611 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
612
613 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
614 priv->rtllib->bSupportRemoteWakeUp = true;
615 else
616 priv->rtllib->bSupportRemoteWakeUp = false;
617
618 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
619 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
620 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
621 }
622
623 void rtl8192_get_eeprom_size(struct net_device *dev)
624 {
625 u16 curCR;
626 struct r8192_priv *priv = rtllib_priv(dev);
627
628 RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
629 curCR = read_nic_dword(dev, EPROM_CMD);
630 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
631 curCR);
632 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
633 EEPROM_93C46;
634 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
635 priv->epromtype);
636 rtl8192_read_eeprom_info(dev);
637 }
638
639 static void rtl8192_hwconfig(struct net_device *dev)
640 {
641 u32 regRATR = 0, regRRSR = 0;
642 u8 regBwOpMode = 0, regTmp = 0;
643 struct r8192_priv *priv = rtllib_priv(dev);
644
645 switch (priv->rtllib->mode) {
646 case WIRELESS_MODE_B:
647 regBwOpMode = BW_OPMODE_20MHZ;
648 regRATR = RATE_ALL_CCK;
649 regRRSR = RATE_ALL_CCK;
650 break;
651 case WIRELESS_MODE_A:
652 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
653 regRATR = RATE_ALL_OFDM_AG;
654 regRRSR = RATE_ALL_OFDM_AG;
655 break;
656 case WIRELESS_MODE_G:
657 regBwOpMode = BW_OPMODE_20MHZ;
658 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
659 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
660 break;
661 case WIRELESS_MODE_AUTO:
662 case WIRELESS_MODE_N_24G:
663 regBwOpMode = BW_OPMODE_20MHZ;
664 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
665 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
666 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
667 break;
668 case WIRELESS_MODE_N_5G:
669 regBwOpMode = BW_OPMODE_5G;
670 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
671 RATE_ALL_OFDM_2SS;
672 regRRSR = RATE_ALL_OFDM_AG;
673 break;
674 default:
675 regBwOpMode = BW_OPMODE_20MHZ;
676 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
677 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
678 break;
679 }
680
681 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
682 {
683 u32 ratr_value = 0;
684 ratr_value = regRATR;
685 if (priv->rf_type == RF_1T2R)
686 ratr_value &= ~(RATE_ALL_OFDM_2SS);
687 write_nic_dword(dev, RATR0, ratr_value);
688 write_nic_byte(dev, UFWP, 1);
689 }
690 regTmp = read_nic_byte(dev, 0x313);
691 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
692 write_nic_dword(dev, RRSR, regRRSR);
693
694 write_nic_word(dev, RETRY_LIMIT,
695 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
696 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
697 }
698
699 bool rtl8192_adapter_start(struct net_device *dev)
700 {
701 struct r8192_priv *priv = rtllib_priv(dev);
702 u32 ulRegRead;
703 bool rtStatus = true;
704 u8 tmpvalue;
705 u8 ICVersion, SwitchingRegulatorOutput;
706 bool bfirmwareok = true;
707 u32 tmpRegA, tmpRegC, TempCCk;
708 int i = 0;
709 u32 retry_times = 0;
710
711 RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
712 priv->being_init_adapter = true;
713
714 start:
715 rtl8192_pci_resetdescring(dev);
716 priv->Rf_Mode = RF_OP_By_SW_3wire;
717 if (priv->ResetProgress == RESET_TYPE_NORESET) {
718 write_nic_byte(dev, ANAPAR, 0x37);
719 mdelay(500);
720 }
721 priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
722
723 if (priv->RegRfOff == true)
724 priv->rtllib->eRFPowerState = eRfOff;
725
726 ulRegRead = read_nic_dword(dev, CPU_GEN);
727 if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
728 ulRegRead |= CPU_GEN_SYSTEM_RESET;
729 else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
730 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
731 else
732 RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)"
733 "\n", __func__, priv->pFirmware->firmware_status);
734
735 write_nic_dword(dev, CPU_GEN, ulRegRead);
736
737 ICVersion = read_nic_byte(dev, IC_VERRSION);
738 if (ICVersion >= 0x4) {
739 SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
740 if (SwitchingRegulatorOutput != 0xb8) {
741 write_nic_byte(dev, SWREGULATOR, 0xa8);
742 mdelay(1);
743 write_nic_byte(dev, SWREGULATOR, 0xb8);
744 }
745 }
746 RT_TRACE(COMP_INIT, "BB Config Start!\n");
747 rtStatus = rtl8192_BBConfig(dev);
748 if (rtStatus != true) {
749 RT_TRACE(COMP_ERR, "BB Config failed\n");
750 return rtStatus;
751 }
752 RT_TRACE(COMP_INIT, "BB Config Finished!\n");
753
754 priv->LoopbackMode = RTL819X_NO_LOOPBACK;
755 if (priv->ResetProgress == RESET_TYPE_NORESET) {
756 ulRegRead = read_nic_dword(dev, CPU_GEN);
757 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
758 ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
759 CPU_GEN_NO_LOOPBACK_SET);
760 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
761 ulRegRead |= CPU_CCK_LOOPBACK;
762 else
763 RT_TRACE(COMP_ERR, "Serious error: wrong loopback"
764 " mode setting\n");
765
766 write_nic_dword(dev, CPU_GEN, ulRegRead);
767
768 udelay(500);
769 }
770 rtl8192_hwconfig(dev);
771 write_nic_byte(dev, CMDR, CR_RE | CR_TE);
772
773 write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
774 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
775 write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
776 write_nic_word(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
777 write_nic_dword(dev, RCR, priv->ReceiveConfig);
778
779 write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
780 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
781 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
782 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
783 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
784 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
785 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
786 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
787 write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
788 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
789 write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
790 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
791 RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
792 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
793 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
794
795 rtl8192_tx_enable(dev);
796 rtl8192_rx_enable(dev);
797 ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR)) |
798 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
799 write_nic_dword(dev, RRSR, ulRegRead);
800 write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
801
802 write_nic_byte(dev, ACK_TIMEOUT, 0x30);
803
804 if (priv->ResetProgress == RESET_TYPE_NORESET)
805 rtl8192_SetWirelessMode(dev, priv->rtllib->mode);
806 CamResetAllEntry(dev);
807 {
808 u8 SECR_value = 0x0;
809 SECR_value |= SCR_TxEncEnable;
810 SECR_value |= SCR_RxDecEnable;
811 SECR_value |= SCR_NoSKMC;
812 write_nic_byte(dev, SECR, SECR_value);
813 }
814 write_nic_word(dev, ATIMWND, 2);
815 write_nic_word(dev, BCN_INTERVAL, 100);
816 {
817 int i;
818 for (i = 0; i < QOS_QUEUE_NUM; i++)
819 write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
820 }
821 write_nic_byte(dev, 0xbe, 0xc0);
822
823 rtl8192_phy_configmac(dev);
824
825 if (priv->card_8192_version > (u8) VERSION_8190_BD) {
826 rtl8192_phy_getTxPower(dev);
827 rtl8192_phy_setTxPower(dev, priv->chan);
828 }
829
830 tmpvalue = read_nic_byte(dev, IC_VERRSION);
831 priv->IC_Cut = tmpvalue;
832 RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
833 if (priv->IC_Cut >= IC_VersionCut_D) {
834 if (priv->IC_Cut == IC_VersionCut_D) {
835 /* no matter what checkpatch says, braces are needed */
836 RT_TRACE(COMP_INIT, "D-cut\n");
837 } else if (priv->IC_Cut == IC_VersionCut_E) {
838 RT_TRACE(COMP_INIT, "E-cut\n");
839 }
840 } else {
841 RT_TRACE(COMP_INIT, "Before C-cut\n");
842 }
843
844 RT_TRACE(COMP_INIT, "Load Firmware!\n");
845 bfirmwareok = init_firmware(dev);
846 if (!bfirmwareok) {
847 if (retry_times < 10) {
848 retry_times++;
849 goto start;
850 } else {
851 rtStatus = false;
852 goto end;
853 }
854 }
855 RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
856 if (priv->ResetProgress == RESET_TYPE_NORESET) {
857 RT_TRACE(COMP_INIT, "RF Config Started!\n");
858 rtStatus = rtl8192_phy_RFConfig(dev);
859 if (rtStatus != true) {
860 RT_TRACE(COMP_ERR, "RF Config failed\n");
861 return rtStatus;
862 }
863 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
864 }
865 rtl8192_phy_updateInitGain(dev);
866
867 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
868 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
869
870 write_nic_byte(dev, 0x87, 0x0);
871
872 if (priv->RegRfOff == true) {
873 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
874 "%s(): Turn off RF for RegRfOff ----------\n",
875 __func__);
876 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW, true);
877 } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
878 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for"
879 " RfOffReason(%d) ----------\n", __func__,
880 priv->rtllib->RfOffReason);
881 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
882 true);
883 } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
884 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for"
885 " RfOffReason(%d) ----------\n", __func__,
886 priv->rtllib->RfOffReason);
887 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
888 true);
889 } else {
890 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
891 __func__);
892 priv->rtllib->eRFPowerState = eRfOn;
893 priv->rtllib->RfOffReason = 0;
894 }
895
896 if (priv->rtllib->FwRWRF)
897 priv->Rf_Mode = RF_OP_By_FW;
898 else
899 priv->Rf_Mode = RF_OP_By_SW_3wire;
900
901 if (priv->ResetProgress == RESET_TYPE_NORESET) {
902 dm_initialize_txpower_tracking(dev);
903
904 if (priv->IC_Cut >= IC_VersionCut_D) {
905 tmpRegA = rtl8192_QueryBBReg(dev,
906 rOFDM0_XATxIQImbalance, bMaskDWord);
907 tmpRegC = rtl8192_QueryBBReg(dev,
908 rOFDM0_XCTxIQImbalance, bMaskDWord);
909 for (i = 0; i < TxBBGainTableLength; i++) {
910 if (tmpRegA ==
911 priv->txbbgain_table[i].txbbgain_value) {
912 priv->rfa_txpowertrackingindex = (u8)i;
913 priv->rfa_txpowertrackingindex_real =
914 (u8)i;
915 priv->rfa_txpowertracking_default =
916 priv->rfa_txpowertrackingindex;
917 break;
918 }
919 }
920
921 TempCCk = rtl8192_QueryBBReg(dev,
922 rCCK0_TxFilter1, bMaskByte2);
923
924 for (i = 0; i < CCKTxBBGainTableLength; i++) {
925 if (TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0]) {
926 priv->CCKPresentAttentuation_20Mdefault = (u8)i;
927 break;
928 }
929 }
930 priv->CCKPresentAttentuation_40Mdefault = 0;
931 priv->CCKPresentAttentuation_difference = 0;
932 priv->CCKPresentAttentuation =
933 priv->CCKPresentAttentuation_20Mdefault;
934 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower"
935 "trackingindex_initial = %d\n",
936 priv->rfa_txpowertrackingindex);
937 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower"
938 "trackingindex_real__initial = %d\n",
939 priv->rfa_txpowertrackingindex_real);
940 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent"
941 "Attentuation_difference_initial = %d\n",
942 priv->CCKPresentAttentuation_difference);
943 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent"
944 "Attentuation_initial = %d\n",
945 priv->CCKPresentAttentuation);
946 priv->btxpower_tracking = false;
947 }
948 }
949 rtl8192_irq_enable(dev);
950 end:
951 priv->being_init_adapter = false;
952 return rtStatus;
953 }
954
955 static void rtl8192_net_update(struct net_device *dev)
956 {
957
958 struct r8192_priv *priv = rtllib_priv(dev);
959 struct rtllib_network *net;
960 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
961 u16 rate_config = 0;
962
963 net = &priv->rtllib->current_network;
964 rtl8192_config_rate(dev, &rate_config);
965 priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
966 priv->basic_rate = rate_config &= 0x15f;
967 write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
968 write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
969
970 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
971 write_nic_word(dev, ATIMWND, 2);
972 write_nic_word(dev, BCN_DMATIME, 256);
973 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
974 write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
975 write_nic_byte(dev, BCN_ERR_THRESH, 100);
976
977 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
978 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
979
980 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
981 }
982 }
983
984 void rtl8192_link_change(struct net_device *dev)
985 {
986 struct r8192_priv *priv = rtllib_priv(dev);
987 struct rtllib_device *ieee = priv->rtllib;
988
989 if (!priv->up)
990 return;
991
992 if (ieee->state == RTLLIB_LINKED) {
993 rtl8192_net_update(dev);
994 priv->ops->update_ratr_table(dev);
995 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
996 (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
997 EnableHWSecurityConfig8192(dev);
998 } else {
999 write_nic_byte(dev, 0x173, 0);
1000 }
1001 rtl8192e_update_msr(dev);
1002
1003 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1004 u32 reg = 0;
1005 reg = read_nic_dword(dev, RCR);
1006 if (priv->rtllib->state == RTLLIB_LINKED) {
1007 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1008 ;
1009 else
1010 priv->ReceiveConfig = reg |= RCR_CBSSID;
1011 } else
1012 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1013
1014 write_nic_dword(dev, RCR, reg);
1015 }
1016 }
1017
1018 void rtl8192_AllowAllDestAddr(struct net_device *dev,
1019 bool bAllowAllDA, bool WriteIntoReg)
1020 {
1021 struct r8192_priv *priv = rtllib_priv(dev);
1022
1023 if (bAllowAllDA)
1024 priv->ReceiveConfig |= RCR_AAP;
1025 else
1026 priv->ReceiveConfig &= ~RCR_AAP;
1027
1028 if (WriteIntoReg)
1029 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1030 }
1031
1032 static u8 MRateToHwRate8190Pci(u8 rate)
1033 {
1034 u8 ret = DESC90_RATE1M;
1035
1036 switch (rate) {
1037 case MGN_1M:
1038 ret = DESC90_RATE1M;
1039 break;
1040 case MGN_2M:
1041 ret = DESC90_RATE2M;
1042 break;
1043 case MGN_5_5M:
1044 ret = DESC90_RATE5_5M;
1045 break;
1046 case MGN_11M:
1047 ret = DESC90_RATE11M;
1048 break;
1049 case MGN_6M:
1050 ret = DESC90_RATE6M;
1051 break;
1052 case MGN_9M:
1053 ret = DESC90_RATE9M;
1054 break;
1055 case MGN_12M:
1056 ret = DESC90_RATE12M;
1057 break;
1058 case MGN_18M:
1059 ret = DESC90_RATE18M;
1060 break;
1061 case MGN_24M:
1062 ret = DESC90_RATE24M;
1063 break;
1064 case MGN_36M:
1065 ret = DESC90_RATE36M;
1066 break;
1067 case MGN_48M:
1068 ret = DESC90_RATE48M;
1069 break;
1070 case MGN_54M:
1071 ret = DESC90_RATE54M;
1072 break;
1073 case MGN_MCS0:
1074 ret = DESC90_RATEMCS0;
1075 break;
1076 case MGN_MCS1:
1077 ret = DESC90_RATEMCS1;
1078 break;
1079 case MGN_MCS2:
1080 ret = DESC90_RATEMCS2;
1081 break;
1082 case MGN_MCS3:
1083 ret = DESC90_RATEMCS3;
1084 break;
1085 case MGN_MCS4:
1086 ret = DESC90_RATEMCS4;
1087 break;
1088 case MGN_MCS5:
1089 ret = DESC90_RATEMCS5;
1090 break;
1091 case MGN_MCS6:
1092 ret = DESC90_RATEMCS6;
1093 break;
1094 case MGN_MCS7:
1095 ret = DESC90_RATEMCS7;
1096 break;
1097 case MGN_MCS8:
1098 ret = DESC90_RATEMCS8;
1099 break;
1100 case MGN_MCS9:
1101 ret = DESC90_RATEMCS9;
1102 break;
1103 case MGN_MCS10:
1104 ret = DESC90_RATEMCS10;
1105 break;
1106 case MGN_MCS11:
1107 ret = DESC90_RATEMCS11;
1108 break;
1109 case MGN_MCS12:
1110 ret = DESC90_RATEMCS12;
1111 break;
1112 case MGN_MCS13:
1113 ret = DESC90_RATEMCS13;
1114 break;
1115 case MGN_MCS14:
1116 ret = DESC90_RATEMCS14;
1117 break;
1118 case MGN_MCS15:
1119 ret = DESC90_RATEMCS15;
1120 break;
1121 case (0x80|0x20):
1122 ret = DESC90_RATEMCS32;
1123 break;
1124 default:
1125 break;
1126 }
1127 return ret;
1128 }
1129
1130 static u8 rtl8192_MapHwQueueToFirmwareQueue(u8 QueueID, u8 priority)
1131 {
1132 u8 QueueSelect = 0x0;
1133
1134 switch (QueueID) {
1135 case BE_QUEUE:
1136 QueueSelect = QSLT_BE;
1137 break;
1138
1139 case BK_QUEUE:
1140 QueueSelect = QSLT_BK;
1141 break;
1142
1143 case VO_QUEUE:
1144 QueueSelect = QSLT_VO;
1145 break;
1146
1147 case VI_QUEUE:
1148 QueueSelect = QSLT_VI;
1149 break;
1150 case MGNT_QUEUE:
1151 QueueSelect = QSLT_MGNT;
1152 break;
1153 case BEACON_QUEUE:
1154 QueueSelect = QSLT_BEACON;
1155 break;
1156 case TXCMD_QUEUE:
1157 QueueSelect = QSLT_CMD;
1158 break;
1159 case HIGH_QUEUE:
1160 QueueSelect = QSLT_HIGH;
1161 break;
1162 default:
1163 RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection:"
1164 " %d\n", QueueID);
1165 break;
1166 }
1167 return QueueSelect;
1168 }
1169
1170 void rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc,
1171 struct cb_desc *cb_desc, struct sk_buff *skb)
1172 {
1173 struct r8192_priv *priv = rtllib_priv(dev);
1174 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1175 PCI_DMA_TODEVICE);
1176 struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1177 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1178 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1179 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1180 pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate);
1181 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1182 pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT,
1183 pTxFwInfo->TxRate,
1184 cb_desc);
1185
1186 if (cb_desc->bAMPDUEnable) {
1187 pTxFwInfo->AllowAggregation = 1;
1188 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1189 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1190 } else {
1191 pTxFwInfo->AllowAggregation = 0;
1192 pTxFwInfo->RxMF = 0;
1193 pTxFwInfo->RxAMD = 0;
1194 }
1195
1196 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
1197 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1198 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1199 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1200 pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate);
1201 pTxFwInfo->RtsBandwidth = 0;
1202 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1203 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1204 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1205 (cb_desc->bRTSUseShortGI ? 1 : 0);
1206 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1207 if (cb_desc->bPacketBW) {
1208 pTxFwInfo->TxBandwidth = 1;
1209 pTxFwInfo->TxSubCarrier = 0;
1210 } else {
1211 pTxFwInfo->TxBandwidth = 0;
1212 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1213 }
1214 } else {
1215 pTxFwInfo->TxBandwidth = 0;
1216 pTxFwInfo->TxSubCarrier = 0;
1217 }
1218
1219 memset((u8 *)pdesc, 0, 12);
1220 pdesc->LINIP = 0;
1221 pdesc->CmdInit = 1;
1222 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1223 pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1224
1225 pdesc->SecCAMID = 0;
1226 pdesc->RATid = cb_desc->RATRIndex;
1227
1228
1229 pdesc->NoEnc = 1;
1230 pdesc->SecType = 0x0;
1231 if (cb_desc->bHwSec) {
1232 static u8 tmp;
1233 if (!tmp) {
1234 RT_TRACE(COMP_DBG, "==>================hw sec\n");
1235 tmp = 1;
1236 }
1237 switch (priv->rtllib->pairwise_key_type) {
1238 case KEY_TYPE_WEP40:
1239 case KEY_TYPE_WEP104:
1240 pdesc->SecType = 0x1;
1241 pdesc->NoEnc = 0;
1242 break;
1243 case KEY_TYPE_TKIP:
1244 pdesc->SecType = 0x2;
1245 pdesc->NoEnc = 0;
1246 break;
1247 case KEY_TYPE_CCMP:
1248 pdesc->SecType = 0x3;
1249 pdesc->NoEnc = 0;
1250 break;
1251 case KEY_TYPE_NA:
1252 pdesc->SecType = 0x0;
1253 pdesc->NoEnc = 1;
1254 break;
1255 }
1256 }
1257
1258 pdesc->PktId = 0x0;
1259
1260 pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue(
1261 cb_desc->queue_index,
1262 cb_desc->priority);
1263 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1264
1265 pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1266 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1267
1268 pdesc->FirstSeg = 1;
1269 pdesc->LastSeg = 1;
1270 pdesc->TxBufferSize = skb->len;
1271
1272 pdesc->TxBuffAddr = cpu_to_le32(mapping);
1273 }
1274
1275 void rtl8192_tx_fill_cmd_desc(struct net_device *dev,
1276 struct tx_desc_cmd *entry,
1277 struct cb_desc *cb_desc, struct sk_buff* skb)
1278 {
1279 struct r8192_priv *priv = rtllib_priv(dev);
1280 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1281 PCI_DMA_TODEVICE);
1282
1283 memset(entry, 0, 12);
1284 entry->LINIP = cb_desc->bLastIniPkt;
1285 entry->FirstSeg = 1;
1286 entry->LastSeg = 1;
1287 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1288 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1289 } else {
1290 struct tx_desc * entry_tmp = (struct tx_desc *)entry;
1291 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1292 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1293 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1294 entry_tmp->Offset);
1295 entry_tmp->QueueSelect = QSLT_CMD;
1296 entry_tmp->TxFWInfoSize = 0x08;
1297 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1298 }
1299 entry->TxBufferSize = skb->len;
1300 entry->TxBuffAddr = cpu_to_le32(mapping);
1301 entry->OWN = 1;
1302 }
1303
1304 static u8 HwRateToMRate90(bool bIsHT, u8 rate)
1305 {
1306 u8 ret_rate = 0x02;
1307
1308 if (!bIsHT) {
1309 switch (rate) {
1310 case DESC90_RATE1M:
1311 ret_rate = MGN_1M;
1312 break;
1313 case DESC90_RATE2M:
1314 ret_rate = MGN_2M;
1315 break;
1316 case DESC90_RATE5_5M:
1317 ret_rate = MGN_5_5M;
1318 break;
1319 case DESC90_RATE11M:
1320 ret_rate = MGN_11M;
1321 break;
1322 case DESC90_RATE6M:
1323 ret_rate = MGN_6M;
1324 break;
1325 case DESC90_RATE9M:
1326 ret_rate = MGN_9M;
1327 break;
1328 case DESC90_RATE12M:
1329 ret_rate = MGN_12M;
1330 break;
1331 case DESC90_RATE18M:
1332 ret_rate = MGN_18M;
1333 break;
1334 case DESC90_RATE24M:
1335 ret_rate = MGN_24M;
1336 break;
1337 case DESC90_RATE36M:
1338 ret_rate = MGN_36M;
1339 break;
1340 case DESC90_RATE48M:
1341 ret_rate = MGN_48M;
1342 break;
1343 case DESC90_RATE54M:
1344 ret_rate = MGN_54M;
1345 break;
1346
1347 default:
1348 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported"
1349 "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
1350 break;
1351 }
1352
1353 } else {
1354 switch (rate) {
1355 case DESC90_RATEMCS0:
1356 ret_rate = MGN_MCS0;
1357 break;
1358 case DESC90_RATEMCS1:
1359 ret_rate = MGN_MCS1;
1360 break;
1361 case DESC90_RATEMCS2:
1362 ret_rate = MGN_MCS2;
1363 break;
1364 case DESC90_RATEMCS3:
1365 ret_rate = MGN_MCS3;
1366 break;
1367 case DESC90_RATEMCS4:
1368 ret_rate = MGN_MCS4;
1369 break;
1370 case DESC90_RATEMCS5:
1371 ret_rate = MGN_MCS5;
1372 break;
1373 case DESC90_RATEMCS6:
1374 ret_rate = MGN_MCS6;
1375 break;
1376 case DESC90_RATEMCS7:
1377 ret_rate = MGN_MCS7;
1378 break;
1379 case DESC90_RATEMCS8:
1380 ret_rate = MGN_MCS8;
1381 break;
1382 case DESC90_RATEMCS9:
1383 ret_rate = MGN_MCS9;
1384 break;
1385 case DESC90_RATEMCS10:
1386 ret_rate = MGN_MCS10;
1387 break;
1388 case DESC90_RATEMCS11:
1389 ret_rate = MGN_MCS11;
1390 break;
1391 case DESC90_RATEMCS12:
1392 ret_rate = MGN_MCS12;
1393 break;
1394 case DESC90_RATEMCS13:
1395 ret_rate = MGN_MCS13;
1396 break;
1397 case DESC90_RATEMCS14:
1398 ret_rate = MGN_MCS14;
1399 break;
1400 case DESC90_RATEMCS15:
1401 ret_rate = MGN_MCS15;
1402 break;
1403 case DESC90_RATEMCS32:
1404 ret_rate = (0x80|0x20);
1405 break;
1406
1407 default:
1408 RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported "
1409 "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
1410 break;
1411 }
1412 }
1413
1414 return ret_rate;
1415 }
1416
1417 static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1418 {
1419 long retsig;
1420
1421 if (currsig >= 61 && currsig <= 100)
1422 retsig = 90 + ((currsig - 60) / 4);
1423 else if (currsig >= 41 && currsig <= 60)
1424 retsig = 78 + ((currsig - 40) / 2);
1425 else if (currsig >= 31 && currsig <= 40)
1426 retsig = 66 + (currsig - 30);
1427 else if (currsig >= 21 && currsig <= 30)
1428 retsig = 54 + (currsig - 20);
1429 else if (currsig >= 5 && currsig <= 20)
1430 retsig = 42 + (((currsig - 5) * 2) / 3);
1431 else if (currsig == 4)
1432 retsig = 36;
1433 else if (currsig == 3)
1434 retsig = 27;
1435 else if (currsig == 2)
1436 retsig = 18;
1437 else if (currsig == 1)
1438 retsig = 9;
1439 else
1440 retsig = currsig;
1441
1442 return retsig;
1443 }
1444
1445
1446 #define rx_hal_is_cck_rate(_pdrvinfo)\
1447 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1448 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1449 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1450 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1451 !_pdrvinfo->RxHT)
1452
1453 static void rtl8192_query_rxphystatus(
1454 struct r8192_priv *priv,
1455 struct rtllib_rx_stats *pstats,
1456 struct rx_desc *pdesc,
1457 struct rx_fwinfo *pdrvinfo,
1458 struct rtllib_rx_stats *precord_stats,
1459 bool bpacket_match_bssid,
1460 bool bpacket_toself,
1461 bool bPacketBeacon,
1462 bool bToSelfBA
1463 )
1464 {
1465 struct phy_sts_ofdm_819xpci *pofdm_buf;
1466 struct phy_sts_cck_819xpci *pcck_buf;
1467 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1468 u8 *prxpkt;
1469 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1470 char rx_pwr[4], rx_pwr_all = 0;
1471 char rx_snrX, rx_evmX;
1472 u8 evm, pwdb_all;
1473 u32 RSSI, total_rssi = 0;
1474 u8 is_cck_rate = 0;
1475 u8 rf_rx_num = 0;
1476 static u8 check_reg824;
1477 static u32 reg824_bit9;
1478
1479 priv->stats.numqry_phystatus++;
1480
1481 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1482 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1483 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1484 bpacket_match_bssid;
1485 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1486 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1487 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1488 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1489 if (check_reg824 == 0) {
1490 reg824_bit9 = rtl8192_QueryBBReg(priv->rtllib->dev,
1491 rFPGA0_XA_HSSIParameter2, 0x200);
1492 check_reg824 = 1;
1493 }
1494
1495
1496 prxpkt = (u8 *)pdrvinfo;
1497
1498 prxpkt += sizeof(struct rx_fwinfo);
1499
1500 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1501 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1502
1503 pstats->RxMIMOSignalQuality[0] = -1;
1504 pstats->RxMIMOSignalQuality[1] = -1;
1505 precord_stats->RxMIMOSignalQuality[0] = -1;
1506 precord_stats->RxMIMOSignalQuality[1] = -1;
1507
1508 if (is_cck_rate) {
1509 u8 report;
1510
1511 priv->stats.numqry_phystatusCCK++;
1512 if (!reg824_bit9) {
1513 report = pcck_buf->cck_agc_rpt & 0xc0;
1514 report = report>>6;
1515 switch (report) {
1516 case 0x3:
1517 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1518 0x3e);
1519 break;
1520 case 0x2:
1521 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1522 0x3e);
1523 break;
1524 case 0x1:
1525 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1526 0x3e);
1527 break;
1528 case 0x0:
1529 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1530 break;
1531 }
1532 } else {
1533 report = pcck_buf->cck_agc_rpt & 0x60;
1534 report = report>>5;
1535 switch (report) {
1536 case 0x3:
1537 rx_pwr_all = -35 -
1538 ((pcck_buf->cck_agc_rpt &
1539 0x1f) << 1);
1540 break;
1541 case 0x2:
1542 rx_pwr_all = -23 -
1543 ((pcck_buf->cck_agc_rpt &
1544 0x1f) << 1);
1545 break;
1546 case 0x1:
1547 rx_pwr_all = -11 -
1548 ((pcck_buf->cck_agc_rpt &
1549 0x1f) << 1);
1550 break;
1551 case 0x0:
1552 rx_pwr_all = -8 -
1553 ((pcck_buf->cck_agc_rpt &
1554 0x1f) << 1);
1555 break;
1556 }
1557 }
1558
1559 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1560 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1561 pstats->RecvSignalPower = rx_pwr_all;
1562
1563 if (bpacket_match_bssid) {
1564 u8 sq;
1565
1566 if (pstats->RxPWDBAll > 40) {
1567 sq = 100;
1568 } else {
1569 sq = pcck_buf->sq_rpt;
1570
1571 if (pcck_buf->sq_rpt > 64)
1572 sq = 0;
1573 else if (pcck_buf->sq_rpt < 20)
1574 sq = 100;
1575 else
1576 sq = ((64-sq) * 100) / 44;
1577 }
1578 pstats->SignalQuality = sq;
1579 precord_stats->SignalQuality = sq;
1580 pstats->RxMIMOSignalQuality[0] = sq;
1581 precord_stats->RxMIMOSignalQuality[0] = sq;
1582 pstats->RxMIMOSignalQuality[1] = -1;
1583 precord_stats->RxMIMOSignalQuality[1] = -1;
1584 }
1585 } else {
1586 priv->stats.numqry_phystatusHT++;
1587 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1588 if (priv->brfpath_rxenable[i])
1589 rf_rx_num++;
1590
1591 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1592 2) - 110;
1593
1594 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1595 rx_snrX = (char)(tmp_rxsnr);
1596 rx_snrX /= 2;
1597 priv->stats.rxSNRdB[i] = (long)rx_snrX;
1598
1599 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
1600 if (priv->brfpath_rxenable[i])
1601 total_rssi += RSSI;
1602
1603 if (bpacket_match_bssid) {
1604 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1605 precord_stats->RxMIMOSignalStrength[i] =
1606 (u8) RSSI;
1607 }
1608 }
1609
1610
1611 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1612 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1613
1614 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1615 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1616 pstats->RecvSignalPower = rx_pwr_all;
1617 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1618 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1619 max_spatial_stream = 2;
1620 else
1621 max_spatial_stream = 1;
1622
1623 for (i = 0; i < max_spatial_stream; i++) {
1624 tmp_rxevm = pofdm_buf->rxevm_X[i];
1625 rx_evmX = (char)(tmp_rxevm);
1626
1627 rx_evmX /= 2;
1628
1629 evm = rtl819x_evm_dbtopercentage(rx_evmX);
1630 if (bpacket_match_bssid) {
1631 if (i == 0) {
1632 pstats->SignalQuality = (u8)(evm &
1633 0xff);
1634 precord_stats->SignalQuality = (u8)(evm
1635 & 0xff);
1636 }
1637 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1638 0xff);
1639 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1640 & 0xff);
1641 }
1642 }
1643
1644
1645 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1646 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1647 &rxsc_sgien_exflg;
1648 if (pdrvinfo->BW)
1649 priv->stats.received_bwtype[1+prxsc->rxsc]++;
1650 else
1651 priv->stats.received_bwtype[0]++;
1652 }
1653
1654 if (is_cck_rate) {
1655 pstats->SignalStrength = precord_stats->SignalStrength =
1656 (u8)(rtl8192_signal_scale_mapping(priv,
1657 (long)pwdb_all));
1658
1659 } else {
1660 if (rf_rx_num != 0)
1661 pstats->SignalStrength = precord_stats->SignalStrength =
1662 (u8)(rtl8192_signal_scale_mapping(priv,
1663 (long)(total_rssi /= rf_rx_num)));
1664 }
1665 }
1666
1667 static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1668 struct rtllib_rx_stats *prev_st,
1669 struct rtllib_rx_stats *curr_st)
1670 {
1671 bool bcheck = false;
1672 u8 rfpath;
1673 u32 ij, tmp_val;
1674 static u32 slide_rssi_index, slide_rssi_statistics;
1675 static u32 slide_evm_index, slide_evm_statistics;
1676 static u32 last_rssi, last_evm;
1677 static u32 slide_beacon_adc_pwdb_index;
1678 static u32 slide_beacon_adc_pwdb_statistics;
1679 static u32 last_beacon_adc_pwdb;
1680 struct rtllib_hdr_3addr *hdr;
1681 u16 sc;
1682 unsigned int frag, seq;
1683
1684 hdr = (struct rtllib_hdr_3addr *)buffer;
1685 sc = le16_to_cpu(hdr->seq_ctl);
1686 frag = WLAN_GET_SEQ_FRAG(sc);
1687 seq = WLAN_GET_SEQ_SEQ(sc);
1688 curr_st->Seq_Num = seq;
1689 if (!prev_st->bIsAMPDU)
1690 bcheck = true;
1691
1692 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1693 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1694 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1695 priv->stats.slide_rssi_total -= last_rssi;
1696 }
1697 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1698
1699 priv->stats.slide_signal_strength[slide_rssi_index++] =
1700 prev_st->SignalStrength;
1701 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1702 slide_rssi_index = 0;
1703
1704 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1705 priv->stats.signal_strength = rtl819x_translate_todbm(priv,
1706 (u8)tmp_val);
1707 curr_st->rssi = priv->stats.signal_strength;
1708 if (!prev_st->bPacketMatchBSSID) {
1709 if (!prev_st->bToSelfBA)
1710 return;
1711 }
1712
1713 if (!bcheck)
1714 return;
1715
1716 rtl819x_process_cck_rxpathsel(priv, prev_st);
1717
1718 priv->stats.num_process_phyinfo++;
1719 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1720 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1721 if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev,
1722 rfpath))
1723 continue;
1724 RT_TRACE(COMP_DBG, "Jacken -> pPreviousstats->RxMIMO"
1725 "SignalStrength[rfpath] = %d\n",
1726 prev_st->RxMIMOSignalStrength[rfpath]);
1727 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1728 priv->stats.rx_rssi_percentage[rfpath] =
1729 prev_st->RxMIMOSignalStrength[rfpath];
1730 }
1731 if (prev_st->RxMIMOSignalStrength[rfpath] >
1732 priv->stats.rx_rssi_percentage[rfpath]) {
1733 priv->stats.rx_rssi_percentage[rfpath] =
1734 ((priv->stats.rx_rssi_percentage[rfpath]
1735 * (RX_SMOOTH - 1)) +
1736 (prev_st->RxMIMOSignalStrength
1737 [rfpath])) / (RX_SMOOTH);
1738 priv->stats.rx_rssi_percentage[rfpath] =
1739 priv->stats.rx_rssi_percentage[rfpath]
1740 + 1;
1741 } else {
1742 priv->stats.rx_rssi_percentage[rfpath] =
1743 ((priv->stats.rx_rssi_percentage[rfpath] *
1744 (RX_SMOOTH-1)) +
1745 (prev_st->RxMIMOSignalStrength[rfpath])) /
1746 (RX_SMOOTH);
1747 }
1748 RT_TRACE(COMP_DBG, "Jacken -> priv->RxStats.RxRSSI"
1749 "Percentage[rfPath] = %d\n",
1750 priv->stats.rx_rssi_percentage[rfpath]);
1751 }
1752 }
1753
1754
1755 if (prev_st->bPacketBeacon) {
1756 if (slide_beacon_adc_pwdb_statistics++ >=
1757 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1758 slide_beacon_adc_pwdb_statistics =
1759 PHY_Beacon_RSSI_SLID_WIN_MAX;
1760 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1761 [slide_beacon_adc_pwdb_index];
1762 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1763 }
1764 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1765 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1766 prev_st->RxPWDBAll;
1767 slide_beacon_adc_pwdb_index++;
1768 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1769 slide_beacon_adc_pwdb_index = 0;
1770 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1771 slide_beacon_adc_pwdb_statistics;
1772 if (prev_st->RxPWDBAll >= 3)
1773 prev_st->RxPWDBAll -= 3;
1774 }
1775
1776 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1777 prev_st->bIsCCK ? "CCK" : "OFDM",
1778 prev_st->RxPWDBAll);
1779
1780 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1781 prev_st->bToSelfBA) {
1782 if (priv->undecorated_smoothed_pwdb < 0)
1783 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1784 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1785 priv->undecorated_smoothed_pwdb =
1786 (((priv->undecorated_smoothed_pwdb) *
1787 (RX_SMOOTH-1)) +
1788 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1789 priv->undecorated_smoothed_pwdb =
1790 priv->undecorated_smoothed_pwdb + 1;
1791 } else {
1792 priv->undecorated_smoothed_pwdb =
1793 (((priv->undecorated_smoothed_pwdb) *
1794 (RX_SMOOTH-1)) +
1795 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1796 }
1797 rtl819x_update_rxsignalstatistics8190pci(priv, prev_st);
1798 }
1799
1800 if (prev_st->SignalQuality != 0) {
1801 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1802 prev_st->bToSelfBA) {
1803 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1804 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1805 last_evm =
1806 priv->stats.slide_evm[slide_evm_index];
1807 priv->stats.slide_evm_total -= last_evm;
1808 }
1809
1810 priv->stats.slide_evm_total += prev_st->SignalQuality;
1811
1812 priv->stats.slide_evm[slide_evm_index++] =
1813 prev_st->SignalQuality;
1814 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1815 slide_evm_index = 0;
1816
1817 tmp_val = priv->stats.slide_evm_total /
1818 slide_evm_statistics;
1819 priv->stats.signal_quality = tmp_val;
1820 priv->stats.last_signal_strength_inpercent = tmp_val;
1821 }
1822
1823 if (prev_st->bPacketToSelf ||
1824 prev_st->bPacketBeacon ||
1825 prev_st->bToSelfBA) {
1826 for (ij = 0; ij < 2; ij++) {
1827 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1828 if (priv->stats.rx_evm_percentage[ij] == 0)
1829 priv->stats.rx_evm_percentage[ij] =
1830 prev_st->RxMIMOSignalQuality[ij];
1831 priv->stats.rx_evm_percentage[ij] =
1832 ((priv->stats.rx_evm_percentage[ij] *
1833 (RX_SMOOTH - 1)) +
1834 (prev_st->RxMIMOSignalQuality[ij])) /
1835 (RX_SMOOTH);
1836 }
1837 }
1838 }
1839 }
1840 }
1841
1842 static void rtl8192_TranslateRxSignalStuff(struct net_device *dev,
1843 struct sk_buff *skb,
1844 struct rtllib_rx_stats *pstats,
1845 struct rx_desc *pdesc,
1846 struct rx_fwinfo *pdrvinfo)
1847 {
1848 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1849 bool bpacket_match_bssid, bpacket_toself;
1850 bool bPacketBeacon = false;
1851 struct rtllib_hdr_3addr *hdr;
1852 bool bToSelfBA = false;
1853 static struct rtllib_rx_stats previous_stats;
1854 u16 fc, type;
1855 u8 *tmp_buf;
1856 u8 *praddr;
1857
1858 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1859
1860 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1861 fc = le16_to_cpu(hdr->frame_ctl);
1862 type = WLAN_FC_GET_TYPE(fc);
1863 praddr = hdr->addr1;
1864
1865 bpacket_match_bssid = ((RTLLIB_FTYPE_CTL != type) &&
1866 (!compare_ether_addr(priv->rtllib->
1867 current_network.bssid,
1868 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1869 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 : hdr->addr3))
1870 && (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1871 bpacket_toself = bpacket_match_bssid && /* check this */
1872 (!compare_ether_addr(praddr,
1873 priv->rtllib->dev->dev_addr));
1874 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1875 bPacketBeacon = true;
1876 if (bpacket_match_bssid)
1877 priv->stats.numpacket_matchbssid++;
1878 if (bpacket_toself)
1879 priv->stats.numpacket_toself++;
1880 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1881 rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1882 &previous_stats, bpacket_match_bssid,
1883 bpacket_toself, bPacketBeacon, bToSelfBA);
1884 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
1885 }
1886
1887 static void rtl8192_UpdateReceivedRateHistogramStatistics(
1888 struct net_device *dev,
1889 struct rtllib_rx_stats *pstats)
1890 {
1891 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1892 u32 rcvType = 1;
1893 u32 rateIndex;
1894 u32 preamble_guardinterval;
1895
1896 if (pstats->bCRC)
1897 rcvType = 2;
1898 else if (pstats->bICV)
1899 rcvType = 3;
1900
1901 if (pstats->bShortPreamble)
1902 preamble_guardinterval = 1;
1903 else
1904 preamble_guardinterval = 0;
1905
1906 switch (pstats->rate) {
1907 case MGN_1M:
1908 rateIndex = 0;
1909 break;
1910 case MGN_2M:
1911 rateIndex = 1;
1912 break;
1913 case MGN_5_5M:
1914 rateIndex = 2;
1915 break;
1916 case MGN_11M:
1917 rateIndex = 3;
1918 break;
1919 case MGN_6M:
1920 rateIndex = 4;
1921 break;
1922 case MGN_9M:
1923 rateIndex = 5;
1924 break;
1925 case MGN_12M:
1926 rateIndex = 6;
1927 break;
1928 case MGN_18M:
1929 rateIndex = 7;
1930 break;
1931 case MGN_24M:
1932 rateIndex = 8;
1933 break;
1934 case MGN_36M:
1935 rateIndex = 9;
1936 break;
1937 case MGN_48M:
1938 rateIndex = 10;
1939 break;
1940 case MGN_54M:
1941 rateIndex = 11;
1942 break;
1943 case MGN_MCS0:
1944 rateIndex = 12;
1945 break;
1946 case MGN_MCS1:
1947 rateIndex = 13;
1948 break;
1949 case MGN_MCS2:
1950 rateIndex = 14;
1951 break;
1952 case MGN_MCS3:
1953 rateIndex = 15;
1954 break;
1955 case MGN_MCS4:
1956 rateIndex = 16;
1957 break;
1958 case MGN_MCS5:
1959 rateIndex = 17;
1960 break;
1961 case MGN_MCS6:
1962 rateIndex = 18;
1963 break;
1964 case MGN_MCS7:
1965 rateIndex = 19;
1966 break;
1967 case MGN_MCS8:
1968 rateIndex = 20;
1969 break;
1970 case MGN_MCS9:
1971 rateIndex = 21;
1972 break;
1973 case MGN_MCS10:
1974 rateIndex = 22;
1975 break;
1976 case MGN_MCS11:
1977 rateIndex = 23;
1978 break;
1979 case MGN_MCS12:
1980 rateIndex = 24;
1981 break;
1982 case MGN_MCS13:
1983 rateIndex = 25;
1984 break;
1985 case MGN_MCS14:
1986 rateIndex = 26;
1987 break;
1988 case MGN_MCS15:
1989 rateIndex = 27;
1990 break;
1991 default:
1992 rateIndex = 28;
1993 break;
1994 }
1995 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
1996 priv->stats.received_rate_histogram[0][rateIndex]++;
1997 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
1998 }
1999
2000 bool rtl8192_rx_query_status_desc(struct net_device *dev,
2001 struct rtllib_rx_stats *stats,
2002 struct rx_desc *pdesc,
2003 struct sk_buff *skb)
2004 {
2005 struct r8192_priv *priv = rtllib_priv(dev);
2006
2007 stats->bICV = pdesc->ICV;
2008 stats->bCRC = pdesc->CRC32;
2009 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2010
2011 stats->Length = pdesc->Length;
2012 if (stats->Length < 24)
2013 stats->bHwError |= 1;
2014
2015 if (stats->bHwError) {
2016 stats->bShift = false;
2017
2018 if (pdesc->CRC32) {
2019 if (pdesc->Length < 500)
2020 priv->stats.rxcrcerrmin++;
2021 else if (pdesc->Length > 1000)
2022 priv->stats.rxcrcerrmax++;
2023 else
2024 priv->stats.rxcrcerrmid++;
2025 }
2026 return false;
2027 } else {
2028 struct rx_fwinfo *pDrvInfo = NULL;
2029 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2030 stats->RxBufShift = ((pdesc->Shift)&0x03);
2031 stats->Decrypted = !pdesc->SWDec;
2032
2033 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2034
2035 stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT,
2036 (u8)pDrvInfo->RxRate);
2037 stats->bShortPreamble = pDrvInfo->SPLCP;
2038
2039 rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats);
2040
2041 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2042 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2043 (pDrvInfo->FirstAGGR == 1);
2044
2045 stats->TimeStampLow = pDrvInfo->TSFL;
2046 stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
2047
2048 rtl819x_UpdateRxPktTimeStamp(dev, stats);
2049
2050 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2051 stats->bShift = 1;
2052
2053 stats->RxIs40MHzPacket = pDrvInfo->BW;
2054
2055 rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc,
2056 pDrvInfo);
2057
2058 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2059 RT_TRACE(COMP_RXDESC, "pDrvInfo->FirstAGGR = %d,"
2060 " pDrvInfo->PartAggr = %d\n",
2061 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2062 skb_trim(skb, skb->len - 4/*sCrcLng*/);
2063
2064
2065 stats->packetlength = stats->Length-4;
2066 stats->fraglength = stats->packetlength;
2067 stats->fragoffset = 0;
2068 stats->ntotalfrag = 1;
2069 return true;
2070 }
2071 }
2072
2073 void rtl8192_halt_adapter(struct net_device *dev, bool reset)
2074 {
2075 struct r8192_priv *priv = rtllib_priv(dev);
2076 int i;
2077 u8 OpMode;
2078 u8 u1bTmp;
2079 u32 ulRegRead;
2080
2081 OpMode = RT_OP_MODE_NO_LINK;
2082 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2083
2084 if (!priv->rtllib->bSupportRemoteWakeUp) {
2085 u1bTmp = 0x0;
2086 write_nic_byte(dev, CMDR, u1bTmp);
2087 }
2088
2089 mdelay(20);
2090
2091 if (!reset) {
2092 mdelay(150);
2093
2094 priv->bHwRfOffAction = 2;
2095
2096 if (!priv->rtllib->bSupportRemoteWakeUp) {
2097 PHY_SetRtl8192eRfOff(dev);
2098 ulRegRead = read_nic_dword(dev, CPU_GEN);
2099 ulRegRead |= CPU_GEN_SYSTEM_RESET;
2100 write_nic_dword(dev, CPU_GEN, ulRegRead);
2101 } else {
2102 write_nic_dword(dev, WFCRC0, 0xffffffff);
2103 write_nic_dword(dev, WFCRC1, 0xffffffff);
2104 write_nic_dword(dev, WFCRC2, 0xffffffff);
2105
2106
2107 write_nic_byte(dev, PMR, 0x5);
2108 write_nic_byte(dev, MacBlkCtrl, 0xa);
2109 }
2110 }
2111
2112 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2113 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2114 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2115 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2116
2117 skb_queue_purge(&priv->skb_queue);
2118 return;
2119 }
2120
2121 void rtl8192_update_ratr_table(struct net_device *dev)
2122 {
2123 struct r8192_priv *priv = rtllib_priv(dev);
2124 struct rtllib_device *ieee = priv->rtllib;
2125 u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2126 u32 ratr_value = 0;
2127 u8 rate_index = 0;
2128
2129 rtl8192_config_rate(dev, (u16 *)(&ratr_value));
2130 ratr_value |= (*(u16 *)(pMcsRate)) << 12;
2131 switch (ieee->mode) {
2132 case IEEE_A:
2133 ratr_value &= 0x00000FF0;
2134 break;
2135 case IEEE_B:
2136 ratr_value &= 0x0000000F;
2137 break;
2138 case IEEE_G:
2139 case IEEE_G|IEEE_B:
2140 ratr_value &= 0x00000FF7;
2141 break;
2142 case IEEE_N_24G:
2143 case IEEE_N_5G:
2144 if (ieee->pHTInfo->PeerMimoPs == 0) {
2145 ratr_value &= 0x0007F007;
2146 } else {
2147 if (priv->rf_type == RF_1T2R)
2148 ratr_value &= 0x000FF007;
2149 else
2150 ratr_value &= 0x0F81F007;
2151 }
2152 break;
2153 default:
2154 break;
2155 }
2156 ratr_value &= 0x0FFFFFFF;
2157 if (ieee->pHTInfo->bCurTxBW40MHz &&
2158 ieee->pHTInfo->bCurShortGI40MHz)
2159 ratr_value |= 0x80000000;
2160 else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2161 ieee->pHTInfo->bCurShortGI20MHz)
2162 ratr_value |= 0x80000000;
2163 write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
2164 write_nic_byte(dev, UFWP, 1);
2165 }
2166
2167 void
2168 rtl8192_InitializeVariables(struct net_device *dev)
2169 {
2170 struct r8192_priv *priv = rtllib_priv(dev);
2171
2172 strcpy(priv->nick, "rtl8192E");
2173
2174 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
2175 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2176 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE /* |
2177 IEEE_SOFTMAC_BEACONS*/;
2178
2179 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2180
2181 priv->ShortRetryLimit = 0x30;
2182 priv->LongRetryLimit = 0x30;
2183
2184 priv->EarlyRxThreshold = 7;
2185 priv->pwrGroupCnt = 0;
2186
2187 priv->bIgnoreSilentReset = false;
2188 priv->enable_gpio0 = 0;
2189
2190 priv->TransmitConfig = 0;
2191
2192 priv->ReceiveConfig = RCR_ADD3 |
2193 RCR_AMF | RCR_ADF |
2194 RCR_AICV |
2195 RCR_AB | RCR_AM | RCR_APM |
2196 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2197 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2198
2199 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2200 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2201 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2202 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2203 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2204 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2205
2206
2207 priv->MidHighPwrTHR_L1 = 0x3B;
2208 priv->MidHighPwrTHR_L2 = 0x40;
2209 priv->PwrDomainProtect = false;
2210
2211 priv->bfirst_after_down = 0;
2212 }
2213
2214 void rtl8192_EnableInterrupt(struct net_device *dev)
2215 {
2216 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2217 priv->irq_enabled = 1;
2218
2219 write_nic_dword(dev, INTA_MASK, priv->irq_mask[0]);
2220
2221 }
2222
2223 void rtl8192_DisableInterrupt(struct net_device *dev)
2224 {
2225 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2226
2227 write_nic_dword(dev, INTA_MASK, 0);
2228
2229 priv->irq_enabled = 0;
2230 }
2231
2232 void rtl8192_ClearInterrupt(struct net_device *dev)
2233 {
2234 u32 tmp = 0;
2235 tmp = read_nic_dword(dev, ISR);
2236 write_nic_dword(dev, ISR, tmp);
2237 }
2238
2239
2240 void rtl8192_enable_rx(struct net_device *dev)
2241 {
2242 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2243 write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2244 }
2245
2246 static const u32 TX_DESC_BASE[] = {
2247 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2248 };
2249
2250 void rtl8192_enable_tx(struct net_device *dev)
2251 {
2252 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2253 u32 i;
2254
2255 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2256 write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2257 }
2258
2259
2260 void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta,
2261 u32 *p_intb)
2262 {
2263 *p_inta = read_nic_dword(dev, ISR);
2264 write_nic_dword(dev, ISR, *p_inta);
2265 }
2266
2267 bool rtl8192_HalRxCheckStuck(struct net_device *dev)
2268 {
2269 struct r8192_priv *priv = rtllib_priv(dev);
2270 u16 RegRxCounter = read_nic_word(dev, 0x130);
2271 bool bStuck = false;
2272 static u8 rx_chk_cnt;
2273 u32 SlotIndex = 0, TotalRxStuckCount = 0;
2274 u8 i;
2275 u8 SilentResetRxSoltNum = 4;
2276
2277 RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2278 __func__, RegRxCounter, priv->RxCounter);
2279
2280 rx_chk_cnt++;
2281 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2282 rx_chk_cnt = 0;
2283 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2284 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2285 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2286 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2287 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2288 if (rx_chk_cnt < 2)
2289 return bStuck;
2290 else
2291 rx_chk_cnt = 0;
2292 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2293 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2294 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2295 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2296 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2297 if (rx_chk_cnt < 4)
2298 return bStuck;
2299 else
2300 rx_chk_cnt = 0;
2301 } else {
2302 if (rx_chk_cnt < 8)
2303 return bStuck;
2304 else
2305 rx_chk_cnt = 0;
2306 }
2307
2308
2309 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2310
2311 if (priv->RxCounter == RegRxCounter) {
2312 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2313
2314 for (i = 0; i < SilentResetRxSoltNum; i++)
2315 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2316
2317 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2318 bStuck = true;
2319 for (i = 0; i < SilentResetRxSoltNum; i++)
2320 TotalRxStuckCount +=
2321 priv->SilentResetRxStuckEvent[i];
2322 }
2323
2324
2325 } else {
2326 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2327 }
2328
2329 priv->RxCounter = RegRxCounter;
2330
2331 return bStuck;
2332 }
2333
2334 bool rtl8192_HalTxCheckStuck(struct net_device *dev)
2335 {
2336 struct r8192_priv *priv = rtllib_priv(dev);
2337 bool bStuck = false;
2338 u16 RegTxCounter = read_nic_word(dev, 0x128);
2339
2340 RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2341 __func__, RegTxCounter, priv->TxCounter);
2342
2343 if (priv->TxCounter == RegTxCounter)
2344 bStuck = true;
2345
2346 priv->TxCounter = RegTxCounter;
2347
2348 return bStuck;
2349 }
2350
2351 bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev)
2352 {
2353 struct r8192_priv *priv = rtllib_priv(dev);
2354 struct rtllib_device *ieee = priv->rtllib;
2355 if (ieee->rtllib_ap_sec_type &&
2356 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2357 SEC_ALG_TKIP))) {
2358 return false;
2359 } else {
2360 return true;
2361 }
2362 }
2363
2364 bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev)
2365 {
2366 bool Reval;
2367 struct r8192_priv *priv = rtllib_priv(dev);
2368 struct rtllib_device *ieee = priv->rtllib;
2369
2370 if (ieee->bHalfWirelessN24GMode == true)
2371 Reval = true;
2372 else
2373 Reval = false;
2374
2375 return Reval;
2376 }
2377
2378 u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
2379 {
2380 u8 tmp_Short;
2381
2382 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
2383 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
2384 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
2385 tmp_Short = 0;
2386
2387 return tmp_Short;
2388 }
2389
2390 void
2391 ActUpdateChannelAccessSetting(
2392 struct net_device *dev,
2393 enum wireless_mode WirelessMode,
2394 struct channel_access_setting *ChnlAccessSetting
2395 )
2396 {
2397 struct r8192_priv *priv = rtllib_priv(dev);
2398
2399 return;
2400
2401 {
2402 u16 SIFS_Timer;
2403
2404 if (WirelessMode == WIRELESS_MODE_G)
2405 SIFS_Timer = 0x0e0e;
2406 else
2407 SIFS_Timer = priv->SifsTime;
2408
2409 priv->rtllib->SetHwRegHandler(dev, HW_VAR_SIFS,
2410 (u8 *)&SIFS_Timer);
2411 }
2412
2413 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree