2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.3"
56 AHCI_MAX_SG
= 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY
= 0xffffffff,
58 AHCI_USE_CLUSTERING
= 0,
61 AHCI_CMD_SLOT_SZ
= AHCI_MAX_CMDS
* AHCI_CMD_SZ
,
63 AHCI_CMD_TBL_CDB
= 0x40,
64 AHCI_CMD_TBL_HDR_SZ
= 0x80,
65 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR_SZ
+ (AHCI_MAX_SG
* 16),
66 AHCI_CMD_TBL_AR_SZ
= AHCI_CMD_TBL_SZ
* AHCI_MAX_CMDS
,
67 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_AR_SZ
+
69 AHCI_IRQ_ON_SG
= (1 << 31),
70 AHCI_CMD_ATAPI
= (1 << 5),
71 AHCI_CMD_WRITE
= (1 << 6),
72 AHCI_CMD_PREFETCH
= (1 << 7),
73 AHCI_CMD_RESET
= (1 << 8),
74 AHCI_CMD_CLR_BUSY
= (1 << 10),
76 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK
= 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251
= 1,
82 /* global controller registers */
83 HOST_CAP
= 0x00, /* host capabilities */
84 HOST_CTL
= 0x04, /* global host control */
85 HOST_IRQ_STAT
= 0x08, /* interrupt status */
86 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
90 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
95 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
96 HOST_CAP_NCQ
= (1 << 30), /* Native Command Queueing */
97 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
99 /* registers for each SATA port */
100 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
101 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
102 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
103 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
104 PORT_IRQ_STAT
= 0x10, /* interrupt status */
105 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
106 PORT_CMD
= 0x18, /* port command */
107 PORT_TFDATA
= 0x20, /* taskfile data */
108 PORT_SIG
= 0x24, /* device TF signature */
109 PORT_CMD_ISSUE
= 0x38, /* command issue */
110 PORT_SCR
= 0x28, /* SATA phy register block */
111 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
112 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
113 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
114 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
116 /* PORT_IRQ_{STAT,MASK} bits */
117 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
118 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
119 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
120 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
121 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
122 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
123 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
124 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
126 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
127 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
128 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
129 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
130 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
131 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
132 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
133 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
134 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
136 PORT_IRQ_FREEZE
= PORT_IRQ_HBUS_ERR
|
141 PORT_IRQ_ERROR
= PORT_IRQ_FREEZE
|
143 PORT_IRQ_HBUS_DATA_ERR
,
144 DEF_PORT_IRQ
= PORT_IRQ_ERROR
| PORT_IRQ_SG_DONE
|
145 PORT_IRQ_SDB_FIS
| PORT_IRQ_DMAS_FIS
|
146 PORT_IRQ_PIOS_FIS
| PORT_IRQ_D2H_REG_FIS
,
149 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
150 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
151 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
152 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
153 PORT_CMD_CLO
= (1 << 3), /* Command list override */
154 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
155 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
156 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
158 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
159 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
160 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
162 /* hpriv->flags bits */
163 AHCI_FLAG_MSI
= (1 << 0),
166 AHCI_FLAG_RESET_NEEDS_CLO
= (1 << 24),
169 struct ahci_cmd_hdr
{
184 struct ahci_host_priv
{
186 u32 cap
; /* cache of HOST_CAP register */
187 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
190 struct ahci_port_priv
{
191 struct ahci_cmd_hdr
*cmd_slot
;
192 dma_addr_t cmd_slot_dma
;
194 dma_addr_t cmd_tbl_dma
;
196 dma_addr_t rx_fis_dma
;
199 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
200 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
201 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
202 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
203 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
204 static void ahci_irq_clear(struct ata_port
*ap
);
205 static int ahci_port_start(struct ata_port
*ap
);
206 static void ahci_port_stop(struct ata_port
*ap
);
207 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
208 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
209 static u8
ahci_check_status(struct ata_port
*ap
);
210 static void ahci_freeze(struct ata_port
*ap
);
211 static void ahci_thaw(struct ata_port
*ap
);
212 static void ahci_error_handler(struct ata_port
*ap
);
213 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
214 static void ahci_remove_one (struct pci_dev
*pdev
);
216 static struct scsi_host_template ahci_sht
= {
217 .module
= THIS_MODULE
,
219 .ioctl
= ata_scsi_ioctl
,
220 .queuecommand
= ata_scsi_queuecmd
,
221 .change_queue_depth
= ata_scsi_change_queue_depth
,
222 .can_queue
= AHCI_MAX_CMDS
- 1,
223 .this_id
= ATA_SHT_THIS_ID
,
224 .sg_tablesize
= AHCI_MAX_SG
,
225 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
226 .emulated
= ATA_SHT_EMULATED
,
227 .use_clustering
= AHCI_USE_CLUSTERING
,
228 .proc_name
= DRV_NAME
,
229 .dma_boundary
= AHCI_DMA_BOUNDARY
,
230 .slave_configure
= ata_scsi_slave_config
,
231 .slave_destroy
= ata_scsi_slave_destroy
,
232 .bios_param
= ata_std_bios_param
,
235 static const struct ata_port_operations ahci_ops
= {
236 .port_disable
= ata_port_disable
,
238 .check_status
= ahci_check_status
,
239 .check_altstatus
= ahci_check_status
,
240 .dev_select
= ata_noop_dev_select
,
242 .tf_read
= ahci_tf_read
,
244 .qc_prep
= ahci_qc_prep
,
245 .qc_issue
= ahci_qc_issue
,
247 .irq_handler
= ahci_interrupt
,
248 .irq_clear
= ahci_irq_clear
,
250 .scr_read
= ahci_scr_read
,
251 .scr_write
= ahci_scr_write
,
253 .freeze
= ahci_freeze
,
256 .error_handler
= ahci_error_handler
,
257 .post_internal_cmd
= ahci_post_internal_cmd
,
259 .port_start
= ahci_port_start
,
260 .port_stop
= ahci_port_stop
,
263 static const struct ata_port_info ahci_port_info
[] = {
267 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
268 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
269 ATA_FLAG_SKIP_D2H_BSY
,
270 .pio_mask
= 0x1f, /* pio0-4 */
271 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
272 .port_ops
= &ahci_ops
,
274 /* board_ahci_vt8251 */
277 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
278 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
279 ATA_FLAG_SKIP_D2H_BSY
|
280 AHCI_FLAG_RESET_NEEDS_CLO
,
281 .pio_mask
= 0x1f, /* pio0-4 */
282 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
283 .port_ops
= &ahci_ops
,
287 static const struct pci_device_id ahci_pci_tbl
[] = {
289 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
290 board_ahci
}, /* ICH6 */
291 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
292 board_ahci
}, /* ICH6M */
293 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
294 board_ahci
}, /* ICH7 */
295 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
296 board_ahci
}, /* ICH7M */
297 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
298 board_ahci
}, /* ICH7R */
299 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
300 board_ahci
}, /* ULi M5288 */
301 { PCI_VENDOR_ID_INTEL
, 0x2681, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
302 board_ahci
}, /* ESB2 */
303 { PCI_VENDOR_ID_INTEL
, 0x2682, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
304 board_ahci
}, /* ESB2 */
305 { PCI_VENDOR_ID_INTEL
, 0x2683, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
306 board_ahci
}, /* ESB2 */
307 { PCI_VENDOR_ID_INTEL
, 0x27c6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
308 board_ahci
}, /* ICH7-M DH */
309 { PCI_VENDOR_ID_INTEL
, 0x2821, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
310 board_ahci
}, /* ICH8 */
311 { PCI_VENDOR_ID_INTEL
, 0x2822, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
312 board_ahci
}, /* ICH8 */
313 { PCI_VENDOR_ID_INTEL
, 0x2824, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
314 board_ahci
}, /* ICH8 */
315 { PCI_VENDOR_ID_INTEL
, 0x2829, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
316 board_ahci
}, /* ICH8M */
317 { PCI_VENDOR_ID_INTEL
, 0x282a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
318 board_ahci
}, /* ICH8M */
321 { 0x197b, 0x2360, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
322 board_ahci
}, /* JMicron JMB360 */
323 { 0x197b, 0x2363, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
324 board_ahci
}, /* JMicron JMB363 */
327 { PCI_VENDOR_ID_ATI
, 0x4380, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
328 board_ahci
}, /* ATI SB600 non-raid */
329 { PCI_VENDOR_ID_ATI
, 0x4381, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
330 board_ahci
}, /* ATI SB600 raid */
333 { PCI_VENDOR_ID_VIA
, 0x3349, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
334 board_ahci_vt8251
}, /* VIA VT8251 */
337 { PCI_VENDOR_ID_NVIDIA
, 0x044c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
338 board_ahci
}, /* MCP65 */
339 { PCI_VENDOR_ID_NVIDIA
, 0x044d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
340 board_ahci
}, /* MCP65 */
341 { PCI_VENDOR_ID_NVIDIA
, 0x044e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
342 board_ahci
}, /* MCP65 */
343 { PCI_VENDOR_ID_NVIDIA
, 0x044f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
344 board_ahci
}, /* MCP65 */
346 { } /* terminate list */
350 static struct pci_driver ahci_pci_driver
= {
352 .id_table
= ahci_pci_tbl
,
353 .probe
= ahci_init_one
,
354 .remove
= ahci_remove_one
,
358 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
360 return base
+ 0x100 + (port
* 0x80);
363 static inline void __iomem
*ahci_port_base (void __iomem
*base
, unsigned int port
)
365 return (void __iomem
*) ahci_port_base_ul((unsigned long)base
, port
);
368 static int ahci_port_start(struct ata_port
*ap
)
370 struct device
*dev
= ap
->host_set
->dev
;
371 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
372 struct ahci_port_priv
*pp
;
373 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
374 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
379 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
382 memset(pp
, 0, sizeof(*pp
));
384 rc
= ata_pad_alloc(ap
, dev
);
390 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
392 ata_pad_free(ap
, dev
);
396 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
399 * First item in chunk of DMA memory: 32-slot command table,
400 * 32 bytes each in size
403 pp
->cmd_slot_dma
= mem_dma
;
405 mem
+= AHCI_CMD_SLOT_SZ
;
406 mem_dma
+= AHCI_CMD_SLOT_SZ
;
409 * Second item: Received-FIS area
412 pp
->rx_fis_dma
= mem_dma
;
414 mem
+= AHCI_RX_FIS_SZ
;
415 mem_dma
+= AHCI_RX_FIS_SZ
;
418 * Third item: data area for storing a single command
419 * and its scatter-gather table
422 pp
->cmd_tbl_dma
= mem_dma
;
424 ap
->private_data
= pp
;
426 if (hpriv
->cap
& HOST_CAP_64
)
427 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
428 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
429 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
431 if (hpriv
->cap
& HOST_CAP_64
)
432 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
433 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
434 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
436 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
437 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
438 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
439 readl(port_mmio
+ PORT_CMD
); /* flush */
445 static void ahci_port_stop(struct ata_port
*ap
)
447 struct device
*dev
= ap
->host_set
->dev
;
448 struct ahci_port_priv
*pp
= ap
->private_data
;
449 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
450 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
453 tmp
= readl(port_mmio
+ PORT_CMD
);
454 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
455 writel(tmp
, port_mmio
+ PORT_CMD
);
456 readl(port_mmio
+ PORT_CMD
); /* flush */
458 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
459 * this is slightly incorrect.
463 ap
->private_data
= NULL
;
464 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
465 pp
->cmd_slot
, pp
->cmd_slot_dma
);
466 ata_pad_free(ap
, dev
);
470 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
475 case SCR_STATUS
: sc_reg
= 0; break;
476 case SCR_CONTROL
: sc_reg
= 1; break;
477 case SCR_ERROR
: sc_reg
= 2; break;
478 case SCR_ACTIVE
: sc_reg
= 3; break;
483 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
487 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
493 case SCR_STATUS
: sc_reg
= 0; break;
494 case SCR_CONTROL
: sc_reg
= 1; break;
495 case SCR_ERROR
: sc_reg
= 2; break;
496 case SCR_ACTIVE
: sc_reg
= 3; break;
501 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
504 static int ahci_stop_engine(struct ata_port
*ap
)
506 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
507 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
511 tmp
= readl(port_mmio
+ PORT_CMD
);
512 tmp
&= ~PORT_CMD_START
;
513 writel(tmp
, port_mmio
+ PORT_CMD
);
515 /* wait for engine to stop. TODO: this could be
516 * as long as 500 msec
520 tmp
= readl(port_mmio
+ PORT_CMD
);
521 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
529 static void ahci_start_engine(struct ata_port
*ap
)
531 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
532 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
535 tmp
= readl(port_mmio
+ PORT_CMD
);
536 tmp
|= PORT_CMD_START
;
537 writel(tmp
, port_mmio
+ PORT_CMD
);
538 readl(port_mmio
+ PORT_CMD
); /* flush */
541 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
543 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
544 struct ata_taskfile tf
;
547 tmp
= readl(port_mmio
+ PORT_SIG
);
548 tf
.lbah
= (tmp
>> 24) & 0xff;
549 tf
.lbam
= (tmp
>> 16) & 0xff;
550 tf
.lbal
= (tmp
>> 8) & 0xff;
551 tf
.nsect
= (tmp
) & 0xff;
553 return ata_dev_classify(&tf
);
556 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
559 dma_addr_t cmd_tbl_dma
;
561 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
563 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
564 pp
->cmd_slot
[tag
].status
= 0;
565 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
566 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
569 static int ahci_clo(struct ata_port
*ap
)
571 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
572 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
575 if (!(hpriv
->cap
& HOST_CAP_CLO
))
578 tmp
= readl(port_mmio
+ PORT_CMD
);
580 writel(tmp
, port_mmio
+ PORT_CMD
);
582 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
583 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
584 if (tmp
& PORT_CMD_CLO
)
590 static int ahci_prereset(struct ata_port
*ap
)
592 if ((ap
->flags
& AHCI_FLAG_RESET_NEEDS_CLO
) &&
593 (ata_busy_wait(ap
, ATA_BUSY
, 1000) & ATA_BUSY
)) {
594 /* ATA_BUSY hasn't cleared, so send a CLO */
598 return ata_std_prereset(ap
);
601 static int ahci_softreset(struct ata_port
*ap
, unsigned int *class)
603 struct ahci_port_priv
*pp
= ap
->private_data
;
604 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
605 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
606 const u32 cmd_fis_len
= 5; /* five dwords */
607 const char *reason
= NULL
;
608 struct ata_taskfile tf
;
615 if (ata_port_offline(ap
)) {
616 DPRINTK("PHY reports no device\n");
617 *class = ATA_DEV_NONE
;
621 /* prepare for SRST (AHCI-1.1 10.4.1) */
622 rc
= ahci_stop_engine(ap
);
624 reason
= "failed to stop engine";
628 /* check BUSY/DRQ, perform Command List Override if necessary */
629 ahci_tf_read(ap
, &tf
);
630 if (tf
.command
& (ATA_BUSY
| ATA_DRQ
)) {
633 if (rc
== -EOPNOTSUPP
) {
634 reason
= "port busy but CLO unavailable";
637 reason
= "port busy but CLO failed";
643 ahci_start_engine(ap
);
645 ata_tf_init(ap
->device
, &tf
);
648 /* issue the first D2H Register FIS */
649 ahci_fill_cmd_slot(pp
, 0,
650 cmd_fis_len
| AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
);
653 ata_tf_to_fis(&tf
, fis
, 0);
654 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
656 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
658 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1, 1, 500);
661 reason
= "1st FIS failed";
665 /* spec says at least 5us, but be generous and sleep for 1ms */
668 /* issue the second D2H Register FIS */
669 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
);
672 ata_tf_to_fis(&tf
, fis
, 0);
673 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
675 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
676 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
678 /* spec mandates ">= 2ms" before checking status.
679 * We wait 150ms, because that was the magic delay used for
680 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
681 * between when the ATA command register is written, and then
682 * status is checked. Because waiting for "a while" before
683 * checking status is fine, post SRST, we perform this magic
684 * delay here as well.
688 *class = ATA_DEV_NONE
;
689 if (ata_port_online(ap
)) {
690 if (ata_busy_sleep(ap
, ATA_TMOUT_BOOT_QUICK
, ATA_TMOUT_BOOT
)) {
692 reason
= "device not ready";
695 *class = ahci_dev_classify(ap
);
698 DPRINTK("EXIT, class=%u\n", *class);
702 ahci_start_engine(ap
);
704 ata_port_printk(ap
, KERN_ERR
, "softreset failed (%s)\n", reason
);
708 static int ahci_hardreset(struct ata_port
*ap
, unsigned int *class)
710 struct ahci_port_priv
*pp
= ap
->private_data
;
711 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
712 struct ata_taskfile tf
;
717 ahci_stop_engine(ap
);
719 /* clear D2H reception area to properly wait for D2H FIS */
720 ata_tf_init(ap
->device
, &tf
);
722 ata_tf_to_fis(&tf
, d2h_fis
, 0);
724 rc
= sata_std_hardreset(ap
, class);
726 ahci_start_engine(ap
);
728 if (rc
== 0 && ata_port_online(ap
))
729 *class = ahci_dev_classify(ap
);
730 if (*class == ATA_DEV_UNKNOWN
)
731 *class = ATA_DEV_NONE
;
733 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
737 static void ahci_postreset(struct ata_port
*ap
, unsigned int *class)
739 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
742 ata_std_postreset(ap
, class);
744 /* Make sure port's ATAPI bit is set appropriately */
745 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
746 if (*class == ATA_DEV_ATAPI
)
747 new_tmp
|= PORT_CMD_ATAPI
;
749 new_tmp
&= ~PORT_CMD_ATAPI
;
750 if (new_tmp
!= tmp
) {
751 writel(new_tmp
, port_mmio
+ PORT_CMD
);
752 readl(port_mmio
+ PORT_CMD
); /* flush */
756 static u8
ahci_check_status(struct ata_port
*ap
)
758 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
760 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
763 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
765 struct ahci_port_priv
*pp
= ap
->private_data
;
766 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
768 ata_tf_from_fis(d2h_fis
, tf
);
771 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
773 struct scatterlist
*sg
;
774 struct ahci_sg
*ahci_sg
;
775 unsigned int n_sg
= 0;
780 * Next, the S/G list.
782 ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
783 ata_for_each_sg(sg
, qc
) {
784 dma_addr_t addr
= sg_dma_address(sg
);
785 u32 sg_len
= sg_dma_len(sg
);
787 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
788 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
789 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
798 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
800 struct ata_port
*ap
= qc
->ap
;
801 struct ahci_port_priv
*pp
= ap
->private_data
;
802 int is_atapi
= is_atapi_taskfile(&qc
->tf
);
805 const u32 cmd_fis_len
= 5; /* five dwords */
809 * Fill in command table information. First, the header,
810 * a SATA Register - Host to Device command FIS.
812 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
814 ata_tf_to_fis(&qc
->tf
, cmd_tbl
, 0);
816 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
817 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
821 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
822 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
825 * Fill in command slot information.
827 opts
= cmd_fis_len
| n_elem
<< 16;
828 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
829 opts
|= AHCI_CMD_WRITE
;
831 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
833 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
836 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
838 struct ahci_port_priv
*pp
= ap
->private_data
;
839 struct ata_eh_info
*ehi
= &ap
->eh_info
;
840 unsigned int err_mask
= 0, action
= 0;
841 struct ata_queued_cmd
*qc
;
844 ata_ehi_clear_desc(ehi
);
846 /* AHCI needs SError cleared; otherwise, it might lock up */
847 serror
= ahci_scr_read(ap
, SCR_ERROR
);
848 ahci_scr_write(ap
, SCR_ERROR
, serror
);
850 /* analyze @irq_stat */
851 ata_ehi_push_desc(ehi
, "irq_stat 0x%08x", irq_stat
);
853 if (irq_stat
& PORT_IRQ_TF_ERR
)
854 err_mask
|= AC_ERR_DEV
;
856 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
857 err_mask
|= AC_ERR_HOST_BUS
;
858 action
|= ATA_EH_SOFTRESET
;
861 if (irq_stat
& PORT_IRQ_IF_ERR
) {
862 err_mask
|= AC_ERR_ATA_BUS
;
863 action
|= ATA_EH_SOFTRESET
;
864 ata_ehi_push_desc(ehi
, ", interface fatal error");
867 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
868 ata_ehi_hotplugged(ehi
);
869 ata_ehi_push_desc(ehi
, ", %s", irq_stat
& PORT_IRQ_CONNECT
?
870 "connection status changed" : "PHY RDY changed");
873 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
874 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
876 err_mask
|= AC_ERR_HSM
;
877 action
|= ATA_EH_SOFTRESET
;
878 ata_ehi_push_desc(ehi
, ", unknown FIS %08x %08x %08x %08x",
879 unk
[0], unk
[1], unk
[2], unk
[3]);
882 /* okay, let's hand over to EH */
883 ehi
->serror
|= serror
;
884 ehi
->action
|= action
;
886 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
888 qc
->err_mask
|= err_mask
;
890 ehi
->err_mask
|= err_mask
;
892 if (irq_stat
& PORT_IRQ_FREEZE
)
898 static void ahci_host_intr(struct ata_port
*ap
)
900 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
901 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
902 struct ata_eh_info
*ehi
= &ap
->eh_info
;
903 u32 status
, qc_active
;
906 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
907 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
909 if (unlikely(status
& PORT_IRQ_ERROR
)) {
910 ahci_error_intr(ap
, status
);
915 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
917 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
919 rc
= ata_qc_complete_multiple(ap
, qc_active
, NULL
);
923 ehi
->err_mask
|= AC_ERR_HSM
;
924 ehi
->action
|= ATA_EH_SOFTRESET
;
929 /* hmmm... a spurious interupt */
931 /* some devices send D2H reg with I bit set during NCQ command phase */
932 if (ap
->sactive
&& status
& PORT_IRQ_D2H_REG_FIS
)
935 /* ignore interim PIO setup fis interrupts */
936 if (ata_tag_valid(ap
->active_tag
)) {
937 struct ata_queued_cmd
*qc
=
938 ata_qc_from_tag(ap
, ap
->active_tag
);
940 if (qc
&& qc
->tf
.protocol
== ATA_PROT_PIO
&&
941 (status
& PORT_IRQ_PIOS_FIS
))
946 ata_port_printk(ap
, KERN_INFO
, "spurious interrupt "
947 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
948 status
, ap
->active_tag
, ap
->sactive
);
951 static void ahci_irq_clear(struct ata_port
*ap
)
956 static irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
, struct pt_regs
*regs
)
958 struct ata_host_set
*host_set
= dev_instance
;
959 struct ahci_host_priv
*hpriv
;
960 unsigned int i
, handled
= 0;
962 u32 irq_stat
, irq_ack
= 0;
966 hpriv
= host_set
->private_data
;
967 mmio
= host_set
->mmio_base
;
969 /* sigh. 0xffffffff is a valid return from h/w */
970 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
971 irq_stat
&= hpriv
->port_map
;
975 spin_lock(&host_set
->lock
);
977 for (i
= 0; i
< host_set
->n_ports
; i
++) {
980 if (!(irq_stat
& (1 << i
)))
983 ap
= host_set
->ports
[i
];
986 VPRINTK("port %u\n", i
);
988 VPRINTK("port %u (no irq)\n", i
);
990 dev_printk(KERN_WARNING
, host_set
->dev
,
991 "interrupt on disabled port %u\n", i
);
998 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
1002 spin_unlock(&host_set
->lock
);
1006 return IRQ_RETVAL(handled
);
1009 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1011 struct ata_port
*ap
= qc
->ap
;
1012 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
1014 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1015 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1016 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1017 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1022 static void ahci_freeze(struct ata_port
*ap
)
1024 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
1025 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1028 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1031 static void ahci_thaw(struct ata_port
*ap
)
1033 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
1034 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1038 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1039 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1040 writel(1 << ap
->id
, mmio
+ HOST_IRQ_STAT
);
1042 /* turn IRQ back on */
1043 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
1046 static void ahci_error_handler(struct ata_port
*ap
)
1048 if (!(ap
->flags
& ATA_FLAG_FROZEN
)) {
1049 /* restart engine */
1050 ahci_stop_engine(ap
);
1051 ahci_start_engine(ap
);
1054 /* perform recovery */
1055 ata_do_eh(ap
, ahci_prereset
, ahci_softreset
, ahci_hardreset
,
1059 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
1061 struct ata_port
*ap
= qc
->ap
;
1063 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1064 qc
->err_mask
|= AC_ERR_OTHER
;
1067 /* make DMA engine forget about the failed command */
1068 ahci_stop_engine(ap
);
1069 ahci_start_engine(ap
);
1073 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
1074 unsigned int port_idx
)
1076 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
1077 base
= ahci_port_base_ul(base
, port_idx
);
1078 VPRINTK("base now==0x%lx\n", base
);
1080 port
->cmd_addr
= base
;
1081 port
->scr_addr
= base
+ PORT_SCR
;
1086 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
1088 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1089 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1090 void __iomem
*mmio
= probe_ent
->mmio_base
;
1092 unsigned int i
, j
, using_dac
;
1094 void __iomem
*port_mmio
;
1096 cap_save
= readl(mmio
+ HOST_CAP
);
1097 cap_save
&= ( (1<<28) | (1<<17) );
1098 cap_save
|= (1 << 27);
1100 /* global controller reset */
1101 tmp
= readl(mmio
+ HOST_CTL
);
1102 if ((tmp
& HOST_RESET
) == 0) {
1103 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
1104 readl(mmio
+ HOST_CTL
); /* flush */
1107 /* reset must complete within 1 second, or
1108 * the hardware should be considered fried.
1112 tmp
= readl(mmio
+ HOST_CTL
);
1113 if (tmp
& HOST_RESET
) {
1114 dev_printk(KERN_ERR
, &pdev
->dev
,
1115 "controller reset failed (0x%x)\n", tmp
);
1119 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
1120 (void) readl(mmio
+ HOST_CTL
); /* flush */
1121 writel(cap_save
, mmio
+ HOST_CAP
);
1122 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
1123 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
1125 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
1128 pci_read_config_word(pdev
, 0x92, &tmp16
);
1130 pci_write_config_word(pdev
, 0x92, tmp16
);
1133 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
1134 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
1135 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
1137 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1138 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
1140 using_dac
= hpriv
->cap
& HOST_CAP_64
;
1142 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1143 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1145 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1147 dev_printk(KERN_ERR
, &pdev
->dev
,
1148 "64-bit DMA enable failed\n");
1153 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1155 dev_printk(KERN_ERR
, &pdev
->dev
,
1156 "32-bit DMA enable failed\n");
1159 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1161 dev_printk(KERN_ERR
, &pdev
->dev
,
1162 "32-bit consistent DMA enable failed\n");
1167 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
1168 #if 0 /* BIOSen initialize this incorrectly */
1169 if (!(hpriv
->port_map
& (1 << i
)))
1173 port_mmio
= ahci_port_base(mmio
, i
);
1174 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
1176 ahci_setup_port(&probe_ent
->port
[i
],
1177 (unsigned long) mmio
, i
);
1179 /* make sure port is not active */
1180 tmp
= readl(port_mmio
+ PORT_CMD
);
1181 VPRINTK("PORT_CMD 0x%x\n", tmp
);
1182 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
1183 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
1184 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
1185 PORT_CMD_FIS_RX
| PORT_CMD_START
);
1186 writel(tmp
, port_mmio
+ PORT_CMD
);
1187 readl(port_mmio
+ PORT_CMD
); /* flush */
1189 /* spec says 500 msecs for each bit, so
1190 * this is slightly incorrect.
1195 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
1200 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
1201 if ((tmp
& 0xf) == 0x3)
1206 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
1207 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
1208 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
1210 /* ack any pending irq events for this port */
1211 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1212 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1214 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1216 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
1219 tmp
= readl(mmio
+ HOST_CTL
);
1220 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1221 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
1222 tmp
= readl(mmio
+ HOST_CTL
);
1223 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1225 pci_set_master(pdev
);
1230 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
1232 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1233 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1234 void __iomem
*mmio
= probe_ent
->mmio_base
;
1235 u32 vers
, cap
, impl
, speed
;
1236 const char *speed_s
;
1240 vers
= readl(mmio
+ HOST_VERSION
);
1242 impl
= hpriv
->port_map
;
1244 speed
= (cap
>> 20) & 0xf;
1247 else if (speed
== 2)
1252 pci_read_config_word(pdev
, 0x0a, &cc
);
1255 else if (cc
== 0x0106)
1257 else if (cc
== 0x0104)
1262 dev_printk(KERN_INFO
, &pdev
->dev
,
1263 "AHCI %02x%02x.%02x%02x "
1264 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1267 (vers
>> 24) & 0xff,
1268 (vers
>> 16) & 0xff,
1272 ((cap
>> 8) & 0x1f) + 1,
1278 dev_printk(KERN_INFO
, &pdev
->dev
,
1284 cap
& (1 << 31) ? "64bit " : "",
1285 cap
& (1 << 30) ? "ncq " : "",
1286 cap
& (1 << 28) ? "ilck " : "",
1287 cap
& (1 << 27) ? "stag " : "",
1288 cap
& (1 << 26) ? "pm " : "",
1289 cap
& (1 << 25) ? "led " : "",
1291 cap
& (1 << 24) ? "clo " : "",
1292 cap
& (1 << 19) ? "nz " : "",
1293 cap
& (1 << 18) ? "only " : "",
1294 cap
& (1 << 17) ? "pmp " : "",
1295 cap
& (1 << 15) ? "pio " : "",
1296 cap
& (1 << 14) ? "slum " : "",
1297 cap
& (1 << 13) ? "part " : ""
1301 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1303 static int printed_version
;
1304 struct ata_probe_ent
*probe_ent
= NULL
;
1305 struct ahci_host_priv
*hpriv
;
1307 void __iomem
*mmio_base
;
1308 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1309 int have_msi
, pci_dev_busy
= 0;
1314 WARN_ON(ATA_MAX_QUEUE
> AHCI_MAX_CMDS
);
1316 if (!printed_version
++)
1317 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1319 rc
= pci_enable_device(pdev
);
1323 rc
= pci_request_regions(pdev
, DRV_NAME
);
1329 if (pci_enable_msi(pdev
) == 0)
1336 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1337 if (probe_ent
== NULL
) {
1342 memset(probe_ent
, 0, sizeof(*probe_ent
));
1343 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1344 INIT_LIST_HEAD(&probe_ent
->node
);
1346 mmio_base
= pci_iomap(pdev
, AHCI_PCI_BAR
, 0);
1347 if (mmio_base
== NULL
) {
1349 goto err_out_free_ent
;
1351 base
= (unsigned long) mmio_base
;
1353 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1356 goto err_out_iounmap
;
1358 memset(hpriv
, 0, sizeof(*hpriv
));
1360 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1361 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1362 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1363 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1364 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1366 probe_ent
->irq
= pdev
->irq
;
1367 probe_ent
->irq_flags
= SA_SHIRQ
;
1368 probe_ent
->mmio_base
= mmio_base
;
1369 probe_ent
->private_data
= hpriv
;
1372 hpriv
->flags
|= AHCI_FLAG_MSI
;
1374 /* JMicron-specific fixup: make sure we're in AHCI mode */
1375 if (pdev
->vendor
== 0x197b)
1376 pci_write_config_byte(pdev
, 0x41, 0xa1);
1378 /* initialize adapter */
1379 rc
= ahci_host_init(probe_ent
);
1383 if (hpriv
->cap
& HOST_CAP_NCQ
)
1384 probe_ent
->host_flags
|= ATA_FLAG_NCQ
;
1386 ahci_print_info(probe_ent
);
1388 /* FIXME: check ata_device_add return value */
1389 ata_device_add(probe_ent
);
1397 pci_iounmap(pdev
, mmio_base
);
1402 pci_disable_msi(pdev
);
1405 pci_release_regions(pdev
);
1408 pci_disable_device(pdev
);
1412 static void ahci_remove_one (struct pci_dev
*pdev
)
1414 struct device
*dev
= pci_dev_to_dev(pdev
);
1415 struct ata_host_set
*host_set
= dev_get_drvdata(dev
);
1416 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
1420 for (i
= 0; i
< host_set
->n_ports
; i
++)
1421 ata_port_detach(host_set
->ports
[i
]);
1423 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1424 free_irq(host_set
->irq
, host_set
);
1426 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1427 struct ata_port
*ap
= host_set
->ports
[i
];
1429 ata_scsi_release(ap
->host
);
1430 scsi_host_put(ap
->host
);
1434 pci_iounmap(pdev
, host_set
->mmio_base
);
1438 pci_disable_msi(pdev
);
1441 pci_release_regions(pdev
);
1442 pci_disable_device(pdev
);
1443 dev_set_drvdata(dev
, NULL
);
1446 static int __init
ahci_init(void)
1448 return pci_module_init(&ahci_pci_driver
);
1451 static void __exit
ahci_exit(void)
1453 pci_unregister_driver(&ahci_pci_driver
);
1457 MODULE_AUTHOR("Jeff Garzik");
1458 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1459 MODULE_LICENSE("GPL");
1460 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1461 MODULE_VERSION(DRV_VERSION
);
1463 module_init(ahci_init
);
1464 module_exit(ahci_exit
);