| blob | 97bd523a027853c3bc578bb283ad4a495607f11d |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <linux/init.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
33 /* Macro to make the code more readable. */
34 #ifdef CONFIG_8xx_CPU6
35 #define DO_8xx_CPU6(val, reg) \
36 li reg, val; \
37 stw reg, 12(r0); \
38 lwz reg, 12(r0);
39 #else
40 #define DO_8xx_CPU6(val, reg)
41 #endif
42 __HEAD
43 _ENTRY(_stext);
44 _ENTRY(_start);
46 /* MPC8xx
47 * This port was done on an MBX board with an 860. Right now I only
48 * support an ELF compressed (zImage) boot from EPPC-Bug because the
49 * code there loads up some registers before calling us:
50 * r3: ptr to board info data
51 * r4: initrd_start or if no initrd then 0
52 * r5: initrd_end - unused if r4 is 0
53 * r6: Start of command line string
54 * r7: End of command line string
55 *
56 * I decided to use conditional compilation instead of checking PVR and
57 * adding more processor specific branches around code I don't need.
58 * Since this is an embedded processor, I also appreciate any memory
59 * savings I can get.
60 *
61 * The MPC8xx does not have any BATs, but it supports large page sizes.
62 * We first initialize the MMU to support 8M byte pages, then load one
63 * entry into each of the instruction and data TLBs to map the first
64 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
65 * the "internal" processor registers before MMU_init is called.
66 *
67 * The TLB code currently contains a major hack. Since I use the condition
68 * code register, I have to save and restore it. I am out of registers, so
69 * I just store it in memory location 0 (the TLB handlers are not reentrant).
70 * To avoid making any decisions, I need to use the "segment" valid bit
71 * in the first level table, but that would require many changes to the
72 * Linux page directory/table functions that I don't want to do right now.
73 *
74 * I used to use SPRG2 for a temporary register in the TLB handler, but it
75 * has since been put to other uses. I now use a hack to save a register
76 * and the CCR at memory location 0.....Someday I'll fix this.....
77 * -- Dan
78 */
79 .globl __start
80 __start:
81 mr r31,r3 /* save parameters */
82 mr r30,r4
83 mr r29,r5
84 mr r28,r6
85 mr r27,r7
87 /* We have to turn on the MMU right away so we get cache modes
88 * set correctly.
89 */
90 bl initial_mmu
92 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
93 * ready to work.
94 */
96 turn_on_mmu:
97 mfmsr r0
98 ori r0,r0,MSR_DR|MSR_IR
99 mtspr SPRN_SRR1,r0
100 lis r0,start_here@h
101 ori r0,r0,start_here@l
102 mtspr SPRN_SRR0,r0
103 SYNC
104 rfi /* enables MMU */
106 /*
107 * Exception entry code. This code runs with address translation
108 * turned off, i.e. using physical addresses.
109 * We assume sprg3 has the physical address of the current
110 * task's thread_struct.
111 */
112 #define EXCEPTION_PROLOG \
113 mtspr SPRN_SPRG_SCRATCH0,r10; \
114 mtspr SPRN_SPRG_SCRATCH1,r11; \
115 mfcr r10; \
116 EXCEPTION_PROLOG_1; \
117 EXCEPTION_PROLOG_2
119 #define EXCEPTION_PROLOG_1 \
120 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
121 andi. r11,r11,MSR_PR; \
122 tophys(r11,r1); /* use tophys(r1) if kernel */ \
123 beq 1f; \
124 mfspr r11,SPRN_SPRG_THREAD; \
125 lwz r11,THREAD_INFO-THREAD(r11); \
126 addi r11,r11,THREAD_SIZE; \
127 tophys(r11,r11); \
128 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
131 #define EXCEPTION_PROLOG_2 \
132 CLR_TOP32(r11); \
133 stw r10,_CCR(r11); /* save registers */ \
134 stw r12,GPR12(r11); \
135 stw r9,GPR9(r11); \
136 mfspr r10,SPRN_SPRG_SCRATCH0; \
137 stw r10,GPR10(r11); \
138 mfspr r12,SPRN_SPRG_SCRATCH1; \
139 stw r12,GPR11(r11); \
140 mflr r10; \
141 stw r10,_LINK(r11); \
142 mfspr r12,SPRN_SRR0; \
143 mfspr r9,SPRN_SRR1; \
144 stw r1,GPR1(r11); \
145 stw r1,0(r11); \
146 tovirt(r1,r11); /* set new kernel sp */ \
147 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
148 MTMSRD(r10); /* (except for mach check in rtas) */ \
149 stw r0,GPR0(r11); \
150 SAVE_4GPRS(3, r11); \
151 SAVE_2GPRS(7, r11)
153 /*
154 * Note: code which follows this uses cr0.eq (set if from kernel),
155 * r11, r12 (SRR0), and r9 (SRR1).
156 *
157 * Note2: once we have set r1 we are in a position to take exceptions
158 * again, and we could thus set MSR:RI at that point.
159 */
161 /*
162 * Exception vectors.
163 */
164 #define EXCEPTION(n, label, hdlr, xfer) \
165 . = n; \
166 label: \
167 EXCEPTION_PROLOG; \
168 addi r3,r1,STACK_FRAME_OVERHEAD; \
169 xfer(n, hdlr)
171 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
172 li r10,trap; \
173 stw r10,_TRAP(r11); \
174 li r10,MSR_KERNEL; \
175 copyee(r10, r9); \
176 bl tfer; \
177 i##n: \
178 .long hdlr; \
179 .long ret
181 #define COPY_EE(d, s) rlwimi d,s,0,16,16
182 #define NOCOPY(d, s)
184 #define EXC_XFER_STD(n, hdlr) \
185 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
186 ret_from_except_full)
188 #define EXC_XFER_LITE(n, hdlr) \
189 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
190 ret_from_except)
192 #define EXC_XFER_EE(n, hdlr) \
193 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
194 ret_from_except_full)
196 #define EXC_XFER_EE_LITE(n, hdlr) \
197 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
198 ret_from_except)
200 /* System reset */
201 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
203 /* Machine check */
204 . = 0x200
205 MachineCheck:
206 EXCEPTION_PROLOG
207 mfspr r4,SPRN_DAR
208 stw r4,_DAR(r11)
209 mfspr r5,SPRN_DSISR
210 stw r5,_DSISR(r11)
211 addi r3,r1,STACK_FRAME_OVERHEAD
212 EXC_XFER_STD(0x200, machine_check_exception)
214 /* Data access exception.
215 * This is "never generated" by the MPC8xx. We jump to it for other
216 * translation errors.
217 */
218 . = 0x300
219 DataAccess:
220 EXCEPTION_PROLOG
221 mfspr r10,SPRN_DSISR
222 stw r10,_DSISR(r11)
223 mr r5,r10
224 mfspr r4,SPRN_DAR
225 EXC_XFER_EE_LITE(0x300, handle_page_fault)
227 /* Instruction access exception.
228 * This is "never generated" by the MPC8xx. We jump to it for other
229 * translation errors.
230 */
231 . = 0x400
232 InstructionAccess:
233 EXCEPTION_PROLOG
234 mr r4,r12
235 mr r5,r9
236 EXC_XFER_EE_LITE(0x400, handle_page_fault)
238 /* External interrupt */
239 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
241 /* Alignment exception */
242 . = 0x600
243 Alignment:
244 EXCEPTION_PROLOG
245 mfspr r4,SPRN_DAR
246 stw r4,_DAR(r11)
247 mfspr r5,SPRN_DSISR
248 stw r5,_DSISR(r11)
249 addi r3,r1,STACK_FRAME_OVERHEAD
250 EXC_XFER_EE(0x600, alignment_exception)
252 /* Program check exception */
253 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
255 /* No FPU on MPC8xx. This exception is not supposed to happen.
256 */
257 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
259 /* Decrementer */
260 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
262 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
263 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
265 /* System call */
266 . = 0xc00
267 SystemCall:
268 EXCEPTION_PROLOG
269 EXC_XFER_EE_LITE(0xc00, DoSyscall)
271 /* Single step - not used on 601 */
272 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
273 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
274 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
276 /* On the MPC8xx, this is a software emulation interrupt. It occurs
277 * for all unimplemented and illegal instructions.
278 */
279 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
281 . = 0x1100
282 /*
283 * For the MPC8xx, this is a software tablewalk to load the instruction
284 * TLB. It is modelled after the example in the Motorola manual. The task
285 * switch loads the M_TWB register with the pointer to the first level table.
286 * If we discover there is no second level table (value is zero) or if there
287 * is an invalid pte, we load that into the TLB, which causes another fault
288 * into the TLB Error interrupt where we can handle such problems.
289 * We have to use the MD_xxx registers for the tablewalk because the
290 * equivalent MI_xxx registers only perform the attribute functions.
291 */
292 InstructionTLBMiss:
293 #ifdef CONFIG_8xx_CPU6
294 stw r3, 8(r0)
295 #endif
296 DO_8xx_CPU6(0x3f80, r3)
297 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
298 mfcr r10
299 stw r10, 0(r0)
300 stw r11, 4(r0)
301 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
302 #ifdef CONFIG_8xx_CPU15
303 addi r11, r10, 0x1000
304 tlbie r11
305 addi r11, r10, -0x1000
306 tlbie r11
307 #endif
308 DO_8xx_CPU6(0x3780, r3)
309 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
310 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
312 /* If we are faulting a kernel address, we have to use the
313 * kernel page tables.
314 */
315 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
316 beq 3f
317 lis r11, swapper_pg_dir@h
318 ori r11, r11, swapper_pg_dir@l
319 rlwimi r10, r11, 0, 2, 19
320 3:
321 lwz r11, 0(r10) /* Get the level 1 entry */
322 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
323 beq 2f /* If zero, don't try to find a pte */
325 /* We have a pte table, so load the MI_TWC with the attributes
326 * for this "segment."
327 */
328 ori r11,r11,1 /* Set valid bit */
329 DO_8xx_CPU6(0x2b80, r3)
330 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
331 DO_8xx_CPU6(0x3b80, r3)
332 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
333 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
334 lwz r10, 0(r11) /* Get the pte */
336 andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
337 cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
338 bne- cr0, 2f
340 /* Clear PP lsb, 0x400 */
341 rlwinm r10, r10, 0, 22, 20
343 /* The Linux PTE won't go exactly into the MMU TLB.
344 * Software indicator bits 22 and 28 must be clear.
345 * Software indicator bits 24, 25, 26, and 27 must be
346 * set. All other Linux PTE bits control the behavior
347 * of the MMU.
348 */
349 li r11, 0x00f0
350 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
351 DO_8xx_CPU6(0x2d80, r3)
352 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
354 mfspr r10, SPRN_M_TW /* Restore registers */
355 lwz r11, 0(r0)
356 mtcr r11
357 lwz r11, 4(r0)
358 #ifdef CONFIG_8xx_CPU6
359 lwz r3, 8(r0)
360 #endif
361 rfi
362 2:
363 mfspr r11, SPRN_SRR1
364 /* clear all error bits as TLB Miss
365 * sets a few unconditionally
366 */
367 rlwinm r11, r11, 0, 0xffff
368 mtspr SPRN_SRR1, r11
370 mfspr r10, SPRN_M_TW /* Restore registers */
371 lwz r11, 0(r0)
372 mtcr r11
373 lwz r11, 4(r0)
374 #ifdef CONFIG_8xx_CPU6
375 lwz r3, 8(r0)
376 #endif
377 b InstructionAccess
379 . = 0x1200
380 DataStoreTLBMiss:
381 #ifdef CONFIG_8xx_CPU6
382 stw r3, 8(r0)
383 #endif
384 DO_8xx_CPU6(0x3f80, r3)
385 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
386 mfcr r10
387 stw r10, 0(r0)
388 stw r11, 4(r0)
389 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
391 /* If we are faulting a kernel address, we have to use the
392 * kernel page tables.
393 */
394 andi. r11, r10, 0x0800
395 beq 3f
396 lis r11, swapper_pg_dir@h
397 ori r11, r11, swapper_pg_dir@l
398 rlwimi r10, r11, 0, 2, 19
399 3:
400 lwz r11, 0(r10) /* Get the level 1 entry */
401 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
402 beq 2f /* If zero, don't try to find a pte */
404 /* We have a pte table, so load fetch the pte from the table.
405 */
406 ori r11, r11, 1 /* Set valid bit in physical L2 page */
407 DO_8xx_CPU6(0x3b80, r3)
408 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
409 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
410 lwz r10, 0(r10) /* Get the pte */
412 /* Insert the Guarded flag into the TWC from the Linux PTE.
413 * It is bit 27 of both the Linux PTE and the TWC (at least
414 * I got that right :-). It will be better when we can put
415 * this into the Linux pgd/pmd and load it in the operation
416 * above.
417 */
418 rlwimi r11, r10, 0, 27, 27
419 DO_8xx_CPU6(0x3b80, r3)
420 mtspr SPRN_MD_TWC, r11
422 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
423 * We also need to know if the insn is a load/store, so:
424 * Clear _PAGE_PRESENT and load that which will
425 * trap into DTLB Error with store bit set accordinly.
426 */
427 /* PRESENT=0x1, ACCESSED=0x20
428 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
429 * r10 = (r10 & ~PRESENT) | r11;
430 */
431 rlwinm r11, r10, 32-5, 31, 31
432 and r11, r11, r10
433 rlwimi r10, r11, 0, 31, 31
435 /* Honour kernel RO, User NA */
436 andi. r11, r10, _PAGE_USER | _PAGE_RW
437 bne- cr0, 5f
438 ori r10,r10, 0x200 /* Extended encoding, bit 22 */
439 5: xori r10, r10, _PAGE_RW /* invert RW bit */
441 /* The Linux PTE won't go exactly into the MMU TLB.
442 * Software indicator bits 22 and 28 must be clear.
443 * Software indicator bits 24, 25, 26, and 27 must be
444 * set. All other Linux PTE bits control the behavior
445 * of the MMU.
446 */
447 2: li r11, 0x00f0
448 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
449 DO_8xx_CPU6(0x3d80, r3)
450 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
452 mfspr r10, SPRN_M_TW /* Restore registers */
453 lwz r11, 0(r0)
454 mtcr r11
455 lwz r11, 4(r0)
456 #ifdef CONFIG_8xx_CPU6
457 lwz r3, 8(r0)
458 #endif
459 rfi
461 /* This is an instruction TLB error on the MPC8xx. This could be due
462 * to many reasons, such as executing guarded memory or illegal instruction
463 * addresses. There is nothing to do but handle a big time error fault.
464 */
465 . = 0x1300
466 InstructionTLBError:
467 b InstructionAccess
469 /* This is the data TLB error on the MPC8xx. This could be due to
470 * many reasons, including a dirty update to a pte. We can catch that
471 * one here, but anything else is an error. First, we track down the
472 * Linux pte. If it is valid, write access is allowed, but the
473 * page dirty bit is not set, we will set it and reload the TLB. For
474 * any other case, we bail out to a higher level function that can
475 * handle it.
476 */
477 . = 0x1400
478 DataTLBError:
479 #ifdef CONFIG_8xx_CPU6
480 stw r3, 8(r0)
481 #endif
482 DO_8xx_CPU6(0x3f80, r3)
483 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
484 mfcr r10
485 stw r10, 0(r0)
486 stw r11, 4(r0)
488 mfspr r11, SPRN_DSISR
489 andis. r11, r11, 0x4800 /* !translation or protection */
490 bne 2f /* branch if either is set */
491 /* Only Change bit left now, do it here as it is faster
492 * than trapping to the C fault handler.
493 */
495 /* The EA of a data TLB miss is automatically stored in the MD_EPN
496 * register. The EA of a data TLB error is automatically stored in
497 * the DAR, but not the MD_EPN register. We must copy the 20 most
498 * significant bits of the EA from the DAR to MD_EPN before we
499 * start walking the page tables. We also need to copy the CASID
500 * value from the M_CASID register.
501 * Addendum: The EA of a data TLB error is _supposed_ to be stored
502 * in DAR, but it seems that this doesn't happen in some cases, such
503 * as when the error is due to a dcbi instruction to a page with a
504 * TLB that doesn't have the changed bit set. In such cases, there
505 * does not appear to be any way to recover the EA of the error
506 * since it is neither in DAR nor MD_EPN. As a workaround, the
507 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
508 * are initialized in mapin_ram(). This will avoid the problem,
509 * assuming we only use the dcbi instruction on kernel addresses.
510 */
511 mfspr r10, SPRN_DAR
512 rlwinm r11, r10, 0, 0, 19
513 ori r11, r11, MD_EVALID
514 mfspr r10, SPRN_M_CASID
515 rlwimi r11, r10, 0, 28, 31
516 DO_8xx_CPU6(0x3780, r3)
517 mtspr SPRN_MD_EPN, r11
519 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
521 /* If we are faulting a kernel address, we have to use the
522 * kernel page tables.
523 */
524 andi. r11, r10, 0x0800
525 beq 3f
526 lis r11, swapper_pg_dir@h
527 ori r11, r11, swapper_pg_dir@l
528 rlwimi r10, r11, 0, 2, 19
529 3:
530 lwz r11, 0(r10) /* Get the level 1 entry */
531 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
532 beq 2f /* If zero, bail */
534 /* We have a pte table, so fetch the pte from the table.
535 */
536 ori r11, r11, 1 /* Set valid bit in physical L2 page */
537 DO_8xx_CPU6(0x3b80, r3)
538 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
539 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
540 lwz r10, 0(r11) /* Get the pte */
542 ori r10, r10, _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HWWRITE
543 stw r10, 0(r11) /* and update pte in table */
544 xori r10, r10, _PAGE_RW /* RW bit is inverted */
546 /* The Linux PTE won't go exactly into the MMU TLB.
547 * Software indicator bits 22 and 28 must be clear.
548 * Software indicator bits 24, 25, 26, and 27 must be
549 * set. All other Linux PTE bits control the behavior
550 * of the MMU.
551 */
552 li r11, 0x00f0
553 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
554 DO_8xx_CPU6(0x3d80, r3)
555 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
557 mfspr r10, SPRN_M_TW /* Restore registers */
558 lwz r11, 0(r0)
559 mtcr r11
560 lwz r11, 4(r0)
561 #ifdef CONFIG_8xx_CPU6
562 lwz r3, 8(r0)
563 #endif
564 rfi
565 2:
566 mfspr r10, SPRN_M_TW /* Restore registers */
567 lwz r11, 0(r0)
568 mtcr r11
569 lwz r11, 4(r0)
570 #ifdef CONFIG_8xx_CPU6
571 lwz r3, 8(r0)
572 #endif
573 b DataAccess
575 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
576 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
577 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
578 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
579 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
580 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
581 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
583 /* On the MPC8xx, these next four traps are used for development
584 * support of breakpoints and such. Someday I will get around to
585 * using them.
586 */
587 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
588 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
589 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
590 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
592 . = 0x2000
594 .globl giveup_fpu
595 giveup_fpu:
596 blr
598 /*
599 * This is where the main kernel code starts.
600 */
601 start_here:
602 /* ptr to current */
603 lis r2,init_task@h
604 ori r2,r2,init_task@l
606 /* ptr to phys current thread */
607 tophys(r4,r2)
608 addi r4,r4,THREAD /* init task's THREAD */
609 mtspr SPRN_SPRG_THREAD,r4
610 li r3,0
611 /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */
612 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
614 /* stack */
615 lis r1,init_thread_union@ha
616 addi r1,r1,init_thread_union@l
617 li r0,0
618 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
620 bl early_init /* We have to do this with MMU on */
622 /*
623 * Decide what sort of machine this is and initialize the MMU.
624 */
625 mr r3,r31
626 mr r4,r30
627 mr r5,r29
628 mr r6,r28
629 mr r7,r27
630 bl machine_init
631 bl MMU_init
633 /*
634 * Go back to running unmapped so we can load up new values
635 * and change to using our exception vectors.
636 * On the 8xx, all we have to do is invalidate the TLB to clear
637 * the old 8M byte TLB mappings and load the page table base register.
638 */
639 /* The right way to do this would be to track it down through
640 * init's THREAD like the context switch code does, but this is
641 * easier......until someone changes init's static structures.
642 */
643 lis r6, swapper_pg_dir@h
644 ori r6, r6, swapper_pg_dir@l
645 tophys(r6,r6)
646 #ifdef CONFIG_8xx_CPU6
647 lis r4, cpu6_errata_word@h
648 ori r4, r4, cpu6_errata_word@l
649 li r3, 0x3980
650 stw r3, 12(r4)
651 lwz r3, 12(r4)
652 #endif
653 mtspr SPRN_M_TWB, r6
654 lis r4,2f@h
655 ori r4,r4,2f@l
656 tophys(r4,r4)
657 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
658 mtspr SPRN_SRR0,r4
659 mtspr SPRN_SRR1,r3
660 rfi
661 /* Load up the kernel context */
662 2:
663 SYNC /* Force all PTE updates to finish */
664 tlbia /* Clear all TLB entries */
665 sync /* wait for tlbia/tlbie to finish */
666 TLBSYNC /* ... on all CPUs */
668 /* set up the PTE pointers for the Abatron bdiGDB.
669 */
670 tovirt(r6,r6)
671 lis r5, abatron_pteptrs@h
672 ori r5, r5, abatron_pteptrs@l
673 stw r5, 0xf0(r0) /* Must match your Abatron config file */
674 tophys(r5,r5)
675 stw r6, 0(r5)
677 /* Now turn on the MMU for real! */
678 li r4,MSR_KERNEL
679 lis r3,start_kernel@h
680 ori r3,r3,start_kernel@l
681 mtspr SPRN_SRR0,r3
682 mtspr SPRN_SRR1,r4
683 rfi /* enable MMU and jump to start_kernel */
685 /* Set up the initial MMU state so we can do the first level of
686 * kernel initialization. This maps the first 8 MBytes of memory 1:1
687 * virtual to physical. Also, set the cache mode since that is defined
688 * by TLB entries and perform any additional mapping (like of the IMMR).
689 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
690 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
691 * these mappings is mapped by page tables.
692 */
693 initial_mmu:
694 tlbia /* Invalidate all TLB entries */
695 #ifdef CONFIG_PIN_TLB
696 lis r8, MI_RSV4I@h
697 ori r8, r8, 0x1c00
698 #else
699 li r8, 0
700 #endif
701 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
703 #ifdef CONFIG_PIN_TLB
704 lis r10, (MD_RSV4I | MD_RESETVAL)@h
705 ori r10, r10, 0x1c00
706 mr r8, r10
707 #else
708 lis r10, MD_RESETVAL@h
709 #endif
710 #ifndef CONFIG_8xx_COPYBACK
711 oris r10, r10, MD_WTDEF@h
712 #endif
713 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
715 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
716 * we can load the instruction and data TLB registers with the
717 * same values.
718 */
719 lis r8, KERNELBASE@h /* Create vaddr for TLB */
720 ori r8, r8, MI_EVALID /* Mark it valid */
721 mtspr SPRN_MI_EPN, r8
722 mtspr SPRN_MD_EPN, r8
723 li r8, MI_PS8MEG /* Set 8M byte page */
724 ori r8, r8, MI_SVALID /* Make it valid */
725 mtspr SPRN_MI_TWC, r8
726 mtspr SPRN_MD_TWC, r8
727 li r8, MI_BOOTINIT /* Create RPN for address 0 */
728 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
729 mtspr SPRN_MD_RPN, r8
730 lis r8, MI_Kp@h /* Set the protection mode */
731 mtspr SPRN_MI_AP, r8
732 mtspr SPRN_MD_AP, r8
734 /* Map another 8 MByte at the IMMR to get the processor
735 * internal registers (among other things).
736 */
737 #ifdef CONFIG_PIN_TLB
738 addi r10, r10, 0x0100
739 mtspr SPRN_MD_CTR, r10
740 #endif
741 mfspr r9, 638 /* Get current IMMR */
742 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
744 mr r8, r9 /* Create vaddr for TLB */
745 ori r8, r8, MD_EVALID /* Mark it valid */
746 mtspr SPRN_MD_EPN, r8
747 li r8, MD_PS8MEG /* Set 8M byte page */
748 ori r8, r8, MD_SVALID /* Make it valid */
749 mtspr SPRN_MD_TWC, r8
750 mr r8, r9 /* Create paddr for TLB */
751 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
752 mtspr SPRN_MD_RPN, r8
754 #ifdef CONFIG_PIN_TLB
755 /* Map two more 8M kernel data pages.
756 */
757 addi r10, r10, 0x0100
758 mtspr SPRN_MD_CTR, r10
760 lis r8, KERNELBASE@h /* Create vaddr for TLB */
761 addis r8, r8, 0x0080 /* Add 8M */
762 ori r8, r8, MI_EVALID /* Mark it valid */
763 mtspr SPRN_MD_EPN, r8
764 li r9, MI_PS8MEG /* Set 8M byte page */
765 ori r9, r9, MI_SVALID /* Make it valid */
766 mtspr SPRN_MD_TWC, r9
767 li r11, MI_BOOTINIT /* Create RPN for address 0 */
768 addis r11, r11, 0x0080 /* Add 8M */
769 mtspr SPRN_MD_RPN, r11
771 addis r8, r8, 0x0080 /* Add 8M */
772 mtspr SPRN_MD_EPN, r8
773 mtspr SPRN_MD_TWC, r9
774 addis r11, r11, 0x0080 /* Add 8M */
775 mtspr SPRN_MD_RPN, r11
776 #endif
778 /* Since the cache is enabled according to the information we
779 * just loaded into the TLB, invalidate and enable the caches here.
780 * We should probably check/set other modes....later.
781 */
782 lis r8, IDC_INVALL@h
783 mtspr SPRN_IC_CST, r8
784 mtspr SPRN_DC_CST, r8
785 lis r8, IDC_ENABLE@h
786 mtspr SPRN_IC_CST, r8
787 #ifdef CONFIG_8xx_COPYBACK
788 mtspr SPRN_DC_CST, r8
789 #else
790 /* For a debug option, I left this here to easily enable
791 * the write through cache mode
792 */
793 lis r8, DC_SFWT@h
794 mtspr SPRN_DC_CST, r8
795 lis r8, IDC_ENABLE@h
796 mtspr SPRN_DC_CST, r8
797 #endif
798 blr
801 /*
802 * Set up to use a given MMU context.
803 * r3 is context number, r4 is PGD pointer.
804 *
805 * We place the physical address of the new task page directory loaded
806 * into the MMU base register, and set the ASID compare register with
807 * the new "context."
808 */
809 _GLOBAL(set_context)
811 #ifdef CONFIG_BDI_SWITCH
812 /* Context switch the PTE pointer for the Abatron BDI2000.
813 * The PGDIR is passed as second argument.
814 */
815 lis r5, KERNELBASE@h
816 lwz r5, 0xf0(r5)
817 stw r4, 0x4(r5)
818 #endif
820 #ifdef CONFIG_8xx_CPU6
821 lis r6, cpu6_errata_word@h
822 ori r6, r6, cpu6_errata_word@l
823 tophys (r4, r4)
824 li r7, 0x3980
825 stw r7, 12(r6)
826 lwz r7, 12(r6)
827 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
828 li r7, 0x3380
829 stw r7, 12(r6)
830 lwz r7, 12(r6)
831 mtspr SPRN_M_CASID, r3 /* Update context */
832 #else
833 mtspr SPRN_M_CASID,r3 /* Update context */
834 tophys (r4, r4)
835 mtspr SPRN_M_TWB, r4 /* and pgd */
836 #endif
837 SYNC
838 blr
840 #ifdef CONFIG_8xx_CPU6
841 /* It's here because it is unique to the 8xx.
842 * It is important we get called with interrupts disabled. I used to
843 * do that, but it appears that all code that calls this already had
844 * interrupt disabled.
845 */
846 .globl set_dec_cpu6
847 set_dec_cpu6:
848 lis r7, cpu6_errata_word@h
849 ori r7, r7, cpu6_errata_word@l
850 li r4, 0x2c00
851 stw r4, 8(r7)
852 lwz r4, 8(r7)
853 mtspr 22, r3 /* Update Decrementer */
854 SYNC
855 blr
856 #endif
858 /*
859 * We put a few things here that have to be page-aligned.
860 * This stuff goes at the beginning of the data segment,
861 * which is page-aligned.
862 */
863 .data
864 .globl sdata
865 sdata:
866 .globl empty_zero_page
867 empty_zero_page:
868 .space 4096
870 .globl swapper_pg_dir
871 swapper_pg_dir:
872 .space 4096
874 /* Room for two PTE table poiners, usually the kernel and current user
875 * pointer to their respective root page table (pgdir).
876 */
877 abatron_pteptrs:
878 .space 8
880 #ifdef CONFIG_8xx_CPU6
881 .globl cpu6_errata_word
882 cpu6_errata_word:
883 .space 16
884 #endif