2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
22 * Hardware information only available under NDA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "1.0"
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
44 #define PDPRINTK(fmt, args...)
53 PDC_100_MHZ
= 100000000,
54 PDC_133_MHZ
= 133333333,
58 PDC_GLOBAL_CTL
= 0x1108,
61 PDC_BYTE_COUNT
= 0x1120,
65 static int pdc2027x_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
66 static int pdc2027x_prereset(struct ata_link
*link
, unsigned long deadline
);
67 static void pdc2027x_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
);
68 static void pdc2027x_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
69 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd
*qc
);
70 static unsigned long pdc2027x_mode_filter(struct ata_device
*adev
, unsigned long mask
);
71 static int pdc2027x_cable_detect(struct ata_port
*ap
);
72 static int pdc2027x_set_mode(struct ata_link
*link
, struct ata_device
**r_failed
);
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
82 static struct pdc2027x_pio_timing
{
83 u8 value0
, value1
, value2
;
84 } pdc2027x_pio_timing_tbl
[] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
92 static struct pdc2027x_mdma_timing
{
94 } pdc2027x_mdma_timing_tbl
[] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
100 static struct pdc2027x_udma_timing
{
101 u8 value0
, value1
, value2
;
102 } pdc2027x_udma_timing_tbl
[] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
112 static const struct pci_device_id pdc2027x_pci_tbl
[] = {
113 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20268
), PDC_UDMA_100
},
114 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20269
), PDC_UDMA_133
},
115 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20270
), PDC_UDMA_100
},
116 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20271
), PDC_UDMA_133
},
117 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20275
), PDC_UDMA_133
},
118 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20276
), PDC_UDMA_133
},
119 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20277
), PDC_UDMA_133
},
121 { } /* terminate list */
124 static struct pci_driver pdc2027x_pci_driver
= {
126 .id_table
= pdc2027x_pci_tbl
,
127 .probe
= pdc2027x_init_one
,
128 .remove
= ata_pci_remove_one
,
131 static struct scsi_host_template pdc2027x_sht
= {
132 ATA_BMDMA_SHT(DRV_NAME
),
135 static struct ata_port_operations pdc2027x_pata100_ops
= {
136 .inherits
= &ata_bmdma_port_ops
,
137 .check_atapi_dma
= pdc2027x_check_atapi_dma
,
138 .cable_detect
= pdc2027x_cable_detect
,
139 .prereset
= pdc2027x_prereset
,
142 static struct ata_port_operations pdc2027x_pata133_ops
= {
143 .inherits
= &pdc2027x_pata100_ops
,
144 .mode_filter
= pdc2027x_mode_filter
,
145 .set_piomode
= pdc2027x_set_piomode
,
146 .set_dmamode
= pdc2027x_set_dmamode
,
147 .set_mode
= pdc2027x_set_mode
,
150 static struct ata_port_info pdc2027x_port_info
[] = {
153 .flags
= ATA_FLAG_SLAVE_POSS
,
154 .pio_mask
= ATA_PIO4
,
155 .mwdma_mask
= ATA_MWDMA2
,
156 .udma_mask
= ATA_UDMA5
,
157 .port_ops
= &pdc2027x_pata100_ops
,
161 .flags
= ATA_FLAG_SLAVE_POSS
,
162 .pio_mask
= ATA_PIO4
,
163 .mwdma_mask
= ATA_MWDMA2
,
164 .udma_mask
= ATA_UDMA6
,
165 .port_ops
= &pdc2027x_pata133_ops
,
169 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
170 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
171 MODULE_LICENSE("GPL");
172 MODULE_VERSION(DRV_VERSION
);
173 MODULE_DEVICE_TABLE(pci
, pdc2027x_pci_tbl
);
176 * port_mmio - Get the MMIO address of PDC2027x extended registers
178 * @offset: offset from mmio base
180 static inline void __iomem
*port_mmio(struct ata_port
*ap
, unsigned int offset
)
182 return ap
->host
->iomap
[PDC_MMIO_BAR
] + ap
->port_no
* 0x100 + offset
;
186 * dev_mmio - Get the MMIO address of PDC2027x extended registers
189 * @offset: offset from mmio base
191 static inline void __iomem
*dev_mmio(struct ata_port
*ap
, struct ata_device
*adev
, unsigned int offset
)
193 u8 adj
= (adev
->devno
) ? 0x08 : 0x00;
194 return port_mmio(ap
, offset
) + adj
;
198 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
199 * @ap: Port for which cable detect info is desired
201 * Read 80c cable indicator from Promise extended register.
202 * This register is latched when the system is reset.
205 * None (inherited from caller).
207 static int pdc2027x_cable_detect(struct ata_port
*ap
)
211 /* check cable detect results */
212 cgcr
= ioread32(port_mmio(ap
, PDC_GLOBAL_CTL
));
213 if (cgcr
& (1 << 26))
216 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap
->port_no
);
218 return ATA_CBL_PATA80
;
220 printk(KERN_INFO DRV_NAME
": 40-conductor cable detected on port %d\n", ap
->port_no
);
221 return ATA_CBL_PATA40
;
225 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
228 static inline int pdc2027x_port_enabled(struct ata_port
*ap
)
230 return ioread8(port_mmio(ap
, PDC_ATA_CTL
)) & 0x02;
234 * pdc2027x_prereset - prereset for PATA host controller
236 * @deadline: deadline jiffies for the operation
238 * Probeinit including cable detection.
241 * None (inherited from caller).
244 static int pdc2027x_prereset(struct ata_link
*link
, unsigned long deadline
)
246 /* Check whether port enabled */
247 if (!pdc2027x_port_enabled(link
->ap
))
249 return ata_sff_prereset(link
, deadline
);
253 * pdc2720x_mode_filter - mode selection filter
255 * @mask: list of modes proposed
257 * Block UDMA on devices that cause trouble with this controller.
260 static unsigned long pdc2027x_mode_filter(struct ata_device
*adev
, unsigned long mask
)
262 unsigned char model_num
[ATA_ID_PROD_LEN
+ 1];
263 struct ata_device
*pair
= ata_dev_pair(adev
);
265 if (adev
->class != ATA_DEV_ATA
|| adev
->devno
== 0 || pair
== NULL
)
268 /* Check for slave of a Maxtor at UDMA6 */
269 ata_id_c_string(pair
->id
, model_num
, ATA_ID_PROD
,
270 ATA_ID_PROD_LEN
+ 1);
271 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
272 if (strstr(model_num
, "Maxtor") == NULL
&& pair
->dma_mode
== XFER_UDMA_6
)
273 mask
&= ~ (1 << (6 + ATA_SHIFT_UDMA
));
279 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
280 * @ap: Port to configure
283 * Set PIO mode for device.
286 * None (inherited from caller).
289 static void pdc2027x_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
291 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
294 PDPRINTK("adev->pio_mode[%X]\n", adev
->pio_mode
);
298 printk(KERN_ERR DRV_NAME
": Unknown pio mode [%d] ignored\n", pio
);
303 /* Set the PIO timing registers using value table for 133MHz */
304 PDPRINTK("Set pio regs... \n");
306 ctcr0
= ioread32(dev_mmio(ap
, adev
, PDC_CTCR0
));
308 ctcr0
|= pdc2027x_pio_timing_tbl
[pio
].value0
|
309 (pdc2027x_pio_timing_tbl
[pio
].value1
<< 8);
310 iowrite32(ctcr0
, dev_mmio(ap
, adev
, PDC_CTCR0
));
312 ctcr1
= ioread32(dev_mmio(ap
, adev
, PDC_CTCR1
));
314 ctcr1
|= (pdc2027x_pio_timing_tbl
[pio
].value2
<< 24);
315 iowrite32(ctcr1
, dev_mmio(ap
, adev
, PDC_CTCR1
));
317 PDPRINTK("Set pio regs done\n");
319 PDPRINTK("Set to pio mode[%u] \n", pio
);
323 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
324 * @ap: Port to configure
327 * Set UDMA mode for device.
330 * None (inherited from caller).
332 static void pdc2027x_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
334 unsigned int dma_mode
= adev
->dma_mode
;
337 if ((dma_mode
>= XFER_UDMA_0
) &&
338 (dma_mode
<= XFER_UDMA_6
)) {
339 /* Set the UDMA timing registers with value table for 133MHz */
340 unsigned int udma_mode
= dma_mode
& 0x07;
342 if (dma_mode
== XFER_UDMA_2
) {
345 * If tHOLD is '1', the hardware will add half clock for data hold time.
346 * This code segment seems to be no effect. tHOLD will be overwritten below.
348 ctcr1
= ioread32(dev_mmio(ap
, adev
, PDC_CTCR1
));
349 iowrite32(ctcr1
& ~(1 << 7), dev_mmio(ap
, adev
, PDC_CTCR1
));
352 PDPRINTK("Set udma regs... \n");
354 ctcr1
= ioread32(dev_mmio(ap
, adev
, PDC_CTCR1
));
356 ctcr1
|= pdc2027x_udma_timing_tbl
[udma_mode
].value0
|
357 (pdc2027x_udma_timing_tbl
[udma_mode
].value1
<< 8) |
358 (pdc2027x_udma_timing_tbl
[udma_mode
].value2
<< 16);
359 iowrite32(ctcr1
, dev_mmio(ap
, adev
, PDC_CTCR1
));
361 PDPRINTK("Set udma regs done\n");
363 PDPRINTK("Set to udma mode[%u] \n", udma_mode
);
365 } else if ((dma_mode
>= XFER_MW_DMA_0
) &&
366 (dma_mode
<= XFER_MW_DMA_2
)) {
367 /* Set the MDMA timing registers with value table for 133MHz */
368 unsigned int mdma_mode
= dma_mode
& 0x07;
370 PDPRINTK("Set mdma regs... \n");
371 ctcr0
= ioread32(dev_mmio(ap
, adev
, PDC_CTCR0
));
374 ctcr0
|= (pdc2027x_mdma_timing_tbl
[mdma_mode
].value0
<< 16) |
375 (pdc2027x_mdma_timing_tbl
[mdma_mode
].value1
<< 24);
377 iowrite32(ctcr0
, dev_mmio(ap
, adev
, PDC_CTCR0
));
378 PDPRINTK("Set mdma regs done\n");
380 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode
);
382 printk(KERN_ERR DRV_NAME
": Unknown dma mode [%u] ignored\n", dma_mode
);
387 * pdc2027x_set_mode - Set the timing registers back to correct values.
388 * @link: link to configure
389 * @r_failed: Returned device for failure
391 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
392 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
393 * This function overwrites the possibly incorrect values set by the hardware to be correct.
395 static int pdc2027x_set_mode(struct ata_link
*link
, struct ata_device
**r_failed
)
397 struct ata_port
*ap
= link
->ap
;
398 struct ata_device
*dev
;
401 rc
= ata_do_set_mode(link
, r_failed
);
405 ata_for_each_dev(dev
, link
, ENABLED
) {
406 pdc2027x_set_piomode(ap
, dev
);
409 * Enable prefetch if the device support PIO only.
411 if (dev
->xfer_shift
== ATA_SHIFT_PIO
) {
412 u32 ctcr1
= ioread32(dev_mmio(ap
, dev
, PDC_CTCR1
));
414 iowrite32(ctcr1
, dev_mmio(ap
, dev
, PDC_CTCR1
));
416 PDPRINTK("Turn on prefetch\n");
418 pdc2027x_set_dmamode(ap
, dev
);
425 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
426 * @qc: Metadata associated with taskfile to check
429 * None (inherited from caller).
431 * RETURNS: 0 when ATAPI DMA can be used
434 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd
*qc
)
436 struct scsi_cmnd
*cmd
= qc
->scsicmd
;
437 u8
*scsicmd
= cmd
->cmnd
;
438 int rc
= 1; /* atapi dma off by default */
441 * This workaround is from Promise's GPL driver.
442 * If ATAPI DMA is used for commands not in the
443 * following white list, say MODE_SENSE and REQUEST_SENSE,
444 * pdc2027x might hit the irq lost problem.
446 switch (scsicmd
[0]) {
453 case 0xad: /* READ_DVD_STRUCTURE */
454 case 0xbe: /* READ_CD */
455 /* ATAPI DMA is ok */
466 * pdc_read_counter - Read the ctr counter
467 * @host: target ATA host
470 static long pdc_read_counter(struct ata_host
*host
)
472 void __iomem
*mmio_base
= host
->iomap
[PDC_MMIO_BAR
];
475 u32 bccrl
, bccrh
, bccrlv
, bccrhv
;
478 bccrl
= ioread32(mmio_base
+ PDC_BYTE_COUNT
) & 0x7fff;
479 bccrh
= ioread32(mmio_base
+ PDC_BYTE_COUNT
+ 0x100) & 0x7fff;
481 /* Read the counter values again for verification */
482 bccrlv
= ioread32(mmio_base
+ PDC_BYTE_COUNT
) & 0x7fff;
483 bccrhv
= ioread32(mmio_base
+ PDC_BYTE_COUNT
+ 0x100) & 0x7fff;
485 counter
= (bccrh
<< 15) | bccrl
;
487 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh
, bccrl
);
488 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv
, bccrlv
);
491 * The 30-bit decreasing counter are read by 2 pieces.
492 * Incorrect value may be read when both bccrh and bccrl are changing.
493 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
495 if (retry
&& !(bccrh
== bccrhv
&& bccrl
>= bccrlv
)) {
497 PDPRINTK("rereading counter\n");
505 * adjust_pll - Adjust the PLL input clock in Hz.
507 * @pdc_controller: controller specific information
508 * @host: target ATA host
509 * @pll_clock: The input of PLL in HZ
511 static void pdc_adjust_pll(struct ata_host
*host
, long pll_clock
, unsigned int board_idx
)
513 void __iomem
*mmio_base
= host
->iomap
[PDC_MMIO_BAR
];
515 long pll_clock_khz
= pll_clock
/ 1000;
516 long pout_required
= board_idx
? PDC_133_MHZ
:PDC_100_MHZ
;
517 long ratio
= pout_required
/ pll_clock_khz
;
521 if (unlikely(pll_clock_khz
< 5000L || pll_clock_khz
> 70000L)) {
522 printk(KERN_ERR DRV_NAME
": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz
);
527 PDPRINTK("pout_required is %ld\n", pout_required
);
529 /* Show the current clock value of PLL control register
530 * (maybe already configured by the firmware)
532 pll_ctl
= ioread16(mmio_base
+ PDC_PLL_CTL
);
534 PDPRINTK("pll_ctl[%X]\n", pll_ctl
);
538 * Calculate the ratio of F, R and OD
539 * POUT = (F + 2) / (( R + 2) * NO)
541 if (ratio
< 8600L) { /* 8.6x */
542 /* Using NO = 0x01, R = 0x0D */
544 } else if (ratio
< 12900L) { /* 12.9x */
545 /* Using NO = 0x01, R = 0x08 */
547 } else if (ratio
< 16100L) { /* 16.1x */
548 /* Using NO = 0x01, R = 0x06 */
550 } else if (ratio
< 64000L) { /* 64x */
554 printk(KERN_ERR DRV_NAME
": Invalid ratio %ld, give up!\n", ratio
);
558 F
= (ratio
* (R
+2)) / 1000 - 2;
560 if (unlikely(F
< 0 || F
> 127)) {
562 printk(KERN_ERR DRV_NAME
": F[%d] invalid!\n", F
);
566 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F
, R
, ratio
);
568 pll_ctl
= (R
<< 8) | F
;
570 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl
);
572 iowrite16(pll_ctl
, mmio_base
+ PDC_PLL_CTL
);
573 ioread16(mmio_base
+ PDC_PLL_CTL
); /* flush */
575 /* Wait the PLL circuit to be stable */
580 * Show the current clock value of PLL control register
581 * (maybe configured by the firmware)
583 pll_ctl
= ioread16(mmio_base
+ PDC_PLL_CTL
);
585 PDPRINTK("pll_ctl[%X]\n", pll_ctl
);
592 * detect_pll_input_clock - Detect the PLL input clock in Hz.
593 * @host: target ATA host
594 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
595 * Half of the PCI clock.
597 static long pdc_detect_pll_input_clock(struct ata_host
*host
)
599 void __iomem
*mmio_base
= host
->iomap
[PDC_MMIO_BAR
];
601 long start_count
, end_count
;
602 struct timeval start_time
, end_time
;
603 long pll_clock
, usec_elapsed
;
605 /* Start the test mode */
606 scr
= ioread32(mmio_base
+ PDC_SYS_CTL
);
607 PDPRINTK("scr[%X]\n", scr
);
608 iowrite32(scr
| (0x01 << 14), mmio_base
+ PDC_SYS_CTL
);
609 ioread32(mmio_base
+ PDC_SYS_CTL
); /* flush */
611 /* Read current counter value */
612 start_count
= pdc_read_counter(host
);
613 do_gettimeofday(&start_time
);
615 /* Let the counter run for 100 ms. */
618 /* Read the counter values again */
619 end_count
= pdc_read_counter(host
);
620 do_gettimeofday(&end_time
);
622 /* Stop the test mode */
623 scr
= ioread32(mmio_base
+ PDC_SYS_CTL
);
624 PDPRINTK("scr[%X]\n", scr
);
625 iowrite32(scr
& ~(0x01 << 14), mmio_base
+ PDC_SYS_CTL
);
626 ioread32(mmio_base
+ PDC_SYS_CTL
); /* flush */
628 /* calculate the input clock in Hz */
629 usec_elapsed
= (end_time
.tv_sec
- start_time
.tv_sec
) * 1000000 +
630 (end_time
.tv_usec
- start_time
.tv_usec
);
632 pll_clock
= ((start_count
- end_count
) & 0x3fffffff) / 100 *
633 (100000000 / usec_elapsed
);
635 PDPRINTK("start[%ld] end[%ld] \n", start_count
, end_count
);
636 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock
);
642 * pdc_hardware_init - Initialize the hardware.
643 * @host: target ATA host
644 * @board_idx: board identifier
646 static int pdc_hardware_init(struct ata_host
*host
, unsigned int board_idx
)
651 * Detect PLL input clock rate.
652 * On some system, where PCI bus is running at non-standard clock rate.
653 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
654 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
656 pll_clock
= pdc_detect_pll_input_clock(host
);
658 dev_info(host
->dev
, "PLL input clock %ld kHz\n", pll_clock
/1000);
660 /* Adjust PLL control register */
661 pdc_adjust_pll(host
, pll_clock
, board_idx
);
667 * pdc_ata_setup_port - setup the mmio address
668 * @port: ata ioports to setup
669 * @base: base address
671 static void pdc_ata_setup_port(struct ata_ioports
*port
, void __iomem
*base
)
674 port
->data_addr
= base
;
676 port
->error_addr
= base
+ 0x05;
677 port
->nsect_addr
= base
+ 0x0a;
678 port
->lbal_addr
= base
+ 0x0f;
679 port
->lbam_addr
= base
+ 0x10;
680 port
->lbah_addr
= base
+ 0x15;
681 port
->device_addr
= base
+ 0x1a;
683 port
->status_addr
= base
+ 0x1f;
684 port
->altstatus_addr
=
685 port
->ctl_addr
= base
+ 0x81a;
689 * pdc2027x_init_one - PCI probe function
690 * Called when an instance of PCI adapter is inserted.
691 * This function checks whether the hardware is supported,
692 * initialize hardware and register an instance of ata_host to
693 * libata. (implements struct pci_driver.probe() )
695 * @pdev: instance of pci_dev found
696 * @ent: matching entry in the id_tbl[]
698 static int __devinit
pdc2027x_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
700 static const unsigned long cmd_offset
[] = { 0x17c0, 0x15c0 };
701 static const unsigned long bmdma_offset
[] = { 0x1000, 0x1008 };
702 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
703 const struct ata_port_info
*ppi
[] =
704 { &pdc2027x_port_info
[board_idx
], NULL
};
705 struct ata_host
*host
;
706 void __iomem
*mmio_base
;
709 ata_print_version_once(&pdev
->dev
, DRV_VERSION
);
712 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, 2);
716 /* acquire resources and fill host */
717 rc
= pcim_enable_device(pdev
);
721 rc
= pcim_iomap_regions(pdev
, 1 << PDC_MMIO_BAR
, DRV_NAME
);
724 host
->iomap
= pcim_iomap_table(pdev
);
726 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
730 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
734 mmio_base
= host
->iomap
[PDC_MMIO_BAR
];
736 for (i
= 0; i
< 2; i
++) {
737 struct ata_port
*ap
= host
->ports
[i
];
739 pdc_ata_setup_port(&ap
->ioaddr
, mmio_base
+ cmd_offset
[i
]);
740 ap
->ioaddr
.bmdma_addr
= mmio_base
+ bmdma_offset
[i
];
742 ata_port_pbar_desc(ap
, PDC_MMIO_BAR
, -1, "mmio");
743 ata_port_pbar_desc(ap
, PDC_MMIO_BAR
, cmd_offset
[i
], "cmd");
746 //pci_enable_intx(pdev);
748 /* initialize adapter */
749 if (pdc_hardware_init(host
, board_idx
) != 0)
752 pci_set_master(pdev
);
753 return ata_host_activate(host
, pdev
->irq
, ata_bmdma_interrupt
,
754 IRQF_SHARED
, &pdc2027x_sht
);
758 * pdc2027x_init - Called after this module is loaded into the kernel.
760 static int __init
pdc2027x_init(void)
762 return pci_register_driver(&pdc2027x_pci_driver
);
766 * pdc2027x_exit - Called before this module unloaded from the kernel
768 static void __exit
pdc2027x_exit(void)
770 pci_unregister_driver(&pdc2027x_pci_driver
);
773 module_init(pdc2027x_init
);
774 module_exit(pdc2027x_exit
);