2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
30 struct drm_nouveau_channel_alloc
{
31 uint32_t fb_ctxdma_handle
;
32 uint32_t tt_ctxdma_handle
;
35 uint32_t pushbuf_domains
;
38 uint32_t notifier_handle
;
40 /* DRM-enforced subchannel assignments */
48 struct drm_nouveau_channel_free
{
52 struct drm_nouveau_grobj_alloc
{
58 struct drm_nouveau_notifierobj_alloc
{
65 struct drm_nouveau_gpuobj_free
{
70 /* FIXME : maybe unify {GET,SET}PARAMs */
71 #define NOUVEAU_GETPARAM_PCI_VENDOR 3
72 #define NOUVEAU_GETPARAM_PCI_DEVICE 4
73 #define NOUVEAU_GETPARAM_BUS_TYPE 5
74 #define NOUVEAU_GETPARAM_FB_PHYSICAL 6
75 #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
76 #define NOUVEAU_GETPARAM_FB_SIZE 8
77 #define NOUVEAU_GETPARAM_AGP_SIZE 9
78 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
79 #define NOUVEAU_GETPARAM_CHIPSET_ID 11
80 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
81 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13
82 #define NOUVEAU_GETPARAM_PTIMER_TIME 14
83 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
84 struct drm_nouveau_getparam
{
89 struct drm_nouveau_setparam
{
94 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
95 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
96 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
97 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
99 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
100 #define NOUVEAU_GEM_TILE_16BPP 0x00000001
101 #define NOUVEAU_GEM_TILE_32BPP 0x00000002
102 #define NOUVEAU_GEM_TILE_ZETA 0x00000004
103 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
105 struct drm_nouveau_gem_info
{
115 struct drm_nouveau_gem_new
{
116 struct drm_nouveau_gem_info info
;
117 uint32_t channel_hint
;
121 #define NOUVEAU_GEM_MAX_BUFFERS 1024
122 struct drm_nouveau_gem_pushbuf_bo_presumed
{
128 struct drm_nouveau_gem_pushbuf_bo
{
131 uint32_t read_domains
;
132 uint32_t write_domains
;
133 uint32_t valid_domains
;
134 struct drm_nouveau_gem_pushbuf_bo_presumed presumed
;
137 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
138 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
139 #define NOUVEAU_GEM_RELOC_OR (1 << 2)
140 #define NOUVEAU_GEM_MAX_RELOCS 1024
141 struct drm_nouveau_gem_pushbuf_reloc
{
142 uint32_t reloc_bo_index
;
143 uint32_t reloc_bo_offset
;
151 #define NOUVEAU_GEM_MAX_PUSH 512
152 struct drm_nouveau_gem_pushbuf_push
{
159 struct drm_nouveau_gem_pushbuf
{
169 uint64_t vram_available
;
170 uint64_t gart_available
;
173 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
174 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
175 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
176 struct drm_nouveau_gem_cpu_prep
{
181 struct drm_nouveau_gem_cpu_fini
{
185 enum nouveau_bus_type
{
191 struct drm_nouveau_sarea
{
194 #define DRM_NOUVEAU_GETPARAM 0x00
195 #define DRM_NOUVEAU_SETPARAM 0x01
196 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
197 #define DRM_NOUVEAU_CHANNEL_FREE 0x03
198 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04
199 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
200 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06
201 #define DRM_NOUVEAU_GEM_NEW 0x40
202 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
203 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
204 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
205 #define DRM_NOUVEAU_GEM_INFO 0x44
207 #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
208 #define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
209 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
210 #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
211 #define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
212 #define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
213 #define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
214 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
215 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
216 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
217 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
218 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
220 #endif /* __NOUVEAU_DRM_H__ */