2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses
);
21 EXPORT_SYMBOL(pci_root_buses
);
23 LIST_HEAD(pci_devices
);
26 * Some device drivers need know if pci is initiated.
27 * Basically, we think pci is not initiated when there
28 * is no device in list of pci_devices.
30 int no_pci_devices(void)
32 return list_empty(&pci_devices
);
35 EXPORT_SYMBOL(no_pci_devices
);
37 #ifdef HAVE_PCI_LEGACY
39 * pci_create_legacy_files - create legacy I/O port and memory files
40 * @b: bus to create files under
42 * Some platforms allow access to legacy I/O port and ISA memory space on
43 * a per-bus basis. This routine creates the files and ties them into
44 * their associated read, write and mmap files from pci-sysfs.c
46 static void pci_create_legacy_files(struct pci_bus
*b
)
48 b
->legacy_io
= kzalloc(sizeof(struct bin_attribute
) * 2,
51 b
->legacy_io
->attr
.name
= "legacy_io";
52 b
->legacy_io
->size
= 0xffff;
53 b
->legacy_io
->attr
.mode
= S_IRUSR
| S_IWUSR
;
54 b
->legacy_io
->read
= pci_read_legacy_io
;
55 b
->legacy_io
->write
= pci_write_legacy_io
;
56 class_device_create_bin_file(&b
->class_dev
, b
->legacy_io
);
58 /* Allocated above after the legacy_io struct */
59 b
->legacy_mem
= b
->legacy_io
+ 1;
60 b
->legacy_mem
->attr
.name
= "legacy_mem";
61 b
->legacy_mem
->size
= 1024*1024;
62 b
->legacy_mem
->attr
.mode
= S_IRUSR
| S_IWUSR
;
63 b
->legacy_mem
->mmap
= pci_mmap_legacy_mem
;
64 class_device_create_bin_file(&b
->class_dev
, b
->legacy_mem
);
68 void pci_remove_legacy_files(struct pci_bus
*b
)
71 class_device_remove_bin_file(&b
->class_dev
, b
->legacy_io
);
72 class_device_remove_bin_file(&b
->class_dev
, b
->legacy_mem
);
73 kfree(b
->legacy_io
); /* both are allocated here */
76 #else /* !HAVE_PCI_LEGACY */
77 static inline void pci_create_legacy_files(struct pci_bus
*bus
) { return; }
78 void pci_remove_legacy_files(struct pci_bus
*bus
) { return; }
79 #endif /* HAVE_PCI_LEGACY */
82 * PCI Bus Class Devices
84 static ssize_t
pci_bus_show_cpuaffinity(struct class_device
*class_dev
,
90 cpumask
= pcibus_to_cpumask(to_pci_bus(class_dev
));
91 ret
= cpumask_scnprintf(buf
, PAGE_SIZE
, cpumask
);
96 CLASS_DEVICE_ATTR(cpuaffinity
, S_IRUGO
, pci_bus_show_cpuaffinity
, NULL
);
101 static void release_pcibus_dev(struct class_device
*class_dev
)
103 struct pci_bus
*pci_bus
= to_pci_bus(class_dev
);
106 put_device(pci_bus
->bridge
);
110 static struct class pcibus_class
= {
112 .release
= &release_pcibus_dev
,
115 static int __init
pcibus_class_init(void)
117 return class_register(&pcibus_class
);
119 postcore_initcall(pcibus_class_init
);
122 * Translate the low bits of the PCI base
123 * to the resource type
125 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
127 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
128 return IORESOURCE_IO
;
130 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
131 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
133 return IORESOURCE_MEM
;
137 * Find the extent of a PCI decode..
139 static u32
pci_size(u32 base
, u32 maxbase
, u32 mask
)
141 u32 size
= mask
& maxbase
; /* Find the significant bits */
145 /* Get the lowest of them to find the decode size, and
146 from that the extent. */
147 size
= (size
& ~(size
-1)) - 1;
149 /* base == maxbase can be valid only if the BAR has
150 already been programmed with all 1s. */
151 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
157 static u64
pci_size64(u64 base
, u64 maxbase
, u64 mask
)
159 u64 size
= mask
& maxbase
; /* Find the significant bits */
163 /* Get the lowest of them to find the decode size, and
164 from that the extent. */
165 size
= (size
& ~(size
-1)) - 1;
167 /* base == maxbase can be valid only if the BAR has
168 already been programmed with all 1s. */
169 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
175 static inline int is_64bit_memory(u32 mask
)
177 if ((mask
& (PCI_BASE_ADDRESS_SPACE
|PCI_BASE_ADDRESS_MEM_TYPE_MASK
)) ==
178 (PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
))
183 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
185 unsigned int pos
, reg
, next
;
187 struct resource
*res
;
189 for(pos
=0; pos
<howmany
; pos
= next
) {
195 res
= &dev
->resource
[pos
];
196 res
->name
= pci_name(dev
);
197 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
198 pci_read_config_dword(dev
, reg
, &l
);
199 pci_write_config_dword(dev
, reg
, ~0);
200 pci_read_config_dword(dev
, reg
, &sz
);
201 pci_write_config_dword(dev
, reg
, l
);
202 if (!sz
|| sz
== 0xffffffff)
207 if ((l
& PCI_BASE_ADDRESS_SPACE
) ==
208 PCI_BASE_ADDRESS_SPACE_MEMORY
) {
209 sz
= pci_size(l
, sz
, (u32
)PCI_BASE_ADDRESS_MEM_MASK
);
211 * For 64bit prefetchable memory sz could be 0, if the
212 * real size is bigger than 4G, so we need to check
215 if (!is_64bit_memory(l
) && !sz
)
217 res
->start
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
218 res
->flags
|= l
& ~PCI_BASE_ADDRESS_MEM_MASK
;
220 sz
= pci_size(l
, sz
, PCI_BASE_ADDRESS_IO_MASK
& 0xffff);
223 res
->start
= l
& PCI_BASE_ADDRESS_IO_MASK
;
224 res
->flags
|= l
& ~PCI_BASE_ADDRESS_IO_MASK
;
226 res
->end
= res
->start
+ (unsigned long) sz
;
227 res
->flags
|= pci_calc_resource_flags(l
);
228 if (is_64bit_memory(l
)) {
231 pci_read_config_dword(dev
, reg
+4, &lhi
);
232 pci_write_config_dword(dev
, reg
+4, ~0);
233 pci_read_config_dword(dev
, reg
+4, &szhi
);
234 pci_write_config_dword(dev
, reg
+4, lhi
);
235 sz64
= ((u64
)szhi
<< 32) | raw_sz
;
236 l64
= ((u64
)lhi
<< 32) | l
;
237 sz64
= pci_size64(l64
, sz64
, PCI_BASE_ADDRESS_MEM_MASK
);
239 #if BITS_PER_LONG == 64
246 res
->start
= l64
& PCI_BASE_ADDRESS_MEM_MASK
;
247 res
->end
= res
->start
+ sz64
;
249 if (sz64
> 0x100000000ULL
) {
250 printk(KERN_ERR
"PCI: Unable to handle 64-bit "
251 "BAR for device %s\n", pci_name(dev
));
255 /* 64-bit wide address, treat as disabled */
256 pci_write_config_dword(dev
, reg
,
257 l
& ~(u32
)PCI_BASE_ADDRESS_MEM_MASK
);
258 pci_write_config_dword(dev
, reg
+4, 0);
266 dev
->rom_base_reg
= rom
;
267 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
268 res
->name
= pci_name(dev
);
269 pci_read_config_dword(dev
, rom
, &l
);
270 pci_write_config_dword(dev
, rom
, ~PCI_ROM_ADDRESS_ENABLE
);
271 pci_read_config_dword(dev
, rom
, &sz
);
272 pci_write_config_dword(dev
, rom
, l
);
275 if (sz
&& sz
!= 0xffffffff) {
276 sz
= pci_size(l
, sz
, (u32
)PCI_ROM_ADDRESS_MASK
);
278 res
->flags
= (l
& IORESOURCE_ROM_ENABLE
) |
279 IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
280 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
281 res
->start
= l
& PCI_ROM_ADDRESS_MASK
;
282 res
->end
= res
->start
+ (unsigned long) sz
;
288 void pci_read_bridge_bases(struct pci_bus
*child
)
290 struct pci_dev
*dev
= child
->self
;
291 u8 io_base_lo
, io_limit_lo
;
292 u16 mem_base_lo
, mem_limit_lo
;
293 unsigned long base
, limit
;
294 struct resource
*res
;
297 if (!dev
) /* It's a host bus, nothing to read */
300 if (dev
->transparent
) {
301 printk(KERN_INFO
"PCI: Transparent bridge - %s\n", pci_name(dev
));
302 for(i
= 3; i
< PCI_BUS_NUM_RESOURCES
; i
++)
303 child
->resource
[i
] = child
->parent
->resource
[i
- 3];
307 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
309 res
= child
->resource
[0];
310 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
311 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
312 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
313 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
315 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
316 u16 io_base_hi
, io_limit_hi
;
317 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
318 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
319 base
|= (io_base_hi
<< 16);
320 limit
|= (io_limit_hi
<< 16);
324 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
328 res
->end
= limit
+ 0xfff;
331 res
= child
->resource
[1];
332 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
333 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
334 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
335 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
337 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
339 res
->end
= limit
+ 0xfffff;
342 res
= child
->resource
[2];
343 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
344 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
345 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
346 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
348 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
349 u32 mem_base_hi
, mem_limit_hi
;
350 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
351 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
354 * Some bridges set the base > limit by default, and some
355 * (broken) BIOSes do not initialize them. If we find
356 * this, just assume they are not being used.
358 if (mem_base_hi
<= mem_limit_hi
) {
359 #if BITS_PER_LONG == 64
360 base
|= ((long) mem_base_hi
) << 32;
361 limit
|= ((long) mem_limit_hi
) << 32;
363 if (mem_base_hi
|| mem_limit_hi
) {
364 printk(KERN_ERR
"PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev
));
371 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
373 res
->end
= limit
+ 0xfffff;
377 static struct pci_bus
* pci_alloc_bus(void)
381 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
383 INIT_LIST_HEAD(&b
->node
);
384 INIT_LIST_HEAD(&b
->children
);
385 INIT_LIST_HEAD(&b
->devices
);
390 static struct pci_bus
* __devinit
391 pci_alloc_child_bus(struct pci_bus
*parent
, struct pci_dev
*bridge
, int busnr
)
393 struct pci_bus
*child
;
398 * Allocate a new bus, and inherit stuff from the parent..
400 child
= pci_alloc_bus();
404 child
->self
= bridge
;
405 child
->parent
= parent
;
406 child
->ops
= parent
->ops
;
407 child
->sysdata
= parent
->sysdata
;
408 child
->bus_flags
= parent
->bus_flags
;
409 child
->bridge
= get_device(&bridge
->dev
);
411 child
->class_dev
.class = &pcibus_class
;
412 sprintf(child
->class_dev
.class_id
, "%04x:%02x", pci_domain_nr(child
), busnr
);
413 retval
= class_device_register(&child
->class_dev
);
416 retval
= class_device_create_file(&child
->class_dev
,
417 &class_device_attr_cpuaffinity
);
419 goto error_file_create
;
422 * Set up the primary, secondary and subordinate
425 child
->number
= child
->secondary
= busnr
;
426 child
->primary
= parent
->secondary
;
427 child
->subordinate
= 0xff;
429 /* Set up default resource pointers and names.. */
430 for (i
= 0; i
< 4; i
++) {
431 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
432 child
->resource
[i
]->name
= child
->name
;
434 bridge
->subordinate
= child
;
439 class_device_unregister(&child
->class_dev
);
445 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
447 struct pci_bus
*child
;
449 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
451 down_write(&pci_bus_sem
);
452 list_add_tail(&child
->node
, &parent
->children
);
453 up_write(&pci_bus_sem
);
458 static void pci_enable_crs(struct pci_dev
*dev
)
461 int rpcap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
465 pci_read_config_word(dev
, rpcap
+ PCI_CAP_FLAGS
, &cap
);
466 if (((cap
& PCI_EXP_FLAGS_TYPE
) >> 4) != PCI_EXP_TYPE_ROOT_PORT
)
469 pci_read_config_word(dev
, rpcap
+ PCI_EXP_RTCTL
, &rpctl
);
470 rpctl
|= PCI_EXP_RTCTL_CRSSVE
;
471 pci_write_config_word(dev
, rpcap
+ PCI_EXP_RTCTL
, rpctl
);
474 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
476 struct pci_bus
*parent
= child
->parent
;
478 /* Attempts to fix that up are really dangerous unless
479 we're going to re-assign all bus numbers. */
480 if (!pcibios_assign_all_busses())
483 while (parent
->parent
&& parent
->subordinate
< max
) {
484 parent
->subordinate
= max
;
485 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
486 parent
= parent
->parent
;
490 unsigned int pci_scan_child_bus(struct pci_bus
*bus
);
493 * If it's a bridge, configure it and scan the bus behind it.
494 * For CardBus bridges, we don't scan behind as the devices will
495 * be handled by the bridge driver itself.
497 * We need to process bridges in two passes -- first we scan those
498 * already configured by the BIOS and after we are done with all of
499 * them, we proceed to assigning numbers to the remaining buses in
500 * order to avoid overlaps between old and new bus numbers.
502 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
* dev
, int max
, int pass
)
504 struct pci_bus
*child
;
505 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
509 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
511 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
512 pci_name(dev
), buses
& 0xffffff, pass
);
514 /* Disable MasterAbortMode during probing to avoid reporting
515 of bus errors (in some architectures) */
516 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
517 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
518 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
522 if ((buses
& 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus
) {
523 unsigned int cmax
, busnr
;
525 * Bus already configured by firmware, process it in the first
526 * pass and just note the configuration.
530 busnr
= (buses
>> 8) & 0xFF;
533 * If we already got to this bus through a different bridge,
534 * ignore it. This can happen with the i450NX chipset.
536 if (pci_find_bus(pci_domain_nr(bus
), busnr
)) {
537 printk(KERN_INFO
"PCI: Bus %04x:%02x already known\n",
538 pci_domain_nr(bus
), busnr
);
542 child
= pci_add_new_bus(bus
, dev
, busnr
);
545 child
->primary
= buses
& 0xFF;
546 child
->subordinate
= (buses
>> 16) & 0xFF;
547 child
->bridge_ctl
= bctl
;
549 cmax
= pci_scan_child_bus(child
);
552 if (child
->subordinate
> max
)
553 max
= child
->subordinate
;
556 * We need to assign a number to this bus which we always
557 * do in the second pass.
560 if (pcibios_assign_all_busses())
561 /* Temporarily disable forwarding of the
562 configuration cycles on all bridges in
563 this bus segment to avoid possible
564 conflicts in the second pass between two
565 bridges programmed with overlapping
567 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
573 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
575 /* Prevent assigning a bus number that already exists.
576 * This can happen when a bridge is hot-plugged */
577 if (pci_find_bus(pci_domain_nr(bus
), max
+1))
579 child
= pci_add_new_bus(bus
, dev
, ++max
);
580 buses
= (buses
& 0xff000000)
581 | ((unsigned int)(child
->primary
) << 0)
582 | ((unsigned int)(child
->secondary
) << 8)
583 | ((unsigned int)(child
->subordinate
) << 16);
586 * yenta.c forces a secondary latency timer of 176.
587 * Copy that behaviour here.
590 buses
&= ~0xff000000;
591 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
595 * We need to blast all three values with a single write.
597 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
600 child
->bridge_ctl
= bctl
| PCI_BRIDGE_CTL_NO_ISA
;
602 * Adjust subordinate busnr in parent buses.
603 * We do this before scanning for children because
604 * some devices may not be detected if the bios
607 pci_fixup_parent_subordinate_busnr(child
, max
);
608 /* Now we can scan all subordinate buses... */
609 max
= pci_scan_child_bus(child
);
611 * now fix it up again since we have found
612 * the real value of max.
614 pci_fixup_parent_subordinate_busnr(child
, max
);
617 * For CardBus bridges, we leave 4 bus numbers
618 * as cards with a PCI-to-PCI bridge can be
621 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
622 struct pci_bus
*parent
= bus
;
623 if (pci_find_bus(pci_domain_nr(bus
),
626 while (parent
->parent
) {
627 if ((!pcibios_assign_all_busses()) &&
628 (parent
->subordinate
> max
) &&
629 (parent
->subordinate
<= max
+i
)) {
632 parent
= parent
->parent
;
636 * Often, there are two cardbus bridges
637 * -- try to leave one valid bus number
645 pci_fixup_parent_subordinate_busnr(child
, max
);
648 * Set the subordinate bus number to its real value.
650 child
->subordinate
= max
;
651 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
654 sprintf(child
->name
, (is_cardbus
? "PCI CardBus #%02x" : "PCI Bus #%02x"), child
->number
);
656 /* Has only triggered on CardBus, fixup is in yenta_socket */
657 while (bus
->parent
) {
658 if ((child
->subordinate
> bus
->subordinate
) ||
659 (child
->number
> bus
->subordinate
) ||
660 (child
->number
< bus
->number
) ||
661 (child
->subordinate
< bus
->number
)) {
662 pr_debug("PCI: Bus #%02x (-#%02x) is %s"
663 "hidden behind%s bridge #%02x (-#%02x)\n",
664 child
->number
, child
->subordinate
,
665 (bus
->number
> child
->subordinate
&&
666 bus
->subordinate
< child
->number
) ?
667 "wholly " : " partially",
668 bus
->self
->transparent
? " transparent" : " ",
669 bus
->number
, bus
->subordinate
);
675 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
681 * Read interrupt line and base address registers.
682 * The architecture-dependent code can tweak these, of course.
684 static void pci_read_irq(struct pci_dev
*dev
)
688 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
691 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
695 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
698 * pci_setup_device - fill in class and map information of a device
699 * @dev: the device structure to fill
701 * Initialize the device structure with information about the device's
702 * vendor,class,memory and IO-space addresses,IRQ lines etc.
703 * Called at initialisation of the PCI subsystem and by CardBus services.
704 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
707 static int pci_setup_device(struct pci_dev
* dev
)
711 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
712 dev
->bus
->number
, PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
));
714 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
715 dev
->revision
= class & 0xff;
716 class >>= 8; /* upper 3 bytes */
720 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev
),
721 dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
723 /* "Unknown power state" */
724 dev
->current_state
= PCI_UNKNOWN
;
726 /* Early fixups, before probing the BARs */
727 pci_fixup_device(pci_fixup_early
, dev
);
728 class = dev
->class >> 8;
730 switch (dev
->hdr_type
) { /* header type */
731 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
732 if (class == PCI_CLASS_BRIDGE_PCI
)
735 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
736 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
737 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
740 * Do the ugly legacy mode stuff here rather than broken chip
741 * quirk code. Legacy mode ATA controllers have fixed
742 * addresses. These are not always echoed in BAR0-3, and
743 * BAR0-3 in a few cases contain junk!
745 if (class == PCI_CLASS_STORAGE_IDE
) {
747 struct pci_bus_region region
;
749 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
750 if ((progif
& 1) == 0) {
751 struct resource resource
= {
754 .flags
= LEGACY_IO_RESOURCE
,
757 pcibios_resource_to_bus(dev
, ®ion
, &resource
);
758 dev
->resource
[0].start
= region
.start
;
759 dev
->resource
[0].end
= region
.end
;
760 dev
->resource
[0].flags
= resource
.flags
;
761 resource
.start
= 0x3F6;
762 resource
.end
= 0x3F6;
763 resource
.flags
= LEGACY_IO_RESOURCE
;
764 pcibios_resource_to_bus(dev
, ®ion
, &resource
);
765 dev
->resource
[1].start
= region
.start
;
766 dev
->resource
[1].end
= region
.end
;
767 dev
->resource
[1].flags
= resource
.flags
;
769 if ((progif
& 4) == 0) {
770 struct resource resource
= {
773 .flags
= LEGACY_IO_RESOURCE
,
776 pcibios_resource_to_bus(dev
, ®ion
, &resource
);
777 dev
->resource
[2].start
= region
.start
;
778 dev
->resource
[2].end
= region
.end
;
779 dev
->resource
[2].flags
= resource
.flags
;
780 resource
.start
= 0x376;
781 resource
.end
= 0x376;
782 resource
.flags
= LEGACY_IO_RESOURCE
;
783 pcibios_resource_to_bus(dev
, ®ion
, &resource
);
784 dev
->resource
[3].start
= region
.start
;
785 dev
->resource
[3].end
= region
.end
;
786 dev
->resource
[3].flags
= resource
.flags
;
791 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
792 if (class != PCI_CLASS_BRIDGE_PCI
)
794 /* The PCI-to-PCI bridge spec requires that subtractive
795 decoding (i.e. transparent) bridge must have programming
796 interface code of 0x01. */
798 dev
->transparent
= ((dev
->class & 0xff) == 1);
799 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
802 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
803 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
806 pci_read_bases(dev
, 1, 0);
807 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
808 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
811 default: /* unknown header */
812 printk(KERN_ERR
"PCI: device %s has unknown header type %02x, ignoring.\n",
813 pci_name(dev
), dev
->hdr_type
);
817 printk(KERN_ERR
"PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
818 pci_name(dev
), class, dev
->hdr_type
);
819 dev
->class = PCI_CLASS_NOT_DEFINED
;
822 /* We found a fine healthy device, go go go... */
827 * pci_release_dev - free a pci device structure when all users of it are finished.
828 * @dev: device that's been disconnected
830 * Will be called only by the device core when all users of this pci device are
833 static void pci_release_dev(struct device
*dev
)
835 struct pci_dev
*pci_dev
;
837 pci_dev
= to_pci_dev(dev
);
842 * pci_cfg_space_size - get the configuration space size of the PCI device.
845 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
846 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
847 * access it. Maybe we don't have a way to generate extended config space
848 * accesses, or the device is behind a reverse Express bridge. So we try
849 * reading the dword at 0x100 which must either be 0 or a valid extended
852 int pci_cfg_space_size(struct pci_dev
*dev
)
857 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
859 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
863 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
864 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
868 if (pci_read_config_dword(dev
, 256, &status
) != PCIBIOS_SUCCESSFUL
)
870 if (status
== 0xffffffff)
873 return PCI_CFG_SPACE_EXP_SIZE
;
876 return PCI_CFG_SPACE_SIZE
;
879 static void pci_release_bus_bridge_dev(struct device
*dev
)
884 struct pci_dev
*alloc_pci_dev(void)
888 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
892 INIT_LIST_HEAD(&dev
->global_list
);
893 INIT_LIST_HEAD(&dev
->bus_list
);
895 pci_msi_init_pci_dev(dev
);
899 EXPORT_SYMBOL(alloc_pci_dev
);
902 * Read the config data for a PCI device, sanity-check it
903 * and fill in the dev structure...
905 static struct pci_dev
* __devinit
906 pci_scan_device(struct pci_bus
*bus
, int devfn
)
913 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
916 /* some broken boards return 0 or ~0 if a slot is empty: */
917 if (l
== 0xffffffff || l
== 0x00000000 ||
918 l
== 0x0000ffff || l
== 0xffff0000)
921 /* Configuration request Retry Status */
922 while (l
== 0xffff0001) {
925 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
927 /* Card hasn't responded in 60 seconds? Must be stuck. */
928 if (delay
> 60 * 1000) {
929 printk(KERN_WARNING
"Device %04x:%02x:%02x.%d not "
930 "responding\n", pci_domain_nr(bus
),
931 bus
->number
, PCI_SLOT(devfn
),
937 if (pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
))
940 dev
= alloc_pci_dev();
945 dev
->sysdata
= bus
->sysdata
;
946 dev
->dev
.parent
= bus
->bridge
;
947 dev
->dev
.bus
= &pci_bus_type
;
949 dev
->hdr_type
= hdr_type
& 0x7f;
950 dev
->multifunction
= !!(hdr_type
& 0x80);
951 dev
->vendor
= l
& 0xffff;
952 dev
->device
= (l
>> 16) & 0xffff;
953 dev
->cfg_size
= pci_cfg_space_size(dev
);
954 dev
->error_state
= pci_channel_io_normal
;
956 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
957 set this higher, assuming the system even supports it. */
958 dev
->dma_mask
= 0xffffffff;
959 if (pci_setup_device(dev
) < 0) {
967 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
969 device_initialize(&dev
->dev
);
970 dev
->dev
.release
= pci_release_dev
;
973 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
974 dev
->dev
.dma_mask
= &dev
->dma_mask
;
975 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
977 /* Fix up broken headers */
978 pci_fixup_device(pci_fixup_header
, dev
);
981 * Add the device to our list of discovered devices
982 * and the bus list for fixup functions, etc.
984 INIT_LIST_HEAD(&dev
->global_list
);
985 down_write(&pci_bus_sem
);
986 list_add_tail(&dev
->bus_list
, &bus
->devices
);
987 up_write(&pci_bus_sem
);
990 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
994 dev
= pci_scan_device(bus
, devfn
);
998 pci_device_add(dev
, bus
);
1004 * pci_scan_slot - scan a PCI slot on a bus for devices.
1005 * @bus: PCI bus to scan
1006 * @devfn: slot number to scan (must have zero function.)
1008 * Scan a PCI slot on the specified PCI bus for devices, adding
1009 * discovered devices to the @bus->devices list. New devices
1010 * will have an empty dev->global_list head.
1012 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1017 scan_all_fns
= pcibios_scan_all_fns(bus
, devfn
);
1019 for (func
= 0; func
< 8; func
++, devfn
++) {
1020 struct pci_dev
*dev
;
1022 dev
= pci_scan_single_device(bus
, devfn
);
1027 * If this is a single function device,
1028 * don't scan past the first function.
1030 if (!dev
->multifunction
) {
1032 dev
->multifunction
= 1;
1038 if (func
== 0 && !scan_all_fns
)
1045 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
1047 unsigned int devfn
, pass
, max
= bus
->secondary
;
1048 struct pci_dev
*dev
;
1050 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus
), bus
->number
);
1052 /* Go find them, Rover! */
1053 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1054 pci_scan_slot(bus
, devfn
);
1057 * After performing arch-dependent fixup of the bus, look behind
1058 * all PCI-to-PCI bridges on this bus.
1060 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus
), bus
->number
);
1061 pcibios_fixup_bus(bus
);
1062 for (pass
=0; pass
< 2; pass
++)
1063 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1064 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1065 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1066 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1070 * We've scanned the bus and so we know all about what's on
1071 * the other side of any bridges that may be on this bus plus
1074 * Return how far we've got finding sub-buses.
1076 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1077 pci_domain_nr(bus
), bus
->number
, max
);
1081 unsigned int __devinit
pci_do_scan_bus(struct pci_bus
*bus
)
1085 max
= pci_scan_child_bus(bus
);
1088 * Make the discovered devices available.
1090 pci_bus_add_devices(bus
);
1095 struct pci_bus
* pci_create_bus(struct device
*parent
,
1096 int bus
, struct pci_ops
*ops
, void *sysdata
)
1102 b
= pci_alloc_bus();
1106 dev
= kmalloc(sizeof(*dev
), GFP_KERNEL
);
1112 b
->sysdata
= sysdata
;
1115 if (pci_find_bus(pci_domain_nr(b
), bus
)) {
1116 /* If we already got to this bus through a different bridge, ignore it */
1117 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b
), bus
);
1121 down_write(&pci_bus_sem
);
1122 list_add_tail(&b
->node
, &pci_root_buses
);
1123 up_write(&pci_bus_sem
);
1125 memset(dev
, 0, sizeof(*dev
));
1126 dev
->parent
= parent
;
1127 dev
->release
= pci_release_bus_bridge_dev
;
1128 sprintf(dev
->bus_id
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1129 error
= device_register(dev
);
1132 b
->bridge
= get_device(dev
);
1134 b
->class_dev
.class = &pcibus_class
;
1135 sprintf(b
->class_dev
.class_id
, "%04x:%02x", pci_domain_nr(b
), bus
);
1136 error
= class_device_register(&b
->class_dev
);
1138 goto class_dev_reg_err
;
1139 error
= class_device_create_file(&b
->class_dev
, &class_device_attr_cpuaffinity
);
1141 goto class_dev_create_file_err
;
1143 /* Create legacy_io and legacy_mem files for this bus */
1144 pci_create_legacy_files(b
);
1146 error
= sysfs_create_link(&b
->class_dev
.kobj
, &b
->bridge
->kobj
, "bridge");
1148 goto sys_create_link_err
;
1150 b
->number
= b
->secondary
= bus
;
1151 b
->resource
[0] = &ioport_resource
;
1152 b
->resource
[1] = &iomem_resource
;
1156 sys_create_link_err
:
1157 class_device_remove_file(&b
->class_dev
, &class_device_attr_cpuaffinity
);
1158 class_dev_create_file_err
:
1159 class_device_unregister(&b
->class_dev
);
1161 device_unregister(dev
);
1163 down_write(&pci_bus_sem
);
1165 up_write(&pci_bus_sem
);
1171 EXPORT_SYMBOL_GPL(pci_create_bus
);
1173 struct pci_bus
*pci_scan_bus_parented(struct device
*parent
,
1174 int bus
, struct pci_ops
*ops
, void *sysdata
)
1178 b
= pci_create_bus(parent
, bus
, ops
, sysdata
);
1180 b
->subordinate
= pci_scan_child_bus(b
);
1183 EXPORT_SYMBOL(pci_scan_bus_parented
);
1185 #ifdef CONFIG_HOTPLUG
1186 EXPORT_SYMBOL(pci_add_new_bus
);
1187 EXPORT_SYMBOL(pci_do_scan_bus
);
1188 EXPORT_SYMBOL(pci_scan_slot
);
1189 EXPORT_SYMBOL(pci_scan_bridge
);
1190 EXPORT_SYMBOL(pci_scan_single_device
);
1191 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1194 static int __init
pci_sort_bf_cmp(const struct pci_dev
*a
, const struct pci_dev
*b
)
1196 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
1197 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
1199 if (a
->bus
->number
< b
->bus
->number
) return -1;
1200 else if (a
->bus
->number
> b
->bus
->number
) return 1;
1202 if (a
->devfn
< b
->devfn
) return -1;
1203 else if (a
->devfn
> b
->devfn
) return 1;
1209 * Yes, this forcably breaks the klist abstraction temporarily. It
1210 * just wants to sort the klist, not change reference counts and
1211 * take/drop locks rapidly in the process. It does all this while
1212 * holding the lock for the list, so objects can't otherwise be
1213 * added/removed while we're swizzling.
1215 static void __init
pci_insertion_sort_klist(struct pci_dev
*a
, struct list_head
*list
)
1217 struct list_head
*pos
;
1218 struct klist_node
*n
;
1222 list_for_each(pos
, list
) {
1223 n
= container_of(pos
, struct klist_node
, n_node
);
1224 dev
= container_of(n
, struct device
, knode_bus
);
1225 b
= to_pci_dev(dev
);
1226 if (pci_sort_bf_cmp(a
, b
) <= 0) {
1227 list_move_tail(&a
->dev
.knode_bus
.n_node
, &b
->dev
.knode_bus
.n_node
);
1231 list_move_tail(&a
->dev
.knode_bus
.n_node
, list
);
1234 static void __init
pci_sort_breadthfirst_klist(void)
1236 LIST_HEAD(sorted_devices
);
1237 struct list_head
*pos
, *tmp
;
1238 struct klist_node
*n
;
1240 struct pci_dev
*pdev
;
1242 spin_lock(&pci_bus_type
.klist_devices
.k_lock
);
1243 list_for_each_safe(pos
, tmp
, &pci_bus_type
.klist_devices
.k_list
) {
1244 n
= container_of(pos
, struct klist_node
, n_node
);
1245 dev
= container_of(n
, struct device
, knode_bus
);
1246 pdev
= to_pci_dev(dev
);
1247 pci_insertion_sort_klist(pdev
, &sorted_devices
);
1249 list_splice(&sorted_devices
, &pci_bus_type
.klist_devices
.k_list
);
1250 spin_unlock(&pci_bus_type
.klist_devices
.k_lock
);
1253 static void __init
pci_insertion_sort_devices(struct pci_dev
*a
, struct list_head
*list
)
1257 list_for_each_entry(b
, list
, global_list
) {
1258 if (pci_sort_bf_cmp(a
, b
) <= 0) {
1259 list_move_tail(&a
->global_list
, &b
->global_list
);
1263 list_move_tail(&a
->global_list
, list
);
1266 static void __init
pci_sort_breadthfirst_devices(void)
1268 LIST_HEAD(sorted_devices
);
1269 struct pci_dev
*dev
, *tmp
;
1271 down_write(&pci_bus_sem
);
1272 list_for_each_entry_safe(dev
, tmp
, &pci_devices
, global_list
) {
1273 pci_insertion_sort_devices(dev
, &sorted_devices
);
1275 list_splice(&sorted_devices
, &pci_devices
);
1276 up_write(&pci_bus_sem
);
1279 void __init
pci_sort_breadthfirst(void)
1281 pci_sort_breadthfirst_devices();
1282 pci_sort_breadthfirst_klist();