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[PATCH] ep93xx build fix
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / gdth.c
blobd5740bbdef3e8e98a032ff951b1985ade6c46be6
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-04 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-04 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.2.x, 2.4.x, 2.6.x supported *
31 * *
32 * $Log: gdth.c,v $
33 * Revision 1.73 2004/03/31 13:33:03 achim
34 * Special command 0xfd implemented to detect 64-bit DMA support
35 *
36 * Revision 1.72 2004/03/17 08:56:04 achim
37 * 64-bit DMA only enabled if FW >= x.43
38 *
39 * Revision 1.71 2004/03/05 15:51:29 achim
40 * Screen service: separate message buffer, bugfixes
41 *
42 * Revision 1.70 2004/02/27 12:19:07 achim
43 * Bugfix: Reset bit in config (0xfe) call removed
44 *
45 * Revision 1.69 2004/02/20 09:50:24 achim
46 * Compatibility changes for kernels < 2.4.20
47 * Bugfix screen service command size
48 * pci_set_dma_mask() error handling added
49 *
50 * Revision 1.68 2004/02/19 15:46:54 achim
51 * 64-bit DMA bugfixes
52 * Drive size bugfix for drives > 1TB
53 *
54 * Revision 1.67 2004/01/14 13:11:57 achim
55 * Tool access over /proc no longer supported
56 * Bugfixes IOCTLs
57 *
58 * Revision 1.66 2003/12/19 15:04:06 achim
59 * Bugfixes support for drives > 2TB
60 *
61 * Revision 1.65 2003/12/15 11:21:56 achim
62 * 64-bit DMA support added
63 * Support for drives > 2 TB implemented
64 * Kernels 2.2.x, 2.4.x, 2.6.x supported
65 *
66 * Revision 1.64 2003/09/17 08:30:26 achim
67 * EISA/ISA controller scan disabled
68 * Command line switch probe_eisa_isa added
69 *
70 * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
71 * Minor cleanups in gdth_ioctl.
72 *
73 * Revision 1.62 2003/02/27 15:01:59 achim
74 * Dynamic DMA mapping implemented
75 * New (character device) IOCTL interface added
76 * Other controller related changes made
77 *
78 * Revision 1.61 2002/11/08 13:09:52 boji
79 * Added support for XSCALE based RAID Controllers
80 * Fixed SCREENSERVICE initialization in SMP cases
81 * Added checks for gdth_polling before GDTH_HA_LOCK
82 *
83 * Revision 1.60 2002/02/05 09:35:22 achim
84 * MODULE_LICENSE only if kernel >= 2.4.11
85 *
86 * Revision 1.59 2002/01/30 09:46:33 achim
87 * Small changes
88 *
89 * Revision 1.58 2002/01/29 15:30:02 achim
90 * Set default value of shared_access to Y
91 * New status S_CACHE_RESERV for clustering added
92 *
93 * Revision 1.57 2001/08/21 11:16:35 achim
94 * Bugfix free_irq()
95 *
96 * Revision 1.56 2001/08/09 11:19:39 achim
97 * struct scsi_host_template changes
98 *
99 * Revision 1.55 2001/08/09 10:11:28 achim
100 * Command HOST_UNFREEZE_IO before cache service init.
101 *
102 * Revision 1.54 2001/07/20 13:48:12 achim
103 * Expand: gdth_analyse_hdrive() removed
104 *
105 * Revision 1.53 2001/07/17 09:52:49 achim
106 * Small OEM related change
107 *
108 * Revision 1.52 2001/06/19 15:06:20 achim
109 * New host command GDT_UNFREEZE_IO added
110 *
111 * Revision 1.51 2001/05/22 06:42:37 achim
112 * PCI: Subdevice ID added
113 *
114 * Revision 1.50 2001/05/17 13:42:16 achim
115 * Support for Intel Storage RAID Controllers added
116 *
117 * Revision 1.50 2001/05/17 12:12:34 achim
118 * Support for Intel Storage RAID Controllers added
119 *
120 * Revision 1.49 2001/03/15 15:07:17 achim
121 * New __setup interface for boot command line options added
122 *
123 * Revision 1.48 2001/02/06 12:36:28 achim
124 * Bugfix Cluster protocol
125 *
126 * Revision 1.47 2001/01/10 14:42:06 achim
127 * New switch shared_access added
128 *
129 * Revision 1.46 2001/01/09 08:11:35 achim
130 * gdth_command() removed
131 * meaning of Scsi_Pointer members changed
132 *
133 * Revision 1.45 2000/11/16 12:02:24 achim
134 * Changes for kernel 2.4
135 *
136 * Revision 1.44 2000/10/11 08:44:10 achim
137 * Clustering changes: New flag media_changed added
138 *
139 * Revision 1.43 2000/09/20 12:59:01 achim
140 * DPMEM remap functions for all PCI controller types implemented
141 * Small changes for ia64 platform
142 *
143 * Revision 1.42 2000/07/20 09:04:50 achim
144 * Small changes for kernel 2.4
145 *
146 * Revision 1.41 2000/07/04 14:11:11 achim
147 * gdth_analyse_hdrive() added to rescan drives after online expansion
148 *
149 * Revision 1.40 2000/06/27 11:24:16 achim
150 * Changes Clustering, Screenservice
151 *
152 * Revision 1.39 2000/06/15 13:09:04 achim
153 * Changes for gdth_do_cmd()
154 *
155 * Revision 1.38 2000/06/15 12:08:43 achim
156 * Bugfix gdth_sync_event(), service SCREENSERVICE
157 * Data direction for command 0xc2 changed to DOU
158 *
159 * Revision 1.37 2000/05/25 13:50:10 achim
160 * New driver parameter virt_ctr added
161 *
162 * Revision 1.36 2000/05/04 08:50:46 achim
163 * Event buffer now in gdth_ha_str
164 *
165 * Revision 1.35 2000/03/03 10:44:08 achim
166 * New event_string only valid for the RP controller family
167 *
168 * Revision 1.34 2000/03/02 14:55:29 achim
169 * New mechanism for async. event handling implemented
170 *
171 * Revision 1.33 2000/02/21 15:37:37 achim
172 * Bugfix Alpha platform + DPMEM above 4GB
173 *
174 * Revision 1.32 2000/02/14 16:17:37 achim
175 * Bugfix sense_buffer[] + raw devices
176 *
177 * Revision 1.31 2000/02/10 10:29:00 achim
178 * Delete sense_buffer[0], if command OK
179 *
180 * Revision 1.30 1999/11/02 13:42:39 achim
181 * ARRAY_DRV_LIST2 implemented
182 * Now 255 log. and 100 host drives supported
183 *
184 * Revision 1.29 1999/10/05 13:28:47 achim
185 * GDT_CLUST_RESET added
186 *
187 * Revision 1.28 1999/08/12 13:44:54 achim
188 * MOUNTALL removed
189 * Cluster drives -> removeable drives
190 *
191 * Revision 1.27 1999/06/22 07:22:38 achim
192 * Small changes
193 *
194 * Revision 1.26 1999/06/10 16:09:12 achim
195 * Cluster Host Drive support: Bugfixes
196 *
197 * Revision 1.25 1999/06/01 16:03:56 achim
198 * gdth_init_pci(): Manipulate config. space to start RP controller
199 *
200 * Revision 1.24 1999/05/26 11:53:06 achim
201 * Cluster Host Drive support added
202 *
203 * Revision 1.23 1999/03/26 09:12:31 achim
204 * Default value for hdr_channel set to 0
205 *
206 * Revision 1.22 1999/03/22 16:27:16 achim
207 * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
208 *
209 * Revision 1.21 1999/03/16 13:40:34 achim
210 * Problems with reserved drives solved
211 * gdth_eh_bus_reset() implemented
212 *
213 * Revision 1.20 1999/03/10 09:08:13 achim
214 * Bugfix: Corrections in gdth_direction_tab[] made
215 * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
216 *
217 * Revision 1.19 1999/03/05 14:38:16 achim
218 * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
219 * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
220 * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
221 * with BIOS disabled and memory test set to Intensive
222 * Enhanced /proc support
223 *
224 * Revision 1.18 1999/02/24 09:54:33 achim
225 * Command line parameter hdr_channel implemented
226 * Bugfix for EISA controllers + Linux 2.2.x
227 *
228 * Revision 1.17 1998/12/17 15:58:11 achim
229 * Command line parameters implemented
230 * Changes for Alpha platforms
231 * PCI controller scan changed
232 * SMP support improved (spin_lock_irqsave(),...)
233 * New async. events, new scan/reserve commands included
234 *
235 * Revision 1.16 1998/09/28 16:08:46 achim
236 * GDT_PCIMPR: DPMEM remapping, if required
237 * mdelay() added
238 *
239 * Revision 1.15 1998/06/03 14:54:06 achim
240 * gdth_delay(), gdth_flush() implemented
241 * Bugfix: gdth_release() changed
242 *
243 * Revision 1.14 1998/05/22 10:01:17 achim
244 * mj: pcibios_strerror() removed
245 * Improved SMP support (if version >= 2.1.95)
246 * gdth_halt(): halt_called flag added (if version < 2.1)
247 *
248 * Revision 1.13 1998/04/16 09:14:57 achim
249 * Reserve drives (for raw service) implemented
250 * New error handling code enabled
251 * Get controller name from board_info() IOCTL
252 * Final round of PCI device driver patches by Martin Mares
253 *
254 * Revision 1.12 1998/03/03 09:32:37 achim
255 * Fibre channel controller support added
256 *
257 * Revision 1.11 1998/01/27 16:19:14 achim
258 * SA_SHIRQ added
259 * add_timer()/del_timer() instead of GDTH_TIMER
260 * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
261 * New error handling included
262 *
263 * Revision 1.10 1997/10/31 12:29:57 achim
264 * Read heads/sectors from host drive
265 *
266 * Revision 1.9 1997/09/04 10:07:25 achim
267 * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
268 * register_reboot_notifier() to get a notify on shutown used
269 *
270 * Revision 1.8 1997/04/02 12:14:30 achim
271 * Version 1.00 (see gdth.h), tested with kernel 2.0.29
272 *
273 * Revision 1.7 1997/03/12 13:33:37 achim
274 * gdth_reset() changed, new async. events
275 *
276 * Revision 1.6 1997/03/04 14:01:11 achim
277 * Shutdown routine gdth_halt() implemented
278 *
279 * Revision 1.5 1997/02/21 09:08:36 achim
280 * New controller included (RP, RP1, RP2 series)
281 * IOCTL interface implemented
282 *
283 * Revision 1.4 1996/07/05 12:48:55 achim
284 * Function gdth_bios_param() implemented
285 * New constant GDTH_MAXC_P_L inserted
286 * GDT_WRITE_THR, GDT_EXT_INFO implemented
287 * Function gdth_reset() changed
288 *
289 * Revision 1.3 1996/05/10 09:04:41 achim
290 * Small changes for Linux 1.2.13
291 *
292 * Revision 1.2 1996/05/09 12:45:27 achim
293 * Loadable module support implemented
294 * /proc support corrections made
295 *
296 * Revision 1.1 1996/04/11 07:35:57 achim
297 * Initial revision
298 *
299 ************************************************************************/
300
301 /* All GDT Disk Array Controllers are fully supported by this driver.
302 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
303 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
304 * list of all controller types.
305 *
306 * If you have one or more GDT3000/3020 EISA controllers with
307 * controller BIOS disabled, you have to set the IRQ values with the
308 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
309 * the IRQ values for the EISA controllers.
310 *
311 * After the optional list of IRQ values, other possible
312 * command line options are:
313 * disable:Y disable driver
314 * disable:N enable driver
315 * reserve_mode:0 reserve no drives for the raw service
316 * reserve_mode:1 reserve all not init., removable drives
317 * reserve_mode:2 reserve all not init. drives
318 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
319 * h- controller no., b- channel no.,
320 * t- target ID, l- LUN
321 * reverse_scan:Y reverse scan order for PCI controllers
322 * reverse_scan:N scan PCI controllers like BIOS
323 * max_ids:x x - target ID count per channel (1..MAXID)
324 * rescan:Y rescan all channels/IDs
325 * rescan:N use all devices found until now
326 * virt_ctr:Y map every channel to a virtual controller
327 * virt_ctr:N use multi channel support
328 * hdr_channel:x x - number of virtual bus for host drives
329 * shared_access:Y disable driver reserve/release protocol to
330 * access a shared resource from several nodes,
331 * appropriate controller firmware required
332 * shared_access:N enable driver reserve/release protocol
333 * probe_eisa_isa:Y scan for EISA/ISA controllers
334 * probe_eisa_isa:N do not scan for EISA/ISA controllers
335 * force_dma32:Y use only 32 bit DMA mode
336 * force_dma32:N use 64 bit DMA mode, if supported
337 *
338 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
339 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
340 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
341 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
342 *
343 * When loading the gdth driver as a module, the same options are available.
344 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
345 * options changes slightly. You must replace all ',' between options
346 * with ' ' and all ':' with '=' and you must use
347 * '1' in place of 'Y' and '0' in place of 'N'.
348 *
349 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
350 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
351 * probe_eisa_isa=0 force_dma32=0"
352 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
353 */
354
355 /* The meaning of the Scsi_Pointer members in this driver is as follows:
356 * ptr: Chaining
357 * this_residual: Command priority
358 * buffer: phys. DMA sense buffer
359 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
360 * buffers_residual: Timeout value
361 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
362 * Message: Additional info (gdth_do_cmd()), DMA direction
363 * have_data_in: Flag for gdth_wait_completion()
364 * sent_command: Opcode special command
365 * phase: Service/parameter/return code special command
366 */
367
368
369 /* interrupt coalescing */
370 /* #define INT_COAL */
371
372 /* statistics */
373 #define GDTH_STATISTICS
374
375 #include <linux/module.h>
376
377 #include <linux/version.h>
378 #include <linux/kernel.h>
379 #include <linux/types.h>
380 #include <linux/pci.h>
381 #include <linux/string.h>
382 #include <linux/ctype.h>
383 #include <linux/ioport.h>
384 #include <linux/delay.h>
385 #include <linux/sched.h>
386 #include <linux/interrupt.h>
387 #include <linux/in.h>
388 #include <linux/proc_fs.h>
389 #include <linux/time.h>
390 #include <linux/timer.h>
391 #include <linux/dma-mapping.h>
392 #ifdef GDTH_RTC
393 #include <linux/mc146818rtc.h>
394 #endif
395 #include <linux/reboot.h>
396
397 #include <asm/dma.h>
398 #include <asm/system.h>
399 #include <asm/io.h>
400 #include <asm/uaccess.h>
401 #include <linux/spinlock.h>
402 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
403 #include <linux/blkdev.h>
404 #else
405 #include <linux/blk.h>
406 #include "sd.h"
407 #endif
408
409 #include "scsi.h"
410 #include <scsi/scsi_host.h>
411 #include "gdth.h"
412 #include "gdth_kcompat.h"
413
414 static void gdth_delay(int milliseconds);
415 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
416 static irqreturn_t gdth_interrupt(int irq, void *dev_id, struct pt_regs *regs);
417 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
418 static int gdth_async_event(int hanum);
419 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
420
421 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
422 static void gdth_next(int hanum);
423 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
424 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
425 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
426 ushort idx, gdth_evt_data *evt);
427 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
428 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
429 gdth_evt_str *estr);
430 static void gdth_clear_events(void);
431
432 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
433 char *buffer,ushort count);
434 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
435 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
436
437 static int gdth_search_eisa(ushort eisa_adr);
438 static int gdth_search_isa(ulong32 bios_adr);
439 static int gdth_search_pci(gdth_pci_str *pcistr);
440 static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
441 ushort vendor, ushort dev);
442 static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
443 static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
444 static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
445 static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
446
447 static void gdth_enable_int(int hanum);
448 static int gdth_get_status(unchar *pIStatus,int irq);
449 static int gdth_test_busy(int hanum);
450 static int gdth_get_cmd_index(int hanum);
451 static void gdth_release_event(int hanum);
452 static int gdth_wait(int hanum,int index,ulong32 time);
453 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
454 ulong64 p2,ulong64 p3);
455 static int gdth_search_drives(int hanum);
456 static int gdth_analyse_hdrive(int hanum, ushort hdrive);
457
458 static const char *gdth_ctr_name(int hanum);
459
460 static int gdth_open(struct inode *inode, struct file *filep);
461 static int gdth_close(struct inode *inode, struct file *filep);
462 static int gdth_ioctl(struct inode *inode, struct file *filep,
463 unsigned int cmd, unsigned long arg);
464
465 static void gdth_flush(int hanum);
466 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
467
468 #ifdef DEBUG_GDTH
469 static unchar DebugState = DEBUG_GDTH;
470
471 #ifdef __SERIAL__
472 #define MAX_SERBUF 160
473 static void ser_init(void);
474 static void ser_puts(char *str);
475 static void ser_putc(char c);
476 static int ser_printk(const char *fmt, ...);
477 static char strbuf[MAX_SERBUF+1];
478 #ifdef __COM2__
479 #define COM_BASE 0x2f8
480 #else
481 #define COM_BASE 0x3f8
482 #endif
483 static void ser_init()
484 {
485 unsigned port=COM_BASE;
486
487 outb(0x80,port+3);
488 outb(0,port+1);
489 /* 19200 Baud, if 9600: outb(12,port) */
490 outb(6, port);
491 outb(3,port+3);
492 outb(0,port+1);
493 /*
494 ser_putc('I');
495 ser_putc(' ');
496 */
497 }
498
499 static void ser_puts(char *str)
500 {
501 char *ptr;
502
503 ser_init();
504 for (ptr=str;*ptr;++ptr)
505 ser_putc(*ptr);
506 }
507
508 static void ser_putc(char c)
509 {
510 unsigned port=COM_BASE;
511
512 while ((inb(port+5) & 0x20)==0);
513 outb(c,port);
514 if (c==0x0a)
515 {
516 while ((inb(port+5) & 0x20)==0);
517 outb(0x0d,port);
518 }
519 }
520
521 static int ser_printk(const char *fmt, ...)
522 {
523 va_list args;
524 int i;
525
526 va_start(args,fmt);
527 i = vsprintf(strbuf,fmt,args);
528 ser_puts(strbuf);
529 va_end(args);
530 return i;
531 }
532
533 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
534 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
535 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
536
537 #else /* !__SERIAL__ */
538 #define TRACE(a) {if (DebugState==1) {printk a;}}
539 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
540 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
541 #endif
542
543 #else /* !DEBUG */
544 #define TRACE(a)
545 #define TRACE2(a)
546 #define TRACE3(a)
547 #endif
548
549 #ifdef GDTH_STATISTICS
550 static ulong32 max_rq=0, max_index=0, max_sg=0;
551 #ifdef INT_COAL
552 static ulong32 max_int_coal=0;
553 #endif
554 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
555 static struct timer_list gdth_timer;
556 #endif
557
558 #define PTR2USHORT(a) (ushort)(ulong)(a)
559 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
560 #define INDEX_OK(i,t) ((i)<sizeof(t)/sizeof((t)[0]))
561
562 #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
563 #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
564 #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
565
566 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
567
568 #define gdth_readb(addr) readb(addr)
569 #define gdth_readw(addr) readw(addr)
570 #define gdth_readl(addr) readl(addr)
571 #define gdth_writeb(b,addr) writeb((b),(addr))
572 #define gdth_writew(b,addr) writew((b),(addr))
573 #define gdth_writel(b,addr) writel((b),(addr))
574
575 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
576 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
577 static unchar gdth_polling; /* polling if TRUE */
578 static unchar gdth_from_wait = FALSE; /* gdth_wait() */
579 static int wait_index,wait_hanum; /* gdth_wait() */
580 static int gdth_ctr_count = 0; /* controller count */
581 static int gdth_ctr_vcount = 0; /* virt. ctr. count */
582 static int gdth_ctr_released = 0; /* gdth_release() */
583 static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
584 static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
585 static unchar gdth_write_through = FALSE; /* write through */
586 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
587 static int elastidx;
588 static int eoldidx;
589 static int major;
590
591 #define DIN 1 /* IN data direction */
592 #define DOU 2 /* OUT data direction */
593 #define DNO DIN /* no data transfer */
594 #define DUN DIN /* unknown data direction */
595 static unchar gdth_direction_tab[0x100] = {
596 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
597 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
598 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
599 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
600 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
601 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
602 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
603 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
604 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
605 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
606 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
607 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
608 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
609 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
610 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
611 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
612 };
613
614 /* LILO and modprobe/insmod parameters */
615 /* IRQ list for GDT3000/3020 EISA controllers */
616 static int irq[MAXHA] __initdata =
617 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
618 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
619 /* disable driver flag */
620 static int disable __initdata = 0;
621 /* reserve flag */
622 static int reserve_mode = 1;
623 /* reserve list */
624 static int reserve_list[MAX_RES_ARGS] =
625 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
626 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
627 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
628 /* scan order for PCI controllers */
629 static int reverse_scan = 0;
630 /* virtual channel for the host drives */
631 static int hdr_channel = 0;
632 /* max. IDs per channel */
633 static int max_ids = MAXID;
634 /* rescan all IDs */
635 static int rescan = 0;
636 /* map channels to virtual controllers */
637 static int virt_ctr = 0;
638 /* shared access */
639 static int shared_access = 1;
640 /* enable support for EISA and ISA controllers */
641 static int probe_eisa_isa = 0;
642 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
643 static int force_dma32 = 0;
644
645 /* parameters for modprobe/insmod */
646 module_param_array(irq, int, NULL, 0);
647 module_param(disable, int, 0);
648 module_param(reserve_mode, int, 0);
649 module_param_array(reserve_list, int, NULL, 0);
650 module_param(reverse_scan, int, 0);
651 module_param(hdr_channel, int, 0);
652 module_param(max_ids, int, 0);
653 module_param(rescan, int, 0);
654 module_param(virt_ctr, int, 0);
655 module_param(shared_access, int, 0);
656 module_param(probe_eisa_isa, int, 0);
657 module_param(force_dma32, int, 0);
658 MODULE_AUTHOR("Achim Leubner");
659 MODULE_LICENSE("GPL");
660
661 /* ioctl interface */
662 static struct file_operations gdth_fops = {
663 .ioctl = gdth_ioctl,
664 .open = gdth_open,
665 .release = gdth_close,
666 };
667
668 #include "gdth_proc.h"
669 #include "gdth_proc.c"
670
671 /* notifier block to get a notify on system shutdown/halt/reboot */
672 static struct notifier_block gdth_notifier = {
673 gdth_halt, NULL, 0
674 };
675 static int notifier_disabled = 0;
676
677 static void gdth_delay(int milliseconds)
678 {
679 if (milliseconds == 0) {
680 udelay(1);
681 } else {
682 mdelay(milliseconds);
683 }
684 }
685
686 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
687 {
688 *cyls = size /HEADS/SECS;
689 if (*cyls <= MAXCYLS) {
690 *heads = HEADS;
691 *secs = SECS;
692 } else { /* too high for 64*32 */
693 *cyls = size /MEDHEADS/MEDSECS;
694 if (*cyls <= MAXCYLS) {
695 *heads = MEDHEADS;
696 *secs = MEDSECS;
697 } else { /* too high for 127*63 */
698 *cyls = size /BIGHEADS/BIGSECS;
699 *heads = BIGHEADS;
700 *secs = BIGSECS;
701 }
702 }
703 }
704
705 /* controller search and initialization functions */
706
707 static int __init gdth_search_eisa(ushort eisa_adr)
708 {
709 ulong32 id;
710
711 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
712 id = inl(eisa_adr+ID0REG);
713 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
714 if ((inb(eisa_adr+EISAREG) & 8) == 0)
715 return 0; /* not EISA configured */
716 return 1;
717 }
718 if (id == GDT3_ID) /* GDT3000 */
719 return 1;
720
721 return 0;
722 }
723
724
725 static int __init gdth_search_isa(ulong32 bios_adr)
726 {
727 void __iomem *addr;
728 ulong32 id;
729
730 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
731 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
732 id = gdth_readl(addr);
733 iounmap(addr);
734 if (id == GDT2_ID) /* GDT2000 */
735 return 1;
736 }
737 return 0;
738 }
739
740
741 static int __init gdth_search_pci(gdth_pci_str *pcistr)
742 {
743 ushort device, cnt;
744
745 TRACE(("gdth_search_pci()\n"));
746
747 cnt = 0;
748 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
749 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
750 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
751 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
752 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
753 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
754 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
755 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
756 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
757 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
758 PCI_DEVICE_ID_INTEL_SRC);
759 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
760 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
761 return cnt;
762 }
763
764 /* Vortex only makes RAID controllers.
765 * We do not really want to specify all 550 ids here, so wildcard match.
766 */
767 static struct pci_device_id gdthtable[] __attribute_used__ = {
768 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
769 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
770 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
771 {0}
772 };
773 MODULE_DEVICE_TABLE(pci,gdthtable);
774
775 static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
776 ushort vendor, ushort device)
777 {
778 ulong base0, base1, base2;
779 struct pci_dev *pdev;
780
781 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
782 *cnt, vendor, device));
783
784 pdev = NULL;
785 while ((pdev = pci_find_device(vendor, device, pdev))
786 != NULL) {
787 if (pci_enable_device(pdev))
788 continue;
789 if (*cnt >= MAXHA)
790 return;
791 /* GDT PCI controller found, resources are already in pdev */
792 pcistr[*cnt].pdev = pdev;
793 pcistr[*cnt].vendor_id = vendor;
794 pcistr[*cnt].device_id = device;
795 pcistr[*cnt].subdevice_id = pdev->subsystem_device;
796 pcistr[*cnt].bus = pdev->bus->number;
797 pcistr[*cnt].device_fn = pdev->devfn;
798 pcistr[*cnt].irq = pdev->irq;
799 base0 = pci_resource_flags(pdev, 0);
800 base1 = pci_resource_flags(pdev, 1);
801 base2 = pci_resource_flags(pdev, 2);
802 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
803 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
804 if (!(base0 & IORESOURCE_MEM))
805 continue;
806 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
807 } else { /* GDT6110, GDT6120, .. */
808 if (!(base0 & IORESOURCE_MEM) ||
809 !(base2 & IORESOURCE_MEM) ||
810 !(base1 & IORESOURCE_IO))
811 continue;
812 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
813 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
814 pcistr[*cnt].io = pci_resource_start(pdev, 1);
815 }
816 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
817 pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
818 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
819 (*cnt)++;
820 }
821 }
822
823
824 static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
825 {
826 gdth_pci_str temp;
827 int i, changed;
828
829 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
830 if (cnt == 0)
831 return;
832
833 do {
834 changed = FALSE;
835 for (i = 0; i < cnt-1; ++i) {
836 if (!reverse_scan) {
837 if ((pcistr[i].bus > pcistr[i+1].bus) ||
838 (pcistr[i].bus == pcistr[i+1].bus &&
839 PCI_SLOT(pcistr[i].device_fn) >
840 PCI_SLOT(pcistr[i+1].device_fn))) {
841 temp = pcistr[i];
842 pcistr[i] = pcistr[i+1];
843 pcistr[i+1] = temp;
844 changed = TRUE;
845 }
846 } else {
847 if ((pcistr[i].bus < pcistr[i+1].bus) ||
848 (pcistr[i].bus == pcistr[i+1].bus &&
849 PCI_SLOT(pcistr[i].device_fn) <
850 PCI_SLOT(pcistr[i+1].device_fn))) {
851 temp = pcistr[i];
852 pcistr[i] = pcistr[i+1];
853 pcistr[i+1] = temp;
854 changed = TRUE;
855 }
856 }
857 }
858 } while (changed);
859 }
860
861
862 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
863 {
864 ulong32 retries,id;
865 unchar prot_ver,eisacf,i,irq_found;
866
867 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
868
869 /* disable board interrupts, deinitialize services */
870 outb(0xff,eisa_adr+EDOORREG);
871 outb(0x00,eisa_adr+EDENABREG);
872 outb(0x00,eisa_adr+EINTENABREG);
873
874 outb(0xff,eisa_adr+LDOORREG);
875 retries = INIT_RETRIES;
876 gdth_delay(20);
877 while (inb(eisa_adr+EDOORREG) != 0xff) {
878 if (--retries == 0) {
879 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
880 return 0;
881 }
882 gdth_delay(1);
883 TRACE2(("wait for DEINIT: retries=%d\n",retries));
884 }
885 prot_ver = inb(eisa_adr+MAILBOXREG);
886 outb(0xff,eisa_adr+EDOORREG);
887 if (prot_ver != PROTOCOL_VERSION) {
888 printk("GDT-EISA: Illegal protocol version\n");
889 return 0;
890 }
891 ha->bmic = eisa_adr;
892 ha->brd_phys = (ulong32)eisa_adr >> 12;
893
894 outl(0,eisa_adr+MAILBOXREG);
895 outl(0,eisa_adr+MAILBOXREG+4);
896 outl(0,eisa_adr+MAILBOXREG+8);
897 outl(0,eisa_adr+MAILBOXREG+12);
898
899 /* detect IRQ */
900 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
901 ha->oem_id = OEM_ID_ICP;
902 ha->type = GDT_EISA;
903 ha->stype = id;
904 outl(1,eisa_adr+MAILBOXREG+8);
905 outb(0xfe,eisa_adr+LDOORREG);
906 retries = INIT_RETRIES;
907 gdth_delay(20);
908 while (inb(eisa_adr+EDOORREG) != 0xfe) {
909 if (--retries == 0) {
910 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
911 return 0;
912 }
913 gdth_delay(1);
914 }
915 ha->irq = inb(eisa_adr+MAILBOXREG);
916 outb(0xff,eisa_adr+EDOORREG);
917 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
918 /* check the result */
919 if (ha->irq == 0) {
920 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
921 for (i = 0, irq_found = FALSE;
922 i < MAXHA && irq[i] != 0xff; ++i) {
923 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
924 irq_found = TRUE;
925 break;
926 }
927 }
928 if (irq_found) {
929 ha->irq = irq[i];
930 irq[i] = 0;
931 printk("GDT-EISA: Can not detect controller IRQ,\n");
932 printk("Use IRQ setting from command line (IRQ = %d)\n",
933 ha->irq);
934 } else {
935 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
936 printk("the controller BIOS or use command line parameters\n");
937 return 0;
938 }
939 }
940 } else {
941 eisacf = inb(eisa_adr+EISAREG) & 7;
942 if (eisacf > 4) /* level triggered */
943 eisacf -= 4;
944 ha->irq = gdth_irq_tab[eisacf];
945 ha->oem_id = OEM_ID_ICP;
946 ha->type = GDT_EISA;
947 ha->stype = id;
948 }
949
950 ha->dma64_support = 0;
951 return 1;
952 }
953
954
955 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
956 {
957 register gdt2_dpram_str __iomem *dp2_ptr;
958 int i;
959 unchar irq_drq,prot_ver;
960 ulong32 retries;
961
962 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
963
964 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
965 if (ha->brd == NULL) {
966 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
967 return 0;
968 }
969 dp2_ptr = ha->brd;
970 gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
971 /* reset interface area */
972 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
973 if (gdth_readl(&dp2_ptr->u) != 0) {
974 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
975 iounmap(ha->brd);
976 return 0;
977 }
978
979 /* disable board interrupts, read DRQ and IRQ */
980 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
981 gdth_writeb(0x00, &dp2_ptr->io.irqen);
982 gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
983 gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
984
985 irq_drq = gdth_readb(&dp2_ptr->io.rq);
986 for (i=0; i<3; ++i) {
987 if ((irq_drq & 1)==0)
988 break;
989 irq_drq >>= 1;
990 }
991 ha->drq = gdth_drq_tab[i];
992
993 irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
994 for (i=1; i<5; ++i) {
995 if ((irq_drq & 1)==0)
996 break;
997 irq_drq >>= 1;
998 }
999 ha->irq = gdth_irq_tab[i];
1000
1001 /* deinitialize services */
1002 gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
1003 gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
1004 gdth_writeb(0, &dp2_ptr->io.event);
1005 retries = INIT_RETRIES;
1006 gdth_delay(20);
1007 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
1008 if (--retries == 0) {
1009 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
1010 iounmap(ha->brd);
1011 return 0;
1012 }
1013 gdth_delay(1);
1014 }
1015 prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
1016 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1017 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1018 if (prot_ver != PROTOCOL_VERSION) {
1019 printk("GDT-ISA: Illegal protocol version\n");
1020 iounmap(ha->brd);
1021 return 0;
1022 }
1023
1024 ha->oem_id = OEM_ID_ICP;
1025 ha->type = GDT_ISA;
1026 ha->ic_all_size = sizeof(dp2_ptr->u);
1027 ha->stype= GDT2_ID;
1028 ha->brd_phys = bios_adr >> 4;
1029
1030 /* special request to controller BIOS */
1031 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
1032 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
1033 gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
1034 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
1035 gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
1036 gdth_writeb(0, &dp2_ptr->io.event);
1037 retries = INIT_RETRIES;
1038 gdth_delay(20);
1039 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
1040 if (--retries == 0) {
1041 printk("GDT-ISA: Initialization error\n");
1042 iounmap(ha->brd);
1043 return 0;
1044 }
1045 gdth_delay(1);
1046 }
1047 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1048 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1049
1050 ha->dma64_support = 0;
1051 return 1;
1052 }
1053
1054
1055 static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
1056 {
1057 register gdt6_dpram_str __iomem *dp6_ptr;
1058 register gdt6c_dpram_str __iomem *dp6c_ptr;
1059 register gdt6m_dpram_str __iomem *dp6m_ptr;
1060 ulong32 retries;
1061 unchar prot_ver;
1062 ushort command;
1063 int i, found = FALSE;
1064
1065 TRACE(("gdth_init_pci()\n"));
1066
1067 if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
1068 ha->oem_id = OEM_ID_INTEL;
1069 else
1070 ha->oem_id = OEM_ID_ICP;
1071 ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
1072 ha->stype = (ulong32)pcistr->device_id;
1073 ha->subdevice_id = pcistr->subdevice_id;
1074 ha->irq = pcistr->irq;
1075 ha->pdev = pcistr->pdev;
1076
1077 if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1078 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1079 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
1080 if (ha->brd == NULL) {
1081 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1082 return 0;
1083 }
1084 /* check and reset interface area */
1085 dp6_ptr = ha->brd;
1086 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1087 if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
1088 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1089 pcistr->dpmem);
1090 found = FALSE;
1091 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1092 iounmap(ha->brd);
1093 ha->brd = ioremap(i, sizeof(ushort));
1094 if (ha->brd == NULL) {
1095 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1096 return 0;
1097 }
1098 if (gdth_readw(ha->brd) != 0xffff) {
1099 TRACE2(("init_pci_old() address 0x%x busy\n", i));
1100 continue;
1101 }
1102 iounmap(ha->brd);
1103 pci_write_config_dword(pcistr->pdev,
1104 PCI_BASE_ADDRESS_0, i);
1105 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
1106 if (ha->brd == NULL) {
1107 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1108 return 0;
1109 }
1110 dp6_ptr = ha->brd;
1111 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1112 if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1113 printk("GDT-PCI: Use free address at 0x%x\n", i);
1114 found = TRUE;
1115 break;
1116 }
1117 }
1118 if (!found) {
1119 printk("GDT-PCI: No free address found!\n");
1120 iounmap(ha->brd);
1121 return 0;
1122 }
1123 }
1124 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
1125 if (gdth_readl(&dp6_ptr->u) != 0) {
1126 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1127 iounmap(ha->brd);
1128 return 0;
1129 }
1130
1131 /* disable board interrupts, deinit services */
1132 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1133 gdth_writeb(0x00, &dp6_ptr->io.irqen);
1134 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
1135 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
1136
1137 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
1138 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
1139 gdth_writeb(0, &dp6_ptr->io.event);
1140 retries = INIT_RETRIES;
1141 gdth_delay(20);
1142 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1143 if (--retries == 0) {
1144 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1145 iounmap(ha->brd);
1146 return 0;
1147 }
1148 gdth_delay(1);
1149 }
1150 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
1151 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1152 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1153 if (prot_ver != PROTOCOL_VERSION) {
1154 printk("GDT-PCI: Illegal protocol version\n");
1155 iounmap(ha->brd);
1156 return 0;
1157 }
1158
1159 ha->type = GDT_PCI;
1160 ha->ic_all_size = sizeof(dp6_ptr->u);
1161
1162 /* special command to controller BIOS */
1163 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
1164 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
1165 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
1166 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
1167 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
1168 gdth_writeb(0, &dp6_ptr->io.event);
1169 retries = INIT_RETRIES;
1170 gdth_delay(20);
1171 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1172 if (--retries == 0) {
1173 printk("GDT-PCI: Initialization error\n");
1174 iounmap(ha->brd);
1175 return 0;
1176 }
1177 gdth_delay(1);
1178 }
1179 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1180 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1181
1182 ha->dma64_support = 0;
1183
1184 } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1185 ha->plx = (gdt6c_plx_regs *)pcistr->io;
1186 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
1187 pcistr->dpmem,ha->irq));
1188 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1189 if (ha->brd == NULL) {
1190 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1191 iounmap(ha->brd);
1192 return 0;
1193 }
1194 /* check and reset interface area */
1195 dp6c_ptr = ha->brd;
1196 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1197 if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1198 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1199 pcistr->dpmem);
1200 found = FALSE;
1201 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1202 iounmap(ha->brd);
1203 ha->brd = ioremap(i, sizeof(ushort));
1204 if (ha->brd == NULL) {
1205 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1206 return 0;
1207 }
1208 if (gdth_readw(ha->brd) != 0xffff) {
1209 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1210 continue;
1211 }
1212 iounmap(ha->brd);
1213 pci_write_config_dword(pcistr->pdev,
1214 PCI_BASE_ADDRESS_2, i);
1215 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1216 if (ha->brd == NULL) {
1217 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1218 return 0;
1219 }
1220 dp6c_ptr = ha->brd;
1221 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1222 if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1223 printk("GDT-PCI: Use free address at 0x%x\n", i);
1224 found = TRUE;
1225 break;
1226 }
1227 }
1228 if (!found) {
1229 printk("GDT-PCI: No free address found!\n");
1230 iounmap(ha->brd);
1231 return 0;
1232 }
1233 }
1234 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1235 if (gdth_readl(&dp6c_ptr->u) != 0) {
1236 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1237 iounmap(ha->brd);
1238 return 0;
1239 }
1240
1241 /* disable board interrupts, deinit services */
1242 outb(0x00,PTR2USHORT(&ha->plx->control1));
1243 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1244
1245 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1246 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1247
1248 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1249 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1250
1251 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1252
1253 retries = INIT_RETRIES;
1254 gdth_delay(20);
1255 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1256 if (--retries == 0) {
1257 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1258 iounmap(ha->brd);
1259 return 0;
1260 }
1261 gdth_delay(1);
1262 }
1263 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
1264 gdth_writeb(0, &dp6c_ptr->u.ic.Status);
1265 if (prot_ver != PROTOCOL_VERSION) {
1266 printk("GDT-PCI: Illegal protocol version\n");
1267 iounmap(ha->brd);
1268 return 0;
1269 }
1270
1271 ha->type = GDT_PCINEW;
1272 ha->ic_all_size = sizeof(dp6c_ptr->u);
1273
1274 /* special command to controller BIOS */
1275 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1276 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1277 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1278 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1279 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1280
1281 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1282
1283 retries = INIT_RETRIES;
1284 gdth_delay(20);
1285 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1286 if (--retries == 0) {
1287 printk("GDT-PCI: Initialization error\n");
1288 iounmap(ha->brd);
1289 return 0;
1290 }
1291 gdth_delay(1);
1292 }
1293 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
1294
1295 ha->dma64_support = 0;
1296
1297 } else { /* MPR */
1298 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1299 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1300 if (ha->brd == NULL) {
1301 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1302 return 0;
1303 }
1304
1305 /* manipulate config. space to enable DPMEM, start RP controller */
1306 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1307 command |= 6;
1308 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1309 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1310 pci_resource_start(pcistr->pdev, 8) = 0UL;
1311 i = 0xFEFF0001UL;
1312 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1313 gdth_delay(1);
1314 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1315 pci_resource_start(pcistr->pdev, 8));
1316
1317 dp6m_ptr = ha->brd;
1318
1319 /* Ensure that it is safe to access the non HW portions of DPMEM.
1320 * Aditional check needed for Xscale based RAID controllers */
1321 while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1322 gdth_delay(1);
1323
1324 /* check and reset interface area */
1325 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1326 if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1327 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1328 pcistr->dpmem);
1329 found = FALSE;
1330 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1331 iounmap(ha->brd);
1332 ha->brd = ioremap(i, sizeof(ushort));
1333 if (ha->brd == NULL) {
1334 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1335 return 0;
1336 }
1337 if (gdth_readw(ha->brd) != 0xffff) {
1338 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1339 continue;
1340 }
1341 iounmap(ha->brd);
1342 pci_write_config_dword(pcistr->pdev,
1343 PCI_BASE_ADDRESS_0, i);
1344 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1345 if (ha->brd == NULL) {
1346 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1347 return 0;
1348 }
1349 dp6m_ptr = ha->brd;
1350 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1351 if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1352 printk("GDT-PCI: Use free address at 0x%x\n", i);
1353 found = TRUE;
1354 break;
1355 }
1356 }
1357 if (!found) {
1358 printk("GDT-PCI: No free address found!\n");
1359 iounmap(ha->brd);
1360 return 0;
1361 }
1362 }
1363 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1364
1365 /* disable board interrupts, deinit services */
1366 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1367 &dp6m_ptr->i960r.edoor_en_reg);
1368 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1369 gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1370 gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1371
1372 gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1373 gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1374 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1375 retries = INIT_RETRIES;
1376 gdth_delay(20);
1377 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1378 if (--retries == 0) {
1379 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1380 iounmap(ha->brd);
1381 return 0;
1382 }
1383 gdth_delay(1);
1384 }
1385 prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
1386 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1387 if (prot_ver != PROTOCOL_VERSION) {
1388 printk("GDT-PCI: Illegal protocol version\n");
1389 iounmap(ha->brd);
1390 return 0;
1391 }
1392
1393 ha->type = GDT_PCIMPR;
1394 ha->ic_all_size = sizeof(dp6m_ptr->u);
1395
1396 /* special command to controller BIOS */
1397 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1398 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1399 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1400 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1401 gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1402 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1403 retries = INIT_RETRIES;
1404 gdth_delay(20);
1405 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1406 if (--retries == 0) {
1407 printk("GDT-PCI: Initialization error\n");
1408 iounmap(ha->brd);
1409 return 0;
1410 }
1411 gdth_delay(1);
1412 }
1413 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1414
1415 /* read FW version to detect 64-bit DMA support */
1416 gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1417 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1418 retries = INIT_RETRIES;
1419 gdth_delay(20);
1420 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1421 if (--retries == 0) {
1422 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1423 iounmap(ha->brd);
1424 return 0;
1425 }
1426 gdth_delay(1);
1427 }
1428 prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1429 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1430 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1431 ha->dma64_support = 0;
1432 else
1433 ha->dma64_support = 1;
1434 }
1435
1436 return 1;
1437 }
1438
1439
1440 /* controller protocol functions */
1441
1442 static void __init gdth_enable_int(int hanum)
1443 {
1444 gdth_ha_str *ha;
1445 ulong flags;
1446 gdt2_dpram_str __iomem *dp2_ptr;
1447 gdt6_dpram_str __iomem *dp6_ptr;
1448 gdt6m_dpram_str __iomem *dp6m_ptr;
1449
1450 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1451 ha = HADATA(gdth_ctr_tab[hanum]);
1452 spin_lock_irqsave(&ha->smp_lock, flags);
1453
1454 if (ha->type == GDT_EISA) {
1455 outb(0xff, ha->bmic + EDOORREG);
1456 outb(0xff, ha->bmic + EDENABREG);
1457 outb(0x01, ha->bmic + EINTENABREG);
1458 } else if (ha->type == GDT_ISA) {
1459 dp2_ptr = ha->brd;
1460 gdth_writeb(1, &dp2_ptr->io.irqdel);
1461 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1462 gdth_writeb(1, &dp2_ptr->io.irqen);
1463 } else if (ha->type == GDT_PCI) {
1464 dp6_ptr = ha->brd;
1465 gdth_writeb(1, &dp6_ptr->io.irqdel);
1466 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1467 gdth_writeb(1, &dp6_ptr->io.irqen);
1468 } else if (ha->type == GDT_PCINEW) {
1469 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1470 outb(0x03, PTR2USHORT(&ha->plx->control1));
1471 } else if (ha->type == GDT_PCIMPR) {
1472 dp6m_ptr = ha->brd;
1473 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1474 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1475 &dp6m_ptr->i960r.edoor_en_reg);
1476 }
1477 spin_unlock_irqrestore(&ha->smp_lock, flags);
1478 }
1479
1480
1481 static int gdth_get_status(unchar *pIStatus,int irq)
1482 {
1483 register gdth_ha_str *ha;
1484 int i;
1485
1486 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1487 irq,gdth_ctr_count));
1488
1489 *pIStatus = 0;
1490 for (i=0; i<gdth_ctr_count; ++i) {
1491 ha = HADATA(gdth_ctr_tab[i]);
1492 if (ha->irq != (unchar)irq) /* check IRQ */
1493 continue;
1494 if (ha->type == GDT_EISA)
1495 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1496 else if (ha->type == GDT_ISA)
1497 *pIStatus =
1498 gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1499 else if (ha->type == GDT_PCI)
1500 *pIStatus =
1501 gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1502 else if (ha->type == GDT_PCINEW)
1503 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1504 else if (ha->type == GDT_PCIMPR)
1505 *pIStatus =
1506 gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1507
1508 if (*pIStatus)
1509 return i; /* board found */
1510 }
1511 return -1;
1512 }
1513
1514
1515 static int gdth_test_busy(int hanum)
1516 {
1517 register gdth_ha_str *ha;
1518 register int gdtsema0 = 0;
1519
1520 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1521
1522 ha = HADATA(gdth_ctr_tab[hanum]);
1523 if (ha->type == GDT_EISA)
1524 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1525 else if (ha->type == GDT_ISA)
1526 gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1527 else if (ha->type == GDT_PCI)
1528 gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1529 else if (ha->type == GDT_PCINEW)
1530 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1531 else if (ha->type == GDT_PCIMPR)
1532 gdtsema0 =
1533 (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1534
1535 return (gdtsema0 & 1);
1536 }
1537
1538
1539 static int gdth_get_cmd_index(int hanum)
1540 {
1541 register gdth_ha_str *ha;
1542 int i;
1543
1544 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1545
1546 ha = HADATA(gdth_ctr_tab[hanum]);
1547 for (i=0; i<GDTH_MAXCMDS; ++i) {
1548 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1549 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1550 ha->cmd_tab[i].service = ha->pccb->Service;
1551 ha->pccb->CommandIndex = (ulong32)i+2;
1552 return (i+2);
1553 }
1554 }
1555 return 0;
1556 }
1557
1558
1559 static void gdth_set_sema0(int hanum)
1560 {
1561 register gdth_ha_str *ha;
1562
1563 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1564
1565 ha = HADATA(gdth_ctr_tab[hanum]);
1566 if (ha->type == GDT_EISA) {
1567 outb(1, ha->bmic + SEMA0REG);
1568 } else if (ha->type == GDT_ISA) {
1569 gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1570 } else if (ha->type == GDT_PCI) {
1571 gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1572 } else if (ha->type == GDT_PCINEW) {
1573 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1574 } else if (ha->type == GDT_PCIMPR) {
1575 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1576 }
1577 }
1578
1579
1580 static void gdth_copy_command(int hanum)
1581 {
1582 register gdth_ha_str *ha;
1583 register gdth_cmd_str *cmd_ptr;
1584 register gdt6m_dpram_str __iomem *dp6m_ptr;
1585 register gdt6c_dpram_str __iomem *dp6c_ptr;
1586 gdt6_dpram_str __iomem *dp6_ptr;
1587 gdt2_dpram_str __iomem *dp2_ptr;
1588 ushort cp_count,dp_offset,cmd_no;
1589
1590 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1591
1592 ha = HADATA(gdth_ctr_tab[hanum]);
1593 cp_count = ha->cmd_len;
1594 dp_offset= ha->cmd_offs_dpmem;
1595 cmd_no = ha->cmd_cnt;
1596 cmd_ptr = ha->pccb;
1597
1598 ++ha->cmd_cnt;
1599 if (ha->type == GDT_EISA)
1600 return; /* no DPMEM, no copy */
1601
1602 /* set cpcount dword aligned */
1603 if (cp_count & 3)
1604 cp_count += (4 - (cp_count & 3));
1605
1606 ha->cmd_offs_dpmem += cp_count;
1607
1608 /* set offset and service, copy command to DPMEM */
1609 if (ha->type == GDT_ISA) {
1610 dp2_ptr = ha->brd;
1611 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1612 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1613 gdth_writew((ushort)cmd_ptr->Service,
1614 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1615 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1616 } else if (ha->type == GDT_PCI) {
1617 dp6_ptr = ha->brd;
1618 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1619 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1620 gdth_writew((ushort)cmd_ptr->Service,
1621 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1622 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1623 } else if (ha->type == GDT_PCINEW) {
1624 dp6c_ptr = ha->brd;
1625 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1626 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1627 gdth_writew((ushort)cmd_ptr->Service,
1628 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1629 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1630 } else if (ha->type == GDT_PCIMPR) {
1631 dp6m_ptr = ha->brd;
1632 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1633 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1634 gdth_writew((ushort)cmd_ptr->Service,
1635 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1636 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1637 }
1638 }
1639
1640
1641 static void gdth_release_event(int hanum)
1642 {
1643 register gdth_ha_str *ha;
1644
1645 TRACE(("gdth_release_event() hanum %d\n",hanum));
1646 ha = HADATA(gdth_ctr_tab[hanum]);
1647
1648 #ifdef GDTH_STATISTICS
1649 {
1650 ulong32 i,j;
1651 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1652 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1653 ++i;
1654 }
1655 if (max_index < i) {
1656 max_index = i;
1657 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1658 }
1659 }
1660 #endif
1661
1662 if (ha->pccb->OpCode == GDT_INIT)
1663 ha->pccb->Service |= 0x80;
1664
1665 if (ha->type == GDT_EISA) {
1666 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1667 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1668 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1669 } else if (ha->type == GDT_ISA) {
1670 gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1671 } else if (ha->type == GDT_PCI) {
1672 gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1673 } else if (ha->type == GDT_PCINEW) {
1674 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1675 } else if (ha->type == GDT_PCIMPR) {
1676 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1677 }
1678 }
1679
1680
1681 static int gdth_wait(int hanum,int index,ulong32 time)
1682 {
1683 gdth_ha_str *ha;
1684 int answer_found = FALSE;
1685
1686 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1687
1688 ha = HADATA(gdth_ctr_tab[hanum]);
1689 if (index == 0)
1690 return 1; /* no wait required */
1691
1692 gdth_from_wait = TRUE;
1693 do {
1694 gdth_interrupt((int)ha->irq,ha,NULL);
1695 if (wait_hanum==hanum && wait_index==index) {
1696 answer_found = TRUE;
1697 break;
1698 }
1699 gdth_delay(1);
1700 } while (--time);
1701 gdth_from_wait = FALSE;
1702
1703 while (gdth_test_busy(hanum))
1704 gdth_delay(0);
1705
1706 return (answer_found);
1707 }
1708
1709
1710 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1711 ulong64 p2,ulong64 p3)
1712 {
1713 register gdth_ha_str *ha;
1714 register gdth_cmd_str *cmd_ptr;
1715 int retries,index;
1716
1717 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1718
1719 ha = HADATA(gdth_ctr_tab[hanum]);
1720 cmd_ptr = ha->pccb;
1721 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1722
1723 /* make command */
1724 for (retries = INIT_RETRIES;;) {
1725 cmd_ptr->Service = service;
1726 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1727 if (!(index=gdth_get_cmd_index(hanum))) {
1728 TRACE(("GDT: No free command index found\n"));
1729 return 0;
1730 }
1731 gdth_set_sema0(hanum);
1732 cmd_ptr->OpCode = opcode;
1733 cmd_ptr->BoardNode = LOCALBOARD;
1734 if (service == CACHESERVICE) {
1735 if (opcode == GDT_IOCTL) {
1736 cmd_ptr->u.ioctl.subfunc = p1;
1737 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1738 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1739 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1740 } else {
1741 if (ha->cache_feat & GDT_64BIT) {
1742 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1743 cmd_ptr->u.cache64.BlockNo = p2;
1744 } else {
1745 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1746 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1747 }
1748 }
1749 } else if (service == SCSIRAWSERVICE) {
1750 if (ha->raw_feat & GDT_64BIT) {
1751 cmd_ptr->u.raw64.direction = p1;
1752 cmd_ptr->u.raw64.bus = (unchar)p2;
1753 cmd_ptr->u.raw64.target = (unchar)p3;
1754 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1755 } else {
1756 cmd_ptr->u.raw.direction = p1;
1757 cmd_ptr->u.raw.bus = (unchar)p2;
1758 cmd_ptr->u.raw.target = (unchar)p3;
1759 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1760 }
1761 } else if (service == SCREENSERVICE) {
1762 if (opcode == GDT_REALTIME) {
1763 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1764 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1765 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1766 }
1767 }
1768 ha->cmd_len = sizeof(gdth_cmd_str);
1769 ha->cmd_offs_dpmem = 0;
1770 ha->cmd_cnt = 0;
1771 gdth_copy_command(hanum);
1772 gdth_release_event(hanum);
1773 gdth_delay(20);
1774 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1775 printk("GDT: Initialization error (timeout service %d)\n",service);
1776 return 0;
1777 }
1778 if (ha->status != S_BSY || --retries == 0)
1779 break;
1780 gdth_delay(1);
1781 }
1782
1783 return (ha->status != S_OK ? 0:1);
1784 }
1785
1786
1787 /* search for devices */
1788
1789 static int __init gdth_search_drives(int hanum)
1790 {
1791 register gdth_ha_str *ha;
1792 ushort cdev_cnt, i;
1793 int ok;
1794 ulong32 bus_no, drv_cnt, drv_no, j;
1795 gdth_getch_str *chn;
1796 gdth_drlist_str *drl;
1797 gdth_iochan_str *ioc;
1798 gdth_raw_iochan_str *iocr;
1799 gdth_arcdl_str *alst;
1800 gdth_alist_str *alst2;
1801 gdth_oem_str_ioctl *oemstr;
1802 #ifdef INT_COAL
1803 gdth_perf_modes *pmod;
1804 #endif
1805
1806 #ifdef GDTH_RTC
1807 unchar rtc[12];
1808 ulong flags;
1809 #endif
1810
1811 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1812 ha = HADATA(gdth_ctr_tab[hanum]);
1813 ok = 0;
1814
1815 /* initialize controller services, at first: screen service */
1816 ha->screen_feat = 0;
1817 if (!force_dma32) {
1818 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1819 if (ok)
1820 ha->screen_feat = GDT_64BIT;
1821 }
1822 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1823 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1824 if (!ok) {
1825 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1826 hanum, ha->status);
1827 return 0;
1828 }
1829 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1830
1831 #ifdef GDTH_RTC
1832 /* read realtime clock info, send to controller */
1833 /* 1. wait for the falling edge of update flag */
1834 spin_lock_irqsave(&rtc_lock, flags);
1835 for (j = 0; j < 1000000; ++j)
1836 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1837 break;
1838 for (j = 0; j < 1000000; ++j)
1839 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1840 break;
1841 /* 2. read info */
1842 do {
1843 for (j = 0; j < 12; ++j)
1844 rtc[j] = CMOS_READ(j);
1845 } while (rtc[0] != CMOS_READ(0));
1846 spin_lock_irqrestore(&rtc_lock, flags);
1847 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1848 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1849 /* 3. send to controller firmware */
1850 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1851 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1852 #endif
1853
1854 /* unfreeze all IOs */
1855 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1856
1857 /* initialize cache service */
1858 ha->cache_feat = 0;
1859 if (!force_dma32) {
1860 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1861 if (ok)
1862 ha->cache_feat = GDT_64BIT;
1863 }
1864 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1865 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1866 if (!ok) {
1867 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1868 hanum, ha->status);
1869 return 0;
1870 }
1871 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1872 cdev_cnt = (ushort)ha->info;
1873 ha->fw_vers = ha->service;
1874
1875 #ifdef INT_COAL
1876 if (ha->type == GDT_PCIMPR) {
1877 /* set perf. modes */
1878 pmod = (gdth_perf_modes *)ha->pscratch;
1879 pmod->version = 1;
1880 pmod->st_mode = 1; /* enable one status buffer */
1881 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1882 pmod->st_buff_indx1 = COALINDEX;
1883 pmod->st_buff_addr2 = 0;
1884 pmod->st_buff_u_addr2 = 0;
1885 pmod->st_buff_indx2 = 0;
1886 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1887 pmod->cmd_mode = 0; // disable all cmd buffers
1888 pmod->cmd_buff_addr1 = 0;
1889 pmod->cmd_buff_u_addr1 = 0;
1890 pmod->cmd_buff_indx1 = 0;
1891 pmod->cmd_buff_addr2 = 0;
1892 pmod->cmd_buff_u_addr2 = 0;
1893 pmod->cmd_buff_indx2 = 0;
1894 pmod->cmd_buff_size = 0;
1895 pmod->reserved1 = 0;
1896 pmod->reserved2 = 0;
1897 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
1898 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1899 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
1900 }
1901 }
1902 #endif
1903
1904 /* detect number of buses - try new IOCTL */
1905 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1906 iocr->hdr.version = 0xffffffff;
1907 iocr->hdr.list_entries = MAXBUS;
1908 iocr->hdr.first_chan = 0;
1909 iocr->hdr.last_chan = MAXBUS-1;
1910 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1911 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
1912 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1913 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1914 ha->bus_cnt = iocr->hdr.chan_count;
1915 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1916 if (iocr->list[bus_no].proc_id < MAXID)
1917 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1918 else
1919 ha->bus_id[bus_no] = 0xff;
1920 }
1921 } else {
1922 /* old method */
1923 chn = (gdth_getch_str *)ha->pscratch;
1924 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1925 chn->channel_no = bus_no;
1926 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
1927 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1928 IO_CHANNEL | INVALID_CHANNEL,
1929 sizeof(gdth_getch_str))) {
1930 if (bus_no == 0) {
1931 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1932 hanum, ha->status);
1933 return 0;
1934 }
1935 break;
1936 }
1937 if (chn->siop_id < MAXID)
1938 ha->bus_id[bus_no] = chn->siop_id;
1939 else
1940 ha->bus_id[bus_no] = 0xff;
1941 }
1942 ha->bus_cnt = (unchar)bus_no;
1943 }
1944 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1945
1946 /* read cache configuration */
1947 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
1948 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1949 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1950 hanum, ha->status);
1951 return 0;
1952 }
1953 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1954 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1955 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1956 ha->cpar.write_back,ha->cpar.block_size));
1957
1958 /* read board info and features */
1959 ha->more_proc = FALSE;
1960 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
1961 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1962 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1963 sizeof(gdth_binfo_str));
1964 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
1965 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1966 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1967 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1968 ha->more_proc = TRUE;
1969 }
1970 } else {
1971 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1972 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
1973 }
1974 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1975
1976 /* read more informations */
1977 if (ha->more_proc) {
1978 /* physical drives, channel addresses */
1979 ioc = (gdth_iochan_str *)ha->pscratch;
1980 ioc->hdr.version = 0xffffffff;
1981 ioc->hdr.list_entries = MAXBUS;
1982 ioc->hdr.first_chan = 0;
1983 ioc->hdr.last_chan = MAXBUS-1;
1984 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1985 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
1986 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1987 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1988 ha->raw[bus_no].address = ioc->list[bus_no].address;
1989 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1990 }
1991 } else {
1992 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1993 ha->raw[bus_no].address = IO_CHANNEL;
1994 ha->raw[bus_no].local_no = bus_no;
1995 }
1996 }
1997 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1998 chn = (gdth_getch_str *)ha->pscratch;
1999 chn->channel_no = ha->raw[bus_no].local_no;
2000 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2001 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2002 ha->raw[bus_no].address | INVALID_CHANNEL,
2003 sizeof(gdth_getch_str))) {
2004 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
2005 TRACE2(("Channel %d: %d phys. drives\n",
2006 bus_no,chn->drive_cnt));
2007 }
2008 if (ha->raw[bus_no].pdev_cnt > 0) {
2009 drl = (gdth_drlist_str *)ha->pscratch;
2010 drl->sc_no = ha->raw[bus_no].local_no;
2011 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
2012 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2013 SCSI_DR_LIST | L_CTRL_PATTERN,
2014 ha->raw[bus_no].address | INVALID_CHANNEL,
2015 sizeof(gdth_drlist_str))) {
2016 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
2017 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
2018 } else {
2019 ha->raw[bus_no].pdev_cnt = 0;
2020 }
2021 }
2022 }
2023
2024 /* logical drives */
2025 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
2026 INVALID_CHANNEL,sizeof(ulong32))) {
2027 drv_cnt = *(ulong32 *)ha->pscratch;
2028 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
2029 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
2030 for (j = 0; j < drv_cnt; ++j) {
2031 drv_no = ((ulong32 *)ha->pscratch)[j];
2032 if (drv_no < MAX_LDRIVES) {
2033 ha->hdr[drv_no].is_logdrv = TRUE;
2034 TRACE2(("Drive %d is log. drive\n",drv_no));
2035 }
2036 }
2037 }
2038 alst = (gdth_arcdl_str *)ha->pscratch;
2039 alst->entries_avail = MAX_LDRIVES;
2040 alst->first_entry = 0;
2041 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
2042 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2043 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
2044 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
2045 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
2046 for (j = 0; j < alst->entries_init; ++j) {
2047 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
2048 ha->hdr[j].is_master = alst->list[j].is_master;
2049 ha->hdr[j].is_parity = alst->list[j].is_parity;
2050 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
2051 ha->hdr[j].master_no = alst->list[j].cd_handle;
2052 }
2053 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2054 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
2055 0, 35 * sizeof(gdth_alist_str))) {
2056 for (j = 0; j < 35; ++j) {
2057 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
2058 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
2059 ha->hdr[j].is_master = alst2->is_master;
2060 ha->hdr[j].is_parity = alst2->is_parity;
2061 ha->hdr[j].is_hotfix = alst2->is_hotfix;
2062 ha->hdr[j].master_no = alst2->cd_handle;
2063 }
2064 }
2065 }
2066 }
2067
2068 /* initialize raw service */
2069 ha->raw_feat = 0;
2070 if (!force_dma32) {
2071 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
2072 if (ok)
2073 ha->raw_feat = GDT_64BIT;
2074 }
2075 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
2076 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
2077 if (!ok) {
2078 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
2079 hanum, ha->status);
2080 return 0;
2081 }
2082 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
2083
2084 /* set/get features raw service (scatter/gather) */
2085 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
2086 0,0)) {
2087 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
2088 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
2089 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
2090 ha->info));
2091 ha->raw_feat |= (ushort)ha->info;
2092 }
2093 }
2094
2095 /* set/get features cache service (equal to raw service) */
2096 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
2097 SCATTER_GATHER,0)) {
2098 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
2099 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
2100 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
2101 ha->info));
2102 ha->cache_feat |= (ushort)ha->info;
2103 }
2104 }
2105
2106 /* reserve drives for raw service */
2107 if (reserve_mode != 0) {
2108 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
2109 reserve_mode == 1 ? 1 : 3, 0, 0);
2110 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
2111 ha->status));
2112 }
2113 for (i = 0; i < MAX_RES_ARGS; i += 4) {
2114 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
2115 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
2116 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
2117 reserve_list[i], reserve_list[i+1],
2118 reserve_list[i+2], reserve_list[i+3]));
2119 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
2120 reserve_list[i+1], reserve_list[i+2] |
2121 (reserve_list[i+3] << 8))) {
2122 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
2123 hanum, ha->status);
2124 }
2125 }
2126 }
2127
2128 /* Determine OEM string using IOCTL */
2129 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
2130 oemstr->params.ctl_version = 0x01;
2131 oemstr->params.buffer_size = sizeof(oemstr->text);
2132 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2133 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
2134 sizeof(gdth_oem_str_ioctl))) {
2135 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
2136 printk("GDT-HA %d: Vendor: %s Name: %s\n",
2137 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
2138 /* Save the Host Drive inquiry data */
2139 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2140 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
2141 sizeof(ha->oem_name));
2142 #else
2143 strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
2144 ha->oem_name[7] = '\0';
2145 #endif
2146 } else {
2147 /* Old method, based on PCI ID */
2148 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
2149 printk("GDT-HA %d: Name: %s\n",
2150 hanum,ha->binfo.type_string);
2151 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2152 if (ha->oem_id == OEM_ID_INTEL)
2153 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
2154 else
2155 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
2156 #else
2157 if (ha->oem_id == OEM_ID_INTEL)
2158 strcpy(ha->oem_name,"Intel ");
2159 else
2160 strcpy(ha->oem_name,"ICP ");
2161 #endif
2162 }
2163
2164 /* scanning for host drives */
2165 for (i = 0; i < cdev_cnt; ++i)
2166 gdth_analyse_hdrive(hanum,i);
2167
2168 TRACE(("gdth_search_drives() OK\n"));
2169 return 1;
2170 }
2171
2172 static int gdth_analyse_hdrive(int hanum,ushort hdrive)
2173 {
2174 register gdth_ha_str *ha;
2175 ulong32 drv_cyls;
2176 int drv_hds, drv_secs;
2177
2178 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
2179 if (hdrive >= MAX_HDRIVES)
2180 return 0;
2181 ha = HADATA(gdth_ctr_tab[hanum]);
2182
2183 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
2184 return 0;
2185 ha->hdr[hdrive].present = TRUE;
2186 ha->hdr[hdrive].size = ha->info;
2187
2188 /* evaluate mapping (sectors per head, heads per cylinder) */
2189 ha->hdr[hdrive].size &= ~SECS32;
2190 if (ha->info2 == 0) {
2191 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
2192 } else {
2193 drv_hds = ha->info2 & 0xff;
2194 drv_secs = (ha->info2 >> 8) & 0xff;
2195 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
2196 }
2197 ha->hdr[hdrive].heads = (unchar)drv_hds;
2198 ha->hdr[hdrive].secs = (unchar)drv_secs;
2199 /* round size */
2200 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
2201
2202 if (ha->cache_feat & GDT_64BIT) {
2203 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
2204 && ha->info2 != 0) {
2205 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
2206 }
2207 }
2208 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
2209 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
2210
2211 /* get informations about device */
2212 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
2213 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
2214 hdrive,ha->info));
2215 ha->hdr[hdrive].devtype = (ushort)ha->info;
2216 }
2217
2218 /* cluster info */
2219 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
2220 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
2221 hdrive,ha->info));
2222 if (!shared_access)
2223 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
2224 }
2225
2226 /* R/W attributes */
2227 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
2228 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2229 hdrive,ha->info));
2230 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2231 }
2232
2233 return 1;
2234 }
2235
2236
2237 /* command queueing/sending functions */
2238
2239 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2240 {
2241 register gdth_ha_str *ha;
2242 register Scsi_Cmnd *pscp;
2243 register Scsi_Cmnd *nscp;
2244 ulong flags;
2245 unchar b, t;
2246
2247 TRACE(("gdth_putq() priority %d\n",priority));
2248 ha = HADATA(gdth_ctr_tab[hanum]);
2249 spin_lock_irqsave(&ha->smp_lock, flags);
2250
2251 scp->SCp.this_residual = (int)priority;
2252 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
2253 t = scp->device->id;
2254 if (priority >= DEFAULT_PRI) {
2255 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2256 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
2257 TRACE2(("gdth_putq(): locked IO -> update_timeout()\n"));
2258 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2259 }
2260 }
2261
2262 if (ha->req_first==NULL) {
2263 ha->req_first = scp; /* queue was empty */
2264 scp->SCp.ptr = NULL;
2265 } else { /* queue not empty */
2266 pscp = ha->req_first;
2267 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2268 /* priority: 0-highest,..,0xff-lowest */
2269 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2270 pscp = nscp;
2271 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2272 }
2273 pscp->SCp.ptr = (char *)scp;
2274 scp->SCp.ptr = (char *)nscp;
2275 }
2276 spin_unlock_irqrestore(&ha->smp_lock, flags);
2277
2278 #ifdef GDTH_STATISTICS
2279 flags = 0;
2280 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2281 ++flags;
2282 if (max_rq < flags) {
2283 max_rq = flags;
2284 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2285 }
2286 #endif
2287 }
2288
2289 static void gdth_next(int hanum)
2290 {
2291 register gdth_ha_str *ha;
2292 register Scsi_Cmnd *pscp;
2293 register Scsi_Cmnd *nscp;
2294 unchar b, t, l, firsttime;
2295 unchar this_cmd, next_cmd;
2296 ulong flags = 0;
2297 int cmd_index;
2298
2299 TRACE(("gdth_next() hanum %d\n",hanum));
2300 ha = HADATA(gdth_ctr_tab[hanum]);
2301 if (!gdth_polling)
2302 spin_lock_irqsave(&ha->smp_lock, flags);
2303
2304 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2305 this_cmd = firsttime = TRUE;
2306 next_cmd = gdth_polling ? FALSE:TRUE;
2307 cmd_index = 0;
2308
2309 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2310 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2311 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2312 b = virt_ctr ? NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2313 t = nscp->device->id;
2314 l = nscp->device->lun;
2315 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2316 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2317 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2318 continue;
2319 }
2320
2321 if (firsttime) {
2322 if (gdth_test_busy(hanum)) { /* controller busy ? */
2323 TRACE(("gdth_next() controller %d busy !\n",hanum));
2324 if (!gdth_polling) {
2325 spin_unlock_irqrestore(&ha->smp_lock, flags);
2326 return;
2327 }
2328 while (gdth_test_busy(hanum))
2329 gdth_delay(1);
2330 }
2331 firsttime = FALSE;
2332 }
2333
2334 if (nscp->done != gdth_scsi_done || nscp->cmnd[0] != 0xff) {
2335 if (nscp->SCp.phase == -1) {
2336 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2337 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2338 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2339 b, t, l));
2340 /* TEST_UNIT_READY -> set scan mode */
2341 if ((ha->scan_mode & 0x0f) == 0) {
2342 if (b == 0 && t == 0 && l == 0) {
2343 ha->scan_mode |= 1;
2344 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2345 }
2346 } else if ((ha->scan_mode & 0x0f) == 1) {
2347 if (b == 0 && ((t == 0 && l == 1) ||
2348 (t == 1 && l == 0))) {
2349 nscp->SCp.sent_command = GDT_SCAN_START;
2350 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2351 | SCSIRAWSERVICE;
2352 ha->scan_mode = 0x12;
2353 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2354 ha->scan_mode));
2355 } else {
2356 ha->scan_mode &= 0x10;
2357 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2358 }
2359 } else if (ha->scan_mode == 0x12) {
2360 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2361 nscp->SCp.phase = SCSIRAWSERVICE;
2362 nscp->SCp.sent_command = GDT_SCAN_END;
2363 ha->scan_mode &= 0x10;
2364 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2365 ha->scan_mode));
2366 }
2367 }
2368 }
2369 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2370 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2371 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2372 /* always GDT_CLUST_INFO! */
2373 nscp->SCp.sent_command = GDT_CLUST_INFO;
2374 }
2375 }
2376 }
2377
2378 if (nscp->SCp.sent_command != -1) {
2379 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2380 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2381 this_cmd = FALSE;
2382 next_cmd = FALSE;
2383 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2384 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2385 this_cmd = FALSE;
2386 next_cmd = FALSE;
2387 } else {
2388 memset((char*)nscp->sense_buffer,0,16);
2389 nscp->sense_buffer[0] = 0x70;
2390 nscp->sense_buffer[2] = NOT_READY;
2391 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2392 if (!nscp->SCp.have_data_in)
2393 nscp->SCp.have_data_in++;
2394 else
2395 nscp->scsi_done(nscp);
2396 }
2397 } else if (nscp->done == gdth_scsi_done && nscp->cmnd[0] == 0xff) {
2398 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2399 this_cmd = FALSE;
2400 next_cmd = FALSE;
2401 } else if (b != ha->virt_bus) {
2402 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2403 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2404 this_cmd = FALSE;
2405 else
2406 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2407 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2408 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2409 nscp->cmnd[0], b, t, l));
2410 nscp->result = DID_BAD_TARGET << 16;
2411 if (!nscp->SCp.have_data_in)
2412 nscp->SCp.have_data_in++;
2413 else
2414 nscp->scsi_done(nscp);
2415 } else {
2416 switch (nscp->cmnd[0]) {
2417 case TEST_UNIT_READY:
2418 case INQUIRY:
2419 case REQUEST_SENSE:
2420 case READ_CAPACITY:
2421 case VERIFY:
2422 case START_STOP:
2423 case MODE_SENSE:
2424 case SERVICE_ACTION_IN:
2425 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2426 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2427 nscp->cmnd[4],nscp->cmnd[5]));
2428 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2429 /* return UNIT_ATTENTION */
2430 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2431 nscp->cmnd[0], t));
2432 ha->hdr[t].media_changed = FALSE;
2433 memset((char*)nscp->sense_buffer,0,16);
2434 nscp->sense_buffer[0] = 0x70;
2435 nscp->sense_buffer[2] = UNIT_ATTENTION;
2436 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2437 if (!nscp->SCp.have_data_in)
2438 nscp->SCp.have_data_in++;
2439 else
2440 nscp->scsi_done(nscp);
2441 } else if (gdth_internal_cache_cmd(hanum,nscp))
2442 nscp->scsi_done(nscp);
2443 break;
2444
2445 case ALLOW_MEDIUM_REMOVAL:
2446 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2447 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2448 nscp->cmnd[4],nscp->cmnd[5]));
2449 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2450 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2451 nscp->result = DID_OK << 16;
2452 nscp->sense_buffer[0] = 0;
2453 if (!nscp->SCp.have_data_in)
2454 nscp->SCp.have_data_in++;
2455 else
2456 nscp->scsi_done(nscp);
2457 } else {
2458 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2459 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2460 nscp->cmnd[4],nscp->cmnd[3]));
2461 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2462 this_cmd = FALSE;
2463 }
2464 break;
2465
2466 case RESERVE:
2467 case RELEASE:
2468 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2469 "RESERVE" : "RELEASE"));
2470 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2471 this_cmd = FALSE;
2472 break;
2473
2474 case READ_6:
2475 case WRITE_6:
2476 case READ_10:
2477 case WRITE_10:
2478 case READ_16:
2479 case WRITE_16:
2480 if (ha->hdr[t].media_changed) {
2481 /* return UNIT_ATTENTION */
2482 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2483 nscp->cmnd[0], t));
2484 ha->hdr[t].media_changed = FALSE;
2485 memset((char*)nscp->sense_buffer,0,16);
2486 nscp->sense_buffer[0] = 0x70;
2487 nscp->sense_buffer[2] = UNIT_ATTENTION;
2488 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2489 if (!nscp->SCp.have_data_in)
2490 nscp->SCp.have_data_in++;
2491 else
2492 nscp->scsi_done(nscp);
2493 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2494 this_cmd = FALSE;
2495 break;
2496
2497 default:
2498 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2499 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2500 nscp->cmnd[4],nscp->cmnd[5]));
2501 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2502 hanum, nscp->cmnd[0]);
2503 nscp->result = DID_ABORT << 16;
2504 if (!nscp->SCp.have_data_in)
2505 nscp->SCp.have_data_in++;
2506 else
2507 nscp->scsi_done(nscp);
2508 break;
2509 }
2510 }
2511
2512 if (!this_cmd)
2513 break;
2514 if (nscp == ha->req_first)
2515 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2516 else
2517 pscp->SCp.ptr = nscp->SCp.ptr;
2518 if (!next_cmd)
2519 break;
2520 }
2521
2522 if (ha->cmd_cnt > 0) {
2523 gdth_release_event(hanum);
2524 }
2525
2526 if (!gdth_polling)
2527 spin_unlock_irqrestore(&ha->smp_lock, flags);
2528
2529 if (gdth_polling && ha->cmd_cnt > 0) {
2530 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2531 printk("GDT-HA %d: Command %d timed out !\n",
2532 hanum,cmd_index);
2533 }
2534 }
2535
2536 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2537 char *buffer,ushort count)
2538 {
2539 ushort cpcount,i;
2540 ushort cpsum,cpnow;
2541 struct scatterlist *sl;
2542 gdth_ha_str *ha;
2543 char *address;
2544
2545 cpcount = count<=(ushort)scp->bufflen ? count:(ushort)scp->bufflen;
2546 ha = HADATA(gdth_ctr_tab[hanum]);
2547
2548 if (scp->use_sg) {
2549 sl = (struct scatterlist *)scp->request_buffer;
2550 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
2551 unsigned long flags;
2552 cpnow = (ushort)sl->length;
2553 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2554 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2555 if (cpsum+cpnow > cpcount)
2556 cpnow = cpcount - cpsum;
2557 cpsum += cpnow;
2558 if (!sl->page) {
2559 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2560 hanum);
2561 return;
2562 }
2563 local_irq_save(flags);
2564 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2565 memcpy(address,buffer,cpnow);
2566 flush_dcache_page(sl->page);
2567 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2568 local_irq_restore(flags);
2569 if (cpsum == cpcount)
2570 break;
2571 buffer += cpnow;
2572 }
2573 } else {
2574 TRACE(("copy_internal() count %d\n",cpcount));
2575 memcpy((char*)scp->request_buffer,buffer,cpcount);
2576 }
2577 }
2578
2579 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2580 {
2581 register gdth_ha_str *ha;
2582 unchar t;
2583 gdth_inq_data inq;
2584 gdth_rdcap_data rdc;
2585 gdth_sense_data sd;
2586 gdth_modep_data mpd;
2587
2588 ha = HADATA(gdth_ctr_tab[hanum]);
2589 t = scp->device->id;
2590 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2591 scp->cmnd[0],t));
2592
2593 scp->result = DID_OK << 16;
2594 scp->sense_buffer[0] = 0;
2595
2596 switch (scp->cmnd[0]) {
2597 case TEST_UNIT_READY:
2598 case VERIFY:
2599 case START_STOP:
2600 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2601 break;
2602
2603 case INQUIRY:
2604 TRACE2(("Inquiry hdrive %d devtype %d\n",
2605 t,ha->hdr[t].devtype));
2606 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2607 /* you can here set all disks to removable, if you want to do
2608 a flush using the ALLOW_MEDIUM_REMOVAL command */
2609 inq.modif_rmb = 0x00;
2610 if ((ha->hdr[t].devtype & 1) ||
2611 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2612 inq.modif_rmb = 0x80;
2613 inq.version = 2;
2614 inq.resp_aenc = 2;
2615 inq.add_length= 32;
2616 strcpy(inq.vendor,ha->oem_name);
2617 sprintf(inq.product,"Host Drive #%02d",t);
2618 strcpy(inq.revision," ");
2619 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2620 break;
2621
2622 case REQUEST_SENSE:
2623 TRACE2(("Request sense hdrive %d\n",t));
2624 sd.errorcode = 0x70;
2625 sd.segno = 0x00;
2626 sd.key = NO_SENSE;
2627 sd.info = 0;
2628 sd.add_length= 0;
2629 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2630 break;
2631
2632 case MODE_SENSE:
2633 TRACE2(("Mode sense hdrive %d\n",t));
2634 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2635 mpd.hd.data_length = sizeof(gdth_modep_data);
2636 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2637 mpd.hd.bd_length = sizeof(mpd.bd);
2638 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2639 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2640 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2641 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2642 break;
2643
2644 case READ_CAPACITY:
2645 TRACE2(("Read capacity hdrive %d\n",t));
2646 if (ha->hdr[t].size > (ulong64)0xffffffff)
2647 rdc.last_block_no = 0xffffffff;
2648 else
2649 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2650 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2651 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2652 break;
2653
2654 case SERVICE_ACTION_IN:
2655 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2656 (ha->cache_feat & GDT_64BIT)) {
2657 gdth_rdcap16_data rdc16;
2658
2659 TRACE2(("Read capacity (16) hdrive %d\n",t));
2660 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2661 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2662 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2663 } else {
2664 scp->result = DID_ABORT << 16;
2665 }
2666 break;
2667
2668 default:
2669 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2670 break;
2671 }
2672
2673 if (!scp->SCp.have_data_in)
2674 scp->SCp.have_data_in++;
2675 else
2676 return 1;
2677
2678 return 0;
2679 }
2680
2681 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2682 {
2683 register gdth_ha_str *ha;
2684 register gdth_cmd_str *cmdp;
2685 struct scatterlist *sl;
2686 ulong32 cnt, blockcnt;
2687 ulong64 no, blockno;
2688 dma_addr_t phys_addr;
2689 int i, cmd_index, read_write, sgcnt, mode64;
2690 struct page *page;
2691 ulong offset;
2692
2693 ha = HADATA(gdth_ctr_tab[hanum]);
2694 cmdp = ha->pccb;
2695 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2696 scp->cmnd[0],scp->cmd_len,hdrive));
2697
2698 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2699 return 0;
2700
2701 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2702 /* test for READ_16, WRITE_16 if !mode64 ? ---
2703 not required, should not occur due to error return on
2704 READ_CAPACITY_16 */
2705
2706 cmdp->Service = CACHESERVICE;
2707 cmdp->RequestBuffer = scp;
2708 /* search free command index */
2709 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2710 TRACE(("GDT: No free command index found\n"));
2711 return 0;
2712 }
2713 /* if it's the first command, set command semaphore */
2714 if (ha->cmd_cnt == 0)
2715 gdth_set_sema0(hanum);
2716
2717 /* fill command */
2718 read_write = 0;
2719 if (scp->SCp.sent_command != -1)
2720 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2721 else if (scp->cmnd[0] == RESERVE)
2722 cmdp->OpCode = GDT_RESERVE_DRV;
2723 else if (scp->cmnd[0] == RELEASE)
2724 cmdp->OpCode = GDT_RELEASE_DRV;
2725 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2726 if (scp->cmnd[4] & 1) /* prevent ? */
2727 cmdp->OpCode = GDT_MOUNT;
2728 else if (scp->cmnd[3] & 1) /* removable drive ? */
2729 cmdp->OpCode = GDT_UNMOUNT;
2730 else
2731 cmdp->OpCode = GDT_FLUSH;
2732 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2733 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2734 ) {
2735 read_write = 1;
2736 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2737 (ha->cache_feat & GDT_WR_THROUGH)))
2738 cmdp->OpCode = GDT_WRITE_THR;
2739 else
2740 cmdp->OpCode = GDT_WRITE;
2741 } else {
2742 read_write = 2;
2743 cmdp->OpCode = GDT_READ;
2744 }
2745
2746 cmdp->BoardNode = LOCALBOARD;
2747 if (mode64) {
2748 cmdp->u.cache64.DeviceNo = hdrive;
2749 cmdp->u.cache64.BlockNo = 1;
2750 cmdp->u.cache64.sg_canz = 0;
2751 } else {
2752 cmdp->u.cache.DeviceNo = hdrive;
2753 cmdp->u.cache.BlockNo = 1;
2754 cmdp->u.cache.sg_canz = 0;
2755 }
2756
2757 if (read_write) {
2758 if (scp->cmd_len == 16) {
2759 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2760 blockno = be64_to_cpu(no);
2761 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2762 blockcnt = be32_to_cpu(cnt);
2763 } else if (scp->cmd_len == 10) {
2764 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2765 blockno = be32_to_cpu(no);
2766 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2767 blockcnt = be16_to_cpu(cnt);
2768 } else {
2769 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2770 blockno = be32_to_cpu(no) & 0x001fffffUL;
2771 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2772 }
2773 if (mode64) {
2774 cmdp->u.cache64.BlockNo = blockno;
2775 cmdp->u.cache64.BlockCnt = blockcnt;
2776 } else {
2777 cmdp->u.cache.BlockNo = (ulong32)blockno;
2778 cmdp->u.cache.BlockCnt = blockcnt;
2779 }
2780
2781 if (scp->use_sg) {
2782 sl = (struct scatterlist *)scp->request_buffer;
2783 sgcnt = scp->use_sg;
2784 scp->SCp.Status = GDTH_MAP_SG;
2785 scp->SCp.Message = (read_write == 1 ?
2786 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2787 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2788 if (mode64) {
2789 cmdp->u.cache64.DestAddr= (ulong64)-1;
2790 cmdp->u.cache64.sg_canz = sgcnt;
2791 for (i=0; i<sgcnt; ++i,++sl) {
2792 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2793 #ifdef GDTH_DMA_STATISTICS
2794 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2795 ha->dma64_cnt++;
2796 else
2797 ha->dma32_cnt++;
2798 #endif
2799 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2800 }
2801 } else {
2802 cmdp->u.cache.DestAddr= 0xffffffff;
2803 cmdp->u.cache.sg_canz = sgcnt;
2804 for (i=0; i<sgcnt; ++i,++sl) {
2805 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2806 #ifdef GDTH_DMA_STATISTICS
2807 ha->dma32_cnt++;
2808 #endif
2809 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2810 }
2811 }
2812
2813 #ifdef GDTH_STATISTICS
2814 if (max_sg < (ulong32)sgcnt) {
2815 max_sg = (ulong32)sgcnt;
2816 TRACE3(("GDT: max_sg = %d\n",max_sg));
2817 }
2818 #endif
2819
2820 } else if (scp->request_bufflen) {
2821 scp->SCp.Status = GDTH_MAP_SINGLE;
2822 scp->SCp.Message = (read_write == 1 ?
2823 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2824 page = virt_to_page(scp->request_buffer);
2825 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2826 phys_addr = pci_map_page(ha->pdev,page,offset,
2827 scp->request_bufflen,scp->SCp.Message);
2828 scp->SCp.dma_handle = phys_addr;
2829 if (mode64) {
2830 if (ha->cache_feat & SCATTER_GATHER) {
2831 cmdp->u.cache64.DestAddr = (ulong64)-1;
2832 cmdp->u.cache64.sg_canz = 1;
2833 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2834 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2835 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2836 } else {
2837 cmdp->u.cache64.DestAddr = phys_addr;
2838 cmdp->u.cache64.sg_canz= 0;
2839 }
2840 } else {
2841 if (ha->cache_feat & SCATTER_GATHER) {
2842 cmdp->u.cache.DestAddr = 0xffffffff;
2843 cmdp->u.cache.sg_canz = 1;
2844 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2845 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2846 cmdp->u.cache.sg_lst[1].sg_len = 0;
2847 } else {
2848 cmdp->u.cache.DestAddr = phys_addr;
2849 cmdp->u.cache.sg_canz= 0;
2850 }
2851 }
2852 }
2853 }
2854 /* evaluate command size, check space */
2855 if (mode64) {
2856 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2857 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2858 cmdp->u.cache64.sg_lst[0].sg_ptr,
2859 cmdp->u.cache64.sg_lst[0].sg_len));
2860 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2861 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2862 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2863 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2864 } else {
2865 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2866 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2867 cmdp->u.cache.sg_lst[0].sg_ptr,
2868 cmdp->u.cache.sg_lst[0].sg_len));
2869 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2870 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2871 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2872 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2873 }
2874 if (ha->cmd_len & 3)
2875 ha->cmd_len += (4 - (ha->cmd_len & 3));
2876
2877 if (ha->cmd_cnt > 0) {
2878 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2879 ha->ic_all_size) {
2880 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2881 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2882 return 0;
2883 }
2884 }
2885
2886 /* copy command */
2887 gdth_copy_command(hanum);
2888 return cmd_index;
2889 }
2890
2891 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
2892 {
2893 register gdth_ha_str *ha;
2894 register gdth_cmd_str *cmdp;
2895 struct scatterlist *sl;
2896 ushort i;
2897 dma_addr_t phys_addr, sense_paddr;
2898 int cmd_index, sgcnt, mode64;
2899 unchar t,l;
2900 struct page *page;
2901 ulong offset;
2902
2903 ha = HADATA(gdth_ctr_tab[hanum]);
2904 t = scp->device->id;
2905 l = scp->device->lun;
2906 cmdp = ha->pccb;
2907 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2908 scp->cmnd[0],b,t,l));
2909
2910 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2911 return 0;
2912
2913 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2914
2915 cmdp->Service = SCSIRAWSERVICE;
2916 cmdp->RequestBuffer = scp;
2917 /* search free command index */
2918 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2919 TRACE(("GDT: No free command index found\n"));
2920 return 0;
2921 }
2922 /* if it's the first command, set command semaphore */
2923 if (ha->cmd_cnt == 0)
2924 gdth_set_sema0(hanum);
2925
2926 /* fill command */
2927 if (scp->SCp.sent_command != -1) {
2928 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
2929 cmdp->BoardNode = LOCALBOARD;
2930 if (mode64) {
2931 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
2932 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2933 cmdp->OpCode, cmdp->u.raw64.direction));
2934 /* evaluate command size */
2935 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2936 } else {
2937 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
2938 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2939 cmdp->OpCode, cmdp->u.raw.direction));
2940 /* evaluate command size */
2941 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2942 }
2943
2944 } else {
2945 page = virt_to_page(scp->sense_buffer);
2946 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
2947 sense_paddr = pci_map_page(ha->pdev,page,offset,
2948 16,PCI_DMA_FROMDEVICE);
2949 scp->SCp.buffer = (struct scatterlist *)((ulong32)sense_paddr);
2950 /* high part, if 64bit */
2951 scp->host_scribble = (char *)(ulong32)((ulong64)sense_paddr >> 32);
2952 cmdp->OpCode = GDT_WRITE; /* always */
2953 cmdp->BoardNode = LOCALBOARD;
2954 if (mode64) {
2955 cmdp->u.raw64.reserved = 0;
2956 cmdp->u.raw64.mdisc_time = 0;
2957 cmdp->u.raw64.mcon_time = 0;
2958 cmdp->u.raw64.clen = scp->cmd_len;
2959 cmdp->u.raw64.target = t;
2960 cmdp->u.raw64.lun = l;
2961 cmdp->u.raw64.bus = b;
2962 cmdp->u.raw64.priority = 0;
2963 cmdp->u.raw64.sdlen = scp->request_bufflen;
2964 cmdp->u.raw64.sense_len = 16;
2965 cmdp->u.raw64.sense_data = sense_paddr;
2966 cmdp->u.raw64.direction =
2967 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2968 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
2969 } else {
2970 cmdp->u.raw.reserved = 0;
2971 cmdp->u.raw.mdisc_time = 0;
2972 cmdp->u.raw.mcon_time = 0;
2973 cmdp->u.raw.clen = scp->cmd_len;
2974 cmdp->u.raw.target = t;
2975 cmdp->u.raw.lun = l;
2976 cmdp->u.raw.bus = b;
2977 cmdp->u.raw.priority = 0;
2978 cmdp->u.raw.link_p = 0;
2979 cmdp->u.raw.sdlen = scp->request_bufflen;
2980 cmdp->u.raw.sense_len = 16;
2981 cmdp->u.raw.sense_data = sense_paddr;
2982 cmdp->u.raw.direction =
2983 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2984 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
2985 }
2986
2987 if (scp->use_sg) {
2988 sl = (struct scatterlist *)scp->request_buffer;
2989 sgcnt = scp->use_sg;
2990 scp->SCp.Status = GDTH_MAP_SG;
2991 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
2992 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2993 if (mode64) {
2994 cmdp->u.raw64.sdata = (ulong64)-1;
2995 cmdp->u.raw64.sg_ranz = sgcnt;
2996 for (i=0; i<sgcnt; ++i,++sl) {
2997 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2998 #ifdef GDTH_DMA_STATISTICS
2999 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
3000 ha->dma64_cnt++;
3001 else
3002 ha->dma32_cnt++;
3003 #endif
3004 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
3005 }
3006 } else {
3007 cmdp->u.raw.sdata = 0xffffffff;
3008 cmdp->u.raw.sg_ranz = sgcnt;
3009 for (i=0; i<sgcnt; ++i,++sl) {
3010 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
3011 #ifdef GDTH_DMA_STATISTICS
3012 ha->dma32_cnt++;
3013 #endif
3014 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
3015 }
3016 }
3017
3018 #ifdef GDTH_STATISTICS
3019 if (max_sg < sgcnt) {
3020 max_sg = sgcnt;
3021 TRACE3(("GDT: max_sg = %d\n",sgcnt));
3022 }
3023 #endif
3024
3025 } else {
3026 scp->SCp.Status = GDTH_MAP_SINGLE;
3027 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3028 page = virt_to_page(scp->request_buffer);
3029 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
3030 phys_addr = pci_map_page(ha->pdev,page,offset,
3031 scp->request_bufflen,scp->SCp.Message);
3032 scp->SCp.dma_handle = phys_addr;
3033
3034 if (mode64) {
3035 if (ha->raw_feat & SCATTER_GATHER) {
3036 cmdp->u.raw64.sdata = (ulong64)-1;
3037 cmdp->u.raw64.sg_ranz= 1;
3038 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
3039 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
3040 cmdp->u.raw64.sg_lst[1].sg_len = 0;
3041 } else {
3042 cmdp->u.raw64.sdata = phys_addr;
3043 cmdp->u.raw64.sg_ranz= 0;
3044 }
3045 } else {
3046 if (ha->raw_feat & SCATTER_GATHER) {
3047 cmdp->u.raw.sdata = 0xffffffff;
3048 cmdp->u.raw.sg_ranz= 1;
3049 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
3050 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
3051 cmdp->u.raw.sg_lst[1].sg_len = 0;
3052 } else {
3053 cmdp->u.raw.sdata = phys_addr;
3054 cmdp->u.raw.sg_ranz= 0;
3055 }
3056 }
3057 }
3058 if (mode64) {
3059 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3060 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
3061 cmdp->u.raw64.sg_lst[0].sg_ptr,
3062 cmdp->u.raw64.sg_lst[0].sg_len));
3063 /* evaluate command size */
3064 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
3065 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
3066 } else {
3067 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3068 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
3069 cmdp->u.raw.sg_lst[0].sg_ptr,
3070 cmdp->u.raw.sg_lst[0].sg_len));
3071 /* evaluate command size */
3072 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
3073 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
3074 }
3075 }
3076 /* check space */
3077 if (ha->cmd_len & 3)
3078 ha->cmd_len += (4 - (ha->cmd_len & 3));
3079
3080 if (ha->cmd_cnt > 0) {
3081 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3082 ha->ic_all_size) {
3083 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
3084 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3085 return 0;
3086 }
3087 }
3088
3089 /* copy command */
3090 gdth_copy_command(hanum);
3091 return cmd_index;
3092 }
3093
3094 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
3095 {
3096 register gdth_ha_str *ha;
3097 register gdth_cmd_str *cmdp;
3098 int cmd_index;
3099
3100 ha = HADATA(gdth_ctr_tab[hanum]);
3101 cmdp= ha->pccb;
3102 TRACE2(("gdth_special_cmd(): "));
3103
3104 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3105 return 0;
3106
3107 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
3108 cmdp->RequestBuffer = scp;
3109
3110 /* search free command index */
3111 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3112 TRACE(("GDT: No free command index found\n"));
3113 return 0;
3114 }
3115
3116 /* if it's the first command, set command semaphore */
3117 if (ha->cmd_cnt == 0)
3118 gdth_set_sema0(hanum);
3119
3120 /* evaluate command size, check space */
3121 if (cmdp->OpCode == GDT_IOCTL) {
3122 TRACE2(("IOCTL\n"));
3123 ha->cmd_len =
3124 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
3125 } else if (cmdp->Service == CACHESERVICE) {
3126 TRACE2(("cache command %d\n",cmdp->OpCode));
3127 if (ha->cache_feat & GDT_64BIT)
3128 ha->cmd_len =
3129 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
3130 else
3131 ha->cmd_len =
3132 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
3133 } else if (cmdp->Service == SCSIRAWSERVICE) {
3134 TRACE2(("raw command %d\n",cmdp->OpCode));
3135 if (ha->raw_feat & GDT_64BIT)
3136 ha->cmd_len =
3137 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
3138 else
3139 ha->cmd_len =
3140 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
3141 }
3142
3143 if (ha->cmd_len & 3)
3144 ha->cmd_len += (4 - (ha->cmd_len & 3));
3145
3146 if (ha->cmd_cnt > 0) {
3147 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3148 ha->ic_all_size) {
3149 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
3150 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3151 return 0;
3152 }
3153 }
3154
3155 /* copy command */
3156 gdth_copy_command(hanum);
3157 return cmd_index;
3158 }
3159
3160
3161 /* Controller event handling functions */
3162 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
3163 ushort idx, gdth_evt_data *evt)
3164 {
3165 gdth_evt_str *e;
3166 struct timeval tv;
3167
3168 /* no GDTH_LOCK_HA() ! */
3169 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
3170 if (source == 0) /* no source -> no event */
3171 return NULL;
3172
3173 if (ebuffer[elastidx].event_source == source &&
3174 ebuffer[elastidx].event_idx == idx &&
3175 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
3176 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
3177 (char *)&evt->eu, evt->size)) ||
3178 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
3179 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
3180 (char *)&evt->event_string)))) {
3181 e = &ebuffer[elastidx];
3182 do_gettimeofday(&tv);
3183 e->last_stamp = tv.tv_sec;
3184 ++e->same_count;
3185 } else {
3186 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
3187 ++elastidx;
3188 if (elastidx == MAX_EVENTS)
3189 elastidx = 0;
3190 if (elastidx == eoldidx) { /* reached mark ? */
3191 ++eoldidx;
3192 if (eoldidx == MAX_EVENTS)
3193 eoldidx = 0;
3194 }
3195 }
3196 e = &ebuffer[elastidx];
3197 e->event_source = source;
3198 e->event_idx = idx;
3199 do_gettimeofday(&tv);
3200 e->first_stamp = e->last_stamp = tv.tv_sec;
3201 e->same_count = 1;
3202 e->event_data = *evt;
3203 e->application = 0;
3204 }
3205 return e;
3206 }
3207
3208 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
3209 {
3210 gdth_evt_str *e;
3211 int eindex;
3212 ulong flags;
3213
3214 TRACE2(("gdth_read_event() handle %d\n", handle));
3215 spin_lock_irqsave(&ha->smp_lock, flags);
3216 if (handle == -1)
3217 eindex = eoldidx;
3218 else
3219 eindex = handle;
3220 estr->event_source = 0;
3221
3222 if (eindex >= MAX_EVENTS) {
3223 spin_unlock_irqrestore(&ha->smp_lock, flags);
3224 return eindex;
3225 }
3226 e = &ebuffer[eindex];
3227 if (e->event_source != 0) {
3228 if (eindex != elastidx) {
3229 if (++eindex == MAX_EVENTS)
3230 eindex = 0;
3231 } else {
3232 eindex = -1;
3233 }
3234 memcpy(estr, e, sizeof(gdth_evt_str));
3235 }
3236 spin_unlock_irqrestore(&ha->smp_lock, flags);
3237 return eindex;
3238 }
3239
3240 static void gdth_readapp_event(gdth_ha_str *ha,
3241 unchar application, gdth_evt_str *estr)
3242 {
3243 gdth_evt_str *e;
3244 int eindex;
3245 ulong flags;
3246 unchar found = FALSE;
3247
3248 TRACE2(("gdth_readapp_event() app. %d\n", application));
3249 spin_lock_irqsave(&ha->smp_lock, flags);
3250 eindex = eoldidx;
3251 for (;;) {
3252 e = &ebuffer[eindex];
3253 if (e->event_source == 0)
3254 break;
3255 if ((e->application & application) == 0) {
3256 e->application |= application;
3257 found = TRUE;
3258 break;
3259 }
3260 if (eindex == elastidx)
3261 break;
3262 if (++eindex == MAX_EVENTS)
3263 eindex = 0;
3264 }
3265 if (found)
3266 memcpy(estr, e, sizeof(gdth_evt_str));
3267 else
3268 estr->event_source = 0;
3269 spin_unlock_irqrestore(&ha->smp_lock, flags);
3270 }
3271
3272 static void gdth_clear_events(void)
3273 {
3274 TRACE(("gdth_clear_events()"));
3275
3276 eoldidx = elastidx = 0;
3277 ebuffer[0].event_source = 0;
3278 }
3279
3280
3281 /* SCSI interface functions */
3282
3283 static irqreturn_t gdth_interrupt(int irq,void *dev_id,struct pt_regs *regs)
3284 {
3285 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3286 register gdth_ha_str *ha;
3287 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3288 gdt6_dpram_str __iomem *dp6_ptr;
3289 gdt2_dpram_str __iomem *dp2_ptr;
3290 Scsi_Cmnd *scp;
3291 int hanum, rval, i;
3292 unchar IStatus;
3293 ushort Service;
3294 ulong flags = 0;
3295 #ifdef INT_COAL
3296 int coalesced = FALSE;
3297 int next = FALSE;
3298 gdth_coal_status *pcs = NULL;
3299 int act_int_coal = 0;
3300 #endif
3301
3302 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3303
3304 /* if polling and not from gdth_wait() -> return */
3305 if (gdth_polling) {
3306 if (!gdth_from_wait) {
3307 return IRQ_HANDLED;
3308 }
3309 }
3310
3311 if (!gdth_polling)
3312 spin_lock_irqsave(&ha2->smp_lock, flags);
3313 wait_index = 0;
3314
3315 /* search controller */
3316 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3317 /* spurious interrupt */
3318 if (!gdth_polling)
3319 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3320 return IRQ_HANDLED;
3321 }
3322 ha = HADATA(gdth_ctr_tab[hanum]);
3323
3324 #ifdef GDTH_STATISTICS
3325 ++act_ints;
3326 #endif
3327
3328 #ifdef INT_COAL
3329 /* See if the fw is returning coalesced status */
3330 if (IStatus == COALINDEX) {
3331 /* Coalesced status. Setup the initial status
3332 buffer pointer and flags */
3333 pcs = ha->coal_stat;
3334 coalesced = TRUE;
3335 next = TRUE;
3336 }
3337
3338 do {
3339 if (coalesced) {
3340 /* For coalesced requests all status
3341 information is found in the status buffer */
3342 IStatus = (unchar)(pcs->status & 0xff);
3343 }
3344 #endif
3345
3346 if (ha->type == GDT_EISA) {
3347 if (IStatus & 0x80) { /* error flag */
3348 IStatus &= ~0x80;
3349 ha->status = inw(ha->bmic + MAILBOXREG+8);
3350 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3351 } else /* no error */
3352 ha->status = S_OK;
3353 ha->info = inl(ha->bmic + MAILBOXREG+12);
3354 ha->service = inw(ha->bmic + MAILBOXREG+10);
3355 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3356
3357 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3358 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3359 } else if (ha->type == GDT_ISA) {
3360 dp2_ptr = ha->brd;
3361 if (IStatus & 0x80) { /* error flag */
3362 IStatus &= ~0x80;
3363 ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
3364 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3365 } else /* no error */
3366 ha->status = S_OK;
3367 ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
3368 ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
3369 ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
3370
3371 gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3372 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3373 gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3374 } else if (ha->type == GDT_PCI) {
3375 dp6_ptr = ha->brd;
3376 if (IStatus & 0x80) { /* error flag */
3377 IStatus &= ~0x80;
3378 ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
3379 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3380 } else /* no error */
3381 ha->status = S_OK;
3382 ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
3383 ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
3384 ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
3385
3386 gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3387 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3388 gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3389 } else if (ha->type == GDT_PCINEW) {
3390 if (IStatus & 0x80) { /* error flag */
3391 IStatus &= ~0x80;
3392 ha->status = inw(PTR2USHORT(&ha->plx->status));
3393 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3394 } else
3395 ha->status = S_OK;
3396 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3397 ha->service = inw(PTR2USHORT(&ha->plx->service));
3398 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3399
3400 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3401 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3402 } else if (ha->type == GDT_PCIMPR) {
3403 dp6m_ptr = ha->brd;
3404 if (IStatus & 0x80) { /* error flag */
3405 IStatus &= ~0x80;
3406 #ifdef INT_COAL
3407 if (coalesced)
3408 ha->status = pcs->ext_status && 0xffff;
3409 else
3410 #endif
3411 ha->status = gdth_readw(&dp6m_ptr->i960r.status);
3412 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3413 } else /* no error */
3414 ha->status = S_OK;
3415 #ifdef INT_COAL
3416 /* get information */
3417 if (coalesced) {
3418 ha->info = pcs->info0;
3419 ha->info2 = pcs->info1;
3420 ha->service = (pcs->ext_status >> 16) && 0xffff;
3421 } else
3422 #endif
3423 {
3424 ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
3425 ha->service = gdth_readw(&dp6m_ptr->i960r.service);
3426 ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
3427 }
3428 /* event string */
3429 if (IStatus == ASYNCINDEX) {
3430 if (ha->service != SCREENSERVICE &&
3431 (ha->fw_vers & 0xff) >= 0x1a) {
3432 ha->dvr.severity = gdth_readb
3433 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3434 for (i = 0; i < 256; ++i) {
3435 ha->dvr.event_string[i] = gdth_readb
3436 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3437 if (ha->dvr.event_string[i] == 0)
3438 break;
3439 }
3440 }
3441 }
3442 #ifdef INT_COAL
3443 /* Make sure that non coalesced interrupts get cleared
3444 before being handled by gdth_async_event/gdth_sync_event */
3445 if (!coalesced)
3446 #endif
3447 {
3448 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3449 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3450 }
3451 } else {
3452 TRACE2(("gdth_interrupt() unknown controller type\n"));
3453 if (!gdth_polling)
3454 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3455 return IRQ_HANDLED;
3456 }
3457
3458 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3459 IStatus,ha->status,ha->info));
3460
3461 if (gdth_from_wait) {
3462 wait_hanum = hanum;
3463 wait_index = (int)IStatus;
3464 }
3465
3466 if (IStatus == ASYNCINDEX) {
3467 TRACE2(("gdth_interrupt() async. event\n"));
3468 gdth_async_event(hanum);
3469 if (!gdth_polling)
3470 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3471 gdth_next(hanum);
3472 return IRQ_HANDLED;
3473 }
3474
3475 if (IStatus == SPEZINDEX) {
3476 TRACE2(("Service unknown or not initialized !\n"));
3477 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3478 ha->dvr.eu.driver.ionode = hanum;
3479 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3480 if (!gdth_polling)
3481 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3482 return IRQ_HANDLED;
3483 }
3484 scp = ha->cmd_tab[IStatus-2].cmnd;
3485 Service = ha->cmd_tab[IStatus-2].service;
3486 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3487 if (scp == UNUSED_CMND) {
3488 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3489 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3490 ha->dvr.eu.driver.ionode = hanum;
3491 ha->dvr.eu.driver.index = IStatus;
3492 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3493 if (!gdth_polling)
3494 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3495 return IRQ_HANDLED;
3496 }
3497 if (scp == INTERNAL_CMND) {
3498 TRACE(("gdth_interrupt() answer to internal command\n"));
3499 if (!gdth_polling)
3500 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3501 return IRQ_HANDLED;
3502 }
3503
3504 TRACE(("gdth_interrupt() sync. status\n"));
3505 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3506 if (!gdth_polling)
3507 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3508 if (rval == 2) {
3509 gdth_putq(hanum,scp,scp->SCp.this_residual);
3510 } else if (rval == 1) {
3511 scp->scsi_done(scp);
3512 }
3513
3514 #ifdef INT_COAL
3515 if (coalesced) {
3516 /* go to the next status in the status buffer */
3517 ++pcs;
3518 #ifdef GDTH_STATISTICS
3519 ++act_int_coal;
3520 if (act_int_coal > max_int_coal) {
3521 max_int_coal = act_int_coal;
3522 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3523 }
3524 #endif
3525 /* see if there is another status */
3526 if (pcs->status == 0)
3527 /* Stop the coalesce loop */
3528 next = FALSE;
3529 }
3530 } while (next);
3531
3532 /* coalescing only for new GDT_PCIMPR controllers available */
3533 if (ha->type == GDT_PCIMPR && coalesced) {
3534 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3535 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3536 }
3537 #endif
3538
3539 gdth_next(hanum);
3540 return IRQ_HANDLED;
3541 }
3542
3543 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3544 {
3545 register gdth_ha_str *ha;
3546 gdth_msg_str *msg;
3547 gdth_cmd_str *cmdp;
3548 unchar b, t;
3549
3550 ha = HADATA(gdth_ctr_tab[hanum]);
3551 cmdp = ha->pccb;
3552 TRACE(("gdth_sync_event() serv %d status %d\n",
3553 service,ha->status));
3554
3555 if (service == SCREENSERVICE) {
3556 msg = ha->pmsg;
3557 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3558 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3559 if (msg->msg_len > MSGLEN+1)
3560 msg->msg_len = MSGLEN+1;
3561 if (msg->msg_len)
3562 if (!(msg->msg_answer && msg->msg_ext)) {
3563 msg->msg_text[msg->msg_len] = '\0';
3564 printk("%s",msg->msg_text);
3565 }
3566
3567 if (msg->msg_ext && !msg->msg_answer) {
3568 while (gdth_test_busy(hanum))
3569 gdth_delay(0);
3570 cmdp->Service = SCREENSERVICE;
3571 cmdp->RequestBuffer = SCREEN_CMND;
3572 gdth_get_cmd_index(hanum);
3573 gdth_set_sema0(hanum);
3574 cmdp->OpCode = GDT_READ;
3575 cmdp->BoardNode = LOCALBOARD;
3576 cmdp->u.screen.reserved = 0;
3577 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3578 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3579 ha->cmd_offs_dpmem = 0;
3580 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3581 + sizeof(ulong64);
3582 ha->cmd_cnt = 0;
3583 gdth_copy_command(hanum);
3584 gdth_release_event(hanum);
3585 return 0;
3586 }
3587
3588 if (msg->msg_answer && msg->msg_alen) {
3589 /* default answers (getchar() not possible) */
3590 if (msg->msg_alen == 1) {
3591 msg->msg_alen = 0;
3592 msg->msg_len = 1;
3593 msg->msg_text[0] = 0;
3594 } else {
3595 msg->msg_alen -= 2;
3596 msg->msg_len = 2;
3597 msg->msg_text[0] = 1;
3598 msg->msg_text[1] = 0;
3599 }
3600 msg->msg_ext = 0;
3601 msg->msg_answer = 0;
3602 while (gdth_test_busy(hanum))
3603 gdth_delay(0);
3604 cmdp->Service = SCREENSERVICE;
3605 cmdp->RequestBuffer = SCREEN_CMND;
3606 gdth_get_cmd_index(hanum);
3607 gdth_set_sema0(hanum);
3608 cmdp->OpCode = GDT_WRITE;
3609 cmdp->BoardNode = LOCALBOARD;
3610 cmdp->u.screen.reserved = 0;
3611 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3612 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3613 ha->cmd_offs_dpmem = 0;
3614 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3615 + sizeof(ulong64);
3616 ha->cmd_cnt = 0;
3617 gdth_copy_command(hanum);
3618 gdth_release_event(hanum);
3619 return 0;
3620 }
3621 printk("\n");
3622
3623 } else {
3624 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3625 t = scp->device->id;
3626 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3627 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3628 }
3629 /* cache or raw service */
3630 if (ha->status == S_BSY) {
3631 TRACE2(("Controller busy -> retry !\n"));
3632 if (scp->SCp.sent_command == GDT_MOUNT)
3633 scp->SCp.sent_command = GDT_CLUST_INFO;
3634 /* retry */
3635 return 2;
3636 }
3637 if (scp->SCp.Status == GDTH_MAP_SG)
3638 pci_unmap_sg(ha->pdev,scp->request_buffer,
3639 scp->use_sg,scp->SCp.Message);
3640 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3641 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3642 scp->request_bufflen,scp->SCp.Message);
3643 if (scp->SCp.buffer) {
3644 dma_addr_t addr;
3645 addr = (dma_addr_t)(ulong32)scp->SCp.buffer;
3646 if (scp->host_scribble)
3647 addr += (dma_addr_t)((ulong64)(ulong32)scp->host_scribble << 32);
3648 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3649 }
3650
3651 if (ha->status == S_OK) {
3652 scp->SCp.Status = S_OK;
3653 scp->SCp.Message = ha->info;
3654 if (scp->SCp.sent_command != -1) {
3655 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3656 scp->SCp.sent_command));
3657 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3658 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3659 ha->hdr[t].cluster_type = (unchar)ha->info;
3660 if (!(ha->hdr[t].cluster_type &
3661 CLUSTER_MOUNTED)) {
3662 /* NOT MOUNTED -> MOUNT */
3663 scp->SCp.sent_command = GDT_MOUNT;
3664 if (ha->hdr[t].cluster_type &
3665 CLUSTER_RESERVED) {
3666 /* cluster drive RESERVED (on the other node) */
3667 scp->SCp.phase = -2; /* reservation conflict */
3668 }
3669 } else {
3670 scp->SCp.sent_command = -1;
3671 }
3672 } else {
3673 if (scp->SCp.sent_command == GDT_MOUNT) {
3674 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3675 ha->hdr[t].media_changed = TRUE;
3676 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3677 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3678 ha->hdr[t].media_changed = TRUE;
3679 }
3680 scp->SCp.sent_command = -1;
3681 }
3682 /* retry */
3683 scp->SCp.this_residual = HIGH_PRI;
3684 return 2;
3685 } else {
3686 /* RESERVE/RELEASE ? */
3687 if (scp->cmnd[0] == RESERVE) {
3688 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3689 } else if (scp->cmnd[0] == RELEASE) {
3690 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3691 }
3692 scp->result = DID_OK << 16;
3693 scp->sense_buffer[0] = 0;
3694 }
3695 } else {
3696 scp->SCp.Status = ha->status;
3697 scp->SCp.Message = ha->info;
3698
3699 if (scp->SCp.sent_command != -1) {
3700 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3701 scp->SCp.sent_command, ha->status));
3702 if (scp->SCp.sent_command == GDT_SCAN_START ||
3703 scp->SCp.sent_command == GDT_SCAN_END) {
3704 scp->SCp.sent_command = -1;
3705 /* retry */
3706 scp->SCp.this_residual = HIGH_PRI;
3707 return 2;
3708 }
3709 memset((char*)scp->sense_buffer,0,16);
3710 scp->sense_buffer[0] = 0x70;
3711 scp->sense_buffer[2] = NOT_READY;
3712 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3713 } else if (service == CACHESERVICE) {
3714 if (ha->status == S_CACHE_UNKNOWN &&
3715 (ha->hdr[t].cluster_type &
3716 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3717 /* bus reset -> force GDT_CLUST_INFO */
3718 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3719 }
3720 memset((char*)scp->sense_buffer,0,16);
3721 if (ha->status == (ushort)S_CACHE_RESERV) {
3722 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3723 } else {
3724 scp->sense_buffer[0] = 0x70;
3725 scp->sense_buffer[2] = NOT_READY;
3726 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3727 }
3728 if (scp->done != gdth_scsi_done) {
3729 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3730 ha->dvr.eu.sync.ionode = hanum;
3731 ha->dvr.eu.sync.service = service;
3732 ha->dvr.eu.sync.status = ha->status;
3733 ha->dvr.eu.sync.info = ha->info;
3734 ha->dvr.eu.sync.hostdrive = t;
3735 if (ha->status >= 0x8000)
3736 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3737 else
3738 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3739 }
3740 } else {
3741 /* sense buffer filled from controller firmware (DMA) */
3742 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3743 scp->result = DID_BAD_TARGET << 16;
3744 } else {
3745 scp->result = (DID_OK << 16) | ha->info;
3746 }
3747 }
3748 }
3749 if (!scp->SCp.have_data_in)
3750 scp->SCp.have_data_in++;
3751 else
3752 return 1;
3753 }
3754
3755 return 0;
3756 }
3757
3758 static char *async_cache_tab[] = {
3759 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3760 "GDT HA %u, service %u, async. status %u/%lu unknown",
3761 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3762 "GDT HA %u, service %u, async. status %u/%lu unknown",
3763 /* 2*/ "\005\000\002\006\004"
3764 "GDT HA %u, Host Drive %lu not ready",
3765 /* 3*/ "\005\000\002\006\004"
3766 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3767 /* 4*/ "\005\000\002\006\004"
3768 "GDT HA %u, mirror update on Host Drive %lu failed",
3769 /* 5*/ "\005\000\002\006\004"
3770 "GDT HA %u, Mirror Drive %lu failed",
3771 /* 6*/ "\005\000\002\006\004"
3772 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3773 /* 7*/ "\005\000\002\006\004"
3774 "GDT HA %u, Host Drive %lu write protected",
3775 /* 8*/ "\005\000\002\006\004"
3776 "GDT HA %u, media changed in Host Drive %lu",
3777 /* 9*/ "\005\000\002\006\004"
3778 "GDT HA %u, Host Drive %lu is offline",
3779 /*10*/ "\005\000\002\006\004"
3780 "GDT HA %u, media change of Mirror Drive %lu",
3781 /*11*/ "\005\000\002\006\004"
3782 "GDT HA %u, Mirror Drive %lu is write protected",
3783 /*12*/ "\005\000\002\006\004"
3784 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3785 /*13*/ "\007\000\002\006\002\010\002"
3786 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3787 /*14*/ "\005\000\002\006\002"
3788 "GDT HA %u, Array Drive %u: FAIL state entered",
3789 /*15*/ "\005\000\002\006\002"
3790 "GDT HA %u, Array Drive %u: error",
3791 /*16*/ "\007\000\002\006\002\010\002"
3792 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3793 /*17*/ "\005\000\002\006\002"
3794 "GDT HA %u, Array Drive %u: parity build failed",
3795 /*18*/ "\005\000\002\006\002"
3796 "GDT HA %u, Array Drive %u: drive rebuild failed",
3797 /*19*/ "\005\000\002\010\002"
3798 "GDT HA %u, Test of Hot Fix %u failed",
3799 /*20*/ "\005\000\002\006\002"
3800 "GDT HA %u, Array Drive %u: drive build finished successfully",
3801 /*21*/ "\005\000\002\006\002"
3802 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3803 /*22*/ "\007\000\002\006\002\010\002"
3804 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3805 /*23*/ "\005\000\002\006\002"
3806 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3807 /*24*/ "\005\000\002\010\002"
3808 "GDT HA %u, mirror update on Cache Drive %u completed",
3809 /*25*/ "\005\000\002\010\002"
3810 "GDT HA %u, mirror update on Cache Drive %lu failed",
3811 /*26*/ "\005\000\002\006\002"
3812 "GDT HA %u, Array Drive %u: drive rebuild started",
3813 /*27*/ "\005\000\002\012\001"
3814 "GDT HA %u, Fault bus %u: SHELF OK detected",
3815 /*28*/ "\005\000\002\012\001"
3816 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3817 /*29*/ "\007\000\002\012\001\013\001"
3818 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3819 /*30*/ "\007\000\002\012\001\013\001"
3820 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3821 /*31*/ "\007\000\002\012\001\013\001"
3822 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3823 /*32*/ "\007\000\002\012\001\013\001"
3824 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3825 /*33*/ "\007\000\002\012\001\013\001"
3826 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3827 /*34*/ "\011\000\002\012\001\013\001\006\004"
3828 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3829 /*35*/ "\007\000\002\012\001\013\001"
3830 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3831 /*36*/ "\007\000\002\012\001\013\001"
3832 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3833 /*37*/ "\007\000\002\012\001\006\004"
3834 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3835 /*38*/ "\007\000\002\012\001\013\001"
3836 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3837 /*39*/ "\007\000\002\012\001\013\001"
3838 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3839 /*40*/ "\007\000\002\012\001\013\001"
3840 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3841 /*41*/ "\007\000\002\012\001\013\001"
3842 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3843 /*42*/ "\005\000\002\006\002"
3844 "GDT HA %u, Array Drive %u: drive build started",
3845 /*43*/ "\003\000\002"
3846 "GDT HA %u, DRAM parity error detected",
3847 /*44*/ "\005\000\002\006\002"
3848 "GDT HA %u, Mirror Drive %u: update started",
3849 /*45*/ "\007\000\002\006\002\010\002"
3850 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3851 /*46*/ "\005\000\002\006\002"
3852 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3853 /*47*/ "\005\000\002\006\002"
3854 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3855 /*48*/ "\005\000\002\006\002"
3856 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3857 /*49*/ "\005\000\002\006\002"
3858 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3859 /*50*/ "\007\000\002\012\001\013\001"
3860 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3861 /*51*/ "\005\000\002\006\002"
3862 "GDT HA %u, Array Drive %u: expand started",
3863 /*52*/ "\005\000\002\006\002"
3864 "GDT HA %u, Array Drive %u: expand finished successfully",
3865 /*53*/ "\005\000\002\006\002"
3866 "GDT HA %u, Array Drive %u: expand failed",
3867 /*54*/ "\003\000\002"
3868 "GDT HA %u, CPU temperature critical",
3869 /*55*/ "\003\000\002"
3870 "GDT HA %u, CPU temperature OK",
3871 /*56*/ "\005\000\002\006\004"
3872 "GDT HA %u, Host drive %lu created",
3873 /*57*/ "\005\000\002\006\002"
3874 "GDT HA %u, Array Drive %u: expand restarted",
3875 /*58*/ "\005\000\002\006\002"
3876 "GDT HA %u, Array Drive %u: expand stopped",
3877 /*59*/ "\005\000\002\010\002"
3878 "GDT HA %u, Mirror Drive %u: drive build quited",
3879 /*60*/ "\005\000\002\006\002"
3880 "GDT HA %u, Array Drive %u: parity build quited",
3881 /*61*/ "\005\000\002\006\002"
3882 "GDT HA %u, Array Drive %u: drive rebuild quited",
3883 /*62*/ "\005\000\002\006\002"
3884 "GDT HA %u, Array Drive %u: parity verify started",
3885 /*63*/ "\005\000\002\006\002"
3886 "GDT HA %u, Array Drive %u: parity verify done",
3887 /*64*/ "\005\000\002\006\002"
3888 "GDT HA %u, Array Drive %u: parity verify failed",
3889 /*65*/ "\005\000\002\006\002"
3890 "GDT HA %u, Array Drive %u: parity error detected",
3891 /*66*/ "\005\000\002\006\002"
3892 "GDT HA %u, Array Drive %u: parity verify quited",
3893 /*67*/ "\005\000\002\006\002"
3894 "GDT HA %u, Host Drive %u reserved",
3895 /*68*/ "\005\000\002\006\002"
3896 "GDT HA %u, Host Drive %u mounted and released",
3897 /*69*/ "\005\000\002\006\002"
3898 "GDT HA %u, Host Drive %u released",
3899 /*70*/ "\003\000\002"
3900 "GDT HA %u, DRAM error detected and corrected with ECC",
3901 /*71*/ "\003\000\002"
3902 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3903 /*72*/ "\011\000\002\012\001\013\001\014\001"
3904 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3905 /*73*/ "\005\000\002\006\002"
3906 "GDT HA %u, Host drive %u resetted locally",
3907 /*74*/ "\005\000\002\006\002"
3908 "GDT HA %u, Host drive %u resetted remotely",
3909 /*75*/ "\003\000\002"
3910 "GDT HA %u, async. status 75 unknown",
3911 };
3912
3913
3914 static int gdth_async_event(int hanum)
3915 {
3916 gdth_ha_str *ha;
3917 gdth_cmd_str *cmdp;
3918 int cmd_index;
3919
3920 ha = HADATA(gdth_ctr_tab[hanum]);
3921 cmdp= ha->pccb;
3922 TRACE2(("gdth_async_event() ha %d serv %d\n",
3923 hanum,ha->service));
3924
3925 if (ha->service == SCREENSERVICE) {
3926 if (ha->status == MSG_REQUEST) {
3927 while (gdth_test_busy(hanum))
3928 gdth_delay(0);
3929 cmdp->Service = SCREENSERVICE;
3930 cmdp->RequestBuffer = SCREEN_CMND;
3931 cmd_index = gdth_get_cmd_index(hanum);
3932 gdth_set_sema0(hanum);
3933 cmdp->OpCode = GDT_READ;
3934 cmdp->BoardNode = LOCALBOARD;
3935 cmdp->u.screen.reserved = 0;
3936 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3937 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3938 ha->cmd_offs_dpmem = 0;
3939 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3940 + sizeof(ulong64);
3941 ha->cmd_cnt = 0;
3942 gdth_copy_command(hanum);
3943 if (ha->type == GDT_EISA)
3944 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
3945 else if (ha->type == GDT_ISA)
3946 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
3947 else
3948 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
3949 (ushort)((ha->brd_phys>>3)&0x1f));
3950 gdth_release_event(hanum);
3951 }
3952
3953 } else {
3954 if (ha->type == GDT_PCIMPR &&
3955 (ha->fw_vers & 0xff) >= 0x1a) {
3956 ha->dvr.size = 0;
3957 ha->dvr.eu.async.ionode = hanum;
3958 ha->dvr.eu.async.status = ha->status;
3959 /* severity and event_string already set! */
3960 } else {
3961 ha->dvr.size = sizeof(ha->dvr.eu.async);
3962 ha->dvr.eu.async.ionode = hanum;
3963 ha->dvr.eu.async.service = ha->service;
3964 ha->dvr.eu.async.status = ha->status;
3965 ha->dvr.eu.async.info = ha->info;
3966 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3967 }
3968 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3969 gdth_log_event( &ha->dvr, NULL );
3970
3971 /* new host drive from expand? */
3972 if (ha->service == CACHESERVICE && ha->status == 56) {
3973 TRACE2(("gdth_async_event(): new host drive %d created\n",
3974 (ushort)ha->info));
3975 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
3976 }
3977 }
3978 return 1;
3979 }
3980
3981 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3982 {
3983 gdth_stackframe stack;
3984 char *f = NULL;
3985 int i,j;
3986
3987 TRACE2(("gdth_log_event()\n"));
3988 if (dvr->size == 0) {
3989 if (buffer == NULL) {
3990 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3991 } else {
3992 sprintf(buffer,"Adapter %d: %s\n",
3993 dvr->eu.async.ionode,dvr->event_string);
3994 }
3995 } else if (dvr->eu.async.service == CACHESERVICE &&
3996 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3997 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3998 dvr->eu.async.status));
3999
4000 f = async_cache_tab[dvr->eu.async.status];
4001
4002 /* i: parameter to push, j: stack element to fill */
4003 for (j=0,i=1; i < f[0]; i+=2) {
4004 switch (f[i+1]) {
4005 case 4:
4006 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
4007 break;
4008 case 2:
4009 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
4010 break;
4011 case 1:
4012 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
4013 break;
4014 default:
4015 break;
4016 }
4017 }
4018
4019 if (buffer == NULL) {
4020 printk(&f[(int)f[0]],stack);
4021 printk("\n");
4022 } else {
4023 sprintf(buffer,&f[(int)f[0]],stack);
4024 }
4025
4026 } else {
4027 if (buffer == NULL) {
4028 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
4029 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4030 } else {
4031 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
4032 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4033 }
4034 }
4035 }
4036
4037 #ifdef GDTH_STATISTICS
4038 static void gdth_timeout(ulong data)
4039 {
4040 ulong32 i;
4041 Scsi_Cmnd *nscp;
4042 gdth_ha_str *ha;
4043 ulong flags;
4044 int hanum = 0;
4045
4046 ha = HADATA(gdth_ctr_tab[hanum]);
4047 spin_lock_irqsave(&ha->smp_lock, flags);
4048
4049 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
4050 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
4051 ++act_stats;
4052
4053 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
4054 ++act_rq;
4055
4056 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
4057 act_ints, act_ios, act_stats, act_rq));
4058 act_ints = act_ios = 0;
4059
4060 gdth_timer.expires = jiffies + 30 * HZ;
4061 add_timer(&gdth_timer);
4062 spin_unlock_irqrestore(&ha->smp_lock, flags);
4063 }
4064 #endif
4065
4066 static void __init internal_setup(char *str,int *ints)
4067 {
4068 int i, argc;
4069 char *cur_str, *argv;
4070
4071 TRACE2(("internal_setup() str %s ints[0] %d\n",
4072 str ? str:"NULL", ints ? ints[0]:0));
4073
4074 /* read irq[] from ints[] */
4075 if (ints) {
4076 argc = ints[0];
4077 if (argc > 0) {
4078 if (argc > MAXHA)
4079 argc = MAXHA;
4080 for (i = 0; i < argc; ++i)
4081 irq[i] = ints[i+1];
4082 }
4083 }
4084
4085 /* analyse string */
4086 argv = str;
4087 while (argv && (cur_str = strchr(argv, ':'))) {
4088 int val = 0, c = *++cur_str;
4089
4090 if (c == 'n' || c == 'N')
4091 val = 0;
4092 else if (c == 'y' || c == 'Y')
4093 val = 1;
4094 else
4095 val = (int)simple_strtoul(cur_str, NULL, 0);
4096
4097 if (!strncmp(argv, "disable:", 8))
4098 disable = val;
4099 else if (!strncmp(argv, "reserve_mode:", 13))
4100 reserve_mode = val;
4101 else if (!strncmp(argv, "reverse_scan:", 13))
4102 reverse_scan = val;
4103 else if (!strncmp(argv, "hdr_channel:", 12))
4104 hdr_channel = val;
4105 else if (!strncmp(argv, "max_ids:", 8))
4106 max_ids = val;
4107 else if (!strncmp(argv, "rescan:", 7))
4108 rescan = val;
4109 else if (!strncmp(argv, "virt_ctr:", 9))
4110 virt_ctr = val;
4111 else if (!strncmp(argv, "shared_access:", 14))
4112 shared_access = val;
4113 else if (!strncmp(argv, "probe_eisa_isa:", 15))
4114 probe_eisa_isa = val;
4115 else if (!strncmp(argv, "reserve_list:", 13)) {
4116 reserve_list[0] = val;
4117 for (i = 1; i < MAX_RES_ARGS; i++) {
4118 cur_str = strchr(cur_str, ',');
4119 if (!cur_str)
4120 break;
4121 if (!isdigit((int)*++cur_str)) {
4122 --cur_str;
4123 break;
4124 }
4125 reserve_list[i] =
4126 (int)simple_strtoul(cur_str, NULL, 0);
4127 }
4128 if (!cur_str)
4129 break;
4130 argv = ++cur_str;
4131 continue;
4132 }
4133
4134 if ((argv = strchr(argv, ',')))
4135 ++argv;
4136 }
4137 }
4138
4139 int __init option_setup(char *str)
4140 {
4141 int ints[MAXHA];
4142 char *cur = str;
4143 int i = 1;
4144
4145 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
4146
4147 while (cur && isdigit(*cur) && i <= MAXHA) {
4148 ints[i++] = simple_strtoul(cur, NULL, 0);
4149 if ((cur = strchr(cur, ',')) != NULL) cur++;
4150 }
4151
4152 ints[0] = i - 1;
4153 internal_setup(cur, ints);
4154 return 1;
4155 }
4156
4157 static int __init gdth_detect(struct scsi_host_template *shtp)
4158 {
4159 struct Scsi_Host *shp;
4160 gdth_pci_str pcistr[MAXHA];
4161 gdth_ha_str *ha;
4162 ulong32 isa_bios;
4163 ushort eisa_slot;
4164 int i,hanum,cnt,ctr,err;
4165 unchar b;
4166
4167
4168 #ifdef DEBUG_GDTH
4169 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
4170 DebugState);
4171 printk(" Destination of debugging information: ");
4172 #ifdef __SERIAL__
4173 #ifdef __COM2__
4174 printk("Serial port COM2\n");
4175 #else
4176 printk("Serial port COM1\n");
4177 #endif
4178 #else
4179 printk("Console\n");
4180 #endif
4181 gdth_delay(3000);
4182 #endif
4183
4184 TRACE(("gdth_detect()\n"));
4185
4186 if (disable) {
4187 printk("GDT-HA: Controller driver disabled from command line !\n");
4188 return 0;
4189 }
4190
4191 printk("GDT-HA: Storage RAID Controller Driver. Version: %s \n",GDTH_VERSION_STR);
4192 /* initializations */
4193 gdth_polling = TRUE; b = 0;
4194 gdth_clear_events();
4195
4196 /* As default we do not probe for EISA or ISA controllers */
4197 if (probe_eisa_isa) {
4198 /* scanning for controllers, at first: ISA controller */
4199 for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
4200 dma_addr_t scratch_dma_handle;
4201 scratch_dma_handle = 0;
4202
4203 if (gdth_ctr_count >= MAXHA)
4204 break;
4205 if (gdth_search_isa(isa_bios)) { /* controller found */
4206 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4207 if (shp == NULL)
4208 continue;
4209
4210 ha = HADATA(shp);
4211 if (!gdth_init_isa(isa_bios,ha)) {
4212 scsi_unregister(shp);
4213 continue;
4214 }
4215 #ifdef __ia64__
4216 break;
4217 #else
4218 /* controller found and initialized */
4219 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4220 isa_bios,ha->irq,ha->drq);
4221
4222 if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
4223 printk("GDT-ISA: Unable to allocate IRQ\n");
4224 scsi_unregister(shp);
4225 continue;
4226 }
4227 if (request_dma(ha->drq,"gdth")) {
4228 printk("GDT-ISA: Unable to allocate DMA channel\n");
4229 free_irq(ha->irq,ha);
4230 scsi_unregister(shp);
4231 continue;
4232 }
4233 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4234 enable_dma(ha->drq);
4235 shp->unchecked_isa_dma = 1;
4236 shp->irq = ha->irq;
4237 shp->dma_channel = ha->drq;
4238 hanum = gdth_ctr_count;
4239 gdth_ctr_tab[gdth_ctr_count++] = shp;
4240 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4241
4242 NUMDATA(shp)->hanum = (ushort)hanum;
4243 NUMDATA(shp)->busnum= 0;
4244
4245 ha->pccb = CMDDATA(shp);
4246 ha->ccb_phys = 0L;
4247 ha->pdev = NULL;
4248 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4249 &scratch_dma_handle);
4250 ha->scratch_phys = scratch_dma_handle;
4251 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4252 &scratch_dma_handle);
4253 ha->msg_phys = scratch_dma_handle;
4254 #ifdef INT_COAL
4255 ha->coal_stat = (gdth_coal_status *)
4256 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4257 MAXOFFSETS, &scratch_dma_handle);
4258 ha->coal_stat_phys = scratch_dma_handle;
4259 #endif
4260
4261 ha->scratch_busy = FALSE;
4262 ha->req_first = NULL;
4263 ha->tid_cnt = MAX_HDRIVES;
4264 if (max_ids > 0 && max_ids < ha->tid_cnt)
4265 ha->tid_cnt = max_ids;
4266 for (i=0; i<GDTH_MAXCMDS; ++i)
4267 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4268 ha->scan_mode = rescan ? 0x10 : 0;
4269
4270 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4271 !gdth_search_drives(hanum)) {
4272 printk("GDT-ISA: Error during device scan\n");
4273 --gdth_ctr_count;
4274 --gdth_ctr_vcount;
4275
4276 #ifdef INT_COAL
4277 if (ha->coal_stat)
4278 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4279 MAXOFFSETS, ha->coal_stat,
4280 ha->coal_stat_phys);
4281 #endif
4282 if (ha->pscratch)
4283 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4284 ha->pscratch, ha->scratch_phys);
4285 if (ha->pmsg)
4286 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4287 ha->pmsg, ha->msg_phys);
4288
4289 free_irq(ha->irq,ha);
4290 scsi_unregister(shp);
4291 continue;
4292 }
4293 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4294 hdr_channel = ha->bus_cnt;
4295 ha->virt_bus = hdr_channel;
4296
4297 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4298 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4299 shp->highmem_io = 0;
4300 #endif
4301 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4302 shp->max_cmd_len = 16;
4303
4304 shp->max_id = ha->tid_cnt;
4305 shp->max_lun = MAXLUN;
4306 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4307 if (virt_ctr) {
4308 virt_ctr = 1;
4309 /* register addit. SCSI channels as virtual controllers */
4310 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4311 shp = scsi_register(shtp,sizeof(gdth_num_str));
4312 shp->unchecked_isa_dma = 1;
4313 shp->irq = ha->irq;
4314 shp->dma_channel = ha->drq;
4315 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4316 NUMDATA(shp)->hanum = (ushort)hanum;
4317 NUMDATA(shp)->busnum = b;
4318 }
4319 }
4320
4321 spin_lock_init(&ha->smp_lock);
4322 gdth_enable_int(hanum);
4323 #endif /* !__ia64__ */
4324 }
4325 }
4326
4327 /* scanning for EISA controllers */
4328 for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
4329 dma_addr_t scratch_dma_handle;
4330 scratch_dma_handle = 0;
4331
4332 if (gdth_ctr_count >= MAXHA)
4333 break;
4334 if (gdth_search_eisa(eisa_slot)) { /* controller found */
4335 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4336 if (shp == NULL)
4337 continue;
4338
4339 ha = HADATA(shp);
4340 if (!gdth_init_eisa(eisa_slot,ha)) {
4341 scsi_unregister(shp);
4342 continue;
4343 }
4344 /* controller found and initialized */
4345 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4346 eisa_slot>>12,ha->irq);
4347
4348 if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
4349 printk("GDT-EISA: Unable to allocate IRQ\n");
4350 scsi_unregister(shp);
4351 continue;
4352 }
4353 shp->unchecked_isa_dma = 0;
4354 shp->irq = ha->irq;
4355 shp->dma_channel = 0xff;
4356 hanum = gdth_ctr_count;
4357 gdth_ctr_tab[gdth_ctr_count++] = shp;
4358 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4359
4360 NUMDATA(shp)->hanum = (ushort)hanum;
4361 NUMDATA(shp)->busnum= 0;
4362 TRACE2(("EISA detect Bus 0: hanum %d\n",
4363 NUMDATA(shp)->hanum));
4364
4365 ha->pccb = CMDDATA(shp);
4366 ha->ccb_phys = 0L;
4367
4368 ha->pdev = NULL;
4369 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4370 &scratch_dma_handle);
4371 ha->scratch_phys = scratch_dma_handle;
4372 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4373 &scratch_dma_handle);
4374 ha->msg_phys = scratch_dma_handle;
4375 #ifdef INT_COAL
4376 ha->coal_stat = (gdth_coal_status *)
4377 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4378 MAXOFFSETS, &scratch_dma_handle);
4379 ha->coal_stat_phys = scratch_dma_handle;
4380 #endif
4381 ha->ccb_phys =
4382 pci_map_single(ha->pdev,ha->pccb,
4383 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4384 ha->scratch_busy = FALSE;
4385 ha->req_first = NULL;
4386 ha->tid_cnt = MAX_HDRIVES;
4387 if (max_ids > 0 && max_ids < ha->tid_cnt)
4388 ha->tid_cnt = max_ids;
4389 for (i=0; i<GDTH_MAXCMDS; ++i)
4390 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4391 ha->scan_mode = rescan ? 0x10 : 0;
4392
4393 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4394 !gdth_search_drives(hanum)) {
4395 printk("GDT-EISA: Error during device scan\n");
4396 --gdth_ctr_count;
4397 --gdth_ctr_vcount;
4398 #ifdef INT_COAL
4399 if (ha->coal_stat)
4400 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4401 MAXOFFSETS, ha->coal_stat,
4402 ha->coal_stat_phys);
4403 #endif
4404 if (ha->pscratch)
4405 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4406 ha->pscratch, ha->scratch_phys);
4407 if (ha->pmsg)
4408 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4409 ha->pmsg, ha->msg_phys);
4410 if (ha->ccb_phys)
4411 pci_unmap_single(ha->pdev,ha->ccb_phys,
4412 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4413 free_irq(ha->irq,ha);
4414 scsi_unregister(shp);
4415 continue;
4416 }
4417 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4418 hdr_channel = ha->bus_cnt;
4419 ha->virt_bus = hdr_channel;
4420
4421 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4422 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4423 shp->highmem_io = 0;
4424 #endif
4425 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4426 shp->max_cmd_len = 16;
4427
4428 shp->max_id = ha->tid_cnt;
4429 shp->max_lun = MAXLUN;
4430 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4431 if (virt_ctr) {
4432 virt_ctr = 1;
4433 /* register addit. SCSI channels as virtual controllers */
4434 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4435 shp = scsi_register(shtp,sizeof(gdth_num_str));
4436 shp->unchecked_isa_dma = 0;
4437 shp->irq = ha->irq;
4438 shp->dma_channel = 0xff;
4439 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4440 NUMDATA(shp)->hanum = (ushort)hanum;
4441 NUMDATA(shp)->busnum = b;
4442 }
4443 }
4444
4445 spin_lock_init(&ha->smp_lock);
4446 gdth_enable_int(hanum);
4447 }
4448 }
4449 }
4450
4451 /* scanning for PCI controllers */
4452 cnt = gdth_search_pci(pcistr);
4453 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
4454 gdth_sort_pci(pcistr,cnt);
4455 for (ctr = 0; ctr < cnt; ++ctr) {
4456 dma_addr_t scratch_dma_handle;
4457 scratch_dma_handle = 0;
4458
4459 if (gdth_ctr_count >= MAXHA)
4460 break;
4461 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4462 if (shp == NULL)
4463 continue;
4464
4465 ha = HADATA(shp);
4466 if (!gdth_init_pci(&pcistr[ctr],ha)) {
4467 scsi_unregister(shp);
4468 continue;
4469 }
4470 /* controller found and initialized */
4471 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4472 pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
4473
4474 if (request_irq(ha->irq, gdth_interrupt,
4475 SA_INTERRUPT|SA_SHIRQ, "gdth", ha))
4476 {
4477 printk("GDT-PCI: Unable to allocate IRQ\n");
4478 scsi_unregister(shp);
4479 continue;
4480 }
4481 shp->unchecked_isa_dma = 0;
4482 shp->irq = ha->irq;
4483 shp->dma_channel = 0xff;
4484 hanum = gdth_ctr_count;
4485 gdth_ctr_tab[gdth_ctr_count++] = shp;
4486 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4487
4488 NUMDATA(shp)->hanum = (ushort)hanum;
4489 NUMDATA(shp)->busnum= 0;
4490
4491 ha->pccb = CMDDATA(shp);
4492 ha->ccb_phys = 0L;
4493
4494 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4495 &scratch_dma_handle);
4496 ha->scratch_phys = scratch_dma_handle;
4497 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4498 &scratch_dma_handle);
4499 ha->msg_phys = scratch_dma_handle;
4500 #ifdef INT_COAL
4501 ha->coal_stat = (gdth_coal_status *)
4502 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4503 MAXOFFSETS, &scratch_dma_handle);
4504 ha->coal_stat_phys = scratch_dma_handle;
4505 #endif
4506 ha->scratch_busy = FALSE;
4507 ha->req_first = NULL;
4508 ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
4509 if (max_ids > 0 && max_ids < ha->tid_cnt)
4510 ha->tid_cnt = max_ids;
4511 for (i=0; i<GDTH_MAXCMDS; ++i)
4512 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4513 ha->scan_mode = rescan ? 0x10 : 0;
4514
4515 err = FALSE;
4516 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4517 !gdth_search_drives(hanum)) {
4518 err = TRUE;
4519 } else {
4520 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4521 hdr_channel = ha->bus_cnt;
4522 ha->virt_bus = hdr_channel;
4523
4524
4525 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4526 scsi_set_pci_device(shp, pcistr[ctr].pdev);
4527 #endif
4528 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
4529 /* 64-bit DMA only supported from FW >= x.43 */
4530 (!ha->dma64_support)) {
4531 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4532 printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
4533 err = TRUE;
4534 }
4535 } else {
4536 shp->max_cmd_len = 16;
4537 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
4538 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
4539 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4540 printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
4541 err = TRUE;
4542 }
4543 }
4544 }
4545
4546 if (err) {
4547 printk("GDT-PCI %d: Error during device scan\n", hanum);
4548 --gdth_ctr_count;
4549 --gdth_ctr_vcount;
4550 #ifdef INT_COAL
4551 if (ha->coal_stat)
4552 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4553 MAXOFFSETS, ha->coal_stat,
4554 ha->coal_stat_phys);
4555 #endif
4556 if (ha->pscratch)
4557 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4558 ha->pscratch, ha->scratch_phys);
4559 if (ha->pmsg)
4560 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4561 ha->pmsg, ha->msg_phys);
4562 free_irq(ha->irq,ha);
4563 scsi_unregister(shp);
4564 continue;
4565 }
4566
4567 shp->max_id = ha->tid_cnt;
4568 shp->max_lun = MAXLUN;
4569 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4570 if (virt_ctr) {
4571 virt_ctr = 1;
4572 /* register addit. SCSI channels as virtual controllers */
4573 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4574 shp = scsi_register(shtp,sizeof(gdth_num_str));
4575 shp->unchecked_isa_dma = 0;
4576 shp->irq = ha->irq;
4577 shp->dma_channel = 0xff;
4578 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4579 NUMDATA(shp)->hanum = (ushort)hanum;
4580 NUMDATA(shp)->busnum = b;
4581 }
4582 }
4583
4584 spin_lock_init(&ha->smp_lock);
4585 gdth_enable_int(hanum);
4586 }
4587
4588 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4589 if (gdth_ctr_count > 0) {
4590 #ifdef GDTH_STATISTICS
4591 TRACE2(("gdth_detect(): Initializing timer !\n"));
4592 init_timer(&gdth_timer);
4593 gdth_timer.expires = jiffies + HZ;
4594 gdth_timer.data = 0L;
4595 gdth_timer.function = gdth_timeout;
4596 add_timer(&gdth_timer);
4597 #endif
4598 major = register_chrdev(0,"gdth",&gdth_fops);
4599 notifier_disabled = 0;
4600 register_reboot_notifier(&gdth_notifier);
4601 }
4602 gdth_polling = FALSE;
4603 return gdth_ctr_vcount;
4604 }
4605
4606 static int gdth_release(struct Scsi_Host *shp)
4607 {
4608 int hanum;
4609 gdth_ha_str *ha;
4610
4611 TRACE2(("gdth_release()\n"));
4612 if (NUMDATA(shp)->busnum == 0) {
4613 hanum = NUMDATA(shp)->hanum;
4614 ha = HADATA(gdth_ctr_tab[hanum]);
4615 if (ha->sdev) {
4616 scsi_free_host_dev(ha->sdev);
4617 ha->sdev = NULL;
4618 }
4619 gdth_flush(hanum);
4620
4621 if (shp->irq) {
4622 free_irq(shp->irq,ha);
4623 }
4624 #ifndef __ia64__
4625 if (shp->dma_channel != 0xff) {
4626 free_dma(shp->dma_channel);
4627 }
4628 #endif
4629 #ifdef INT_COAL
4630 if (ha->coal_stat)
4631 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4632 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4633 #endif
4634 if (ha->pscratch)
4635 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4636 ha->pscratch, ha->scratch_phys);
4637 if (ha->pmsg)
4638 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4639 ha->pmsg, ha->msg_phys);
4640 if (ha->ccb_phys)
4641 pci_unmap_single(ha->pdev,ha->ccb_phys,
4642 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4643 gdth_ctr_released++;
4644 TRACE2(("gdth_release(): HA %d of %d\n",
4645 gdth_ctr_released, gdth_ctr_count));
4646
4647 if (gdth_ctr_released == gdth_ctr_count) {
4648 #ifdef GDTH_STATISTICS
4649 del_timer(&gdth_timer);
4650 #endif
4651 unregister_chrdev(major,"gdth");
4652 unregister_reboot_notifier(&gdth_notifier);
4653 }
4654 }
4655
4656 scsi_unregister(shp);
4657 return 0;
4658 }
4659
4660
4661 static const char *gdth_ctr_name(int hanum)
4662 {
4663 gdth_ha_str *ha;
4664
4665 TRACE2(("gdth_ctr_name()\n"));
4666
4667 ha = HADATA(gdth_ctr_tab[hanum]);
4668
4669 if (ha->type == GDT_EISA) {
4670 switch (ha->stype) {
4671 case GDT3_ID:
4672 return("GDT3000/3020");
4673 case GDT3A_ID:
4674 return("GDT3000A/3020A/3050A");
4675 case GDT3B_ID:
4676 return("GDT3000B/3010A");
4677 }
4678 } else if (ha->type == GDT_ISA) {
4679 return("GDT2000/2020");
4680 } else if (ha->type == GDT_PCI) {
4681 switch (ha->stype) {
4682 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4683 return("GDT6000/6020/6050");
4684 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4685 return("GDT6000B/6010");
4686 }
4687 }
4688 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4689
4690 return("");
4691 }
4692
4693 static const char *gdth_info(struct Scsi_Host *shp)
4694 {
4695 int hanum;
4696 gdth_ha_str *ha;
4697
4698 TRACE2(("gdth_info()\n"));
4699 hanum = NUMDATA(shp)->hanum;
4700 ha = HADATA(gdth_ctr_tab[hanum]);
4701
4702 return ((const char *)ha->binfo.type_string);
4703 }
4704
4705 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
4706 {
4707 int i, hanum;
4708 gdth_ha_str *ha;
4709 ulong flags;
4710 Scsi_Cmnd *cmnd;
4711 unchar b;
4712
4713 TRACE2(("gdth_eh_bus_reset()\n"));
4714
4715 hanum = NUMDATA(scp->device->host)->hanum;
4716 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4717 ha = HADATA(gdth_ctr_tab[hanum]);
4718
4719 /* clear command tab */
4720 spin_lock_irqsave(&ha->smp_lock, flags);
4721 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4722 cmnd = ha->cmd_tab[i].cmnd;
4723 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4724 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4725 }
4726 spin_unlock_irqrestore(&ha->smp_lock, flags);
4727
4728 if (b == ha->virt_bus) {
4729 /* host drives */
4730 for (i = 0; i < MAX_HDRIVES; ++i) {
4731 if (ha->hdr[i].present) {
4732 spin_lock_irqsave(&ha->smp_lock, flags);
4733 gdth_polling = TRUE;
4734 while (gdth_test_busy(hanum))
4735 gdth_delay(0);
4736 if (gdth_internal_cmd(hanum, CACHESERVICE,
4737 GDT_CLUST_RESET, i, 0, 0))
4738 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4739 gdth_polling = FALSE;
4740 spin_unlock_irqrestore(&ha->smp_lock, flags);
4741 }
4742 }
4743 } else {
4744 /* raw devices */
4745 spin_lock_irqsave(&ha->smp_lock, flags);
4746 for (i = 0; i < MAXID; ++i)
4747 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4748 gdth_polling = TRUE;
4749 while (gdth_test_busy(hanum))
4750 gdth_delay(0);
4751 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4752 BUS_L2P(ha,b), 0, 0);
4753 gdth_polling = FALSE;
4754 spin_unlock_irqrestore(&ha->smp_lock, flags);
4755 }
4756 return SUCCESS;
4757 }
4758
4759 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4760 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
4761 #else
4762 static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
4763 #endif
4764 {
4765 unchar b, t;
4766 int hanum;
4767 gdth_ha_str *ha;
4768 struct scsi_device *sd;
4769 unsigned capacity;
4770
4771 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4772 sd = sdev;
4773 capacity = cap;
4774 #else
4775 sd = disk->device;
4776 capacity = disk->capacity;
4777 #endif
4778 hanum = NUMDATA(sd->host)->hanum;
4779 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4780 t = sd->id;
4781 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4782 ha = HADATA(gdth_ctr_tab[hanum]);
4783
4784 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4785 /* raw device or host drive without mapping information */
4786 TRACE2(("Evaluate mapping\n"));
4787 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4788 } else {
4789 ip[0] = ha->hdr[t].heads;
4790 ip[1] = ha->hdr[t].secs;
4791 ip[2] = capacity / ip[0] / ip[1];
4792 }
4793
4794 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4795 ip[0],ip[1],ip[2]));
4796 return 0;
4797 }
4798
4799
4800 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
4801 {
4802 int hanum;
4803 int priority;
4804
4805 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4806
4807 scp->scsi_done = (void *)done;
4808 scp->SCp.have_data_in = 1;
4809 scp->SCp.phase = -1;
4810 scp->SCp.sent_command = -1;
4811 scp->SCp.Status = GDTH_MAP_NONE;
4812 scp->SCp.buffer = (struct scatterlist *)NULL;
4813
4814 hanum = NUMDATA(scp->device->host)->hanum;
4815 #ifdef GDTH_STATISTICS
4816 ++act_ios;
4817 #endif
4818
4819 priority = DEFAULT_PRI;
4820 if (scp->done == gdth_scsi_done)
4821 priority = scp->SCp.this_residual;
4822 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4823 gdth_putq( hanum, scp, priority );
4824 gdth_next( hanum );
4825 return 0;
4826 }
4827
4828
4829 static int gdth_open(struct inode *inode, struct file *filep)
4830 {
4831 gdth_ha_str *ha;
4832 int i;
4833
4834 for (i = 0; i < gdth_ctr_count; i++) {
4835 ha = HADATA(gdth_ctr_tab[i]);
4836 if (!ha->sdev)
4837 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4838 }
4839
4840 TRACE(("gdth_open()\n"));
4841 return 0;
4842 }
4843
4844 static int gdth_close(struct inode *inode, struct file *filep)
4845 {
4846 TRACE(("gdth_close()\n"));
4847 return 0;
4848 }
4849
4850 static int ioc_event(void __user *arg)
4851 {
4852 gdth_ioctl_event evt;
4853 gdth_ha_str *ha;
4854 ulong flags;
4855
4856 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4857 evt.ionode >= gdth_ctr_count)
4858 return -EFAULT;
4859 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4860
4861 if (evt.erase == 0xff) {
4862 if (evt.event.event_source == ES_TEST)
4863 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4864 else if (evt.event.event_source == ES_DRIVER)
4865 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4866 else if (evt.event.event_source == ES_SYNC)
4867 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4868 else
4869 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4870 spin_lock_irqsave(&ha->smp_lock, flags);
4871 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4872 &evt.event.event_data);
4873 spin_unlock_irqrestore(&ha->smp_lock, flags);
4874 } else if (evt.erase == 0xfe) {
4875 gdth_clear_events();
4876 } else if (evt.erase == 0) {
4877 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4878 } else {
4879 gdth_readapp_event(ha, evt.erase, &evt.event);
4880 }
4881 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4882 return -EFAULT;
4883 return 0;
4884 }
4885
4886 static int ioc_lockdrv(void __user *arg)
4887 {
4888 gdth_ioctl_lockdrv ldrv;
4889 unchar i, j;
4890 ulong flags;
4891 gdth_ha_str *ha;
4892
4893 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
4894 ldrv.ionode >= gdth_ctr_count)
4895 return -EFAULT;
4896 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
4897
4898 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4899 j = ldrv.drives[i];
4900 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4901 continue;
4902 if (ldrv.lock) {
4903 spin_lock_irqsave(&ha->smp_lock, flags);
4904 ha->hdr[j].lock = 1;
4905 spin_unlock_irqrestore(&ha->smp_lock, flags);
4906 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
4907 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
4908 } else {
4909 spin_lock_irqsave(&ha->smp_lock, flags);
4910 ha->hdr[j].lock = 0;
4911 spin_unlock_irqrestore(&ha->smp_lock, flags);
4912 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
4913 gdth_next(ldrv.ionode);
4914 }
4915 }
4916 return 0;
4917 }
4918
4919 static int ioc_resetdrv(void __user *arg, char *cmnd)
4920 {
4921 gdth_ioctl_reset res;
4922 gdth_cmd_str cmd;
4923 int hanum;
4924 gdth_ha_str *ha;
4925 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4926 Scsi_Request *srp;
4927 #else
4928 Scsi_Cmnd *scp;
4929 #endif
4930
4931 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4932 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
4933 return -EFAULT;
4934 hanum = res.ionode;
4935 ha = HADATA(gdth_ctr_tab[hanum]);
4936
4937 if (!ha->hdr[res.number].present)
4938 return 0;
4939 memset(&cmd, 0, sizeof(gdth_cmd_str));
4940 cmd.Service = CACHESERVICE;
4941 cmd.OpCode = GDT_CLUST_RESET;
4942 if (ha->cache_feat & GDT_64BIT)
4943 cmd.u.cache64.DeviceNo = res.number;
4944 else
4945 cmd.u.cache.DeviceNo = res.number;
4946 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4947 srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
4948 if (!srp)
4949 return -ENOMEM;
4950 srp->sr_cmd_len = 12;
4951 srp->sr_use_sg = 0;
4952 gdth_do_req(srp, &cmd, cmnd, 30);
4953 res.status = (ushort)srp->sr_command->SCp.Status;
4954 scsi_release_request(srp);
4955 #else
4956 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
4957 if (!scp)
4958 return -ENOMEM;
4959 scp->cmd_len = 12;
4960 scp->use_sg = 0;
4961 gdth_do_cmd(scp, &cmd, cmnd, 30);
4962 res.status = (ushort)scp->SCp.Status;
4963 scsi_release_command(scp);
4964 #endif
4965
4966 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4967 return -EFAULT;
4968 return 0;
4969 }
4970
4971 static int ioc_general(void __user *arg, char *cmnd)
4972 {
4973 gdth_ioctl_general gen;
4974 char *buf = NULL;
4975 ulong64 paddr;
4976 int hanum;
4977 gdth_ha_str *ha;
4978 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4979 Scsi_Request *srp;
4980 #else
4981 Scsi_Cmnd *scp;
4982 #endif
4983
4984 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
4985 gen.ionode >= gdth_ctr_count)
4986 return -EFAULT;
4987 hanum = gen.ionode;
4988 ha = HADATA(gdth_ctr_tab[hanum]);
4989 if (gen.data_len + gen.sense_len != 0) {
4990 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
4991 FALSE, &paddr)))
4992 return -EFAULT;
4993 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4994 gen.data_len + gen.sense_len)) {
4995 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4996 return -EFAULT;
4997 }
4998
4999 if (gen.command.OpCode == GDT_IOCTL) {
5000 gen.command.u.ioctl.p_param = paddr;
5001 } else if (gen.command.Service == CACHESERVICE) {
5002 if (ha->cache_feat & GDT_64BIT) {
5003 /* copy elements from 32-bit IOCTL structure */
5004 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
5005 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
5006 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
5007 /* addresses */
5008 if (ha->cache_feat & SCATTER_GATHER) {
5009 gen.command.u.cache64.DestAddr = (ulong64)-1;
5010 gen.command.u.cache64.sg_canz = 1;
5011 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
5012 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
5013 gen.command.u.cache64.sg_lst[1].sg_len = 0;
5014 } else {
5015 gen.command.u.cache64.DestAddr = paddr;
5016 gen.command.u.cache64.sg_canz = 0;
5017 }
5018 } else {
5019 if (ha->cache_feat & SCATTER_GATHER) {
5020 gen.command.u.cache.DestAddr = 0xffffffff;
5021 gen.command.u.cache.sg_canz = 1;
5022 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
5023 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
5024 gen.command.u.cache.sg_lst[1].sg_len = 0;
5025 } else {
5026 gen.command.u.cache.DestAddr = paddr;
5027 gen.command.u.cache.sg_canz = 0;
5028 }
5029 }
5030 } else if (gen.command.Service == SCSIRAWSERVICE) {
5031 if (ha->raw_feat & GDT_64BIT) {
5032 /* copy elements from 32-bit IOCTL structure */
5033 char cmd[16];
5034 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
5035 gen.command.u.raw64.bus = gen.command.u.raw.bus;
5036 gen.command.u.raw64.lun = gen.command.u.raw.lun;
5037 gen.command.u.raw64.target = gen.command.u.raw.target;
5038 memcpy(cmd, gen.command.u.raw.cmd, 16);
5039 memcpy(gen.command.u.raw64.cmd, cmd, 16);
5040 gen.command.u.raw64.clen = gen.command.u.raw.clen;
5041 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
5042 gen.command.u.raw64.direction = gen.command.u.raw.direction;
5043 /* addresses */
5044 if (ha->raw_feat & SCATTER_GATHER) {
5045 gen.command.u.raw64.sdata = (ulong64)-1;
5046 gen.command.u.raw64.sg_ranz = 1;
5047 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
5048 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
5049 gen.command.u.raw64.sg_lst[1].sg_len = 0;
5050 } else {
5051 gen.command.u.raw64.sdata = paddr;
5052 gen.command.u.raw64.sg_ranz = 0;
5053 }
5054 gen.command.u.raw64.sense_data = paddr + gen.data_len;
5055 } else {
5056 if (ha->raw_feat & SCATTER_GATHER) {
5057 gen.command.u.raw.sdata = 0xffffffff;
5058 gen.command.u.raw.sg_ranz = 1;
5059 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
5060 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
5061 gen.command.u.raw.sg_lst[1].sg_len = 0;
5062 } else {
5063 gen.command.u.raw.sdata = paddr;
5064 gen.command.u.raw.sg_ranz = 0;
5065 }
5066 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
5067 }
5068 } else {
5069 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5070 return -EFAULT;
5071 }
5072 }
5073
5074 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5075 srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
5076 if (!srp)
5077 return -ENOMEM;
5078 srp->sr_cmd_len = 12;
5079 srp->sr_use_sg = 0;
5080 gdth_do_req(srp, &gen.command, cmnd, gen.timeout);
5081 gen.status = srp->sr_command->SCp.Status;
5082 gen.info = srp->sr_command->SCp.Message;
5083 scsi_release_request(srp);
5084 #else
5085 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5086 if (!scp)
5087 return -ENOMEM;
5088 scp->cmd_len = 12;
5089 scp->use_sg = 0;
5090 gdth_do_cmd(scp, &gen.command, cmnd, gen.timeout);
5091 gen.status = scp->SCp.Status;
5092 gen.info = scp->SCp.Message;
5093 scsi_release_command(scp);
5094 #endif
5095
5096 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
5097 gen.data_len + gen.sense_len)) {
5098 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5099 return -EFAULT;
5100 }
5101 if (copy_to_user(arg, &gen,
5102 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
5103 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5104 return -EFAULT;
5105 }
5106 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5107 return 0;
5108 }
5109
5110 static int ioc_hdrlist(void __user *arg, char *cmnd)
5111 {
5112 gdth_ioctl_rescan *rsc;
5113 gdth_cmd_str *cmd;
5114 gdth_ha_str *ha;
5115 unchar i;
5116 int hanum, rc = -ENOMEM;
5117 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5118 Scsi_Request *srp;
5119 #else
5120 Scsi_Cmnd *scp;
5121 #endif
5122
5123 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5124 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5125 if (!rsc || !cmd)
5126 goto free_fail;
5127
5128 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5129 rsc->ionode >= gdth_ctr_count) {
5130 rc = -EFAULT;
5131 goto free_fail;
5132 }
5133 hanum = rsc->ionode;
5134 ha = HADATA(gdth_ctr_tab[hanum]);
5135 memset(cmd, 0, sizeof(gdth_cmd_str));
5136
5137 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5138 srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
5139 if (!srp)
5140 goto free_fail;
5141 srp->sr_cmd_len = 12;
5142 srp->sr_use_sg = 0;
5143 #else
5144 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5145 if (!scp)
5146 goto free_fail;
5147 scp->cmd_len = 12;
5148 scp->use_sg = 0;
5149 #endif
5150
5151 for (i = 0; i < MAX_HDRIVES; ++i) {
5152 if (!ha->hdr[i].present) {
5153 rsc->hdr_list[i].bus = 0xff;
5154 continue;
5155 }
5156 rsc->hdr_list[i].bus = ha->virt_bus;
5157 rsc->hdr_list[i].target = i;
5158 rsc->hdr_list[i].lun = 0;
5159 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5160 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
5161 cmd->Service = CACHESERVICE;
5162 cmd->OpCode = GDT_CLUST_INFO;
5163 if (ha->cache_feat & GDT_64BIT)
5164 cmd->u.cache64.DeviceNo = i;
5165 else
5166 cmd->u.cache.DeviceNo = i;
5167 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5168 gdth_do_req(srp, cmd, cmnd, 30);
5169 if (srp->sr_command->SCp.Status == S_OK)
5170 rsc->hdr_list[i].cluster_type = srp->sr_command->SCp.Message;
5171 #else
5172 gdth_do_cmd(scp, cmd, cmnd, 30);
5173 if (scp->SCp.Status == S_OK)
5174 rsc->hdr_list[i].cluster_type = scp->SCp.Message;
5175 #endif
5176 }
5177 }
5178 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5179 scsi_release_request(srp);
5180 #else
5181 scsi_release_command(scp);
5182 #endif
5183
5184 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5185 rc = -EFAULT;
5186 else
5187 rc = 0;
5188
5189 free_fail:
5190 kfree(rsc);
5191 kfree(cmd);
5192 return rc;
5193 }
5194
5195 static int ioc_rescan(void __user *arg, char *cmnd)
5196 {
5197 gdth_ioctl_rescan *rsc;
5198 gdth_cmd_str *cmd;
5199 ushort i, status, hdr_cnt;
5200 ulong32 info;
5201 int hanum, cyls, hds, secs;
5202 int rc = -ENOMEM;
5203 ulong flags;
5204 gdth_ha_str *ha;
5205 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5206 Scsi_Request *srp;
5207 #else
5208 Scsi_Cmnd *scp;
5209 #endif
5210
5211 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5212 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5213 if (!cmd || !rsc)
5214 goto free_fail;
5215
5216 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5217 rsc->ionode >= gdth_ctr_count) {
5218 rc = -EFAULT;
5219 goto free_fail;
5220 }
5221 hanum = rsc->ionode;
5222 ha = HADATA(gdth_ctr_tab[hanum]);
5223 memset(cmd, 0, sizeof(gdth_cmd_str));
5224
5225 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5226 srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
5227 if (!srp)
5228 goto free_fail;
5229 srp->sr_cmd_len = 12;
5230 srp->sr_use_sg = 0;
5231 #else
5232 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5233 if (!scp)
5234 goto free_fail;
5235 scp->cmd_len = 12;
5236 scp->use_sg = 0;
5237 #endif
5238
5239 if (rsc->flag == 0) {
5240 /* old method: re-init. cache service */
5241 cmd->Service = CACHESERVICE;
5242 if (ha->cache_feat & GDT_64BIT) {
5243 cmd->OpCode = GDT_X_INIT_HOST;
5244 cmd->u.cache64.DeviceNo = LINUX_OS;
5245 } else {
5246 cmd->OpCode = GDT_INIT;
5247 cmd->u.cache.DeviceNo = LINUX_OS;
5248 }
5249 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5250 gdth_do_req(srp, cmd, cmnd, 30);
5251 status = (ushort)srp->sr_command->SCp.Status;
5252 info = (ulong32)srp->sr_command->SCp.Message;
5253 #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
5254 gdth_do_cmd(scp, cmd, cmnd, 30);
5255 status = (ushort)scp->SCp.Status;
5256 info = (ulong32)scp->SCp.Message;
5257 #else
5258 gdth_do_cmd(&scp, cmd, cmnd, 30);
5259 status = (ushort)scp.SCp.Status;
5260 info = (ulong32)scp.SCp.Message;
5261 #endif
5262 i = 0;
5263 hdr_cnt = (status == S_OK ? (ushort)info : 0);
5264 } else {
5265 i = rsc->hdr_no;
5266 hdr_cnt = i + 1;
5267 }
5268
5269 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
5270 cmd->Service = CACHESERVICE;
5271 cmd->OpCode = GDT_INFO;
5272 if (ha->cache_feat & GDT_64BIT)
5273 cmd->u.cache64.DeviceNo = i;
5274 else
5275 cmd->u.cache.DeviceNo = i;
5276 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5277 gdth_do_req(srp, cmd, cmnd, 30);
5278 status = (ushort)srp->sr_command->SCp.Status;
5279 info = (ulong32)srp->sr_command->SCp.Message;
5280 #else
5281 gdth_do_cmd(scp, cmd, cmnd, 30);
5282 status = (ushort)scp->SCp.Status;
5283 info = (ulong32)scp->SCp.Message;
5284 #endif
5285 spin_lock_irqsave(&ha->smp_lock, flags);
5286 rsc->hdr_list[i].bus = ha->virt_bus;
5287 rsc->hdr_list[i].target = i;
5288 rsc->hdr_list[i].lun = 0;
5289 if (status != S_OK) {
5290 ha->hdr[i].present = FALSE;
5291 } else {
5292 ha->hdr[i].present = TRUE;
5293 ha->hdr[i].size = info;
5294 /* evaluate mapping */
5295 ha->hdr[i].size &= ~SECS32;
5296 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
5297 ha->hdr[i].heads = hds;
5298 ha->hdr[i].secs = secs;
5299 /* round size */
5300 ha->hdr[i].size = cyls * hds * secs;
5301 }
5302 spin_unlock_irqrestore(&ha->smp_lock, flags);
5303 if (status != S_OK)
5304 continue;
5305
5306 /* extended info, if GDT_64BIT, for drives > 2 TB */
5307 /* but we need ha->info2, not yet stored in scp->SCp */
5308
5309 /* devtype, cluster info, R/W attribs */
5310 cmd->Service = CACHESERVICE;
5311 cmd->OpCode = GDT_DEVTYPE;
5312 if (ha->cache_feat & GDT_64BIT)
5313 cmd->u.cache64.DeviceNo = i;
5314 else
5315 cmd->u.cache.DeviceNo = i;
5316 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5317 gdth_do_req(srp, cmd, cmnd, 30);
5318 status = (ushort)srp->sr_command->SCp.Status;
5319 info = (ulong32)srp->sr_command->SCp.Message;
5320 #else
5321 gdth_do_cmd(scp, cmd, cmnd, 30);
5322 status = (ushort)scp->SCp.Status;
5323 info = (ulong32)scp->SCp.Message;
5324 #endif
5325 spin_lock_irqsave(&ha->smp_lock, flags);
5326 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
5327 spin_unlock_irqrestore(&ha->smp_lock, flags);
5328
5329 cmd->Service = CACHESERVICE;
5330 cmd->OpCode = GDT_CLUST_INFO;
5331 if (ha->cache_feat & GDT_64BIT)
5332 cmd->u.cache64.DeviceNo = i;
5333 else
5334 cmd->u.cache.DeviceNo = i;
5335 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5336 gdth_do_req(srp, cmd, cmnd, 30);
5337 status = (ushort)srp->sr_command->SCp.Status;
5338 info = (ulong32)srp->sr_command->SCp.Message;
5339 #else
5340 gdth_do_cmd(scp, cmd, cmnd, 30);
5341 status = (ushort)scp->SCp.Status;
5342 info = (ulong32)scp->SCp.Message;
5343 #endif
5344 spin_lock_irqsave(&ha->smp_lock, flags);
5345 ha->hdr[i].cluster_type =
5346 ((status == S_OK && !shared_access) ? (ushort)info : 0);
5347 spin_unlock_irqrestore(&ha->smp_lock, flags);
5348 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5349
5350 cmd->Service = CACHESERVICE;
5351 cmd->OpCode = GDT_RW_ATTRIBS;
5352 if (ha->cache_feat & GDT_64BIT)
5353 cmd->u.cache64.DeviceNo = i;
5354 else
5355 cmd->u.cache.DeviceNo = i;
5356 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5357 gdth_do_req(srp, cmd, cmnd, 30);
5358 status = (ushort)srp->sr_command->SCp.Status;
5359 info = (ulong32)srp->sr_command->SCp.Message;
5360 #else
5361 gdth_do_cmd(scp, cmd, cmnd, 30);
5362 status = (ushort)scp->SCp.Status;
5363 info = (ulong32)scp->SCp.Message;
5364 #endif
5365 spin_lock_irqsave(&ha->smp_lock, flags);
5366 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
5367 spin_unlock_irqrestore(&ha->smp_lock, flags);
5368 }
5369 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5370 scsi_release_request(srp);
5371 #else
5372 scsi_release_command(scp);
5373 #endif
5374
5375 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5376 rc = -EFAULT;
5377 else
5378 rc = 0;
5379
5380 free_fail:
5381 kfree(rsc);
5382 kfree(cmd);
5383 return rc;
5384 }
5385
5386 static int gdth_ioctl(struct inode *inode, struct file *filep,
5387 unsigned int cmd, unsigned long arg)
5388 {
5389 gdth_ha_str *ha;
5390 Scsi_Cmnd *scp;
5391 ulong flags;
5392 char cmnd[MAX_COMMAND_SIZE];
5393 void __user *argp = (void __user *)arg;
5394
5395 memset(cmnd, 0xff, 12);
5396
5397 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
5398
5399 switch (cmd) {
5400 case GDTIOCTL_CTRCNT:
5401 {
5402 int cnt = gdth_ctr_count;
5403 if (put_user(cnt, (int __user *)argp))
5404 return -EFAULT;
5405 break;
5406 }
5407
5408 case GDTIOCTL_DRVERS:
5409 {
5410 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
5411 if (put_user(ver, (int __user *)argp))
5412 return -EFAULT;
5413 break;
5414 }
5415
5416 case GDTIOCTL_OSVERS:
5417 {
5418 gdth_ioctl_osvers osv;
5419
5420 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
5421 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
5422 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
5423 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
5424 return -EFAULT;
5425 break;
5426 }
5427
5428 case GDTIOCTL_CTRTYPE:
5429 {
5430 gdth_ioctl_ctrtype ctrt;
5431
5432 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
5433 ctrt.ionode >= gdth_ctr_count)
5434 return -EFAULT;
5435 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
5436 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
5437 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
5438 } else {
5439 if (ha->type != GDT_PCIMPR) {
5440 ctrt.type = (unchar)((ha->stype<<4) + 6);
5441 } else {
5442 ctrt.type =
5443 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
5444 if (ha->stype >= 0x300)
5445 ctrt.ext_type = 0x6000 | ha->subdevice_id;
5446 else
5447 ctrt.ext_type = 0x6000 | ha->stype;
5448 }
5449 ctrt.device_id = ha->stype;
5450 ctrt.sub_device_id = ha->subdevice_id;
5451 }
5452 ctrt.info = ha->brd_phys;
5453 ctrt.oem_id = ha->oem_id;
5454 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
5455 return -EFAULT;
5456 break;
5457 }
5458
5459 case GDTIOCTL_GENERAL:
5460 return ioc_general(argp, cmnd);
5461
5462 case GDTIOCTL_EVENT:
5463 return ioc_event(argp);
5464
5465 case GDTIOCTL_LOCKDRV:
5466 return ioc_lockdrv(argp);
5467
5468 case GDTIOCTL_LOCKCHN:
5469 {
5470 gdth_ioctl_lockchn lchn;
5471 unchar i, j;
5472
5473 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
5474 lchn.ionode >= gdth_ctr_count)
5475 return -EFAULT;
5476 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
5477
5478 i = lchn.channel;
5479 if (i < ha->bus_cnt) {
5480 if (lchn.lock) {
5481 spin_lock_irqsave(&ha->smp_lock, flags);
5482 ha->raw[i].lock = 1;
5483 spin_unlock_irqrestore(&ha->smp_lock, flags);
5484 for (j = 0; j < ha->tid_cnt; ++j) {
5485 gdth_wait_completion(lchn.ionode, i, j);
5486 gdth_stop_timeout(lchn.ionode, i, j);
5487 }
5488 } else {
5489 spin_lock_irqsave(&ha->smp_lock, flags);
5490 ha->raw[i].lock = 0;
5491 spin_unlock_irqrestore(&ha->smp_lock, flags);
5492 for (j = 0; j < ha->tid_cnt; ++j) {
5493 gdth_start_timeout(lchn.ionode, i, j);
5494 gdth_next(lchn.ionode);
5495 }
5496 }
5497 }
5498 break;
5499 }
5500
5501 case GDTIOCTL_RESCAN:
5502 return ioc_rescan(argp, cmnd);
5503
5504 case GDTIOCTL_HDRLIST:
5505 return ioc_hdrlist(argp, cmnd);
5506
5507 case GDTIOCTL_RESET_BUS:
5508 {
5509 gdth_ioctl_reset res;
5510 int hanum, rval;
5511
5512 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
5513 res.ionode >= gdth_ctr_count)
5514 return -EFAULT;
5515 hanum = res.ionode;
5516 ha = HADATA(gdth_ctr_tab[hanum]);
5517
5518 /* Because we need a Scsi_Cmnd struct., we make a scsi_allocate device also for kernels >=2.6.x */
5519 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5520 scp = scsi_get_command(ha->sdev, GFP_KERNEL);
5521 if (!scp)
5522 return -ENOMEM;
5523 scp->cmd_len = 12;
5524 scp->use_sg = 0;
5525 scp->device->channel = virt_ctr ? 0 : res.number;
5526 rval = gdth_eh_bus_reset(scp);
5527 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5528 scsi_put_command(scp);
5529 #else
5530 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5531 if (!scp)
5532 return -ENOMEM;
5533 scp->cmd_len = 12;
5534 scp->use_sg = 0;
5535 scp->channel = virt_ctr ? 0 : res.number;
5536 rval = gdth_eh_bus_reset(scp);
5537 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5538 scsi_release_command(scp);
5539 #endif
5540 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
5541 return -EFAULT;
5542 break;
5543 }
5544
5545 case GDTIOCTL_RESET_DRV:
5546 return ioc_resetdrv(argp, cmnd);
5547
5548 default:
5549 break;
5550 }
5551 return 0;
5552 }
5553
5554
5555 /* flush routine */
5556 static void gdth_flush(int hanum)
5557 {
5558 int i;
5559 gdth_ha_str *ha;
5560 gdth_cmd_str gdtcmd;
5561 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5562 Scsi_Request *srp;
5563 #else
5564 Scsi_Cmnd *scp;
5565 #endif
5566 struct scsi_device *sdev;
5567 char cmnd[MAX_COMMAND_SIZE];
5568 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5569
5570 TRACE2(("gdth_flush() hanum %d\n",hanum));
5571 ha = HADATA(gdth_ctr_tab[hanum]);
5572
5573 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5574 sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
5575 srp = scsi_allocate_request(sdev, GFP_KERNEL);
5576 if (!srp)
5577 return;
5578 srp->sr_cmd_len = 12;
5579 srp->sr_use_sg = 0;
5580 #else
5581 sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
5582 scp = scsi_allocate_device(sdev, 1, FALSE);
5583 if (!scp)
5584 return;
5585 scp->cmd_len = 12;
5586 scp->use_sg = 0;
5587 #endif
5588
5589 for (i = 0; i < MAX_HDRIVES; ++i) {
5590 if (ha->hdr[i].present) {
5591 gdtcmd.BoardNode = LOCALBOARD;
5592 gdtcmd.Service = CACHESERVICE;
5593 gdtcmd.OpCode = GDT_FLUSH;
5594 if (ha->cache_feat & GDT_64BIT) {
5595 gdtcmd.u.cache64.DeviceNo = i;
5596 gdtcmd.u.cache64.BlockNo = 1;
5597 gdtcmd.u.cache64.sg_canz = 0;
5598 } else {
5599 gdtcmd.u.cache.DeviceNo = i;
5600 gdtcmd.u.cache.BlockNo = 1;
5601 gdtcmd.u.cache.sg_canz = 0;
5602 }
5603 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
5604 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5605 gdth_do_req(srp, &gdtcmd, cmnd, 30);
5606 #else
5607 gdth_do_cmd(scp, &gdtcmd, cmnd, 30);
5608 #endif
5609 }
5610 }
5611 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5612 scsi_release_request(srp);
5613 scsi_free_host_dev(sdev);
5614 #else
5615 scsi_release_command(scp);
5616 scsi_free_host_dev(sdev);
5617 #endif
5618 }
5619
5620 /* shutdown routine */
5621 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5622 {
5623 int hanum;
5624 #ifndef __alpha__
5625 gdth_cmd_str gdtcmd;
5626 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5627 Scsi_Request *srp;
5628 struct scsi_device *sdev;
5629 #else
5630 Scsi_Cmnd *scp;
5631 struct scsi_device *sdev;
5632 #endif
5633 char cmnd[MAX_COMMAND_SIZE];
5634 #endif
5635
5636 if (notifier_disabled)
5637 return NOTIFY_OK;
5638
5639 TRACE2(("gdth_halt() event %d\n",(int)event));
5640 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5641 return NOTIFY_DONE;
5642
5643 notifier_disabled = 1;
5644 printk("GDT-HA: Flushing all host drives .. ");
5645 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
5646 gdth_flush(hanum);
5647
5648 #ifndef __alpha__
5649 /* controller reset */
5650 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5651 gdtcmd.BoardNode = LOCALBOARD;
5652 gdtcmd.Service = CACHESERVICE;
5653 gdtcmd.OpCode = GDT_RESET;
5654 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
5655 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5656 sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
5657 srp = scsi_allocate_request(sdev, GFP_KERNEL);
5658 if (!srp) {
5659 unregister_reboot_notifier(&gdth_notifier);
5660 return NOTIFY_OK;
5661 }
5662 srp->sr_cmd_len = 12;
5663 srp->sr_use_sg = 0;
5664 gdth_do_req(srp, &gdtcmd, cmnd, 10);
5665 scsi_release_request(srp);
5666 scsi_free_host_dev(sdev);
5667 #else
5668 sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
5669 scp = scsi_allocate_device(sdev, 1, FALSE);
5670 if (!scp) {
5671 unregister_reboot_notifier(&gdth_notifier);
5672 return NOTIFY_OK;
5673 }
5674 scp->cmd_len = 12;
5675 scp->use_sg = 0;
5676 gdth_do_cmd(scp, &gdtcmd, cmnd, 10);
5677 scsi_release_command(scp);
5678 scsi_free_host_dev(sdev);
5679 #endif
5680 #endif
5681 }
5682 printk("Done.\n");
5683
5684 #ifdef GDTH_STATISTICS
5685 del_timer(&gdth_timer);
5686 #endif
5687 return NOTIFY_OK;
5688 }
5689
5690 static struct scsi_host_template driver_template = {
5691 .proc_name = "gdth",
5692 .proc_info = gdth_proc_info,
5693 .name = "GDT SCSI Disk Array Controller",
5694 .detect = gdth_detect,
5695 .release = gdth_release,
5696 .info = gdth_info,
5697 .queuecommand = gdth_queuecommand,
5698 .eh_bus_reset_handler = gdth_eh_bus_reset,
5699 .bios_param = gdth_bios_param,
5700 .can_queue = GDTH_MAXCMDS,
5701 .this_id = -1,
5702 .sg_tablesize = GDTH_MAXSG,
5703 .cmd_per_lun = GDTH_MAXC_P_L,
5704 .unchecked_isa_dma = 1,
5705 .use_clustering = ENABLE_CLUSTERING,
5706 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
5707 .use_new_eh_code = 1,
5708 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
5709 .highmem_io = 1,
5710 #endif
5711 #endif
5712 };
5713
5714 #include "scsi_module.c"
5715 #ifndef MODULE
5716 __setup("gdth=", option_setup);
5717 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree