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ath9k: unify edma and non-edma tx code, improve tx fifo handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / xmit.c
blobec012b4317afb1ccdf5ea4b7014ac7448094f38d
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18 #include "ar9003_mac.h"
19
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34
35 static u16 bits_per_symbol[][2] = {
36 /* 20MHz 40MHz */
37 { 26, 54 }, /* 0: BPSK */
38 { 52, 108 }, /* 1: QPSK 1/2 */
39 { 78, 162 }, /* 2: QPSK 3/4 */
40 { 104, 216 }, /* 3: 16-QAM 1/2 */
41 { 156, 324 }, /* 4: 16-QAM 3/4 */
42 { 208, 432 }, /* 5: 64-QAM 2/3 */
43 { 234, 486 }, /* 6: 64-QAM 3/4 */
44 { 260, 540 }, /* 7: 64-QAM 5/6 */
45 };
46
47 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
48
49 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
50 struct ath_atx_tid *tid,
51 struct list_head *bf_head);
52 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
53 struct ath_txq *txq, struct list_head *bf_q,
54 struct ath_tx_status *ts, int txok, int sendbar);
55 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
56 struct list_head *head, bool internal);
57 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
58 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
59 struct ath_tx_status *ts, int nframes, int nbad,
60 int txok, bool update_rc);
61 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
62 int seqno);
63
64 enum {
65 MCS_HT20,
66 MCS_HT20_SGI,
67 MCS_HT40,
68 MCS_HT40_SGI,
69 };
70
71 static int ath_max_4ms_framelen[4][32] = {
72 [MCS_HT20] = {
73 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
74 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
75 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
76 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
77 },
78 [MCS_HT20_SGI] = {
79 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
80 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
81 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
82 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
83 },
84 [MCS_HT40] = {
85 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
86 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
87 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
88 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
89 },
90 [MCS_HT40_SGI] = {
91 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
92 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
93 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
94 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
95 }
96 };
97
98 /*********************/
99 /* Aggregation logic */
100 /*********************/
101
102 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
103 {
104 struct ath_atx_ac *ac = tid->ac;
105
106 if (tid->paused)
107 return;
108
109 if (tid->sched)
110 return;
111
112 tid->sched = true;
113 list_add_tail(&tid->list, &ac->tid_q);
114
115 if (ac->sched)
116 return;
117
118 ac->sched = true;
119 list_add_tail(&ac->list, &txq->axq_acq);
120 }
121
122 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
123 {
124 struct ath_txq *txq = tid->ac->txq;
125
126 WARN_ON(!tid->paused);
127
128 spin_lock_bh(&txq->axq_lock);
129 tid->paused = false;
130
131 if (list_empty(&tid->buf_q))
132 goto unlock;
133
134 ath_tx_queue_tid(txq, tid);
135 ath_txq_schedule(sc, txq);
136 unlock:
137 spin_unlock_bh(&txq->axq_lock);
138 }
139
140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
141 {
142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 sizeof(tx_info->rate_driver_data));
145 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
146 }
147
148 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
149 {
150 struct ath_txq *txq = tid->ac->txq;
151 struct ath_buf *bf;
152 struct list_head bf_head;
153 struct ath_tx_status ts;
154 struct ath_frame_info *fi;
155
156 INIT_LIST_HEAD(&bf_head);
157
158 memset(&ts, 0, sizeof(ts));
159 spin_lock_bh(&txq->axq_lock);
160
161 while (!list_empty(&tid->buf_q)) {
162 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
163 list_move_tail(&bf->list, &bf_head);
164
165 spin_unlock_bh(&txq->axq_lock);
166 fi = get_frame_info(bf->bf_mpdu);
167 if (fi->retries) {
168 ath_tx_update_baw(sc, tid, fi->seqno);
169 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
170 } else {
171 ath_tx_send_normal(sc, txq, NULL, &bf_head);
172 }
173 spin_lock_bh(&txq->axq_lock);
174 }
175
176 spin_unlock_bh(&txq->axq_lock);
177 }
178
179 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
180 int seqno)
181 {
182 int index, cindex;
183
184 index = ATH_BA_INDEX(tid->seq_start, seqno);
185 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
186
187 __clear_bit(cindex, tid->tx_buf);
188
189 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
190 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
191 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
192 }
193 }
194
195 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
196 u16 seqno)
197 {
198 int index, cindex;
199
200 index = ATH_BA_INDEX(tid->seq_start, seqno);
201 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
202 __set_bit(cindex, tid->tx_buf);
203
204 if (index >= ((tid->baw_tail - tid->baw_head) &
205 (ATH_TID_MAX_BUFS - 1))) {
206 tid->baw_tail = cindex;
207 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
208 }
209 }
210
211 /*
212 * TODO: For frame(s) that are in the retry state, we will reuse the
213 * sequence number(s) without setting the retry bit. The
214 * alternative is to give up on these and BAR the receiver's window
215 * forward.
216 */
217 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
218 struct ath_atx_tid *tid)
219
220 {
221 struct ath_buf *bf;
222 struct list_head bf_head;
223 struct ath_tx_status ts;
224 struct ath_frame_info *fi;
225
226 memset(&ts, 0, sizeof(ts));
227 INIT_LIST_HEAD(&bf_head);
228
229 for (;;) {
230 if (list_empty(&tid->buf_q))
231 break;
232
233 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
234 list_move_tail(&bf->list, &bf_head);
235
236 fi = get_frame_info(bf->bf_mpdu);
237 if (fi->retries)
238 ath_tx_update_baw(sc, tid, fi->seqno);
239
240 spin_unlock(&txq->axq_lock);
241 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
242 spin_lock(&txq->axq_lock);
243 }
244
245 tid->seq_next = tid->seq_start;
246 tid->baw_tail = tid->baw_head;
247 }
248
249 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
250 struct sk_buff *skb)
251 {
252 struct ath_frame_info *fi = get_frame_info(skb);
253 struct ieee80211_hdr *hdr;
254
255 TX_STAT_INC(txq->axq_qnum, a_retries);
256 if (fi->retries++ > 0)
257 return;
258
259 hdr = (struct ieee80211_hdr *)skb->data;
260 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
261 }
262
263 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
264 {
265 struct ath_buf *bf = NULL;
266
267 spin_lock_bh(&sc->tx.txbuflock);
268
269 if (unlikely(list_empty(&sc->tx.txbuf))) {
270 spin_unlock_bh(&sc->tx.txbuflock);
271 return NULL;
272 }
273
274 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
275 list_del(&bf->list);
276
277 spin_unlock_bh(&sc->tx.txbuflock);
278
279 return bf;
280 }
281
282 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
283 {
284 spin_lock_bh(&sc->tx.txbuflock);
285 list_add_tail(&bf->list, &sc->tx.txbuf);
286 spin_unlock_bh(&sc->tx.txbuflock);
287 }
288
289 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
290 {
291 struct ath_buf *tbf;
292
293 tbf = ath_tx_get_buffer(sc);
294 if (WARN_ON(!tbf))
295 return NULL;
296
297 ATH_TXBUF_RESET(tbf);
298
299 tbf->bf_mpdu = bf->bf_mpdu;
300 tbf->bf_buf_addr = bf->bf_buf_addr;
301 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
302 tbf->bf_state = bf->bf_state;
303
304 return tbf;
305 }
306
307 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
308 struct ath_tx_status *ts, int txok,
309 int *nframes, int *nbad)
310 {
311 struct ath_frame_info *fi;
312 u16 seq_st = 0;
313 u32 ba[WME_BA_BMP_SIZE >> 5];
314 int ba_index;
315 int isaggr = 0;
316
317 *nbad = 0;
318 *nframes = 0;
319
320 isaggr = bf_isaggr(bf);
321 if (isaggr) {
322 seq_st = ts->ts_seqnum;
323 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
324 }
325
326 while (bf) {
327 fi = get_frame_info(bf->bf_mpdu);
328 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
329
330 (*nframes)++;
331 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
332 (*nbad)++;
333
334 bf = bf->bf_next;
335 }
336 }
337
338
339 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
340 struct ath_buf *bf, struct list_head *bf_q,
341 struct ath_tx_status *ts, int txok, bool retry)
342 {
343 struct ath_node *an = NULL;
344 struct sk_buff *skb;
345 struct ieee80211_sta *sta;
346 struct ieee80211_hw *hw = sc->hw;
347 struct ieee80211_hdr *hdr;
348 struct ieee80211_tx_info *tx_info;
349 struct ath_atx_tid *tid = NULL;
350 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
351 struct list_head bf_head, bf_pending;
352 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
353 u32 ba[WME_BA_BMP_SIZE >> 5];
354 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
355 bool rc_update = true;
356 struct ieee80211_tx_rate rates[4];
357 struct ath_frame_info *fi;
358 int nframes;
359 u8 tidno;
360 bool clear_filter;
361
362 skb = bf->bf_mpdu;
363 hdr = (struct ieee80211_hdr *)skb->data;
364
365 tx_info = IEEE80211_SKB_CB(skb);
366
367 memcpy(rates, tx_info->control.rates, sizeof(rates));
368
369 rcu_read_lock();
370
371 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
372 if (!sta) {
373 rcu_read_unlock();
374
375 INIT_LIST_HEAD(&bf_head);
376 while (bf) {
377 bf_next = bf->bf_next;
378
379 bf->bf_state.bf_type |= BUF_XRETRY;
380 if (!bf->bf_stale || bf_next != NULL)
381 list_move_tail(&bf->list, &bf_head);
382
383 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
384 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
385 0, 0);
386
387 bf = bf_next;
388 }
389 return;
390 }
391
392 an = (struct ath_node *)sta->drv_priv;
393 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
394 tid = ATH_AN_2_TID(an, tidno);
395
396 /*
397 * The hardware occasionally sends a tx status for the wrong TID.
398 * In this case, the BA status cannot be considered valid and all
399 * subframes need to be retransmitted
400 */
401 if (tidno != ts->tid)
402 txok = false;
403
404 isaggr = bf_isaggr(bf);
405 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
406
407 if (isaggr && txok) {
408 if (ts->ts_flags & ATH9K_TX_BA) {
409 seq_st = ts->ts_seqnum;
410 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
411 } else {
412 /*
413 * AR5416 can become deaf/mute when BA
414 * issue happens. Chip needs to be reset.
415 * But AP code may have sychronization issues
416 * when perform internal reset in this routine.
417 * Only enable reset in STA mode for now.
418 */
419 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
420 needreset = 1;
421 }
422 }
423
424 INIT_LIST_HEAD(&bf_pending);
425 INIT_LIST_HEAD(&bf_head);
426
427 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
428 while (bf) {
429 txfail = txpending = sendbar = 0;
430 bf_next = bf->bf_next;
431
432 skb = bf->bf_mpdu;
433 tx_info = IEEE80211_SKB_CB(skb);
434 fi = get_frame_info(skb);
435
436 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
437 /* transmit completion, subframe is
438 * acked by block ack */
439 acked_cnt++;
440 } else if (!isaggr && txok) {
441 /* transmit completion */
442 acked_cnt++;
443 } else {
444 if ((tid->state & AGGR_CLEANUP) || !retry) {
445 /*
446 * cleanup in progress, just fail
447 * the un-acked sub-frames
448 */
449 txfail = 1;
450 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
451 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
452 !an->sleeping)
453 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
454
455 clear_filter = true;
456 txpending = 1;
457 } else {
458 bf->bf_state.bf_type |= BUF_XRETRY;
459 txfail = 1;
460 sendbar = 1;
461 txfail_cnt++;
462 }
463 }
464
465 /*
466 * Make sure the last desc is reclaimed if it
467 * not a holding desc.
468 */
469 if (!bf_last->bf_stale || bf_next != NULL)
470 list_move_tail(&bf->list, &bf_head);
471 else
472 INIT_LIST_HEAD(&bf_head);
473
474 if (!txpending || (tid->state & AGGR_CLEANUP)) {
475 /*
476 * complete the acked-ones/xretried ones; update
477 * block-ack window
478 */
479 spin_lock_bh(&txq->axq_lock);
480 ath_tx_update_baw(sc, tid, fi->seqno);
481 spin_unlock_bh(&txq->axq_lock);
482
483 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
484 memcpy(tx_info->control.rates, rates, sizeof(rates));
485 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
486 rc_update = false;
487 } else {
488 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
489 }
490
491 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
492 !txfail, sendbar);
493 } else {
494 /* retry the un-acked ones */
495 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
496 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
497 if (bf->bf_next == NULL && bf_last->bf_stale) {
498 struct ath_buf *tbf;
499
500 tbf = ath_clone_txbuf(sc, bf_last);
501 /*
502 * Update tx baw and complete the
503 * frame with failed status if we
504 * run out of tx buf.
505 */
506 if (!tbf) {
507 spin_lock_bh(&txq->axq_lock);
508 ath_tx_update_baw(sc, tid, fi->seqno);
509 spin_unlock_bh(&txq->axq_lock);
510
511 bf->bf_state.bf_type |=
512 BUF_XRETRY;
513 ath_tx_rc_status(sc, bf, ts, nframes,
514 nbad, 0, false);
515 ath_tx_complete_buf(sc, bf, txq,
516 &bf_head,
517 ts, 0, 0);
518 break;
519 }
520
521 ath9k_hw_cleartxdesc(sc->sc_ah,
522 tbf->bf_desc);
523 list_add_tail(&tbf->list, &bf_head);
524 } else {
525 /*
526 * Clear descriptor status words for
527 * software retry
528 */
529 ath9k_hw_cleartxdesc(sc->sc_ah,
530 bf->bf_desc);
531 }
532 }
533
534 /*
535 * Put this buffer to the temporary pending
536 * queue to retain ordering
537 */
538 list_splice_tail_init(&bf_head, &bf_pending);
539 }
540
541 bf = bf_next;
542 }
543
544 /* prepend un-acked frames to the beginning of the pending frame queue */
545 if (!list_empty(&bf_pending)) {
546 if (an->sleeping)
547 ieee80211_sta_set_tim(sta);
548
549 spin_lock_bh(&txq->axq_lock);
550 if (clear_filter)
551 tid->ac->clear_ps_filter = true;
552 list_splice(&bf_pending, &tid->buf_q);
553 ath_tx_queue_tid(txq, tid);
554 spin_unlock_bh(&txq->axq_lock);
555 }
556
557 if (tid->state & AGGR_CLEANUP) {
558 ath_tx_flush_tid(sc, tid);
559
560 if (tid->baw_head == tid->baw_tail) {
561 tid->state &= ~AGGR_ADDBA_COMPLETE;
562 tid->state &= ~AGGR_CLEANUP;
563 }
564 }
565
566 rcu_read_unlock();
567
568 if (needreset) {
569 spin_unlock_bh(&sc->sc_pcu_lock);
570 ath_reset(sc, false);
571 spin_lock_bh(&sc->sc_pcu_lock);
572 }
573 }
574
575 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
576 struct ath_atx_tid *tid)
577 {
578 struct sk_buff *skb;
579 struct ieee80211_tx_info *tx_info;
580 struct ieee80211_tx_rate *rates;
581 u32 max_4ms_framelen, frmlen;
582 u16 aggr_limit, legacy = 0;
583 int i;
584
585 skb = bf->bf_mpdu;
586 tx_info = IEEE80211_SKB_CB(skb);
587 rates = tx_info->control.rates;
588
589 /*
590 * Find the lowest frame length among the rate series that will have a
591 * 4ms transmit duration.
592 * TODO - TXOP limit needs to be considered.
593 */
594 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
595
596 for (i = 0; i < 4; i++) {
597 if (rates[i].count) {
598 int modeidx;
599 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
600 legacy = 1;
601 break;
602 }
603
604 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
605 modeidx = MCS_HT40;
606 else
607 modeidx = MCS_HT20;
608
609 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
610 modeidx++;
611
612 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
613 max_4ms_framelen = min(max_4ms_framelen, frmlen);
614 }
615 }
616
617 /*
618 * limit aggregate size by the minimum rate if rate selected is
619 * not a probe rate, if rate selected is a probe rate then
620 * avoid aggregation of this packet.
621 */
622 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
623 return 0;
624
625 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
626 aggr_limit = min((max_4ms_framelen * 3) / 8,
627 (u32)ATH_AMPDU_LIMIT_MAX);
628 else
629 aggr_limit = min(max_4ms_framelen,
630 (u32)ATH_AMPDU_LIMIT_MAX);
631
632 /*
633 * h/w can accept aggregates up to 16 bit lengths (65535).
634 * The IE, however can hold up to 65536, which shows up here
635 * as zero. Ignore 65536 since we are constrained by hw.
636 */
637 if (tid->an->maxampdu)
638 aggr_limit = min(aggr_limit, tid->an->maxampdu);
639
640 return aggr_limit;
641 }
642
643 /*
644 * Returns the number of delimiters to be added to
645 * meet the minimum required mpdudensity.
646 */
647 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
648 struct ath_buf *bf, u16 frmlen)
649 {
650 struct sk_buff *skb = bf->bf_mpdu;
651 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
652 u32 nsymbits, nsymbols;
653 u16 minlen;
654 u8 flags, rix;
655 int width, streams, half_gi, ndelim, mindelim;
656 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
657
658 /* Select standard number of delimiters based on frame length alone */
659 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
660
661 /*
662 * If encryption enabled, hardware requires some more padding between
663 * subframes.
664 * TODO - this could be improved to be dependent on the rate.
665 * The hardware can keep up at lower rates, but not higher rates
666 */
667 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
668 ndelim += ATH_AGGR_ENCRYPTDELIM;
669
670 /*
671 * Convert desired mpdu density from microeconds to bytes based
672 * on highest rate in rate series (i.e. first rate) to determine
673 * required minimum length for subframe. Take into account
674 * whether high rate is 20 or 40Mhz and half or full GI.
675 *
676 * If there is no mpdu density restriction, no further calculation
677 * is needed.
678 */
679
680 if (tid->an->mpdudensity == 0)
681 return ndelim;
682
683 rix = tx_info->control.rates[0].idx;
684 flags = tx_info->control.rates[0].flags;
685 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
686 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
687
688 if (half_gi)
689 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
690 else
691 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
692
693 if (nsymbols == 0)
694 nsymbols = 1;
695
696 streams = HT_RC_2_STREAMS(rix);
697 nsymbits = bits_per_symbol[rix % 8][width] * streams;
698 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
699
700 if (frmlen < minlen) {
701 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
702 ndelim = max(mindelim, ndelim);
703 }
704
705 return ndelim;
706 }
707
708 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
709 struct ath_txq *txq,
710 struct ath_atx_tid *tid,
711 struct list_head *bf_q,
712 int *aggr_len)
713 {
714 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
715 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
716 int rl = 0, nframes = 0, ndelim, prev_al = 0;
717 u16 aggr_limit = 0, al = 0, bpad = 0,
718 al_delta, h_baw = tid->baw_size / 2;
719 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
720 struct ieee80211_tx_info *tx_info;
721 struct ath_frame_info *fi;
722
723 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
724
725 do {
726 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
727 fi = get_frame_info(bf->bf_mpdu);
728
729 /* do not step over block-ack window */
730 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
731 status = ATH_AGGR_BAW_CLOSED;
732 break;
733 }
734
735 if (!rl) {
736 aggr_limit = ath_lookup_rate(sc, bf, tid);
737 rl = 1;
738 }
739
740 /* do not exceed aggregation limit */
741 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
742
743 if (nframes &&
744 (aggr_limit < (al + bpad + al_delta + prev_al))) {
745 status = ATH_AGGR_LIMITED;
746 break;
747 }
748
749 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
750 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
751 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
752 break;
753
754 /* do not exceed subframe limit */
755 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
756 status = ATH_AGGR_LIMITED;
757 break;
758 }
759 nframes++;
760
761 /* add padding for previous frame to aggregation length */
762 al += bpad + al_delta;
763
764 /*
765 * Get the delimiters needed to meet the MPDU
766 * density for this node.
767 */
768 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
769 bpad = PADBYTES(al_delta) + (ndelim << 2);
770
771 bf->bf_next = NULL;
772 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
773
774 /* link buffers of this frame to the aggregate */
775 if (!fi->retries)
776 ath_tx_addto_baw(sc, tid, fi->seqno);
777 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
778 list_move_tail(&bf->list, bf_q);
779 if (bf_prev) {
780 bf_prev->bf_next = bf;
781 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
782 bf->bf_daddr);
783 }
784 bf_prev = bf;
785
786 } while (!list_empty(&tid->buf_q));
787
788 *aggr_len = al;
789
790 return status;
791 #undef PADBYTES
792 }
793
794 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
795 struct ath_atx_tid *tid)
796 {
797 struct ath_buf *bf;
798 enum ATH_AGGR_STATUS status;
799 struct ath_frame_info *fi;
800 struct list_head bf_q;
801 int aggr_len;
802
803 do {
804 if (list_empty(&tid->buf_q))
805 return;
806
807 INIT_LIST_HEAD(&bf_q);
808
809 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
810
811 /*
812 * no frames picked up to be aggregated;
813 * block-ack window is not open.
814 */
815 if (list_empty(&bf_q))
816 break;
817
818 bf = list_first_entry(&bf_q, struct ath_buf, list);
819 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
820
821 if (tid->ac->clear_ps_filter) {
822 tid->ac->clear_ps_filter = false;
823 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
824 }
825
826 /* if only one frame, send as non-aggregate */
827 if (bf == bf->bf_lastbf) {
828 fi = get_frame_info(bf->bf_mpdu);
829
830 bf->bf_state.bf_type &= ~BUF_AGGR;
831 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
832 ath_buf_set_rate(sc, bf, fi->framelen);
833 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
834 continue;
835 }
836
837 /* setup first desc of aggregate */
838 bf->bf_state.bf_type |= BUF_AGGR;
839 ath_buf_set_rate(sc, bf, aggr_len);
840 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
841
842 /* anchor last desc of aggregate */
843 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
844
845 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
846 TX_STAT_INC(txq->axq_qnum, a_aggr);
847
848 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
849 status != ATH_AGGR_BAW_CLOSED);
850 }
851
852 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
853 u16 tid, u16 *ssn)
854 {
855 struct ath_atx_tid *txtid;
856 struct ath_node *an;
857
858 an = (struct ath_node *)sta->drv_priv;
859 txtid = ATH_AN_2_TID(an, tid);
860
861 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
862 return -EAGAIN;
863
864 txtid->state |= AGGR_ADDBA_PROGRESS;
865 txtid->paused = true;
866 *ssn = txtid->seq_start = txtid->seq_next;
867
868 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
869 txtid->baw_head = txtid->baw_tail = 0;
870
871 return 0;
872 }
873
874 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
875 {
876 struct ath_node *an = (struct ath_node *)sta->drv_priv;
877 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
878 struct ath_txq *txq = txtid->ac->txq;
879
880 if (txtid->state & AGGR_CLEANUP)
881 return;
882
883 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
884 txtid->state &= ~AGGR_ADDBA_PROGRESS;
885 return;
886 }
887
888 spin_lock_bh(&txq->axq_lock);
889 txtid->paused = true;
890
891 /*
892 * If frames are still being transmitted for this TID, they will be
893 * cleaned up during tx completion. To prevent race conditions, this
894 * TID can only be reused after all in-progress subframes have been
895 * completed.
896 */
897 if (txtid->baw_head != txtid->baw_tail)
898 txtid->state |= AGGR_CLEANUP;
899 else
900 txtid->state &= ~AGGR_ADDBA_COMPLETE;
901 spin_unlock_bh(&txq->axq_lock);
902
903 ath_tx_flush_tid(sc, txtid);
904 }
905
906 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
907 {
908 struct ath_atx_tid *tid;
909 struct ath_atx_ac *ac;
910 struct ath_txq *txq;
911 bool buffered = false;
912 int tidno;
913
914 for (tidno = 0, tid = &an->tid[tidno];
915 tidno < WME_NUM_TID; tidno++, tid++) {
916
917 if (!tid->sched)
918 continue;
919
920 ac = tid->ac;
921 txq = ac->txq;
922
923 spin_lock_bh(&txq->axq_lock);
924
925 if (!list_empty(&tid->buf_q))
926 buffered = true;
927
928 tid->sched = false;
929 list_del(&tid->list);
930
931 if (ac->sched) {
932 ac->sched = false;
933 list_del(&ac->list);
934 }
935
936 spin_unlock_bh(&txq->axq_lock);
937 }
938
939 return buffered;
940 }
941
942 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
943 {
944 struct ath_atx_tid *tid;
945 struct ath_atx_ac *ac;
946 struct ath_txq *txq;
947 int tidno;
948
949 for (tidno = 0, tid = &an->tid[tidno];
950 tidno < WME_NUM_TID; tidno++, tid++) {
951
952 ac = tid->ac;
953 txq = ac->txq;
954
955 spin_lock_bh(&txq->axq_lock);
956 ac->clear_ps_filter = true;
957
958 if (!list_empty(&tid->buf_q) && !tid->paused) {
959 ath_tx_queue_tid(txq, tid);
960 ath_txq_schedule(sc, txq);
961 }
962
963 spin_unlock_bh(&txq->axq_lock);
964 }
965 }
966
967 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
968 {
969 struct ath_atx_tid *txtid;
970 struct ath_node *an;
971
972 an = (struct ath_node *)sta->drv_priv;
973
974 if (sc->sc_flags & SC_OP_TXAGGR) {
975 txtid = ATH_AN_2_TID(an, tid);
976 txtid->baw_size =
977 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
978 txtid->state |= AGGR_ADDBA_COMPLETE;
979 txtid->state &= ~AGGR_ADDBA_PROGRESS;
980 ath_tx_resume_tid(sc, txtid);
981 }
982 }
983
984 /********************/
985 /* Queue Management */
986 /********************/
987
988 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
989 struct ath_txq *txq)
990 {
991 struct ath_atx_ac *ac, *ac_tmp;
992 struct ath_atx_tid *tid, *tid_tmp;
993
994 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
995 list_del(&ac->list);
996 ac->sched = false;
997 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
998 list_del(&tid->list);
999 tid->sched = false;
1000 ath_tid_drain(sc, txq, tid);
1001 }
1002 }
1003 }
1004
1005 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1006 {
1007 struct ath_hw *ah = sc->sc_ah;
1008 struct ath_common *common = ath9k_hw_common(ah);
1009 struct ath9k_tx_queue_info qi;
1010 static const int subtype_txq_to_hwq[] = {
1011 [WME_AC_BE] = ATH_TXQ_AC_BE,
1012 [WME_AC_BK] = ATH_TXQ_AC_BK,
1013 [WME_AC_VI] = ATH_TXQ_AC_VI,
1014 [WME_AC_VO] = ATH_TXQ_AC_VO,
1015 };
1016 int axq_qnum, i;
1017
1018 memset(&qi, 0, sizeof(qi));
1019 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1020 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1021 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1022 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1023 qi.tqi_physCompBuf = 0;
1024
1025 /*
1026 * Enable interrupts only for EOL and DESC conditions.
1027 * We mark tx descriptors to receive a DESC interrupt
1028 * when a tx queue gets deep; otherwise waiting for the
1029 * EOL to reap descriptors. Note that this is done to
1030 * reduce interrupt load and this only defers reaping
1031 * descriptors, never transmitting frames. Aside from
1032 * reducing interrupts this also permits more concurrency.
1033 * The only potential downside is if the tx queue backs
1034 * up in which case the top half of the kernel may backup
1035 * due to a lack of tx descriptors.
1036 *
1037 * The UAPSD queue is an exception, since we take a desc-
1038 * based intr on the EOSP frames.
1039 */
1040 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1041 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1042 TXQ_FLAG_TXERRINT_ENABLE;
1043 } else {
1044 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1045 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1046 else
1047 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1048 TXQ_FLAG_TXDESCINT_ENABLE;
1049 }
1050 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1051 if (axq_qnum == -1) {
1052 /*
1053 * NB: don't print a message, this happens
1054 * normally on parts with too few tx queues
1055 */
1056 return NULL;
1057 }
1058 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1059 ath_err(common, "qnum %u out of range, max %zu!\n",
1060 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1061 ath9k_hw_releasetxqueue(ah, axq_qnum);
1062 return NULL;
1063 }
1064 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1065 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1066
1067 txq->axq_qnum = axq_qnum;
1068 txq->mac80211_qnum = -1;
1069 txq->axq_link = NULL;
1070 INIT_LIST_HEAD(&txq->axq_q);
1071 INIT_LIST_HEAD(&txq->axq_acq);
1072 spin_lock_init(&txq->axq_lock);
1073 txq->axq_depth = 0;
1074 txq->axq_ampdu_depth = 0;
1075 txq->axq_tx_inprogress = false;
1076 sc->tx.txqsetup |= 1<<axq_qnum;
1077
1078 txq->txq_headidx = txq->txq_tailidx = 0;
1079 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1080 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1081 }
1082 return &sc->tx.txq[axq_qnum];
1083 }
1084
1085 int ath_txq_update(struct ath_softc *sc, int qnum,
1086 struct ath9k_tx_queue_info *qinfo)
1087 {
1088 struct ath_hw *ah = sc->sc_ah;
1089 int error = 0;
1090 struct ath9k_tx_queue_info qi;
1091
1092 if (qnum == sc->beacon.beaconq) {
1093 /*
1094 * XXX: for beacon queue, we just save the parameter.
1095 * It will be picked up by ath_beaconq_config when
1096 * it's necessary.
1097 */
1098 sc->beacon.beacon_qi = *qinfo;
1099 return 0;
1100 }
1101
1102 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1103
1104 ath9k_hw_get_txq_props(ah, qnum, &qi);
1105 qi.tqi_aifs = qinfo->tqi_aifs;
1106 qi.tqi_cwmin = qinfo->tqi_cwmin;
1107 qi.tqi_cwmax = qinfo->tqi_cwmax;
1108 qi.tqi_burstTime = qinfo->tqi_burstTime;
1109 qi.tqi_readyTime = qinfo->tqi_readyTime;
1110
1111 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1112 ath_err(ath9k_hw_common(sc->sc_ah),
1113 "Unable to update hardware queue %u!\n", qnum);
1114 error = -EIO;
1115 } else {
1116 ath9k_hw_resettxqueue(ah, qnum);
1117 }
1118
1119 return error;
1120 }
1121
1122 int ath_cabq_update(struct ath_softc *sc)
1123 {
1124 struct ath9k_tx_queue_info qi;
1125 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1126 int qnum = sc->beacon.cabq->axq_qnum;
1127
1128 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1129 /*
1130 * Ensure the readytime % is within the bounds.
1131 */
1132 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1133 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1134 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1135 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1136
1137 qi.tqi_readyTime = (cur_conf->beacon_interval *
1138 sc->config.cabqReadytime) / 100;
1139 ath_txq_update(sc, qnum, &qi);
1140
1141 return 0;
1142 }
1143
1144 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1145 {
1146 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1147 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1148 }
1149
1150 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1151 struct list_head *list, bool retry_tx)
1152 {
1153 struct ath_buf *bf, *lastbf;
1154 struct list_head bf_head;
1155 struct ath_tx_status ts;
1156
1157 memset(&ts, 0, sizeof(ts));
1158 INIT_LIST_HEAD(&bf_head);
1159
1160 while (!list_empty(list)) {
1161 bf = list_first_entry(list, struct ath_buf, list);
1162
1163 if (bf->bf_stale) {
1164 list_del(&bf->list);
1165
1166 ath_tx_return_buffer(sc, bf);
1167 continue;
1168 }
1169
1170 lastbf = bf->bf_lastbf;
1171 list_cut_position(&bf_head, list, &lastbf->list);
1172
1173 txq->axq_depth--;
1174 if (bf_is_ampdu_not_probing(bf))
1175 txq->axq_ampdu_depth--;
1176
1177 spin_unlock_bh(&txq->axq_lock);
1178 if (bf_isampdu(bf))
1179 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1180 retry_tx);
1181 else
1182 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1183 spin_lock_bh(&txq->axq_lock);
1184 }
1185 }
1186
1187 /*
1188 * Drain a given TX queue (could be Beacon or Data)
1189 *
1190 * This assumes output has been stopped and
1191 * we do not need to block ath_tx_tasklet.
1192 */
1193 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1194 {
1195 spin_lock_bh(&txq->axq_lock);
1196 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1197 int idx = txq->txq_tailidx;
1198
1199 while (!list_empty(&txq->txq_fifo[idx])) {
1200 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1201 retry_tx);
1202
1203 INCR(idx, ATH_TXFIFO_DEPTH);
1204 }
1205 txq->txq_tailidx = idx;
1206 }
1207
1208 txq->axq_link = NULL;
1209 txq->axq_tx_inprogress = false;
1210 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1211
1212 /* flush any pending frames if aggregation is enabled */
1213 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1214 ath_txq_drain_pending_buffers(sc, txq);
1215
1216 spin_unlock_bh(&txq->axq_lock);
1217 }
1218
1219 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1220 {
1221 struct ath_hw *ah = sc->sc_ah;
1222 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1223 struct ath_txq *txq;
1224 int i, npend = 0;
1225
1226 if (sc->sc_flags & SC_OP_INVALID)
1227 return true;
1228
1229 ath9k_hw_abort_tx_dma(ah);
1230
1231 /* Check if any queue remains active */
1232 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1233 if (!ATH_TXQ_SETUP(sc, i))
1234 continue;
1235
1236 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1237 }
1238
1239 if (npend)
1240 ath_err(common, "Failed to stop TX DMA!\n");
1241
1242 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1243 if (!ATH_TXQ_SETUP(sc, i))
1244 continue;
1245
1246 /*
1247 * The caller will resume queues with ieee80211_wake_queues.
1248 * Mark the queue as not stopped to prevent ath_tx_complete
1249 * from waking the queue too early.
1250 */
1251 txq = &sc->tx.txq[i];
1252 txq->stopped = false;
1253 ath_draintxq(sc, txq, retry_tx);
1254 }
1255
1256 return !npend;
1257 }
1258
1259 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1260 {
1261 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1262 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1263 }
1264
1265 /* For each axq_acq entry, for each tid, try to schedule packets
1266 * for transmit until ampdu_depth has reached min Q depth.
1267 */
1268 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1269 {
1270 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1271 struct ath_atx_tid *tid, *last_tid;
1272
1273 if (list_empty(&txq->axq_acq) ||
1274 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1275 return;
1276
1277 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1278 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1279
1280 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1281 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1282 list_del(&ac->list);
1283 ac->sched = false;
1284
1285 while (!list_empty(&ac->tid_q)) {
1286 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1287 list);
1288 list_del(&tid->list);
1289 tid->sched = false;
1290
1291 if (tid->paused)
1292 continue;
1293
1294 ath_tx_sched_aggr(sc, txq, tid);
1295
1296 /*
1297 * add tid to round-robin queue if more frames
1298 * are pending for the tid
1299 */
1300 if (!list_empty(&tid->buf_q))
1301 ath_tx_queue_tid(txq, tid);
1302
1303 if (tid == last_tid ||
1304 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1305 break;
1306 }
1307
1308 if (!list_empty(&ac->tid_q)) {
1309 if (!ac->sched) {
1310 ac->sched = true;
1311 list_add_tail(&ac->list, &txq->axq_acq);
1312 }
1313 }
1314
1315 if (ac == last_ac ||
1316 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1317 return;
1318 }
1319 }
1320
1321 /***********/
1322 /* TX, DMA */
1323 /***********/
1324
1325 /*
1326 * Insert a chain of ath_buf (descriptors) on a txq and
1327 * assume the descriptors are already chained together by caller.
1328 */
1329 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1330 struct list_head *head, bool internal)
1331 {
1332 struct ath_hw *ah = sc->sc_ah;
1333 struct ath_common *common = ath9k_hw_common(ah);
1334 struct ath_buf *bf, *bf_last;
1335 bool puttxbuf = false;
1336 bool edma;
1337
1338 /*
1339 * Insert the frame on the outbound list and
1340 * pass it on to the hardware.
1341 */
1342
1343 if (list_empty(head))
1344 return;
1345
1346 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1347 bf = list_first_entry(head, struct ath_buf, list);
1348 bf_last = list_entry(head->prev, struct ath_buf, list);
1349
1350 ath_dbg(common, ATH_DBG_QUEUE,
1351 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1352
1353 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1354 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1355 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1356 puttxbuf = true;
1357 } else {
1358 list_splice_tail_init(head, &txq->axq_q);
1359
1360 if (txq->axq_link) {
1361 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1362 ath_dbg(common, ATH_DBG_XMIT,
1363 "link[%u] (%p)=%llx (%p)\n",
1364 txq->axq_qnum, txq->axq_link,
1365 ito64(bf->bf_daddr), bf->bf_desc);
1366 } else if (!edma)
1367 puttxbuf = true;
1368
1369 txq->axq_link = bf_last->bf_desc;
1370 }
1371
1372 if (puttxbuf) {
1373 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1374 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1375 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1376 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1377 }
1378
1379 if (!edma) {
1380 TX_STAT_INC(txq->axq_qnum, txstart);
1381 ath9k_hw_txstart(ah, txq->axq_qnum);
1382 }
1383
1384 if (!internal) {
1385 txq->axq_depth++;
1386 if (bf_is_ampdu_not_probing(bf))
1387 txq->axq_ampdu_depth++;
1388 }
1389 }
1390
1391 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1392 struct ath_buf *bf, struct ath_tx_control *txctl)
1393 {
1394 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1395 struct list_head bf_head;
1396
1397 bf->bf_state.bf_type |= BUF_AMPDU;
1398
1399 /*
1400 * Do not queue to h/w when any of the following conditions is true:
1401 * - there are pending frames in software queue
1402 * - the TID is currently paused for ADDBA/BAR request
1403 * - seqno is not within block-ack window
1404 * - h/w queue depth exceeds low water mark
1405 */
1406 if (!list_empty(&tid->buf_q) || tid->paused ||
1407 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1408 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1409 /*
1410 * Add this frame to software queue for scheduling later
1411 * for aggregation.
1412 */
1413 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1414 list_add_tail(&bf->list, &tid->buf_q);
1415 ath_tx_queue_tid(txctl->txq, tid);
1416 return;
1417 }
1418
1419 INIT_LIST_HEAD(&bf_head);
1420 list_add(&bf->list, &bf_head);
1421
1422 /* Add sub-frame to BAW */
1423 if (!fi->retries)
1424 ath_tx_addto_baw(sc, tid, fi->seqno);
1425
1426 /* Queue to h/w without aggregation */
1427 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1428 bf->bf_lastbf = bf;
1429 ath_buf_set_rate(sc, bf, fi->framelen);
1430 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1431 }
1432
1433 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1434 struct ath_atx_tid *tid,
1435 struct list_head *bf_head)
1436 {
1437 struct ath_frame_info *fi;
1438 struct ath_buf *bf;
1439
1440 bf = list_first_entry(bf_head, struct ath_buf, list);
1441 bf->bf_state.bf_type &= ~BUF_AMPDU;
1442
1443 /* update starting sequence number for subsequent ADDBA request */
1444 if (tid)
1445 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1446
1447 bf->bf_lastbf = bf;
1448 fi = get_frame_info(bf->bf_mpdu);
1449 ath_buf_set_rate(sc, bf, fi->framelen);
1450 ath_tx_txqaddbuf(sc, txq, bf_head, false);
1451 TX_STAT_INC(txq->axq_qnum, queued);
1452 }
1453
1454 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1455 {
1456 struct ieee80211_hdr *hdr;
1457 enum ath9k_pkt_type htype;
1458 __le16 fc;
1459
1460 hdr = (struct ieee80211_hdr *)skb->data;
1461 fc = hdr->frame_control;
1462
1463 if (ieee80211_is_beacon(fc))
1464 htype = ATH9K_PKT_TYPE_BEACON;
1465 else if (ieee80211_is_probe_resp(fc))
1466 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1467 else if (ieee80211_is_atim(fc))
1468 htype = ATH9K_PKT_TYPE_ATIM;
1469 else if (ieee80211_is_pspoll(fc))
1470 htype = ATH9K_PKT_TYPE_PSPOLL;
1471 else
1472 htype = ATH9K_PKT_TYPE_NORMAL;
1473
1474 return htype;
1475 }
1476
1477 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1478 int framelen)
1479 {
1480 struct ath_softc *sc = hw->priv;
1481 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1482 struct ieee80211_sta *sta = tx_info->control.sta;
1483 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1484 struct ieee80211_hdr *hdr;
1485 struct ath_frame_info *fi = get_frame_info(skb);
1486 struct ath_node *an = NULL;
1487 struct ath_atx_tid *tid;
1488 enum ath9k_key_type keytype;
1489 u16 seqno = 0;
1490 u8 tidno;
1491
1492 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1493
1494 if (sta)
1495 an = (struct ath_node *) sta->drv_priv;
1496
1497 hdr = (struct ieee80211_hdr *)skb->data;
1498 if (an && ieee80211_is_data_qos(hdr->frame_control) &&
1499 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1500
1501 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1502
1503 /*
1504 * Override seqno set by upper layer with the one
1505 * in tx aggregation state.
1506 */
1507 tid = ATH_AN_2_TID(an, tidno);
1508 seqno = tid->seq_next;
1509 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1510 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1511 }
1512
1513 memset(fi, 0, sizeof(*fi));
1514 if (hw_key)
1515 fi->keyix = hw_key->hw_key_idx;
1516 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1517 fi->keyix = an->ps_key;
1518 else
1519 fi->keyix = ATH9K_TXKEYIX_INVALID;
1520 fi->keytype = keytype;
1521 fi->framelen = framelen;
1522 fi->seqno = seqno;
1523 }
1524
1525 static int setup_tx_flags(struct sk_buff *skb)
1526 {
1527 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1528 int flags = 0;
1529
1530 flags |= ATH9K_TXDESC_INTREQ;
1531
1532 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1533 flags |= ATH9K_TXDESC_NOACK;
1534
1535 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1536 flags |= ATH9K_TXDESC_LDPC;
1537
1538 return flags;
1539 }
1540
1541 /*
1542 * rix - rate index
1543 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1544 * width - 0 for 20 MHz, 1 for 40 MHz
1545 * half_gi - to use 4us v/s 3.6 us for symbol time
1546 */
1547 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1548 int width, int half_gi, bool shortPreamble)
1549 {
1550 u32 nbits, nsymbits, duration, nsymbols;
1551 int streams;
1552
1553 /* find number of symbols: PLCP + data */
1554 streams = HT_RC_2_STREAMS(rix);
1555 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1556 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1557 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1558
1559 if (!half_gi)
1560 duration = SYMBOL_TIME(nsymbols);
1561 else
1562 duration = SYMBOL_TIME_HALFGI(nsymbols);
1563
1564 /* addup duration for legacy/ht training and signal fields */
1565 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1566
1567 return duration;
1568 }
1569
1570 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1571 {
1572 struct ath_hw *ah = sc->sc_ah;
1573 struct ath9k_channel *curchan = ah->curchan;
1574 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1575 (curchan->channelFlags & CHANNEL_5GHZ) &&
1576 (chainmask == 0x7) && (rate < 0x90))
1577 return 0x3;
1578 else
1579 return chainmask;
1580 }
1581
1582 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1583 {
1584 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1585 struct ath9k_11n_rate_series series[4];
1586 struct sk_buff *skb;
1587 struct ieee80211_tx_info *tx_info;
1588 struct ieee80211_tx_rate *rates;
1589 const struct ieee80211_rate *rate;
1590 struct ieee80211_hdr *hdr;
1591 int i, flags = 0;
1592 u8 rix = 0, ctsrate = 0;
1593 bool is_pspoll;
1594
1595 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1596
1597 skb = bf->bf_mpdu;
1598 tx_info = IEEE80211_SKB_CB(skb);
1599 rates = tx_info->control.rates;
1600 hdr = (struct ieee80211_hdr *)skb->data;
1601 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1602
1603 /*
1604 * We check if Short Preamble is needed for the CTS rate by
1605 * checking the BSS's global flag.
1606 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1607 */
1608 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1609 ctsrate = rate->hw_value;
1610 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1611 ctsrate |= rate->hw_value_short;
1612
1613 for (i = 0; i < 4; i++) {
1614 bool is_40, is_sgi, is_sp;
1615 int phy;
1616
1617 if (!rates[i].count || (rates[i].idx < 0))
1618 continue;
1619
1620 rix = rates[i].idx;
1621 series[i].Tries = rates[i].count;
1622
1623 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1624 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1625 flags |= ATH9K_TXDESC_RTSENA;
1626 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1627 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1628 flags |= ATH9K_TXDESC_CTSENA;
1629 }
1630
1631 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1632 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1633 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1634 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1635
1636 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1637 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1638 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1639
1640 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1641 /* MCS rates */
1642 series[i].Rate = rix | 0x80;
1643 series[i].ChSel = ath_txchainmask_reduction(sc,
1644 common->tx_chainmask, series[i].Rate);
1645 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1646 is_40, is_sgi, is_sp);
1647 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1648 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1649 continue;
1650 }
1651
1652 /* legacy rates */
1653 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1654 !(rate->flags & IEEE80211_RATE_ERP_G))
1655 phy = WLAN_RC_PHY_CCK;
1656 else
1657 phy = WLAN_RC_PHY_OFDM;
1658
1659 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1660 series[i].Rate = rate->hw_value;
1661 if (rate->hw_value_short) {
1662 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1663 series[i].Rate |= rate->hw_value_short;
1664 } else {
1665 is_sp = false;
1666 }
1667
1668 if (bf->bf_state.bfs_paprd)
1669 series[i].ChSel = common->tx_chainmask;
1670 else
1671 series[i].ChSel = ath_txchainmask_reduction(sc,
1672 common->tx_chainmask, series[i].Rate);
1673
1674 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1675 phy, rate->bitrate * 100, len, rix, is_sp);
1676 }
1677
1678 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1679 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1680 flags &= ~ATH9K_TXDESC_RTSENA;
1681
1682 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1683 if (flags & ATH9K_TXDESC_RTSENA)
1684 flags &= ~ATH9K_TXDESC_CTSENA;
1685
1686 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1687 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1688 bf->bf_lastbf->bf_desc,
1689 !is_pspoll, ctsrate,
1690 0, series, 4, flags);
1691
1692 }
1693
1694 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1695 struct ath_txq *txq,
1696 struct sk_buff *skb)
1697 {
1698 struct ath_softc *sc = hw->priv;
1699 struct ath_hw *ah = sc->sc_ah;
1700 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1701 struct ath_frame_info *fi = get_frame_info(skb);
1702 struct ath_buf *bf;
1703 struct ath_desc *ds;
1704 int frm_type;
1705
1706 bf = ath_tx_get_buffer(sc);
1707 if (!bf) {
1708 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1709 return NULL;
1710 }
1711
1712 ATH_TXBUF_RESET(bf);
1713
1714 bf->bf_flags = setup_tx_flags(skb);
1715 bf->bf_mpdu = skb;
1716
1717 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1718 skb->len, DMA_TO_DEVICE);
1719 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1720 bf->bf_mpdu = NULL;
1721 bf->bf_buf_addr = 0;
1722 ath_err(ath9k_hw_common(sc->sc_ah),
1723 "dma_mapping_error() on TX\n");
1724 ath_tx_return_buffer(sc, bf);
1725 return NULL;
1726 }
1727
1728 frm_type = get_hw_packet_type(skb);
1729
1730 ds = bf->bf_desc;
1731 ath9k_hw_set_desc_link(ah, ds, 0);
1732
1733 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1734 fi->keyix, fi->keytype, bf->bf_flags);
1735
1736 ath9k_hw_filltxdesc(ah, ds,
1737 skb->len, /* segment length */
1738 true, /* first segment */
1739 true, /* last segment */
1740 ds, /* first descriptor */
1741 bf->bf_buf_addr,
1742 txq->axq_qnum);
1743
1744
1745 return bf;
1746 }
1747
1748 /* FIXME: tx power */
1749 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1750 struct ath_tx_control *txctl)
1751 {
1752 struct sk_buff *skb = bf->bf_mpdu;
1753 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1755 struct list_head bf_head;
1756 struct ath_atx_tid *tid = NULL;
1757 u8 tidno;
1758
1759 spin_lock_bh(&txctl->txq->axq_lock);
1760 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1761 ieee80211_is_data_qos(hdr->frame_control)) {
1762 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1763 IEEE80211_QOS_CTL_TID_MASK;
1764 tid = ATH_AN_2_TID(txctl->an, tidno);
1765
1766 WARN_ON(tid->ac->txq != txctl->txq);
1767 }
1768
1769 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1770 /*
1771 * Try aggregation if it's a unicast data frame
1772 * and the destination is HT capable.
1773 */
1774 ath_tx_send_ampdu(sc, tid, bf, txctl);
1775 } else {
1776 INIT_LIST_HEAD(&bf_head);
1777 list_add_tail(&bf->list, &bf_head);
1778
1779 bf->bf_state.bfs_ftype = txctl->frame_type;
1780 bf->bf_state.bfs_paprd = txctl->paprd;
1781
1782 if (bf->bf_state.bfs_paprd)
1783 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1784 bf->bf_state.bfs_paprd);
1785
1786 if (txctl->paprd)
1787 bf->bf_state.bfs_paprd_timestamp = jiffies;
1788
1789 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1790 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1791
1792 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1793 }
1794
1795 spin_unlock_bh(&txctl->txq->axq_lock);
1796 }
1797
1798 /* Upon failure caller should free skb */
1799 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1800 struct ath_tx_control *txctl)
1801 {
1802 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1803 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1804 struct ieee80211_sta *sta = info->control.sta;
1805 struct ieee80211_vif *vif = info->control.vif;
1806 struct ath_softc *sc = hw->priv;
1807 struct ath_txq *txq = txctl->txq;
1808 struct ath_buf *bf;
1809 int padpos, padsize;
1810 int frmlen = skb->len + FCS_LEN;
1811 int q;
1812
1813 /* NOTE: sta can be NULL according to net/mac80211.h */
1814 if (sta)
1815 txctl->an = (struct ath_node *)sta->drv_priv;
1816
1817 if (info->control.hw_key)
1818 frmlen += info->control.hw_key->icv_len;
1819
1820 /*
1821 * As a temporary workaround, assign seq# here; this will likely need
1822 * to be cleaned up to work better with Beacon transmission and virtual
1823 * BSSes.
1824 */
1825 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1826 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1827 sc->tx.seq_no += 0x10;
1828 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1829 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1830 }
1831
1832 /* Add the padding after the header if this is not already done */
1833 padpos = ath9k_cmn_padpos(hdr->frame_control);
1834 padsize = padpos & 3;
1835 if (padsize && skb->len > padpos) {
1836 if (skb_headroom(skb) < padsize)
1837 return -ENOMEM;
1838
1839 skb_push(skb, padsize);
1840 memmove(skb->data, skb->data + padsize, padpos);
1841 }
1842
1843 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1844 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1845 !ieee80211_is_data(hdr->frame_control))
1846 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1847
1848 setup_frame_info(hw, skb, frmlen);
1849
1850 /*
1851 * At this point, the vif, hw_key and sta pointers in the tx control
1852 * info are no longer valid (overwritten by the ath_frame_info data.
1853 */
1854
1855 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1856 if (unlikely(!bf))
1857 return -ENOMEM;
1858
1859 q = skb_get_queue_mapping(skb);
1860 spin_lock_bh(&txq->axq_lock);
1861 if (txq == sc->tx.txq_map[q] &&
1862 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1863 ieee80211_stop_queue(sc->hw, q);
1864 txq->stopped = 1;
1865 }
1866 spin_unlock_bh(&txq->axq_lock);
1867
1868 ath_tx_start_dma(sc, bf, txctl);
1869
1870 return 0;
1871 }
1872
1873 /*****************/
1874 /* TX Completion */
1875 /*****************/
1876
1877 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1878 int tx_flags, int ftype, struct ath_txq *txq)
1879 {
1880 struct ieee80211_hw *hw = sc->hw;
1881 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1882 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1883 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1884 int q, padpos, padsize;
1885
1886 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1887
1888 if (tx_flags & ATH_TX_BAR)
1889 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1890
1891 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1892 /* Frame was ACKed */
1893 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1894 }
1895
1896 padpos = ath9k_cmn_padpos(hdr->frame_control);
1897 padsize = padpos & 3;
1898 if (padsize && skb->len>padpos+padsize) {
1899 /*
1900 * Remove MAC header padding before giving the frame back to
1901 * mac80211.
1902 */
1903 memmove(skb->data + padsize, skb->data, padpos);
1904 skb_pull(skb, padsize);
1905 }
1906
1907 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1908 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1909 ath_dbg(common, ATH_DBG_PS,
1910 "Going back to sleep after having received TX status (0x%lx)\n",
1911 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1912 PS_WAIT_FOR_CAB |
1913 PS_WAIT_FOR_PSPOLL_DATA |
1914 PS_WAIT_FOR_TX_ACK));
1915 }
1916
1917 q = skb_get_queue_mapping(skb);
1918 if (txq == sc->tx.txq_map[q]) {
1919 spin_lock_bh(&txq->axq_lock);
1920 if (WARN_ON(--txq->pending_frames < 0))
1921 txq->pending_frames = 0;
1922
1923 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1924 ieee80211_wake_queue(sc->hw, q);
1925 txq->stopped = 0;
1926 }
1927 spin_unlock_bh(&txq->axq_lock);
1928 }
1929
1930 ieee80211_tx_status(hw, skb);
1931 }
1932
1933 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1934 struct ath_txq *txq, struct list_head *bf_q,
1935 struct ath_tx_status *ts, int txok, int sendbar)
1936 {
1937 struct sk_buff *skb = bf->bf_mpdu;
1938 unsigned long flags;
1939 int tx_flags = 0;
1940
1941 if (sendbar)
1942 tx_flags = ATH_TX_BAR;
1943
1944 if (!txok) {
1945 tx_flags |= ATH_TX_ERROR;
1946
1947 if (bf_isxretried(bf))
1948 tx_flags |= ATH_TX_XRETRY;
1949 }
1950
1951 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1952 bf->bf_buf_addr = 0;
1953
1954 if (bf->bf_state.bfs_paprd) {
1955 if (time_after(jiffies,
1956 bf->bf_state.bfs_paprd_timestamp +
1957 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1958 dev_kfree_skb_any(skb);
1959 else
1960 complete(&sc->paprd_complete);
1961 } else {
1962 ath_debug_stat_tx(sc, bf, ts, txq);
1963 ath_tx_complete(sc, skb, tx_flags,
1964 bf->bf_state.bfs_ftype, txq);
1965 }
1966 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1967 * accidentally reference it later.
1968 */
1969 bf->bf_mpdu = NULL;
1970
1971 /*
1972 * Return the list of ath_buf of this mpdu to free queue
1973 */
1974 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1975 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1976 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1977 }
1978
1979 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1980 struct ath_tx_status *ts, int nframes, int nbad,
1981 int txok, bool update_rc)
1982 {
1983 struct sk_buff *skb = bf->bf_mpdu;
1984 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1985 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1986 struct ieee80211_hw *hw = sc->hw;
1987 struct ath_hw *ah = sc->sc_ah;
1988 u8 i, tx_rateindex;
1989
1990 if (txok)
1991 tx_info->status.ack_signal = ts->ts_rssi;
1992
1993 tx_rateindex = ts->ts_rateindex;
1994 WARN_ON(tx_rateindex >= hw->max_rates);
1995
1996 if (ts->ts_status & ATH9K_TXERR_FILT)
1997 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1998 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1999 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2000
2001 BUG_ON(nbad > nframes);
2002
2003 tx_info->status.ampdu_len = nframes;
2004 tx_info->status.ampdu_ack_len = nframes - nbad;
2005 }
2006
2007 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2008 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2009 /*
2010 * If an underrun error is seen assume it as an excessive
2011 * retry only if max frame trigger level has been reached
2012 * (2 KB for single stream, and 4 KB for dual stream).
2013 * Adjust the long retry as if the frame was tried
2014 * hw->max_rate_tries times to affect how rate control updates
2015 * PER for the failed rate.
2016 * In case of congestion on the bus penalizing this type of
2017 * underruns should help hardware actually transmit new frames
2018 * successfully by eventually preferring slower rates.
2019 * This itself should also alleviate congestion on the bus.
2020 */
2021 if (ieee80211_is_data(hdr->frame_control) &&
2022 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2023 ATH9K_TX_DELIM_UNDERRUN)) &&
2024 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2025 tx_info->status.rates[tx_rateindex].count =
2026 hw->max_rate_tries;
2027 }
2028
2029 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2030 tx_info->status.rates[i].count = 0;
2031 tx_info->status.rates[i].idx = -1;
2032 }
2033
2034 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2035 }
2036
2037 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2038 struct ath_tx_status *ts, struct ath_buf *bf,
2039 struct list_head *bf_head)
2040 {
2041 int txok;
2042
2043 txq->axq_depth--;
2044 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2045 txq->axq_tx_inprogress = false;
2046 if (bf_is_ampdu_not_probing(bf))
2047 txq->axq_ampdu_depth--;
2048
2049 spin_unlock_bh(&txq->axq_lock);
2050
2051 if (!bf_isampdu(bf)) {
2052 /*
2053 * This frame is sent out as a single frame.
2054 * Use hardware retry status for this frame.
2055 */
2056 if (ts->ts_status & ATH9K_TXERR_XRETRY)
2057 bf->bf_state.bf_type |= BUF_XRETRY;
2058 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2059 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2060 } else
2061 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2062
2063 spin_lock_bh(&txq->axq_lock);
2064
2065 if (sc->sc_flags & SC_OP_TXAGGR)
2066 ath_txq_schedule(sc, txq);
2067 }
2068
2069 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2070 {
2071 struct ath_hw *ah = sc->sc_ah;
2072 struct ath_common *common = ath9k_hw_common(ah);
2073 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2074 struct list_head bf_head;
2075 struct ath_desc *ds;
2076 struct ath_tx_status ts;
2077 int status;
2078
2079 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2080 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2081 txq->axq_link);
2082
2083 spin_lock_bh(&txq->axq_lock);
2084 for (;;) {
2085 if (list_empty(&txq->axq_q)) {
2086 txq->axq_link = NULL;
2087 if (sc->sc_flags & SC_OP_TXAGGR)
2088 ath_txq_schedule(sc, txq);
2089 break;
2090 }
2091 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2092
2093 /*
2094 * There is a race condition that a BH gets scheduled
2095 * after sw writes TxE and before hw re-load the last
2096 * descriptor to get the newly chained one.
2097 * Software must keep the last DONE descriptor as a
2098 * holding descriptor - software does so by marking
2099 * it with the STALE flag.
2100 */
2101 bf_held = NULL;
2102 if (bf->bf_stale) {
2103 bf_held = bf;
2104 if (list_is_last(&bf_held->list, &txq->axq_q))
2105 break;
2106
2107 bf = list_entry(bf_held->list.next, struct ath_buf,
2108 list);
2109 }
2110
2111 lastbf = bf->bf_lastbf;
2112 ds = lastbf->bf_desc;
2113
2114 memset(&ts, 0, sizeof(ts));
2115 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2116 if (status == -EINPROGRESS)
2117 break;
2118
2119 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2120
2121 /*
2122 * Remove ath_buf's of the same transmit unit from txq,
2123 * however leave the last descriptor back as the holding
2124 * descriptor for hw.
2125 */
2126 lastbf->bf_stale = true;
2127 INIT_LIST_HEAD(&bf_head);
2128 if (!list_is_singular(&lastbf->list))
2129 list_cut_position(&bf_head,
2130 &txq->axq_q, lastbf->list.prev);
2131
2132 if (bf_held) {
2133 list_del(&bf_held->list);
2134 ath_tx_return_buffer(sc, bf_held);
2135 }
2136
2137 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2138 }
2139 spin_unlock_bh(&txq->axq_lock);
2140 }
2141
2142 static void ath_tx_complete_poll_work(struct work_struct *work)
2143 {
2144 struct ath_softc *sc = container_of(work, struct ath_softc,
2145 tx_complete_work.work);
2146 struct ath_txq *txq;
2147 int i;
2148 bool needreset = false;
2149 #ifdef CONFIG_ATH9K_DEBUGFS
2150 sc->tx_complete_poll_work_seen++;
2151 #endif
2152
2153 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2154 if (ATH_TXQ_SETUP(sc, i)) {
2155 txq = &sc->tx.txq[i];
2156 spin_lock_bh(&txq->axq_lock);
2157 if (txq->axq_depth) {
2158 if (txq->axq_tx_inprogress) {
2159 needreset = true;
2160 spin_unlock_bh(&txq->axq_lock);
2161 break;
2162 } else {
2163 txq->axq_tx_inprogress = true;
2164 }
2165 }
2166 spin_unlock_bh(&txq->axq_lock);
2167 }
2168
2169 if (needreset) {
2170 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2171 "tx hung, resetting the chip\n");
2172 ath_reset(sc, true);
2173 }
2174
2175 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2176 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2177 }
2178
2179
2180
2181 void ath_tx_tasklet(struct ath_softc *sc)
2182 {
2183 int i;
2184 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2185
2186 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2187
2188 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2189 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2190 ath_tx_processq(sc, &sc->tx.txq[i]);
2191 }
2192 }
2193
2194 void ath_tx_edma_tasklet(struct ath_softc *sc)
2195 {
2196 struct ath_tx_status ts;
2197 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2198 struct ath_hw *ah = sc->sc_ah;
2199 struct ath_txq *txq;
2200 struct ath_buf *bf, *lastbf;
2201 struct list_head bf_head;
2202 int status;
2203
2204 for (;;) {
2205 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2206 if (status == -EINPROGRESS)
2207 break;
2208 if (status == -EIO) {
2209 ath_dbg(common, ATH_DBG_XMIT,
2210 "Error processing tx status\n");
2211 break;
2212 }
2213
2214 /* Skip beacon completions */
2215 if (ts.qid == sc->beacon.beaconq)
2216 continue;
2217
2218 txq = &sc->tx.txq[ts.qid];
2219
2220 spin_lock_bh(&txq->axq_lock);
2221
2222 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2223 spin_unlock_bh(&txq->axq_lock);
2224 return;
2225 }
2226
2227 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2228 struct ath_buf, list);
2229 lastbf = bf->bf_lastbf;
2230
2231 INIT_LIST_HEAD(&bf_head);
2232 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2233 &lastbf->list);
2234
2235 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2236 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2237
2238 if (!list_empty(&txq->axq_q)) {
2239 struct list_head bf_q;
2240
2241 INIT_LIST_HEAD(&bf_q);
2242 txq->axq_link = NULL;
2243 list_splice_tail_init(&txq->axq_q, &bf_q);
2244 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2245 }
2246 }
2247
2248 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2249 spin_unlock_bh(&txq->axq_lock);
2250 }
2251 }
2252
2253 /*****************/
2254 /* Init, Cleanup */
2255 /*****************/
2256
2257 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2258 {
2259 struct ath_descdma *dd = &sc->txsdma;
2260 u8 txs_len = sc->sc_ah->caps.txs_len;
2261
2262 dd->dd_desc_len = size * txs_len;
2263 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2264 &dd->dd_desc_paddr, GFP_KERNEL);
2265 if (!dd->dd_desc)
2266 return -ENOMEM;
2267
2268 return 0;
2269 }
2270
2271 static int ath_tx_edma_init(struct ath_softc *sc)
2272 {
2273 int err;
2274
2275 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2276 if (!err)
2277 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2278 sc->txsdma.dd_desc_paddr,
2279 ATH_TXSTATUS_RING_SIZE);
2280
2281 return err;
2282 }
2283
2284 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2285 {
2286 struct ath_descdma *dd = &sc->txsdma;
2287
2288 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2289 dd->dd_desc_paddr);
2290 }
2291
2292 int ath_tx_init(struct ath_softc *sc, int nbufs)
2293 {
2294 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2295 int error = 0;
2296
2297 spin_lock_init(&sc->tx.txbuflock);
2298
2299 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2300 "tx", nbufs, 1, 1);
2301 if (error != 0) {
2302 ath_err(common,
2303 "Failed to allocate tx descriptors: %d\n", error);
2304 goto err;
2305 }
2306
2307 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2308 "beacon", ATH_BCBUF, 1, 1);
2309 if (error != 0) {
2310 ath_err(common,
2311 "Failed to allocate beacon descriptors: %d\n", error);
2312 goto err;
2313 }
2314
2315 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2316
2317 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2318 error = ath_tx_edma_init(sc);
2319 if (error)
2320 goto err;
2321 }
2322
2323 err:
2324 if (error != 0)
2325 ath_tx_cleanup(sc);
2326
2327 return error;
2328 }
2329
2330 void ath_tx_cleanup(struct ath_softc *sc)
2331 {
2332 if (sc->beacon.bdma.dd_desc_len != 0)
2333 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2334
2335 if (sc->tx.txdma.dd_desc_len != 0)
2336 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2337
2338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2339 ath_tx_edma_cleanup(sc);
2340 }
2341
2342 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2343 {
2344 struct ath_atx_tid *tid;
2345 struct ath_atx_ac *ac;
2346 int tidno, acno;
2347
2348 for (tidno = 0, tid = &an->tid[tidno];
2349 tidno < WME_NUM_TID;
2350 tidno++, tid++) {
2351 tid->an = an;
2352 tid->tidno = tidno;
2353 tid->seq_start = tid->seq_next = 0;
2354 tid->baw_size = WME_MAX_BA;
2355 tid->baw_head = tid->baw_tail = 0;
2356 tid->sched = false;
2357 tid->paused = false;
2358 tid->state &= ~AGGR_CLEANUP;
2359 INIT_LIST_HEAD(&tid->buf_q);
2360 acno = TID_TO_WME_AC(tidno);
2361 tid->ac = &an->ac[acno];
2362 tid->state &= ~AGGR_ADDBA_COMPLETE;
2363 tid->state &= ~AGGR_ADDBA_PROGRESS;
2364 }
2365
2366 for (acno = 0, ac = &an->ac[acno];
2367 acno < WME_NUM_AC; acno++, ac++) {
2368 ac->sched = false;
2369 ac->txq = sc->tx.txq_map[acno];
2370 INIT_LIST_HEAD(&ac->tid_q);
2371 }
2372 }
2373
2374 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2375 {
2376 struct ath_atx_ac *ac;
2377 struct ath_atx_tid *tid;
2378 struct ath_txq *txq;
2379 int tidno;
2380
2381 for (tidno = 0, tid = &an->tid[tidno];
2382 tidno < WME_NUM_TID; tidno++, tid++) {
2383
2384 ac = tid->ac;
2385 txq = ac->txq;
2386
2387 spin_lock_bh(&txq->axq_lock);
2388
2389 if (tid->sched) {
2390 list_del(&tid->list);
2391 tid->sched = false;
2392 }
2393
2394 if (ac->sched) {
2395 list_del(&ac->list);
2396 tid->ac->sched = false;
2397 }
2398
2399 ath_tid_drain(sc, txq, tid);
2400 tid->state &= ~AGGR_ADDBA_COMPLETE;
2401 tid->state &= ~AGGR_CLEANUP;
2402
2403 spin_unlock_bh(&txq->axq_lock);
2404 }
2405 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree