drivers/scsi/sata_qstor.c

   1 /*
   2  *  sata_qstor.c - Pacific Digital Corporation QStor SATA
   3  *
   4  *  Maintained by:  Mark Lord <mlord@pobox.com>
   5  *
   6  *  Copyright 2005 Pacific Digital Corporation.
   7  *  (OSL/GPL code release authorized by Jalil Fadavi).
   8  *
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License as published by
  12  *  the Free Software Foundation; either version 2, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *  GNU General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License
  21  *  along with this program; see the file COPYING.  If not, write to
  22  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  23  *
  24  *
  25  *  libata documentation is available via 'make {ps|pdf}docs',
  26  *  as Documentation/DocBook/libata.*
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/init.h>
  34 #include <linux/blkdev.h>
  35 #include <linux/delay.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/sched.h>
  38 #include <linux/device.h>
  39 #include "scsi.h"
  40 #include <scsi/scsi_host.h>
  41 #include <asm/io.h>
  42 #include <linux/libata.h>
  43
  44 #define DRV_NAME        "sata_qstor"
  45 #define DRV_VERSION     "0.04"
  46
  47 enum {
  48         QS_PORTS                = 4,
  49         QS_MAX_PRD              = LIBATA_MAX_PRD,
  50         QS_CPB_ORDER            = 6,
  51         QS_CPB_BYTES            = (1 << QS_CPB_ORDER),
  52         QS_PRD_BYTES            = QS_MAX_PRD * 16,
  53         QS_PKT_BYTES            = QS_CPB_BYTES + QS_PRD_BYTES,
  54
  55         /* global register offsets */
  56         QS_HCF_CNFG3            = 0x0003, /* host configuration offset */
  57         QS_HID_HPHY             = 0x0004, /* host physical interface info */
  58         QS_HCT_CTRL             = 0x00e4, /* global interrupt mask offset */
  59         QS_HST_SFF              = 0x0100, /* host status fifo offset */
  60         QS_HVS_SERD3            = 0x0393, /* PHY enable offset */
  61
  62         /* global control bits */
  63         QS_HPHY_64BIT           = (1 << 1), /* 64-bit bus detected */
  64         QS_CNFG3_GSRST          = 0x01,     /* global chip reset */
  65         QS_SERD3_PHY_ENA        = 0xf0,     /* PHY detection ENAble*/
  66
  67         /* per-channel register offsets */
  68         QS_CCF_CPBA             = 0x0710, /* chan CPB base address */
  69         QS_CCF_CSEP             = 0x0718, /* chan CPB separation factor */
  70         QS_CFC_HUFT             = 0x0800, /* host upstream fifo threshold */
  71         QS_CFC_HDFT             = 0x0804, /* host downstream fifo threshold */
  72         QS_CFC_DUFT             = 0x0808, /* dev upstream fifo threshold */
  73         QS_CFC_DDFT             = 0x080c, /* dev downstream fifo threshold */
  74         QS_CCT_CTR0             = 0x0900, /* chan control-0 offset */
  75         QS_CCT_CTR1             = 0x0901, /* chan control-1 offset */
  76         QS_CCT_CFF              = 0x0a00, /* chan command fifo offset */
  77
  78         /* channel control bits */
  79         QS_CTR0_REG             = (1 << 1),   /* register mode (vs. pkt mode) */
  80         QS_CTR0_CLER            = (1 << 2),   /* clear channel errors */
  81         QS_CTR1_RDEV            = (1 << 1),   /* sata phy/comms reset */
  82         QS_CTR1_RCHN            = (1 << 4),   /* reset channel logic */
  83         QS_CCF_RUN_PKT          = 0x107,      /* RUN a new dma PKT */
  84
  85         /* pkt sub-field headers */
  86         QS_HCB_HDR              = 0x01,   /* Host Control Block header */
  87         QS_DCB_HDR              = 0x02,   /* Device Control Block header */
  88
  89         /* pkt HCB flag bits */
  90         QS_HF_DIRO              = (1 << 0),   /* data DIRection Out */
  91         QS_HF_DAT               = (1 << 3),   /* DATa pkt */
  92         QS_HF_IEN               = (1 << 4),   /* Interrupt ENable */
  93         QS_HF_VLD               = (1 << 5),   /* VaLiD pkt */
  94
  95         /* pkt DCB flag bits */
  96         QS_DF_PORD              = (1 << 2),   /* Pio OR Dma */
  97         QS_DF_ELBA              = (1 << 3),   /* Extended LBA (lba48) */
  98
  99         /* PCI device IDs */
 100         board_2068_idx          = 0,    /* QStor 4-port SATA/RAID */
 101 };
 102
 103 enum {
 104         QS_DMA_BOUNDARY         = ~0UL
 105 };
 106
 107 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
 108
 109 struct qs_port_priv {
 110         u8                      *pkt;
 111         dma_addr_t              pkt_dma;
 112         qs_state_t              state;
 113 };
 114
 115 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
 116 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
 117 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 118 static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs);
 119 static int qs_port_start(struct ata_port *ap);
 120 static void qs_host_stop(struct ata_host_set *host_set);
 121 static void qs_port_stop(struct ata_port *ap);
 122 static void qs_phy_reset(struct ata_port *ap);
 123 static void qs_qc_prep(struct ata_queued_cmd *qc);
 124 static int qs_qc_issue(struct ata_queued_cmd *qc);
 125 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
 126 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
 127 static u8 qs_bmdma_status(struct ata_port *ap);
 128 static void qs_irq_clear(struct ata_port *ap);
 129 static void qs_eng_timeout(struct ata_port *ap);
 130
 131 static Scsi_Host_Template qs_ata_sht = {
 132         .module                 = THIS_MODULE,
 133         .name                   = DRV_NAME,
 134         .ioctl                  = ata_scsi_ioctl,
 135         .queuecommand           = ata_scsi_queuecmd,
 136         .eh_strategy_handler    = ata_scsi_error,
 137         .can_queue              = ATA_DEF_QUEUE,
 138         .this_id                = ATA_SHT_THIS_ID,
 139         .sg_tablesize           = QS_MAX_PRD,
 140         .max_sectors            = ATA_MAX_SECTORS,
 141         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 142         .emulated               = ATA_SHT_EMULATED,
 143         //FIXME .use_clustering         = ATA_SHT_USE_CLUSTERING,
 144         .use_clustering         = ENABLE_CLUSTERING,
 145         .proc_name              = DRV_NAME,
 146         .dma_boundary           = QS_DMA_BOUNDARY,
 147         .slave_configure        = ata_scsi_slave_config,
 148         .bios_param             = ata_std_bios_param,
 149 };
 150
 151 static const struct ata_port_operations qs_ata_ops = {
 152         .port_disable           = ata_port_disable,
 153         .tf_load                = ata_tf_load,
 154         .tf_read                = ata_tf_read,
 155         .check_status           = ata_check_status,
 156         .check_atapi_dma        = qs_check_atapi_dma,
 157         .exec_command           = ata_exec_command,
 158         .dev_select             = ata_std_dev_select,
 159         .phy_reset              = qs_phy_reset,
 160         .qc_prep                = qs_qc_prep,
 161         .qc_issue               = qs_qc_issue,
 162         .eng_timeout            = qs_eng_timeout,
 163         .irq_handler            = qs_intr,
 164         .irq_clear              = qs_irq_clear,
 165         .scr_read               = qs_scr_read,
 166         .scr_write              = qs_scr_write,
 167         .port_start             = qs_port_start,
 168         .port_stop              = qs_port_stop,
 169         .host_stop              = qs_host_stop,
 170         .bmdma_stop             = qs_bmdma_stop,
 171         .bmdma_status           = qs_bmdma_status,
 172 };
 173
 174 static struct ata_port_info qs_port_info[] = {
 175         /* board_2068_idx */
 176         {
 177                 .sht            = &qs_ata_sht,
 178                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 179                                   ATA_FLAG_SATA_RESET |
 180                                   //FIXME ATA_FLAG_SRST |
 181                                   ATA_FLAG_MMIO,
 182                 .pio_mask       = 0x10, /* pio4 */
 183                 .udma_mask      = 0x7f, /* udma0-6 */
 184                 .port_ops       = &qs_ata_ops,
 185         },
 186 };
 187
 188 static struct pci_device_id qs_ata_pci_tbl[] = {
 189         { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 190           board_2068_idx },
 191
 192         { }     /* terminate list */
 193 };
 194
 195 static struct pci_driver qs_ata_pci_driver = {
 196         .name                   = DRV_NAME,
 197         .id_table               = qs_ata_pci_tbl,
 198         .probe                  = qs_ata_init_one,
 199         .remove                 = ata_pci_remove_one,
 200 };
 201
 202 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
 203 {
 204         return 1;       /* ATAPI DMA not supported */
 205 }
 206
 207 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
 208 {
 209         /* nothing */
 210 }
 211
 212 static u8 qs_bmdma_status(struct ata_port *ap)
 213 {
 214         return 0;
 215 }
 216
 217 static void qs_irq_clear(struct ata_port *ap)
 218 {
 219         /* nothing */
 220 }
 221
 222 static inline void qs_enter_reg_mode(struct ata_port *ap)
 223 {
 224         u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
 225
 226         writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 227         readb(chan + QS_CCT_CTR0);        /* flush */
 228 }
 229
 230 static inline void qs_reset_channel_logic(struct ata_port *ap)
 231 {
 232         u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
 233
 234         writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 235         readb(chan + QS_CCT_CTR0);        /* flush */
 236         qs_enter_reg_mode(ap);
 237 }
 238
 239 static void qs_phy_reset(struct ata_port *ap)
 240 {
 241         struct qs_port_priv *pp = ap->private_data;
 242
 243         pp->state = qs_state_idle;
 244         qs_reset_channel_logic(ap);
 245         sata_phy_reset(ap);
 246 }
 247
 248 static void qs_eng_timeout(struct ata_port *ap)
 249 {
 250         struct qs_port_priv *pp = ap->private_data;
 251
 252         if (pp->state != qs_state_idle) /* healthy paranoia */
 253                 pp->state = qs_state_mmio;
 254         qs_reset_channel_logic(ap);
 255         ata_eng_timeout(ap);
 256 }
 257
 258 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
 259 {
 260         if (sc_reg > SCR_CONTROL)
 261                 return ~0U;
 262         return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
 263 }
 264
 265 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 266 {
 267         if (sc_reg > SCR_CONTROL)
 268                 return;
 269         writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
 270 }
 271
 272 static void qs_fill_sg(struct ata_queued_cmd *qc)
 273 {
 274         struct scatterlist *sg = qc->sg;
 275         struct ata_port *ap = qc->ap;
 276         struct qs_port_priv *pp = ap->private_data;
 277         unsigned int nelem;
 278         u8 *prd = pp->pkt + QS_CPB_BYTES;
 279
 280         assert(sg != NULL);
 281         assert(qc->n_elem > 0);
 282
 283         for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) {
 284                 u64 addr;
 285                 u32 len;
 286
 287                 addr = sg_dma_address(sg);
 288                 *(__le64 *)prd = cpu_to_le64(addr);
 289                 prd += sizeof(u64);
 290
 291                 len = sg_dma_len(sg);
 292                 *(__le32 *)prd = cpu_to_le32(len);
 293                 prd += sizeof(u64);
 294
 295                 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
 296                                         (unsigned long long)addr, len);
 297         }
 298 }
 299
 300 static void qs_qc_prep(struct ata_queued_cmd *qc)
 301 {
 302         struct qs_port_priv *pp = qc->ap->private_data;
 303         u8 dflags = QS_DF_PORD, *buf = pp->pkt;
 304         u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
 305         u64 addr;
 306
 307         VPRINTK("ENTER\n");
 308
 309         qs_enter_reg_mode(qc->ap);
 310         if (qc->tf.protocol != ATA_PROT_DMA) {
 311                 ata_qc_prep(qc);
 312                 return;
 313         }
 314
 315         qs_fill_sg(qc);
 316
 317         if ((qc->tf.flags & ATA_TFLAG_WRITE))
 318                 hflags |= QS_HF_DIRO;
 319         if ((qc->tf.flags & ATA_TFLAG_LBA48))
 320                 dflags |= QS_DF_ELBA;
 321
 322         /* host control block (HCB) */
 323         buf[ 0] = QS_HCB_HDR;
 324         buf[ 1] = hflags;
 325         *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE);
 326         *(__le32 *)(&buf[ 8]) = cpu_to_le32(qc->n_elem);
 327         addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
 328         *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
 329
 330         /* device control block (DCB) */
 331         buf[24] = QS_DCB_HDR;
 332         buf[28] = dflags;
 333
 334         /* frame information structure (FIS) */
 335         ata_tf_to_fis(&qc->tf, &buf[32], 0);
 336 }
 337
 338 static inline void qs_packet_start(struct ata_queued_cmd *qc)
 339 {
 340         struct ata_port *ap = qc->ap;
 341         u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
 342
 343         VPRINTK("ENTER, ap %p\n", ap);
 344
 345         writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
 346         wmb();                             /* flush PRDs and pkt to memory */
 347         writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
 348         readl(chan + QS_CCT_CFF);          /* flush */
 349 }
 350
 351 static int qs_qc_issue(struct ata_queued_cmd *qc)
 352 {
 353         struct qs_port_priv *pp = qc->ap->private_data;
 354
 355         switch (qc->tf.protocol) {
 356         case ATA_PROT_DMA:
 357
 358                 pp->state = qs_state_pkt;
 359                 qs_packet_start(qc);
 360                 return 0;
 361
 362         case ATA_PROT_ATAPI_DMA:
 363                 BUG();
 364                 break;
 365
 366         default:
 367                 break;
 368         }
 369
 370         pp->state = qs_state_mmio;
 371         return ata_qc_issue_prot(qc);
 372 }
 373
 374 static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set)
 375 {
 376         unsigned int handled = 0;
 377         u8 sFFE;
 378         u8 __iomem *mmio_base = host_set->mmio_base;
 379
 380         do {
 381                 u32 sff0 = readl(mmio_base + QS_HST_SFF);
 382                 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
 383                 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
 384                 sFFE  = sff1 >> 31;             /* empty flag */
 385
 386                 if (sEVLD) {
 387                         u8 sDST = sff0 >> 16;   /* dev status */
 388                         u8 sHST = sff1 & 0x3f;  /* host status */
 389                         unsigned int port_no = (sff1 >> 8) & 0x03;
 390                         struct ata_port *ap = host_set->ports[port_no];
 391
 392                         DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
 393                                         sff1, sff0, port_no, sHST, sDST);
 394                         handled = 1;
 395                         if (ap && !(ap->flags &
 396                                     (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
 397                                 struct ata_queued_cmd *qc;
 398                                 struct qs_port_priv *pp = ap->private_data;
 399                                 if (!pp || pp->state != qs_state_pkt)
 400                                         continue;
 401                                 qc = ata_qc_from_tag(ap, ap->active_tag);
 402                                 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
 403                                         switch (sHST) {
 404                                         case 0: /* successful CPB */
 405                                         case 3: /* device error */
 406                                                 pp->state = qs_state_idle;
 407                                                 qs_enter_reg_mode(qc->ap);
 408                                                 ata_qc_complete(qc,
 409                                                         ac_err_mask(sDST));
 410                                                 break;
 411                                         default:
 412                                                 break;
 413                                         }
 414                                 }
 415                         }
 416                 }
 417         } while (!sFFE);
 418         return handled;
 419 }
 420
 421 static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set)
 422 {
 423         unsigned int handled = 0, port_no;
 424
 425         for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
 426                 struct ata_port *ap;
 427                 ap = host_set->ports[port_no];
 428                 if (ap &&
 429                     !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
 430                         struct ata_queued_cmd *qc;
 431                         struct qs_port_priv *pp = ap->private_data;
 432                         if (!pp || pp->state != qs_state_mmio)
 433                                 continue;
 434                         qc = ata_qc_from_tag(ap, ap->active_tag);
 435                         if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
 436
 437                                 /* check main status, clearing INTRQ */
 438                                 u8 status = ata_check_status(ap);
 439                                 if ((status & ATA_BUSY))
 440                                         continue;
 441                                 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
 442                                         ap->id, qc->tf.protocol, status);
 443
 444                                 /* complete taskfile transaction */
 445                                 pp->state = qs_state_idle;
 446                                 ata_qc_complete(qc, ac_err_mask(status));
 447                                 handled = 1;
 448                         }
 449                 }
 450         }
 451         return handled;
 452 }
 453
 454 static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs)
 455 {
 456         struct ata_host_set *host_set = dev_instance;
 457         unsigned int handled = 0;
 458
 459         VPRINTK("ENTER\n");
 460
 461         spin_lock(&host_set->lock);
 462         handled  = qs_intr_pkt(host_set) | qs_intr_mmio(host_set);
 463         spin_unlock(&host_set->lock);
 464
 465         VPRINTK("EXIT\n");
 466
 467         return IRQ_RETVAL(handled);
 468 }
 469
 470 static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base)
 471 {
 472         port->cmd_addr          =
 473         port->data_addr         = base + 0x400;
 474         port->error_addr        =
 475         port->feature_addr      = base + 0x408; /* hob_feature = 0x409 */
 476         port->nsect_addr        = base + 0x410; /* hob_nsect   = 0x411 */
 477         port->lbal_addr         = base + 0x418; /* hob_lbal    = 0x419 */
 478         port->lbam_addr         = base + 0x420; /* hob_lbam    = 0x421 */
 479         port->lbah_addr         = base + 0x428; /* hob_lbah    = 0x429 */
 480         port->device_addr       = base + 0x430;
 481         port->status_addr       =
 482         port->command_addr      = base + 0x438;
 483         port->altstatus_addr    =
 484         port->ctl_addr          = base + 0x440;
 485         port->scr_addr          = base + 0xc00;
 486 }
 487
 488 static int qs_port_start(struct ata_port *ap)
 489 {
 490         struct device *dev = ap->host_set->dev;
 491         struct qs_port_priv *pp;
 492         void __iomem *mmio_base = ap->host_set->mmio_base;
 493         void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
 494         u64 addr;
 495         int rc;
 496
 497         rc = ata_port_start(ap);
 498         if (rc)
 499                 return rc;
 500         qs_enter_reg_mode(ap);
 501         pp = kzalloc(sizeof(*pp), GFP_KERNEL);
 502         if (!pp) {
 503                 rc = -ENOMEM;
 504                 goto err_out;
 505         }
 506         pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
 507                                                                 GFP_KERNEL);
 508         if (!pp->pkt) {
 509                 rc = -ENOMEM;
 510                 goto err_out_kfree;
 511         }
 512         memset(pp->pkt, 0, QS_PKT_BYTES);
 513         ap->private_data = pp;
 514
 515         addr = (u64)pp->pkt_dma;
 516         writel((u32) addr,        chan + QS_CCF_CPBA);
 517         writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
 518         return 0;
 519
 520 err_out_kfree:
 521         kfree(pp);
 522 err_out:
 523         ata_port_stop(ap);
 524         return rc;
 525 }
 526
 527 static void qs_port_stop(struct ata_port *ap)
 528 {
 529         struct device *dev = ap->host_set->dev;
 530         struct qs_port_priv *pp = ap->private_data;
 531
 532         if (pp != NULL) {
 533                 ap->private_data = NULL;
 534                 if (pp->pkt != NULL)
 535                         dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt,
 536                                                                 pp->pkt_dma);
 537                 kfree(pp);
 538         }
 539         ata_port_stop(ap);
 540 }
 541
 542 static void qs_host_stop(struct ata_host_set *host_set)
 543 {
 544         void __iomem *mmio_base = host_set->mmio_base;
 545         struct pci_dev *pdev = to_pci_dev(host_set->dev);
 546
 547         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 548         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 549
 550         pci_iounmap(pdev, mmio_base);
 551 }
 552
 553 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
 554 {
 555         void __iomem *mmio_base = pe->mmio_base;
 556         unsigned int port_no;
 557
 558         writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
 559         writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
 560
 561         /* reset each channel in turn */
 562         for (port_no = 0; port_no < pe->n_ports; ++port_no) {
 563                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 564                 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
 565                 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
 566                 readb(chan + QS_CCT_CTR0);        /* flush */
 567         }
 568         writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
 569
 570         for (port_no = 0; port_no < pe->n_ports; ++port_no) {
 571                 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
 572                 /* set FIFO depths to same settings as Windows driver */
 573                 writew(32, chan + QS_CFC_HUFT);
 574                 writew(32, chan + QS_CFC_HDFT);
 575                 writew(10, chan + QS_CFC_DUFT);
 576                 writew( 8, chan + QS_CFC_DDFT);
 577                 /* set CPB size in bytes, as a power of two */
 578                 writeb(QS_CPB_ORDER,    chan + QS_CCF_CSEP);
 579         }
 580         writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
 581 }
 582
 583 /*
 584  * The QStor understands 64-bit buses, and uses 64-bit fields
 585  * for DMA pointers regardless of bus width.  We just have to
 586  * make sure our DMA masks are set appropriately for whatever
 587  * bridge lies between us and the QStor, and then the DMA mapping
 588  * code will ensure we only ever "see" appropriate buffer addresses.
 589  * If we're 32-bit limited somewhere, then our 64-bit fields will
 590  * just end up with zeros in the upper 32-bits, without any special
 591  * logic required outside of this routine (below).
 592  */
 593 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
 594 {
 595         u32 bus_info = readl(mmio_base + QS_HID_HPHY);
 596         int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
 597
 598         if (have_64bit_bus &&
 599             !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
 600                 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
 601                 if (rc) {
 602                         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 603                         if (rc) {
 604                                 dev_printk(KERN_ERR, &pdev->dev,
 605                                            "64-bit DMA enable failed\n");
 606                                 return rc;
 607                         }
 608                 }
 609         } else {
 610                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 611                 if (rc) {
 612                         dev_printk(KERN_ERR, &pdev->dev,
 613                                 "32-bit DMA enable failed\n");
 614                         return rc;
 615                 }
 616                 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 617                 if (rc) {
 618                         dev_printk(KERN_ERR, &pdev->dev,
 619                                 "32-bit consistent DMA enable failed\n");
 620                         return rc;
 621                 }
 622         }
 623         return 0;
 624 }
 625
 626 static int qs_ata_init_one(struct pci_dev *pdev,
 627                                 const struct pci_device_id *ent)
 628 {
 629         static int printed_version;
 630         struct ata_probe_ent *probe_ent = NULL;
 631         void __iomem *mmio_base;
 632         unsigned int board_idx = (unsigned int) ent->driver_data;
 633         int rc, port_no;
 634
 635         if (!printed_version++)
 636                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 637
 638         rc = pci_enable_device(pdev);
 639         if (rc)
 640                 return rc;
 641
 642         rc = pci_request_regions(pdev, DRV_NAME);
 643         if (rc)
 644                 goto err_out;
 645
 646         if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
 647                 rc = -ENODEV;
 648                 goto err_out_regions;
 649         }
 650
 651         mmio_base = pci_iomap(pdev, 4, 0);
 652         if (mmio_base == NULL) {
 653                 rc = -ENOMEM;
 654                 goto err_out_regions;
 655         }
 656
 657         rc = qs_set_dma_masks(pdev, mmio_base);
 658         if (rc)
 659                 goto err_out_iounmap;
 660
 661         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
 662         if (probe_ent == NULL) {
 663                 rc = -ENOMEM;
 664                 goto err_out_iounmap;
 665         }
 666
 667         memset(probe_ent, 0, sizeof(*probe_ent));
 668         probe_ent->dev = pci_dev_to_dev(pdev);
 669         INIT_LIST_HEAD(&probe_ent->node);
 670
 671         probe_ent->sht          = qs_port_info[board_idx].sht;
 672         probe_ent->host_flags   = qs_port_info[board_idx].host_flags;
 673         probe_ent->pio_mask     = qs_port_info[board_idx].pio_mask;
 674         probe_ent->mwdma_mask   = qs_port_info[board_idx].mwdma_mask;
 675         probe_ent->udma_mask    = qs_port_info[board_idx].udma_mask;
 676         probe_ent->port_ops     = qs_port_info[board_idx].port_ops;
 677
 678         probe_ent->irq          = pdev->irq;
 679         probe_ent->irq_flags    = SA_SHIRQ;
 680         probe_ent->mmio_base    = mmio_base;
 681         probe_ent->n_ports      = QS_PORTS;
 682
 683         for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
 684                 unsigned long chan = (unsigned long)mmio_base +
 685                                                         (port_no * 0x4000);
 686                 qs_ata_setup_port(&probe_ent->port[port_no], chan);
 687         }
 688
 689         pci_set_master(pdev);
 690
 691         /* initialize adapter */
 692         qs_host_init(board_idx, probe_ent);
 693
 694         rc = ata_device_add(probe_ent);
 695         kfree(probe_ent);
 696         if (rc != QS_PORTS)
 697                 goto err_out_iounmap;
 698         return 0;
 699
 700 err_out_iounmap:
 701         pci_iounmap(pdev, mmio_base);
 702 err_out_regions:
 703         pci_release_regions(pdev);
 704 err_out:
 705         pci_disable_device(pdev);
 706         return rc;
 707 }
 708
 709 static int __init qs_ata_init(void)
 710 {
 711         return pci_module_init(&qs_ata_pci_driver);
 712 }
 713
 714 static void __exit qs_ata_exit(void)
 715 {
 716         pci_unregister_driver(&qs_ata_pci_driver);
 717 }
 718
 719 MODULE_AUTHOR("Mark Lord");
 720 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
 721 MODULE_LICENSE("GPL");
 722 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
 723 MODULE_VERSION(DRV_VERSION);
 724
 725 module_init(qs_ata_init);
 726 module_exit(qs_ata_exit);