2 * pdc_adma.c - Pacific Digital Corporation ADMA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Mark Lord
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "pdc_adma"
50 #define DRV_VERSION "0.03"
52 /* macro to calculate base address for ATA regs */
53 #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
55 /* macro to calculate base address for ADMA regs */
56 #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
61 ADMA_PRD_BYTES
= LIBATA_MAX_PRD
* 16,
62 ADMA_PKT_BYTES
= ADMA_CPB_BYTES
+ ADMA_PRD_BYTES
,
64 ADMA_DMA_BOUNDARY
= 0xffffffff,
66 /* global register offsets */
67 ADMA_MODE_LOCK
= 0x00c7,
69 /* per-channel register offsets */
70 ADMA_CONTROL
= 0x0000, /* ADMA control */
71 ADMA_STATUS
= 0x0002, /* ADMA status */
72 ADMA_CPB_COUNT
= 0x0004, /* CPB count */
73 ADMA_CPB_CURRENT
= 0x000c, /* current CPB address */
74 ADMA_CPB_NEXT
= 0x000c, /* next CPB address */
75 ADMA_CPB_LOOKUP
= 0x0010, /* CPB lookup table */
76 ADMA_FIFO_IN
= 0x0014, /* input FIFO threshold */
77 ADMA_FIFO_OUT
= 0x0016, /* output FIFO threshold */
79 /* ADMA_CONTROL register bits */
80 aNIEN
= (1 << 8), /* irq mask: 1==masked */
81 aGO
= (1 << 7), /* packet trigger ("Go!") */
82 aRSTADM
= (1 << 5), /* ADMA logic reset */
83 aPIOMD4
= 0x0003, /* PIO mode 4 */
85 /* ADMA_STATUS register bits */
101 /* ATA register flags */
105 /* ATA register addresses */
106 ADMA_REGS_CONTROL
= 0x0e,
107 ADMA_REGS_SECTOR_COUNT
= 0x12,
108 ADMA_REGS_LBA_LOW
= 0x13,
109 ADMA_REGS_LBA_MID
= 0x14,
110 ADMA_REGS_LBA_HIGH
= 0x15,
111 ADMA_REGS_DEVICE
= 0x16,
112 ADMA_REGS_COMMAND
= 0x17,
115 board_1841_idx
= 0, /* ADMA 2-port controller */
118 typedef enum { adma_state_idle
, adma_state_pkt
, adma_state_mmio
} adma_state_t
;
120 struct adma_port_priv
{
126 static int adma_ata_init_one (struct pci_dev
*pdev
,
127 const struct pci_device_id
*ent
);
128 static irqreturn_t
adma_intr (int irq
, void *dev_instance
,
129 struct pt_regs
*regs
);
130 static int adma_port_start(struct ata_port
*ap
);
131 static void adma_host_stop(struct ata_host_set
*host_set
);
132 static void adma_port_stop(struct ata_port
*ap
);
133 static void adma_phy_reset(struct ata_port
*ap
);
134 static void adma_qc_prep(struct ata_queued_cmd
*qc
);
135 static int adma_qc_issue(struct ata_queued_cmd
*qc
);
136 static int adma_check_atapi_dma(struct ata_queued_cmd
*qc
);
137 static void adma_bmdma_stop(struct ata_queued_cmd
*qc
);
138 static u8
adma_bmdma_status(struct ata_port
*ap
);
139 static void adma_irq_clear(struct ata_port
*ap
);
140 static void adma_eng_timeout(struct ata_port
*ap
);
142 static Scsi_Host_Template adma_ata_sht
= {
143 .module
= THIS_MODULE
,
145 .ioctl
= ata_scsi_ioctl
,
146 .queuecommand
= ata_scsi_queuecmd
,
147 .eh_strategy_handler
= ata_scsi_error
,
148 .can_queue
= ATA_DEF_QUEUE
,
149 .this_id
= ATA_SHT_THIS_ID
,
150 .sg_tablesize
= LIBATA_MAX_PRD
,
151 .max_sectors
= ATA_MAX_SECTORS
,
152 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
153 .emulated
= ATA_SHT_EMULATED
,
154 .use_clustering
= ENABLE_CLUSTERING
,
155 .proc_name
= DRV_NAME
,
156 .dma_boundary
= ADMA_DMA_BOUNDARY
,
157 .slave_configure
= ata_scsi_slave_config
,
158 .bios_param
= ata_std_bios_param
,
161 static const struct ata_port_operations adma_ata_ops
= {
162 .port_disable
= ata_port_disable
,
163 .tf_load
= ata_tf_load
,
164 .tf_read
= ata_tf_read
,
165 .check_status
= ata_check_status
,
166 .check_atapi_dma
= adma_check_atapi_dma
,
167 .exec_command
= ata_exec_command
,
168 .dev_select
= ata_std_dev_select
,
169 .phy_reset
= adma_phy_reset
,
170 .qc_prep
= adma_qc_prep
,
171 .qc_issue
= adma_qc_issue
,
172 .eng_timeout
= adma_eng_timeout
,
173 .irq_handler
= adma_intr
,
174 .irq_clear
= adma_irq_clear
,
175 .port_start
= adma_port_start
,
176 .port_stop
= adma_port_stop
,
177 .host_stop
= adma_host_stop
,
178 .bmdma_stop
= adma_bmdma_stop
,
179 .bmdma_status
= adma_bmdma_status
,
182 static struct ata_port_info adma_port_info
[] = {
185 .sht
= &adma_ata_sht
,
186 .host_flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
|
187 ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
,
188 .pio_mask
= 0x10, /* pio4 */
189 .udma_mask
= 0x1f, /* udma0-4 */
190 .port_ops
= &adma_ata_ops
,
194 static struct pci_device_id adma_ata_pci_tbl
[] = {
195 { PCI_VENDOR_ID_PDC
, 0x1841, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
198 { } /* terminate list */
201 static struct pci_driver adma_ata_pci_driver
= {
203 .id_table
= adma_ata_pci_tbl
,
204 .probe
= adma_ata_init_one
,
205 .remove
= ata_pci_remove_one
,
208 static int adma_check_atapi_dma(struct ata_queued_cmd
*qc
)
210 return 1; /* ATAPI DMA not yet supported */
213 static void adma_bmdma_stop(struct ata_queued_cmd
*qc
)
218 static u8
adma_bmdma_status(struct ata_port
*ap
)
223 static void adma_irq_clear(struct ata_port
*ap
)
228 static void adma_reset_engine(void __iomem
*chan
)
230 /* reset ADMA to idle state */
231 writew(aPIOMD4
| aNIEN
| aRSTADM
, chan
+ ADMA_CONTROL
);
233 writew(aPIOMD4
, chan
+ ADMA_CONTROL
);
237 static void adma_reinit_engine(struct ata_port
*ap
)
239 struct adma_port_priv
*pp
= ap
->private_data
;
240 void __iomem
*mmio_base
= ap
->host_set
->mmio_base
;
241 void __iomem
*chan
= ADMA_REGS(mmio_base
, ap
->port_no
);
243 /* mask/clear ATA interrupts */
244 writeb(ATA_NIEN
, (void __iomem
*)ap
->ioaddr
.ctl_addr
);
245 ata_check_status(ap
);
247 /* reset the ADMA engine */
248 adma_reset_engine(chan
);
250 /* set in-FIFO threshold to 0x100 */
251 writew(0x100, chan
+ ADMA_FIFO_IN
);
253 /* set CPB pointer */
254 writel((u32
)pp
->pkt_dma
, chan
+ ADMA_CPB_NEXT
);
256 /* set out-FIFO threshold to 0x100 */
257 writew(0x100, chan
+ ADMA_FIFO_OUT
);
260 writew(1, chan
+ ADMA_CPB_COUNT
);
262 /* read/discard ADMA status */
263 readb(chan
+ ADMA_STATUS
);
266 static inline void adma_enter_reg_mode(struct ata_port
*ap
)
268 void __iomem
*chan
= ADMA_REGS(ap
->host_set
->mmio_base
, ap
->port_no
);
270 writew(aPIOMD4
, chan
+ ADMA_CONTROL
);
271 readb(chan
+ ADMA_STATUS
); /* flush */
274 static void adma_phy_reset(struct ata_port
*ap
)
276 struct adma_port_priv
*pp
= ap
->private_data
;
278 pp
->state
= adma_state_idle
;
279 adma_reinit_engine(ap
);
284 static void adma_eng_timeout(struct ata_port
*ap
)
286 struct adma_port_priv
*pp
= ap
->private_data
;
288 if (pp
->state
!= adma_state_idle
) /* healthy paranoia */
289 pp
->state
= adma_state_mmio
;
290 adma_reinit_engine(ap
);
294 static int adma_fill_sg(struct ata_queued_cmd
*qc
)
296 struct scatterlist
*sg
= qc
->sg
;
297 struct ata_port
*ap
= qc
->ap
;
298 struct adma_port_priv
*pp
= ap
->private_data
;
300 int nelem
, i
= (2 + buf
[3]) * 8;
301 u8 pFLAGS
= pORD
| ((qc
->tf
.flags
& ATA_TFLAG_WRITE
) ? pDIRO
: 0);
303 for (nelem
= 0; nelem
< qc
->n_elem
; nelem
++,sg
++) {
307 addr
= (u32
)sg_dma_address(sg
);
308 *(__le32
*)(buf
+ i
) = cpu_to_le32(addr
);
311 len
= sg_dma_len(sg
) >> 3;
312 *(__le32
*)(buf
+ i
) = cpu_to_le32(len
);
315 if ((nelem
+ 1) == qc
->n_elem
)
318 buf
[i
++] = qc
->dev
->dma_mode
& 0xf;
319 buf
[i
++] = 0; /* pPKLW */
320 buf
[i
++] = 0; /* reserved */
323 = (pFLAGS
& pEND
) ? 0 : cpu_to_le32(pp
->pkt_dma
+ i
+ 4);
326 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", nelem
,
327 (unsigned long)addr
, len
);
332 static void adma_qc_prep(struct ata_queued_cmd
*qc
)
334 struct adma_port_priv
*pp
= qc
->ap
->private_data
;
336 u32 pkt_dma
= (u32
)pp
->pkt_dma
;
341 adma_enter_reg_mode(qc
->ap
);
342 if (qc
->tf
.protocol
!= ATA_PROT_DMA
) {
347 buf
[i
++] = 0; /* Response flags */
348 buf
[i
++] = 0; /* reserved */
349 buf
[i
++] = cVLD
| cDAT
| cIEN
;
350 i
++; /* cLEN, gets filled in below */
352 *(__le32
*)(buf
+i
) = cpu_to_le32(pkt_dma
); /* cNCPB */
354 i
+= 4; /* cPRD, gets filled in below */
356 buf
[i
++] = 0; /* reserved */
357 buf
[i
++] = 0; /* reserved */
358 buf
[i
++] = 0; /* reserved */
359 buf
[i
++] = 0; /* reserved */
361 /* ATA registers; must be a multiple of 4 */
362 buf
[i
++] = qc
->tf
.device
;
363 buf
[i
++] = ADMA_REGS_DEVICE
;
364 if ((qc
->tf
.flags
& ATA_TFLAG_LBA48
)) {
365 buf
[i
++] = qc
->tf
.hob_nsect
;
366 buf
[i
++] = ADMA_REGS_SECTOR_COUNT
;
367 buf
[i
++] = qc
->tf
.hob_lbal
;
368 buf
[i
++] = ADMA_REGS_LBA_LOW
;
369 buf
[i
++] = qc
->tf
.hob_lbam
;
370 buf
[i
++] = ADMA_REGS_LBA_MID
;
371 buf
[i
++] = qc
->tf
.hob_lbah
;
372 buf
[i
++] = ADMA_REGS_LBA_HIGH
;
374 buf
[i
++] = qc
->tf
.nsect
;
375 buf
[i
++] = ADMA_REGS_SECTOR_COUNT
;
376 buf
[i
++] = qc
->tf
.lbal
;
377 buf
[i
++] = ADMA_REGS_LBA_LOW
;
378 buf
[i
++] = qc
->tf
.lbam
;
379 buf
[i
++] = ADMA_REGS_LBA_MID
;
380 buf
[i
++] = qc
->tf
.lbah
;
381 buf
[i
++] = ADMA_REGS_LBA_HIGH
;
383 buf
[i
++] = ADMA_REGS_CONTROL
;
386 buf
[i
++] = qc
->tf
.command
;
387 buf
[i
++] = ADMA_REGS_COMMAND
| rEND
;
389 buf
[3] = (i
>> 3) - 2; /* cLEN */
390 *(__le32
*)(buf
+8) = cpu_to_le32(pkt_dma
+ i
); /* cPRD */
392 i
= adma_fill_sg(qc
);
393 wmb(); /* flush PRDs and pkt to memory */
395 /* dump out CPB + PRDs for debug */
398 static char obuf
[2048];
399 for (j
= 0; j
< i
; ++j
) {
400 len
+= sprintf(obuf
+len
, "%02x ", buf
[j
]);
402 printk("%s\n", obuf
);
407 printk("%s\n", obuf
);
412 static inline void adma_packet_start(struct ata_queued_cmd
*qc
)
414 struct ata_port
*ap
= qc
->ap
;
415 void __iomem
*chan
= ADMA_REGS(ap
->host_set
->mmio_base
, ap
->port_no
);
417 VPRINTK("ENTER, ap %p\n", ap
);
419 /* fire up the ADMA engine */
420 writew(aPIOMD4
| aGO
, chan
+ ADMA_CONTROL
);
423 static int adma_qc_issue(struct ata_queued_cmd
*qc
)
425 struct adma_port_priv
*pp
= qc
->ap
->private_data
;
427 switch (qc
->tf
.protocol
) {
429 pp
->state
= adma_state_pkt
;
430 adma_packet_start(qc
);
433 case ATA_PROT_ATAPI_DMA
:
441 pp
->state
= adma_state_mmio
;
442 return ata_qc_issue_prot(qc
);
445 static inline unsigned int adma_intr_pkt(struct ata_host_set
*host_set
)
447 unsigned int handled
= 0, port_no
;
448 u8 __iomem
*mmio_base
= host_set
->mmio_base
;
450 for (port_no
= 0; port_no
< host_set
->n_ports
; ++port_no
) {
451 struct ata_port
*ap
= host_set
->ports
[port_no
];
452 struct adma_port_priv
*pp
;
453 struct ata_queued_cmd
*qc
;
454 void __iomem
*chan
= ADMA_REGS(mmio_base
, port_no
);
455 u8 status
= readb(chan
+ ADMA_STATUS
);
460 adma_enter_reg_mode(ap
);
461 if (ap
->flags
& (ATA_FLAG_PORT_DISABLED
| ATA_FLAG_NOINTR
))
463 pp
= ap
->private_data
;
464 if (!pp
|| pp
->state
!= adma_state_pkt
)
466 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
467 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
))) {
468 unsigned int err_mask
= 0;
470 if ((status
& (aPERR
| aPSD
| aUIRQ
)))
471 err_mask
= AC_ERR_OTHER
;
472 else if (pp
->pkt
[0] != cDONE
)
473 err_mask
= AC_ERR_OTHER
;
475 ata_qc_complete(qc
, err_mask
);
481 static inline unsigned int adma_intr_mmio(struct ata_host_set
*host_set
)
483 unsigned int handled
= 0, port_no
;
485 for (port_no
= 0; port_no
< host_set
->n_ports
; ++port_no
) {
487 ap
= host_set
->ports
[port_no
];
488 if (ap
&& (!(ap
->flags
& (ATA_FLAG_PORT_DISABLED
| ATA_FLAG_NOINTR
)))) {
489 struct ata_queued_cmd
*qc
;
490 struct adma_port_priv
*pp
= ap
->private_data
;
491 if (!pp
|| pp
->state
!= adma_state_mmio
)
493 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
494 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
))) {
496 /* check main status, clearing INTRQ */
497 u8 status
= ata_check_status(ap
);
498 if ((status
& ATA_BUSY
))
500 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
501 ap
->id
, qc
->tf
.protocol
, status
);
503 /* complete taskfile transaction */
504 pp
->state
= adma_state_idle
;
505 ata_qc_complete(qc
, ac_err_mask(status
));
513 static irqreturn_t
adma_intr(int irq
, void *dev_instance
, struct pt_regs
*regs
)
515 struct ata_host_set
*host_set
= dev_instance
;
516 unsigned int handled
= 0;
520 spin_lock(&host_set
->lock
);
521 handled
= adma_intr_pkt(host_set
) | adma_intr_mmio(host_set
);
522 spin_unlock(&host_set
->lock
);
526 return IRQ_RETVAL(handled
);
529 static void adma_ata_setup_port(struct ata_ioports
*port
, unsigned long base
)
532 port
->data_addr
= base
+ 0x000;
534 port
->feature_addr
= base
+ 0x004;
535 port
->nsect_addr
= base
+ 0x008;
536 port
->lbal_addr
= base
+ 0x00c;
537 port
->lbam_addr
= base
+ 0x010;
538 port
->lbah_addr
= base
+ 0x014;
539 port
->device_addr
= base
+ 0x018;
541 port
->command_addr
= base
+ 0x01c;
542 port
->altstatus_addr
=
543 port
->ctl_addr
= base
+ 0x038;
546 static int adma_port_start(struct ata_port
*ap
)
548 struct device
*dev
= ap
->host_set
->dev
;
549 struct adma_port_priv
*pp
;
552 rc
= ata_port_start(ap
);
555 adma_enter_reg_mode(ap
);
557 pp
= kcalloc(1, sizeof(*pp
), GFP_KERNEL
);
560 pp
->pkt
= dma_alloc_coherent(dev
, ADMA_PKT_BYTES
, &pp
->pkt_dma
,
565 if ((pp
->pkt_dma
& 7) != 0) {
566 printk("bad alignment for pp->pkt_dma: %08x\n",
568 dma_free_coherent(dev
, ADMA_PKT_BYTES
,
569 pp
->pkt
, pp
->pkt_dma
);
572 memset(pp
->pkt
, 0, ADMA_PKT_BYTES
);
573 ap
->private_data
= pp
;
574 adma_reinit_engine(ap
);
584 static void adma_port_stop(struct ata_port
*ap
)
586 struct device
*dev
= ap
->host_set
->dev
;
587 struct adma_port_priv
*pp
= ap
->private_data
;
589 adma_reset_engine(ADMA_REGS(ap
->host_set
->mmio_base
, ap
->port_no
));
591 ap
->private_data
= NULL
;
593 dma_free_coherent(dev
, ADMA_PKT_BYTES
,
594 pp
->pkt
, pp
->pkt_dma
);
600 static void adma_host_stop(struct ata_host_set
*host_set
)
602 unsigned int port_no
;
604 for (port_no
= 0; port_no
< ADMA_PORTS
; ++port_no
)
605 adma_reset_engine(ADMA_REGS(host_set
->mmio_base
, port_no
));
607 ata_pci_host_stop(host_set
);
610 static void adma_host_init(unsigned int chip_id
,
611 struct ata_probe_ent
*probe_ent
)
613 unsigned int port_no
;
614 void __iomem
*mmio_base
= probe_ent
->mmio_base
;
616 /* enable/lock aGO operation */
617 writeb(7, mmio_base
+ ADMA_MODE_LOCK
);
619 /* reset the ADMA logic */
620 for (port_no
= 0; port_no
< ADMA_PORTS
; ++port_no
)
621 adma_reset_engine(ADMA_REGS(mmio_base
, port_no
));
624 static int adma_set_dma_masks(struct pci_dev
*pdev
, void __iomem
*mmio_base
)
628 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
630 dev_printk(KERN_ERR
, &pdev
->dev
,
631 "32-bit DMA enable failed\n");
634 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
636 dev_printk(KERN_ERR
, &pdev
->dev
,
637 "32-bit consistent DMA enable failed\n");
643 static int adma_ata_init_one(struct pci_dev
*pdev
,
644 const struct pci_device_id
*ent
)
646 static int printed_version
;
647 struct ata_probe_ent
*probe_ent
= NULL
;
648 void __iomem
*mmio_base
;
649 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
652 if (!printed_version
++)
653 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
655 rc
= pci_enable_device(pdev
);
659 rc
= pci_request_regions(pdev
, DRV_NAME
);
663 if ((pci_resource_flags(pdev
, 4) & IORESOURCE_MEM
) == 0) {
665 goto err_out_regions
;
668 mmio_base
= pci_iomap(pdev
, 4, 0);
669 if (mmio_base
== NULL
) {
671 goto err_out_regions
;
674 rc
= adma_set_dma_masks(pdev
, mmio_base
);
676 goto err_out_iounmap
;
678 probe_ent
= kcalloc(1, sizeof(*probe_ent
), GFP_KERNEL
);
679 if (probe_ent
== NULL
) {
681 goto err_out_iounmap
;
684 probe_ent
->dev
= pci_dev_to_dev(pdev
);
685 INIT_LIST_HEAD(&probe_ent
->node
);
687 probe_ent
->sht
= adma_port_info
[board_idx
].sht
;
688 probe_ent
->host_flags
= adma_port_info
[board_idx
].host_flags
;
689 probe_ent
->pio_mask
= adma_port_info
[board_idx
].pio_mask
;
690 probe_ent
->mwdma_mask
= adma_port_info
[board_idx
].mwdma_mask
;
691 probe_ent
->udma_mask
= adma_port_info
[board_idx
].udma_mask
;
692 probe_ent
->port_ops
= adma_port_info
[board_idx
].port_ops
;
694 probe_ent
->irq
= pdev
->irq
;
695 probe_ent
->irq_flags
= SA_SHIRQ
;
696 probe_ent
->mmio_base
= mmio_base
;
697 probe_ent
->n_ports
= ADMA_PORTS
;
699 for (port_no
= 0; port_no
< probe_ent
->n_ports
; ++port_no
) {
700 adma_ata_setup_port(&probe_ent
->port
[port_no
],
701 ADMA_ATA_REGS((unsigned long)mmio_base
, port_no
));
704 pci_set_master(pdev
);
706 /* initialize adapter */
707 adma_host_init(board_idx
, probe_ent
);
709 rc
= ata_device_add(probe_ent
);
711 if (rc
!= ADMA_PORTS
)
712 goto err_out_iounmap
;
716 pci_iounmap(pdev
, mmio_base
);
718 pci_release_regions(pdev
);
720 pci_disable_device(pdev
);
724 static int __init
adma_ata_init(void)
726 return pci_module_init(&adma_ata_pci_driver
);
729 static void __exit
adma_ata_exit(void)
731 pci_unregister_driver(&adma_ata_pci_driver
);
734 MODULE_AUTHOR("Mark Lord");
735 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
736 MODULE_LICENSE("GPL");
737 MODULE_DEVICE_TABLE(pci
, adma_ata_pci_tbl
);
738 MODULE_VERSION(DRV_VERSION
);
740 module_init(adma_ata_init
);
741 module_exit(adma_ata_exit
);