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ARM: LPC32XX: Misc support functions
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / serial / mpc52xx_uart.c
blob84a35f6990169f44c3a387e1cb19ae4e5b7f017c
1 /*
2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
3 *
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
12 *
13 *
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
15 *
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
18 *
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
26 *
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
30 */
31
32 #undef DEBUG
33
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/serial.h>
38 #include <linux/sysrq.h>
39 #include <linux/console.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/of.h>
43 #include <linux/of_platform.h>
44 #include <linux/clk.h>
45
46 #include <asm/mpc52xx.h>
47 #include <asm/mpc52xx_psc.h>
48
49 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50 #define SUPPORT_SYSRQ
51 #endif
52
53 #include <linux/serial_core.h>
54
55
56 /* We've been assigned a range on the "Low-density serial ports" major */
57 #define SERIAL_PSC_MAJOR 204
58 #define SERIAL_PSC_MINOR 148
59
60
61 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
62
63
64 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
65 /* Rem: - We use the read_status_mask as a shadow of
66 * psc->mpc52xx_psc_imr
67 * - It's important that is array is all zero on start as we
68 * use it to know if it's initialized or not ! If it's not sure
69 * it's cleared, then a memset(...,0,...) should be added to
70 * the console_init
71 */
72
73 /* lookup table for matching device nodes to index numbers */
74 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
75
76 static void mpc52xx_uart_of_enumerate(void);
77
78
79 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
80
81
82 /* Forward declaration of the interruption handling routine */
83 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
84 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
85
86
87 /* Simple macro to test if a port is console or not. This one is taken
88 * for serial_core.c and maybe should be moved to serial_core.h ? */
89 #ifdef CONFIG_SERIAL_CORE_CONSOLE
90 #define uart_console(port) \
91 ((port)->cons && (port)->cons->index == (port)->line)
92 #else
93 #define uart_console(port) (0)
94 #endif
95
96 /* ======================================================================== */
97 /* PSC fifo operations for isolating differences between 52xx and 512x */
98 /* ======================================================================== */
99
100 struct psc_ops {
101 void (*fifo_init)(struct uart_port *port);
102 int (*raw_rx_rdy)(struct uart_port *port);
103 int (*raw_tx_rdy)(struct uart_port *port);
104 int (*rx_rdy)(struct uart_port *port);
105 int (*tx_rdy)(struct uart_port *port);
106 int (*tx_empty)(struct uart_port *port);
107 void (*stop_rx)(struct uart_port *port);
108 void (*start_tx)(struct uart_port *port);
109 void (*stop_tx)(struct uart_port *port);
110 void (*rx_clr_irq)(struct uart_port *port);
111 void (*tx_clr_irq)(struct uart_port *port);
112 void (*write_char)(struct uart_port *port, unsigned char c);
113 unsigned char (*read_char)(struct uart_port *port);
114 void (*cw_disable_ints)(struct uart_port *port);
115 void (*cw_restore_ints)(struct uart_port *port);
116 unsigned long (*getuartclk)(void *p);
117 int (*clock)(struct uart_port *port, int enable);
118 int (*fifoc_init)(void);
119 void (*fifoc_uninit)(void);
120 void (*get_irq)(struct uart_port *, struct device_node *);
121 irqreturn_t (*handle_irq)(struct uart_port *port);
122 };
123
124 #ifdef CONFIG_PPC_MPC52xx
125 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
126 static void mpc52xx_psc_fifo_init(struct uart_port *port)
127 {
128 struct mpc52xx_psc __iomem *psc = PSC(port);
129 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
130
131 /* /32 prescaler */
132 out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00);
133
134 out_8(&fifo->rfcntl, 0x00);
135 out_be16(&fifo->rfalarm, 0x1ff);
136 out_8(&fifo->tfcntl, 0x07);
137 out_be16(&fifo->tfalarm, 0x80);
138
139 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
140 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
141 }
142
143 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
144 {
145 return in_be16(&PSC(port)->mpc52xx_psc_status)
146 & MPC52xx_PSC_SR_RXRDY;
147 }
148
149 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
150 {
151 return in_be16(&PSC(port)->mpc52xx_psc_status)
152 & MPC52xx_PSC_SR_TXRDY;
153 }
154
155
156 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
157 {
158 return in_be16(&PSC(port)->mpc52xx_psc_isr)
159 & port->read_status_mask
160 & MPC52xx_PSC_IMR_RXRDY;
161 }
162
163 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
164 {
165 return in_be16(&PSC(port)->mpc52xx_psc_isr)
166 & port->read_status_mask
167 & MPC52xx_PSC_IMR_TXRDY;
168 }
169
170 static int mpc52xx_psc_tx_empty(struct uart_port *port)
171 {
172 return in_be16(&PSC(port)->mpc52xx_psc_status)
173 & MPC52xx_PSC_SR_TXEMP;
174 }
175
176 static void mpc52xx_psc_start_tx(struct uart_port *port)
177 {
178 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
179 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
180 }
181
182 static void mpc52xx_psc_stop_tx(struct uart_port *port)
183 {
184 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
185 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
186 }
187
188 static void mpc52xx_psc_stop_rx(struct uart_port *port)
189 {
190 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
191 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
192 }
193
194 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
195 {
196 }
197
198 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
199 {
200 }
201
202 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
203 {
204 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
205 }
206
207 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
208 {
209 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
210 }
211
212 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
213 {
214 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
215 }
216
217 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
218 {
219 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
220 }
221
222 /* Search for bus-frequency property in this node or a parent */
223 static unsigned long mpc52xx_getuartclk(void *p)
224 {
225 /*
226 * 5200 UARTs have a / 32 prescaler
227 * but the generic serial code assumes 16
228 * so return ipb freq / 2
229 */
230 return mpc5xxx_get_bus_frequency(p) / 2;
231 }
232
233 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
234 {
235 port->irqflags = IRQF_DISABLED;
236 port->irq = irq_of_parse_and_map(np, 0);
237 }
238
239 /* 52xx specific interrupt handler. The caller holds the port lock */
240 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
241 {
242 return mpc5xxx_uart_process_int(port);
243 }
244
245 static struct psc_ops mpc52xx_psc_ops = {
246 .fifo_init = mpc52xx_psc_fifo_init,
247 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
248 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
249 .rx_rdy = mpc52xx_psc_rx_rdy,
250 .tx_rdy = mpc52xx_psc_tx_rdy,
251 .tx_empty = mpc52xx_psc_tx_empty,
252 .stop_rx = mpc52xx_psc_stop_rx,
253 .start_tx = mpc52xx_psc_start_tx,
254 .stop_tx = mpc52xx_psc_stop_tx,
255 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
256 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
257 .write_char = mpc52xx_psc_write_char,
258 .read_char = mpc52xx_psc_read_char,
259 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
260 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
261 .getuartclk = mpc52xx_getuartclk,
262 .get_irq = mpc52xx_psc_get_irq,
263 .handle_irq = mpc52xx_psc_handle_irq,
264 };
265
266 #endif /* CONFIG_MPC52xx */
267
268 #ifdef CONFIG_PPC_MPC512x
269 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
270
271 /* PSC FIFO Controller for mpc512x */
272 struct psc_fifoc {
273 u32 fifoc_cmd;
274 u32 fifoc_int;
275 u32 fifoc_dma;
276 u32 fifoc_axe;
277 u32 fifoc_debug;
278 };
279
280 static struct psc_fifoc __iomem *psc_fifoc;
281 static unsigned int psc_fifoc_irq;
282
283 static void mpc512x_psc_fifo_init(struct uart_port *port)
284 {
285 /* /32 prescaler */
286 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
287
288 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
289 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
290 out_be32(&FIFO_512x(port)->txalarm, 1);
291 out_be32(&FIFO_512x(port)->tximr, 0);
292
293 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
294 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
295 out_be32(&FIFO_512x(port)->rxalarm, 1);
296 out_be32(&FIFO_512x(port)->rximr, 0);
297
298 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
299 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
300 }
301
302 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
303 {
304 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
305 }
306
307 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
308 {
309 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
310 }
311
312 static int mpc512x_psc_rx_rdy(struct uart_port *port)
313 {
314 return in_be32(&FIFO_512x(port)->rxsr)
315 & in_be32(&FIFO_512x(port)->rximr)
316 & MPC512x_PSC_FIFO_ALARM;
317 }
318
319 static int mpc512x_psc_tx_rdy(struct uart_port *port)
320 {
321 return in_be32(&FIFO_512x(port)->txsr)
322 & in_be32(&FIFO_512x(port)->tximr)
323 & MPC512x_PSC_FIFO_ALARM;
324 }
325
326 static int mpc512x_psc_tx_empty(struct uart_port *port)
327 {
328 return in_be32(&FIFO_512x(port)->txsr)
329 & MPC512x_PSC_FIFO_EMPTY;
330 }
331
332 static void mpc512x_psc_stop_rx(struct uart_port *port)
333 {
334 unsigned long rx_fifo_imr;
335
336 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
337 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
338 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
339 }
340
341 static void mpc512x_psc_start_tx(struct uart_port *port)
342 {
343 unsigned long tx_fifo_imr;
344
345 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
346 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
347 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
348 }
349
350 static void mpc512x_psc_stop_tx(struct uart_port *port)
351 {
352 unsigned long tx_fifo_imr;
353
354 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
355 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
356 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
357 }
358
359 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
360 {
361 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
362 }
363
364 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
365 {
366 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
367 }
368
369 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
370 {
371 out_8(&FIFO_512x(port)->txdata_8, c);
372 }
373
374 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
375 {
376 return in_8(&FIFO_512x(port)->rxdata_8);
377 }
378
379 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
380 {
381 port->read_status_mask =
382 in_be32(&FIFO_512x(port)->tximr) << 16 |
383 in_be32(&FIFO_512x(port)->rximr);
384 out_be32(&FIFO_512x(port)->tximr, 0);
385 out_be32(&FIFO_512x(port)->rximr, 0);
386 }
387
388 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
389 {
390 out_be32(&FIFO_512x(port)->tximr,
391 (port->read_status_mask >> 16) & 0x7f);
392 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
393 }
394
395 static unsigned long mpc512x_getuartclk(void *p)
396 {
397 return mpc5xxx_get_bus_frequency(p);
398 }
399
400 /* Init PSC FIFO Controller */
401 static int __init mpc512x_psc_fifoc_init(void)
402 {
403 struct device_node *np;
404
405 np = of_find_compatible_node(NULL, NULL,
406 "fsl,mpc5121-psc-fifo");
407 if (!np) {
408 pr_err("%s: Can't find FIFOC node\n", __func__);
409 return -ENODEV;
410 }
411
412 psc_fifoc = of_iomap(np, 0);
413 if (!psc_fifoc) {
414 pr_err("%s: Can't map FIFOC\n", __func__);
415 return -ENODEV;
416 }
417
418 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
419 of_node_put(np);
420 if (psc_fifoc_irq == NO_IRQ) {
421 pr_err("%s: Can't get FIFOC irq\n", __func__);
422 iounmap(psc_fifoc);
423 return -ENODEV;
424 }
425
426 return 0;
427 }
428
429 static void __exit mpc512x_psc_fifoc_uninit(void)
430 {
431 iounmap(psc_fifoc);
432 }
433
434 /* 512x specific interrupt handler. The caller holds the port lock */
435 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
436 {
437 unsigned long fifoc_int;
438 int psc_num;
439
440 /* Read pending PSC FIFOC interrupts */
441 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
442
443 /* Check if it is an interrupt for this port */
444 psc_num = (port->mapbase & 0xf00) >> 8;
445 if (test_bit(psc_num, &fifoc_int) ||
446 test_bit(psc_num + 16, &fifoc_int))
447 return mpc5xxx_uart_process_int(port);
448
449 return IRQ_NONE;
450 }
451
452 static int mpc512x_psc_clock(struct uart_port *port, int enable)
453 {
454 struct clk *psc_clk;
455 int psc_num;
456 char clk_name[10];
457
458 if (uart_console(port))
459 return 0;
460
461 psc_num = (port->mapbase & 0xf00) >> 8;
462 snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
463 psc_clk = clk_get(port->dev, clk_name);
464 if (IS_ERR(psc_clk)) {
465 dev_err(port->dev, "Failed to get PSC clock entry!\n");
466 return -ENODEV;
467 }
468
469 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
470
471 if (enable)
472 clk_enable(psc_clk);
473 else
474 clk_disable(psc_clk);
475
476 return 0;
477 }
478
479 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
480 {
481 port->irqflags = IRQF_SHARED;
482 port->irq = psc_fifoc_irq;
483 }
484
485 static struct psc_ops mpc512x_psc_ops = {
486 .fifo_init = mpc512x_psc_fifo_init,
487 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
488 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
489 .rx_rdy = mpc512x_psc_rx_rdy,
490 .tx_rdy = mpc512x_psc_tx_rdy,
491 .tx_empty = mpc512x_psc_tx_empty,
492 .stop_rx = mpc512x_psc_stop_rx,
493 .start_tx = mpc512x_psc_start_tx,
494 .stop_tx = mpc512x_psc_stop_tx,
495 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
496 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
497 .write_char = mpc512x_psc_write_char,
498 .read_char = mpc512x_psc_read_char,
499 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
500 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
501 .getuartclk = mpc512x_getuartclk,
502 .clock = mpc512x_psc_clock,
503 .fifoc_init = mpc512x_psc_fifoc_init,
504 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
505 .get_irq = mpc512x_psc_get_irq,
506 .handle_irq = mpc512x_psc_handle_irq,
507 };
508 #endif
509
510 static struct psc_ops *psc_ops;
511
512 /* ======================================================================== */
513 /* UART operations */
514 /* ======================================================================== */
515
516 static unsigned int
517 mpc52xx_uart_tx_empty(struct uart_port *port)
518 {
519 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
520 }
521
522 static void
523 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
524 {
525 if (mctrl & TIOCM_RTS)
526 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
527 else
528 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
529 }
530
531 static unsigned int
532 mpc52xx_uart_get_mctrl(struct uart_port *port)
533 {
534 unsigned int ret = TIOCM_DSR;
535 u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
536
537 if (!(status & MPC52xx_PSC_CTS))
538 ret |= TIOCM_CTS;
539 if (!(status & MPC52xx_PSC_DCD))
540 ret |= TIOCM_CAR;
541
542 return ret;
543 }
544
545 static void
546 mpc52xx_uart_stop_tx(struct uart_port *port)
547 {
548 /* port->lock taken by caller */
549 psc_ops->stop_tx(port);
550 }
551
552 static void
553 mpc52xx_uart_start_tx(struct uart_port *port)
554 {
555 /* port->lock taken by caller */
556 psc_ops->start_tx(port);
557 }
558
559 static void
560 mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
561 {
562 unsigned long flags;
563 spin_lock_irqsave(&port->lock, flags);
564
565 port->x_char = ch;
566 if (ch) {
567 /* Make sure tx interrupts are on */
568 /* Truly necessary ??? They should be anyway */
569 psc_ops->start_tx(port);
570 }
571
572 spin_unlock_irqrestore(&port->lock, flags);
573 }
574
575 static void
576 mpc52xx_uart_stop_rx(struct uart_port *port)
577 {
578 /* port->lock taken by caller */
579 psc_ops->stop_rx(port);
580 }
581
582 static void
583 mpc52xx_uart_enable_ms(struct uart_port *port)
584 {
585 struct mpc52xx_psc __iomem *psc = PSC(port);
586
587 /* clear D_*-bits by reading them */
588 in_8(&psc->mpc52xx_psc_ipcr);
589 /* enable CTS and DCD as IPC interrupts */
590 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
591
592 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
593 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
594 }
595
596 static void
597 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
598 {
599 unsigned long flags;
600 spin_lock_irqsave(&port->lock, flags);
601
602 if (ctl == -1)
603 out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
604 else
605 out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
606
607 spin_unlock_irqrestore(&port->lock, flags);
608 }
609
610 static int
611 mpc52xx_uart_startup(struct uart_port *port)
612 {
613 struct mpc52xx_psc __iomem *psc = PSC(port);
614 int ret;
615
616 if (psc_ops->clock) {
617 ret = psc_ops->clock(port, 1);
618 if (ret)
619 return ret;
620 }
621
622 /* Request IRQ */
623 ret = request_irq(port->irq, mpc52xx_uart_int,
624 port->irqflags, "mpc52xx_psc_uart", port);
625 if (ret)
626 return ret;
627
628 /* Reset/activate the port, clear and enable interrupts */
629 out_8(&psc->command, MPC52xx_PSC_RST_RX);
630 out_8(&psc->command, MPC52xx_PSC_RST_TX);
631
632 out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
633
634 psc_ops->fifo_init(port);
635
636 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
637 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
638
639 return 0;
640 }
641
642 static void
643 mpc52xx_uart_shutdown(struct uart_port *port)
644 {
645 struct mpc52xx_psc __iomem *psc = PSC(port);
646
647 /* Shut down the port. Leave TX active if on a console port */
648 out_8(&psc->command, MPC52xx_PSC_RST_RX);
649 if (!uart_console(port))
650 out_8(&psc->command, MPC52xx_PSC_RST_TX);
651
652 port->read_status_mask = 0;
653 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
654
655 if (psc_ops->clock)
656 psc_ops->clock(port, 0);
657
658 /* Release interrupt */
659 free_irq(port->irq, port);
660 }
661
662 static void
663 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
664 struct ktermios *old)
665 {
666 struct mpc52xx_psc __iomem *psc = PSC(port);
667 unsigned long flags;
668 unsigned char mr1, mr2;
669 unsigned short ctr;
670 unsigned int j, baud, quot;
671
672 /* Prepare what we're gonna write */
673 mr1 = 0;
674
675 switch (new->c_cflag & CSIZE) {
676 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
677 break;
678 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
679 break;
680 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
681 break;
682 case CS8:
683 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
684 }
685
686 if (new->c_cflag & PARENB) {
687 mr1 |= (new->c_cflag & PARODD) ?
688 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
689 } else
690 mr1 |= MPC52xx_PSC_MODE_PARNONE;
691
692
693 mr2 = 0;
694
695 if (new->c_cflag & CSTOPB)
696 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
697 else
698 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
699 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
700 MPC52xx_PSC_MODE_ONE_STOP;
701
702 if (new->c_cflag & CRTSCTS) {
703 mr1 |= MPC52xx_PSC_MODE_RXRTS;
704 mr2 |= MPC52xx_PSC_MODE_TXCTS;
705 }
706
707 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
708 quot = uart_get_divisor(port, baud);
709 ctr = quot & 0xffff;
710
711 /* Get the lock */
712 spin_lock_irqsave(&port->lock, flags);
713
714 /* Update the per-port timeout */
715 uart_update_timeout(port, new->c_cflag, baud);
716
717 /* Do our best to flush TX & RX, so we don't lose anything */
718 /* But we don't wait indefinitely ! */
719 j = 5000000; /* Maximum wait */
720 /* FIXME Can't receive chars since set_termios might be called at early
721 * boot for the console, all stuff is not yet ready to receive at that
722 * time and that just makes the kernel oops */
723 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
724 while (!mpc52xx_uart_tx_empty(port) && --j)
725 udelay(1);
726
727 if (!j)
728 printk(KERN_ERR "mpc52xx_uart.c: "
729 "Unable to flush RX & TX fifos in-time in set_termios."
730 "Some chars may have been lost.\n");
731
732 /* Reset the TX & RX */
733 out_8(&psc->command, MPC52xx_PSC_RST_RX);
734 out_8(&psc->command, MPC52xx_PSC_RST_TX);
735
736 /* Send new mode settings */
737 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
738 out_8(&psc->mode, mr1);
739 out_8(&psc->mode, mr2);
740 out_8(&psc->ctur, ctr >> 8);
741 out_8(&psc->ctlr, ctr & 0xff);
742
743 if (UART_ENABLE_MS(port, new->c_cflag))
744 mpc52xx_uart_enable_ms(port);
745
746 /* Reenable TX & RX */
747 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
748 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
749
750 /* We're all set, release the lock */
751 spin_unlock_irqrestore(&port->lock, flags);
752 }
753
754 static const char *
755 mpc52xx_uart_type(struct uart_port *port)
756 {
757 return port->type == PORT_MPC52xx ? "MPC52xx PSC" : NULL;
758 }
759
760 static void
761 mpc52xx_uart_release_port(struct uart_port *port)
762 {
763 /* remapped by us ? */
764 if (port->flags & UPF_IOREMAP) {
765 iounmap(port->membase);
766 port->membase = NULL;
767 }
768
769 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
770 }
771
772 static int
773 mpc52xx_uart_request_port(struct uart_port *port)
774 {
775 int err;
776
777 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
778 port->membase = ioremap(port->mapbase,
779 sizeof(struct mpc52xx_psc));
780
781 if (!port->membase)
782 return -EINVAL;
783
784 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
785 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
786
787 if (err && (port->flags & UPF_IOREMAP)) {
788 iounmap(port->membase);
789 port->membase = NULL;
790 }
791
792 return err;
793 }
794
795 static void
796 mpc52xx_uart_config_port(struct uart_port *port, int flags)
797 {
798 if ((flags & UART_CONFIG_TYPE)
799 && (mpc52xx_uart_request_port(port) == 0))
800 port->type = PORT_MPC52xx;
801 }
802
803 static int
804 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
805 {
806 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
807 return -EINVAL;
808
809 if ((ser->irq != port->irq) ||
810 (ser->io_type != UPIO_MEM) ||
811 (ser->baud_base != port->uartclk) ||
812 (ser->iomem_base != (void *)port->mapbase) ||
813 (ser->hub6 != 0))
814 return -EINVAL;
815
816 return 0;
817 }
818
819
820 static struct uart_ops mpc52xx_uart_ops = {
821 .tx_empty = mpc52xx_uart_tx_empty,
822 .set_mctrl = mpc52xx_uart_set_mctrl,
823 .get_mctrl = mpc52xx_uart_get_mctrl,
824 .stop_tx = mpc52xx_uart_stop_tx,
825 .start_tx = mpc52xx_uart_start_tx,
826 .send_xchar = mpc52xx_uart_send_xchar,
827 .stop_rx = mpc52xx_uart_stop_rx,
828 .enable_ms = mpc52xx_uart_enable_ms,
829 .break_ctl = mpc52xx_uart_break_ctl,
830 .startup = mpc52xx_uart_startup,
831 .shutdown = mpc52xx_uart_shutdown,
832 .set_termios = mpc52xx_uart_set_termios,
833 /* .pm = mpc52xx_uart_pm, Not supported yet */
834 /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
835 .type = mpc52xx_uart_type,
836 .release_port = mpc52xx_uart_release_port,
837 .request_port = mpc52xx_uart_request_port,
838 .config_port = mpc52xx_uart_config_port,
839 .verify_port = mpc52xx_uart_verify_port
840 };
841
842
843 /* ======================================================================== */
844 /* Interrupt handling */
845 /* ======================================================================== */
846
847 static inline int
848 mpc52xx_uart_int_rx_chars(struct uart_port *port)
849 {
850 struct tty_struct *tty = port->state->port.tty;
851 unsigned char ch, flag;
852 unsigned short status;
853
854 /* While we can read, do so ! */
855 while (psc_ops->raw_rx_rdy(port)) {
856 /* Get the char */
857 ch = psc_ops->read_char(port);
858
859 /* Handle sysreq char */
860 #ifdef SUPPORT_SYSRQ
861 if (uart_handle_sysrq_char(port, ch)) {
862 port->sysrq = 0;
863 continue;
864 }
865 #endif
866
867 /* Store it */
868
869 flag = TTY_NORMAL;
870 port->icount.rx++;
871
872 status = in_be16(&PSC(port)->mpc52xx_psc_status);
873
874 if (status & (MPC52xx_PSC_SR_PE |
875 MPC52xx_PSC_SR_FE |
876 MPC52xx_PSC_SR_RB)) {
877
878 if (status & MPC52xx_PSC_SR_RB) {
879 flag = TTY_BREAK;
880 uart_handle_break(port);
881 port->icount.brk++;
882 } else if (status & MPC52xx_PSC_SR_PE) {
883 flag = TTY_PARITY;
884 port->icount.parity++;
885 }
886 else if (status & MPC52xx_PSC_SR_FE) {
887 flag = TTY_FRAME;
888 port->icount.frame++;
889 }
890
891 /* Clear error condition */
892 out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
893
894 }
895 tty_insert_flip_char(tty, ch, flag);
896 if (status & MPC52xx_PSC_SR_OE) {
897 /*
898 * Overrun is special, since it's
899 * reported immediately, and doesn't
900 * affect the current character
901 */
902 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
903 port->icount.overrun++;
904 }
905 }
906
907 spin_unlock(&port->lock);
908 tty_flip_buffer_push(tty);
909 spin_lock(&port->lock);
910
911 return psc_ops->raw_rx_rdy(port);
912 }
913
914 static inline int
915 mpc52xx_uart_int_tx_chars(struct uart_port *port)
916 {
917 struct circ_buf *xmit = &port->state->xmit;
918
919 /* Process out of band chars */
920 if (port->x_char) {
921 psc_ops->write_char(port, port->x_char);
922 port->icount.tx++;
923 port->x_char = 0;
924 return 1;
925 }
926
927 /* Nothing to do ? */
928 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
929 mpc52xx_uart_stop_tx(port);
930 return 0;
931 }
932
933 /* Send chars */
934 while (psc_ops->raw_tx_rdy(port)) {
935 psc_ops->write_char(port, xmit->buf[xmit->tail]);
936 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
937 port->icount.tx++;
938 if (uart_circ_empty(xmit))
939 break;
940 }
941
942 /* Wake up */
943 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
944 uart_write_wakeup(port);
945
946 /* Maybe we're done after all */
947 if (uart_circ_empty(xmit)) {
948 mpc52xx_uart_stop_tx(port);
949 return 0;
950 }
951
952 return 1;
953 }
954
955 static irqreturn_t
956 mpc5xxx_uart_process_int(struct uart_port *port)
957 {
958 unsigned long pass = ISR_PASS_LIMIT;
959 unsigned int keepgoing;
960 u8 status;
961
962 /* While we have stuff to do, we continue */
963 do {
964 /* If we don't find anything to do, we stop */
965 keepgoing = 0;
966
967 psc_ops->rx_clr_irq(port);
968 if (psc_ops->rx_rdy(port))
969 keepgoing |= mpc52xx_uart_int_rx_chars(port);
970
971 psc_ops->tx_clr_irq(port);
972 if (psc_ops->tx_rdy(port))
973 keepgoing |= mpc52xx_uart_int_tx_chars(port);
974
975 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
976 if (status & MPC52xx_PSC_D_DCD)
977 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
978
979 if (status & MPC52xx_PSC_D_CTS)
980 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
981
982 /* Limit number of iteration */
983 if (!(--pass))
984 keepgoing = 0;
985
986 } while (keepgoing);
987
988 return IRQ_HANDLED;
989 }
990
991 static irqreturn_t
992 mpc52xx_uart_int(int irq, void *dev_id)
993 {
994 struct uart_port *port = dev_id;
995 irqreturn_t ret;
996
997 spin_lock(&port->lock);
998
999 ret = psc_ops->handle_irq(port);
1000
1001 spin_unlock(&port->lock);
1002
1003 return ret;
1004 }
1005
1006 /* ======================================================================== */
1007 /* Console ( if applicable ) */
1008 /* ======================================================================== */
1009
1010 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1011
1012 static void __init
1013 mpc52xx_console_get_options(struct uart_port *port,
1014 int *baud, int *parity, int *bits, int *flow)
1015 {
1016 struct mpc52xx_psc __iomem *psc = PSC(port);
1017 unsigned char mr1;
1018
1019 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1020
1021 /* Read the mode registers */
1022 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
1023 mr1 = in_8(&psc->mode);
1024
1025 /* CT{U,L}R are write-only ! */
1026 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1027
1028 /* Parse them */
1029 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1030 case MPC52xx_PSC_MODE_5_BITS:
1031 *bits = 5;
1032 break;
1033 case MPC52xx_PSC_MODE_6_BITS:
1034 *bits = 6;
1035 break;
1036 case MPC52xx_PSC_MODE_7_BITS:
1037 *bits = 7;
1038 break;
1039 case MPC52xx_PSC_MODE_8_BITS:
1040 default:
1041 *bits = 8;
1042 }
1043
1044 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1045 *parity = 'n';
1046 else
1047 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1048 }
1049
1050 static void
1051 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1052 {
1053 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1054 unsigned int i, j;
1055
1056 /* Disable interrupts */
1057 psc_ops->cw_disable_ints(port);
1058
1059 /* Wait the TX buffer to be empty */
1060 j = 5000000; /* Maximum wait */
1061 while (!mpc52xx_uart_tx_empty(port) && --j)
1062 udelay(1);
1063
1064 /* Write all the chars */
1065 for (i = 0; i < count; i++, s++) {
1066 /* Line return handling */
1067 if (*s == '\n')
1068 psc_ops->write_char(port, '\r');
1069
1070 /* Send the char */
1071 psc_ops->write_char(port, *s);
1072
1073 /* Wait the TX buffer to be empty */
1074 j = 20000; /* Maximum wait */
1075 while (!mpc52xx_uart_tx_empty(port) && --j)
1076 udelay(1);
1077 }
1078
1079 /* Restore interrupt state */
1080 psc_ops->cw_restore_ints(port);
1081 }
1082
1083
1084 static int __init
1085 mpc52xx_console_setup(struct console *co, char *options)
1086 {
1087 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1088 struct device_node *np = mpc52xx_uart_nodes[co->index];
1089 unsigned int uartclk;
1090 struct resource res;
1091 int ret;
1092
1093 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1094 int bits = 8;
1095 int parity = 'n';
1096 int flow = 'n';
1097
1098 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1099 co, co->index, options);
1100
1101 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1102 pr_debug("PSC%x out of range\n", co->index);
1103 return -EINVAL;
1104 }
1105
1106 if (!np) {
1107 pr_debug("PSC%x not found in device tree\n", co->index);
1108 return -EINVAL;
1109 }
1110
1111 pr_debug("Console on ttyPSC%x is %s\n",
1112 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1113
1114 /* Fetch register locations */
1115 ret = of_address_to_resource(np, 0, &res);
1116 if (ret) {
1117 pr_debug("Could not get resources for PSC%x\n", co->index);
1118 return ret;
1119 }
1120
1121 uartclk = psc_ops->getuartclk(np);
1122 if (uartclk == 0) {
1123 pr_debug("Could not find uart clock frequency!\n");
1124 return -EINVAL;
1125 }
1126
1127 /* Basic port init. Needed since we use some uart_??? func before
1128 * real init for early access */
1129 spin_lock_init(&port->lock);
1130 port->uartclk = uartclk;
1131 port->ops = &mpc52xx_uart_ops;
1132 port->mapbase = res.start;
1133 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1134 port->irq = irq_of_parse_and_map(np, 0);
1135
1136 if (port->membase == NULL)
1137 return -EINVAL;
1138
1139 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1140 (void *)port->mapbase, port->membase,
1141 port->irq, port->uartclk);
1142
1143 /* Setup the port parameters accoding to options */
1144 if (options)
1145 uart_parse_options(options, &baud, &parity, &bits, &flow);
1146 else
1147 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1148
1149 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1150 baud, bits, parity, flow);
1151
1152 return uart_set_options(port, co, baud, parity, bits, flow);
1153 }
1154
1155
1156 static struct uart_driver mpc52xx_uart_driver;
1157
1158 static struct console mpc52xx_console = {
1159 .name = "ttyPSC",
1160 .write = mpc52xx_console_write,
1161 .device = uart_console_device,
1162 .setup = mpc52xx_console_setup,
1163 .flags = CON_PRINTBUFFER,
1164 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1165 .data = &mpc52xx_uart_driver,
1166 };
1167
1168
1169 static int __init
1170 mpc52xx_console_init(void)
1171 {
1172 mpc52xx_uart_of_enumerate();
1173 register_console(&mpc52xx_console);
1174 return 0;
1175 }
1176
1177 console_initcall(mpc52xx_console_init);
1178
1179 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1180 #else
1181 #define MPC52xx_PSC_CONSOLE NULL
1182 #endif
1183
1184
1185 /* ======================================================================== */
1186 /* UART Driver */
1187 /* ======================================================================== */
1188
1189 static struct uart_driver mpc52xx_uart_driver = {
1190 .driver_name = "mpc52xx_psc_uart",
1191 .dev_name = "ttyPSC",
1192 .major = SERIAL_PSC_MAJOR,
1193 .minor = SERIAL_PSC_MINOR,
1194 .nr = MPC52xx_PSC_MAXNUM,
1195 .cons = MPC52xx_PSC_CONSOLE,
1196 };
1197
1198 /* ======================================================================== */
1199 /* OF Platform Driver */
1200 /* ======================================================================== */
1201
1202 static struct of_device_id mpc52xx_uart_of_match[] = {
1203 #ifdef CONFIG_PPC_MPC52xx
1204 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1205 /* binding used by old lite5200 device trees: */
1206 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1207 /* binding used by efika: */
1208 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1209 #endif
1210 #ifdef CONFIG_PPC_MPC512x
1211 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1212 #endif
1213 {},
1214 };
1215
1216 static int __devinit
1217 mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match)
1218 {
1219 int idx = -1;
1220 unsigned int uartclk;
1221 struct uart_port *port = NULL;
1222 struct resource res;
1223 int ret;
1224
1225 dev_dbg(&op->dev, "mpc52xx_uart_probe(op=%p, match=%p)\n", op, match);
1226
1227 /* Check validity & presence */
1228 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1229 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1230 break;
1231 if (idx >= MPC52xx_PSC_MAXNUM)
1232 return -EINVAL;
1233 pr_debug("Found %s assigned to ttyPSC%x\n",
1234 mpc52xx_uart_nodes[idx]->full_name, idx);
1235
1236 uartclk = psc_ops->getuartclk(op->dev.of_node);
1237 if (uartclk == 0) {
1238 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1239 return -EINVAL;
1240 }
1241
1242 /* Init the port structure */
1243 port = &mpc52xx_uart_ports[idx];
1244
1245 spin_lock_init(&port->lock);
1246 port->uartclk = uartclk;
1247 port->fifosize = 512;
1248 port->iotype = UPIO_MEM;
1249 port->flags = UPF_BOOT_AUTOCONF |
1250 (uart_console(port) ? 0 : UPF_IOREMAP);
1251 port->line = idx;
1252 port->ops = &mpc52xx_uart_ops;
1253 port->dev = &op->dev;
1254
1255 /* Search for IRQ and mapbase */
1256 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1257 if (ret)
1258 return ret;
1259
1260 port->mapbase = res.start;
1261 if (!port->mapbase) {
1262 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1263 return -EINVAL;
1264 }
1265
1266 psc_ops->get_irq(port, op->dev.of_node);
1267 if (port->irq == NO_IRQ) {
1268 dev_dbg(&op->dev, "Could not get irq\n");
1269 return -EINVAL;
1270 }
1271
1272 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1273 (void *)port->mapbase, port->irq, port->uartclk);
1274
1275 /* Add the port to the uart sub-system */
1276 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1277 if (ret)
1278 return ret;
1279
1280 dev_set_drvdata(&op->dev, (void *)port);
1281 return 0;
1282 }
1283
1284 static int
1285 mpc52xx_uart_of_remove(struct of_device *op)
1286 {
1287 struct uart_port *port = dev_get_drvdata(&op->dev);
1288 dev_set_drvdata(&op->dev, NULL);
1289
1290 if (port)
1291 uart_remove_one_port(&mpc52xx_uart_driver, port);
1292
1293 return 0;
1294 }
1295
1296 #ifdef CONFIG_PM
1297 static int
1298 mpc52xx_uart_of_suspend(struct of_device *op, pm_message_t state)
1299 {
1300 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1301
1302 if (port)
1303 uart_suspend_port(&mpc52xx_uart_driver, port);
1304
1305 return 0;
1306 }
1307
1308 static int
1309 mpc52xx_uart_of_resume(struct of_device *op)
1310 {
1311 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1312
1313 if (port)
1314 uart_resume_port(&mpc52xx_uart_driver, port);
1315
1316 return 0;
1317 }
1318 #endif
1319
1320 static void
1321 mpc52xx_uart_of_assign(struct device_node *np)
1322 {
1323 int i;
1324
1325 /* Find the first free PSC number */
1326 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1327 if (mpc52xx_uart_nodes[i] == NULL) {
1328 of_node_get(np);
1329 mpc52xx_uart_nodes[i] = np;
1330 return;
1331 }
1332 }
1333 }
1334
1335 static void
1336 mpc52xx_uart_of_enumerate(void)
1337 {
1338 static int enum_done;
1339 struct device_node *np;
1340 const struct of_device_id *match;
1341 int i;
1342
1343 if (enum_done)
1344 return;
1345
1346 /* Assign index to each PSC in device tree */
1347 for_each_matching_node(np, mpc52xx_uart_of_match) {
1348 match = of_match_node(mpc52xx_uart_of_match, np);
1349 psc_ops = match->data;
1350 mpc52xx_uart_of_assign(np);
1351 }
1352
1353 enum_done = 1;
1354
1355 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1356 if (mpc52xx_uart_nodes[i])
1357 pr_debug("%s assigned to ttyPSC%x\n",
1358 mpc52xx_uart_nodes[i]->full_name, i);
1359 }
1360 }
1361
1362 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1363
1364 static struct of_platform_driver mpc52xx_uart_of_driver = {
1365 .probe = mpc52xx_uart_of_probe,
1366 .remove = mpc52xx_uart_of_remove,
1367 #ifdef CONFIG_PM
1368 .suspend = mpc52xx_uart_of_suspend,
1369 .resume = mpc52xx_uart_of_resume,
1370 #endif
1371 .driver = {
1372 .name = "mpc52xx-psc-uart",
1373 .owner = THIS_MODULE,
1374 .of_match_table = mpc52xx_uart_of_match,
1375 },
1376 };
1377
1378
1379 /* ======================================================================== */
1380 /* Module */
1381 /* ======================================================================== */
1382
1383 static int __init
1384 mpc52xx_uart_init(void)
1385 {
1386 int ret;
1387
1388 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1389
1390 ret = uart_register_driver(&mpc52xx_uart_driver);
1391 if (ret) {
1392 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1393 __FILE__, ret);
1394 return ret;
1395 }
1396
1397 mpc52xx_uart_of_enumerate();
1398
1399 /*
1400 * Map the PSC FIFO Controller and init if on MPC512x.
1401 */
1402 if (psc_ops && psc_ops->fifoc_init) {
1403 ret = psc_ops->fifoc_init();
1404 if (ret)
1405 return ret;
1406 }
1407
1408 ret = of_register_platform_driver(&mpc52xx_uart_of_driver);
1409 if (ret) {
1410 printk(KERN_ERR "%s: of_register_platform_driver failed (%i)\n",
1411 __FILE__, ret);
1412 uart_unregister_driver(&mpc52xx_uart_driver);
1413 return ret;
1414 }
1415
1416 return 0;
1417 }
1418
1419 static void __exit
1420 mpc52xx_uart_exit(void)
1421 {
1422 if (psc_ops->fifoc_uninit)
1423 psc_ops->fifoc_uninit();
1424
1425 of_unregister_platform_driver(&mpc52xx_uart_of_driver);
1426 uart_unregister_driver(&mpc52xx_uart_driver);
1427 }
1428
1429
1430 module_init(mpc52xx_uart_init);
1431 module_exit(mpc52xx_uart_exit);
1432
1433 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1434 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1435 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree