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Blackfin: clean up irq ifdef logic a bit
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / blackfin / mach-common / ints-priority.c
blob766e9f6d0627ce4e2754bcb65aaaa36d3082f56d
1 /*
2 * Set up the interrupt priorities
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
10 *
11 * Licensed under the GPL-2
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #include <linux/sched.h>
19 #ifdef CONFIG_IPIPE
20 #include <linux/ipipe.h>
21 #endif
22 #include <asm/traps.h>
23 #include <asm/blackfin.h>
24 #include <asm/gpio.h>
25 #include <asm/irq_handler.h>
26 #include <asm/dpmc.h>
27 #include <asm/bfin5xx_spi.h>
28 #include <asm/bfin_sport.h>
29 #include <asm/bfin_can.h>
30
31 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
32
33 #ifdef BF537_FAMILY
34 # define BF537_GENERIC_ERROR_INT_DEMUX
35 # define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
36 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
37 # define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
38 # define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
39 # define UART_ERR_MASK (0x6) /* UART_IIR */
40 # define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
41 #else
42 # undef BF537_GENERIC_ERROR_INT_DEMUX
43 #endif
44
45 /*
46 * NOTES:
47 * - we have separated the physical Hardware interrupt from the
48 * levels that the LINUX kernel sees (see the description in irq.h)
49 * -
50 */
51
52 #ifndef CONFIG_SMP
53 /* Initialize this to an actual value to force it into the .data
54 * section so that we know it is properly initialized at entry into
55 * the kernel but before bss is initialized to zero (which is where
56 * it would live otherwise). The 0x1f magic represents the IRQs we
57 * cannot actually mask out in hardware.
58 */
59 unsigned long bfin_irq_flags = 0x1f;
60 EXPORT_SYMBOL(bfin_irq_flags);
61 #endif
62
63 #ifdef CONFIG_PM
64 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
65 unsigned vr_wakeup;
66 #endif
67
68 static struct ivgx {
69 /* irq number for request_irq, available in mach-bf5xx/irq.h */
70 unsigned int irqno;
71 /* corresponding bit in the SIC_ISR register */
72 unsigned int isrflag;
73 } ivg_table[NR_PERI_INTS];
74
75 static struct ivg_slice {
76 /* position of first irq in ivg_table for given ivg */
77 struct ivgx *ifirst;
78 struct ivgx *istop;
79 } ivg7_13[IVG13 - IVG7 + 1];
80
81
82 /*
83 * Search SIC_IAR and fill tables with the irqvalues
84 * and their positions in the SIC_ISR register.
85 */
86 static void __init search_IAR(void)
87 {
88 unsigned ivg, irq_pos = 0;
89 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
90 int irqN;
91
92 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
93
94 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
95 int irqn;
96 u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
97 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
98 defined(CONFIG_BF538) || defined(CONFIG_BF539)
99 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
100 #else
101 (irqN >> 3)
102 #endif
103 );
104
105 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
106 int iar_shift = (irqn & 7) * 4;
107 if (ivg == (0xf & (iar >> iar_shift))) {
108 ivg_table[irq_pos].irqno = IVG7 + irqn;
109 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
110 ivg7_13[ivg].istop++;
111 irq_pos++;
112 }
113 }
114 }
115 }
116 }
117
118 /*
119 * This is for core internal IRQs
120 */
121
122 static void bfin_ack_noop(struct irq_data *d)
123 {
124 /* Dummy function. */
125 }
126
127 static void bfin_core_mask_irq(struct irq_data *d)
128 {
129 bfin_irq_flags &= ~(1 << d->irq);
130 if (!hard_irqs_disabled())
131 hard_local_irq_enable();
132 }
133
134 static void bfin_core_unmask_irq(struct irq_data *d)
135 {
136 bfin_irq_flags |= 1 << d->irq;
137 /*
138 * If interrupts are enabled, IMASK must contain the same value
139 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
140 * are currently disabled we need not do anything; one of the
141 * callers will take care of setting IMASK to the proper value
142 * when reenabling interrupts.
143 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
144 * what we need.
145 */
146 if (!hard_irqs_disabled())
147 hard_local_irq_enable();
148 return;
149 }
150
151 static void bfin_internal_mask_irq(unsigned int irq)
152 {
153 unsigned long flags = hard_local_irq_save();
154
155 #ifdef SIC_IMASK0
156 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
157 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
158 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
159 ~(1 << mask_bit));
160 # ifdef CONFIG_SMP
161 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
162 ~(1 << mask_bit));
163 # endif
164 #else
165 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
166 ~(1 << SIC_SYSIRQ(irq)));
167 #endif
168
169 hard_local_irq_restore(flags);
170 }
171
172 static void bfin_internal_mask_irq_chip(struct irq_data *d)
173 {
174 bfin_internal_mask_irq(d->irq);
175 }
176
177 #ifdef CONFIG_SMP
178 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
179 const struct cpumask *affinity)
180 #else
181 static void bfin_internal_unmask_irq(unsigned int irq)
182 #endif
183 {
184 unsigned long flags = hard_local_irq_save();
185
186 #ifdef SIC_IMASK0
187 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
188 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
189 # ifdef CONFIG_SMP
190 if (cpumask_test_cpu(0, affinity))
191 # endif
192 bfin_write_SIC_IMASK(mask_bank,
193 bfin_read_SIC_IMASK(mask_bank) |
194 (1 << mask_bit));
195 # ifdef CONFIG_SMP
196 if (cpumask_test_cpu(1, affinity))
197 bfin_write_SICB_IMASK(mask_bank,
198 bfin_read_SICB_IMASK(mask_bank) |
199 (1 << mask_bit));
200 # endif
201 #else
202 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
203 (1 << SIC_SYSIRQ(irq)));
204 #endif
205
206 hard_local_irq_restore(flags);
207 }
208
209 #ifdef CONFIG_SMP
210 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
211 {
212 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
213 }
214
215 static int bfin_internal_set_affinity(struct irq_data *d,
216 const struct cpumask *mask, bool force)
217 {
218 bfin_internal_mask_irq(d->irq);
219 bfin_internal_unmask_irq_affinity(d->irq, mask);
220
221 return 0;
222 }
223 #else
224 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
225 {
226 bfin_internal_unmask_irq(d->irq);
227 }
228 #endif
229
230 #ifdef CONFIG_PM
231 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
232 {
233 u32 bank, bit, wakeup = 0;
234 unsigned long flags;
235 bank = SIC_SYSIRQ(irq) / 32;
236 bit = SIC_SYSIRQ(irq) % 32;
237
238 switch (irq) {
239 #ifdef IRQ_RTC
240 case IRQ_RTC:
241 wakeup |= WAKE;
242 break;
243 #endif
244 #ifdef IRQ_CAN0_RX
245 case IRQ_CAN0_RX:
246 wakeup |= CANWE;
247 break;
248 #endif
249 #ifdef IRQ_CAN1_RX
250 case IRQ_CAN1_RX:
251 wakeup |= CANWE;
252 break;
253 #endif
254 #ifdef IRQ_USB_INT0
255 case IRQ_USB_INT0:
256 wakeup |= USBWE;
257 break;
258 #endif
259 #ifdef CONFIG_BF54x
260 case IRQ_CNT:
261 wakeup |= ROTWE;
262 break;
263 #endif
264 default:
265 break;
266 }
267
268 flags = hard_local_irq_save();
269
270 if (state) {
271 bfin_sic_iwr[bank] |= (1 << bit);
272 vr_wakeup |= wakeup;
273
274 } else {
275 bfin_sic_iwr[bank] &= ~(1 << bit);
276 vr_wakeup &= ~wakeup;
277 }
278
279 hard_local_irq_restore(flags);
280
281 return 0;
282 }
283
284 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
285 {
286 return bfin_internal_set_wake(d->irq, state);
287 }
288 #else
289 # define bfin_internal_set_wake_chip NULL
290 #endif
291
292 static struct irq_chip bfin_core_irqchip = {
293 .name = "CORE",
294 .irq_ack = bfin_ack_noop,
295 .irq_mask = bfin_core_mask_irq,
296 .irq_unmask = bfin_core_unmask_irq,
297 };
298
299 static struct irq_chip bfin_internal_irqchip = {
300 .name = "INTN",
301 .irq_ack = bfin_ack_noop,
302 .irq_mask = bfin_internal_mask_irq_chip,
303 .irq_unmask = bfin_internal_unmask_irq_chip,
304 .irq_mask_ack = bfin_internal_mask_irq_chip,
305 .irq_disable = bfin_internal_mask_irq_chip,
306 .irq_enable = bfin_internal_unmask_irq_chip,
307 #ifdef CONFIG_SMP
308 .irq_set_affinity = bfin_internal_set_affinity,
309 #endif
310 .irq_set_wake = bfin_internal_set_wake_chip,
311 };
312
313 static void bfin_handle_irq(unsigned irq)
314 {
315 #ifdef CONFIG_IPIPE
316 struct pt_regs regs; /* Contents not used. */
317 ipipe_trace_irq_entry(irq);
318 __ipipe_handle_irq(irq, &regs);
319 ipipe_trace_irq_exit(irq);
320 #else /* !CONFIG_IPIPE */
321 generic_handle_irq(irq);
322 #endif /* !CONFIG_IPIPE */
323 }
324
325 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
326 static int error_int_mask;
327
328 static void bfin_generic_error_mask_irq(struct irq_data *d)
329 {
330 error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
331 if (!error_int_mask)
332 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
333 }
334
335 static void bfin_generic_error_unmask_irq(struct irq_data *d)
336 {
337 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
338 error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
339 }
340
341 static struct irq_chip bfin_generic_error_irqchip = {
342 .name = "ERROR",
343 .irq_ack = bfin_ack_noop,
344 .irq_mask_ack = bfin_generic_error_mask_irq,
345 .irq_mask = bfin_generic_error_mask_irq,
346 .irq_unmask = bfin_generic_error_unmask_irq,
347 };
348
349 static void bfin_demux_error_irq(unsigned int int_err_irq,
350 struct irq_desc *inta_desc)
351 {
352 int irq = 0;
353
354 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
355 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
356 irq = IRQ_MAC_ERROR;
357 else
358 #endif
359 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
360 irq = IRQ_SPORT0_ERROR;
361 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
362 irq = IRQ_SPORT1_ERROR;
363 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
364 irq = IRQ_PPI_ERROR;
365 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
366 irq = IRQ_CAN_ERROR;
367 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
368 irq = IRQ_SPI_ERROR;
369 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
370 irq = IRQ_UART0_ERROR;
371 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
372 irq = IRQ_UART1_ERROR;
373
374 if (irq) {
375 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
376 bfin_handle_irq(irq);
377 else {
378
379 switch (irq) {
380 case IRQ_PPI_ERROR:
381 bfin_write_PPI_STATUS(PPI_ERR_MASK);
382 break;
383 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
384 case IRQ_MAC_ERROR:
385 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
386 break;
387 #endif
388 case IRQ_SPORT0_ERROR:
389 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
390 break;
391
392 case IRQ_SPORT1_ERROR:
393 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
394 break;
395
396 case IRQ_CAN_ERROR:
397 bfin_write_CAN_GIS(CAN_ERR_MASK);
398 break;
399
400 case IRQ_SPI_ERROR:
401 bfin_write_SPI_STAT(SPI_ERR_MASK);
402 break;
403
404 default:
405 break;
406 }
407
408 pr_debug("IRQ %d:"
409 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
410 irq);
411 }
412 } else
413 printk(KERN_ERR
414 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
415 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
416 __func__, __FILE__, __LINE__);
417
418 }
419 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
420
421 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
422 static int mac_stat_int_mask;
423
424 static void bfin_mac_status_ack_irq(unsigned int irq)
425 {
426 switch (irq) {
427 case IRQ_MAC_MMCINT:
428 bfin_write_EMAC_MMC_TIRQS(
429 bfin_read_EMAC_MMC_TIRQE() &
430 bfin_read_EMAC_MMC_TIRQS());
431 bfin_write_EMAC_MMC_RIRQS(
432 bfin_read_EMAC_MMC_RIRQE() &
433 bfin_read_EMAC_MMC_RIRQS());
434 break;
435 case IRQ_MAC_RXFSINT:
436 bfin_write_EMAC_RX_STKY(
437 bfin_read_EMAC_RX_IRQE() &
438 bfin_read_EMAC_RX_STKY());
439 break;
440 case IRQ_MAC_TXFSINT:
441 bfin_write_EMAC_TX_STKY(
442 bfin_read_EMAC_TX_IRQE() &
443 bfin_read_EMAC_TX_STKY());
444 break;
445 case IRQ_MAC_WAKEDET:
446 bfin_write_EMAC_WKUP_CTL(
447 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
448 break;
449 default:
450 /* These bits are W1C */
451 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
452 break;
453 }
454 }
455
456 static void bfin_mac_status_mask_irq(struct irq_data *d)
457 {
458 unsigned int irq = d->irq;
459
460 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
461 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
462 switch (irq) {
463 case IRQ_MAC_PHYINT:
464 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
465 break;
466 default:
467 break;
468 }
469 #else
470 if (!mac_stat_int_mask)
471 bfin_internal_mask_irq(IRQ_MAC_ERROR);
472 #endif
473 bfin_mac_status_ack_irq(irq);
474 }
475
476 static void bfin_mac_status_unmask_irq(struct irq_data *d)
477 {
478 unsigned int irq = d->irq;
479
480 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
481 switch (irq) {
482 case IRQ_MAC_PHYINT:
483 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
484 break;
485 default:
486 break;
487 }
488 #else
489 if (!mac_stat_int_mask)
490 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
491 #endif
492 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
493 }
494
495 #ifdef CONFIG_PM
496 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
497 {
498 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
499 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
500 #else
501 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
502 #endif
503 }
504 #else
505 # define bfin_mac_status_set_wake NULL
506 #endif
507
508 static struct irq_chip bfin_mac_status_irqchip = {
509 .name = "MACST",
510 .irq_ack = bfin_ack_noop,
511 .irq_mask_ack = bfin_mac_status_mask_irq,
512 .irq_mask = bfin_mac_status_mask_irq,
513 .irq_unmask = bfin_mac_status_unmask_irq,
514 .irq_set_wake = bfin_mac_status_set_wake,
515 };
516
517 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
518 struct irq_desc *inta_desc)
519 {
520 int i, irq = 0;
521 u32 status = bfin_read_EMAC_SYSTAT();
522
523 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
524 if (status & (1L << i)) {
525 irq = IRQ_MAC_PHYINT + i;
526 break;
527 }
528
529 if (irq) {
530 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
531 bfin_handle_irq(irq);
532 } else {
533 bfin_mac_status_ack_irq(irq);
534 pr_debug("IRQ %d:"
535 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
536 irq);
537 }
538 } else
539 printk(KERN_ERR
540 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
541 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
542 "(EMAC_SYSTAT=0x%X)\n",
543 __func__, __FILE__, __LINE__, status);
544 }
545 #endif
546
547 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
548 {
549 #ifdef CONFIG_IPIPE
550 handle = handle_level_irq;
551 #endif
552 __irq_set_handler_locked(irq, handle);
553 }
554
555 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
556 extern void bfin_gpio_irq_prepare(unsigned gpio);
557
558 #if !defined(CONFIG_BF54x)
559
560 static void bfin_gpio_ack_irq(struct irq_data *d)
561 {
562 /* AFAIK ack_irq in case mask_ack is provided
563 * get's only called for edge sense irqs
564 */
565 set_gpio_data(irq_to_gpio(d->irq), 0);
566 }
567
568 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
569 {
570 unsigned int irq = d->irq;
571 u32 gpionr = irq_to_gpio(irq);
572
573 if (!irqd_is_level_type(d))
574 set_gpio_data(gpionr, 0);
575
576 set_gpio_maska(gpionr, 0);
577 }
578
579 static void bfin_gpio_mask_irq(struct irq_data *d)
580 {
581 set_gpio_maska(irq_to_gpio(d->irq), 0);
582 }
583
584 static void bfin_gpio_unmask_irq(struct irq_data *d)
585 {
586 set_gpio_maska(irq_to_gpio(d->irq), 1);
587 }
588
589 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
590 {
591 u32 gpionr = irq_to_gpio(d->irq);
592
593 if (__test_and_set_bit(gpionr, gpio_enabled))
594 bfin_gpio_irq_prepare(gpionr);
595
596 bfin_gpio_unmask_irq(d);
597
598 return 0;
599 }
600
601 static void bfin_gpio_irq_shutdown(struct irq_data *d)
602 {
603 u32 gpionr = irq_to_gpio(d->irq);
604
605 bfin_gpio_mask_irq(d);
606 __clear_bit(gpionr, gpio_enabled);
607 bfin_gpio_irq_free(gpionr);
608 }
609
610 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
611 {
612 unsigned int irq = d->irq;
613 int ret;
614 char buf[16];
615 u32 gpionr = irq_to_gpio(irq);
616
617 if (type == IRQ_TYPE_PROBE) {
618 /* only probe unenabled GPIO interrupt lines */
619 if (test_bit(gpionr, gpio_enabled))
620 return 0;
621 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
622 }
623
624 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
625 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
626
627 snprintf(buf, 16, "gpio-irq%d", irq);
628 ret = bfin_gpio_irq_request(gpionr, buf);
629 if (ret)
630 return ret;
631
632 if (__test_and_set_bit(gpionr, gpio_enabled))
633 bfin_gpio_irq_prepare(gpionr);
634
635 } else {
636 __clear_bit(gpionr, gpio_enabled);
637 return 0;
638 }
639
640 set_gpio_inen(gpionr, 0);
641 set_gpio_dir(gpionr, 0);
642
643 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
644 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
645 set_gpio_both(gpionr, 1);
646 else
647 set_gpio_both(gpionr, 0);
648
649 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
650 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
651 else
652 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
653
654 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
655 set_gpio_edge(gpionr, 1);
656 set_gpio_inen(gpionr, 1);
657 set_gpio_data(gpionr, 0);
658
659 } else {
660 set_gpio_edge(gpionr, 0);
661 set_gpio_inen(gpionr, 1);
662 }
663
664 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
665 bfin_set_irq_handler(irq, handle_edge_irq);
666 else
667 bfin_set_irq_handler(irq, handle_level_irq);
668
669 return 0;
670 }
671
672 #ifdef CONFIG_PM
673 int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
674 {
675 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
676 }
677 #else
678 # define bfin_gpio_set_wake NULL
679 #endif
680
681 static void bfin_demux_gpio_irq(unsigned int inta_irq,
682 struct irq_desc *desc)
683 {
684 unsigned int i, gpio, mask, irq, search = 0;
685
686 switch (inta_irq) {
687 #if defined(CONFIG_BF53x)
688 case IRQ_PROG_INTA:
689 irq = IRQ_PF0;
690 search = 1;
691 break;
692 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
693 case IRQ_MAC_RX:
694 irq = IRQ_PH0;
695 break;
696 # endif
697 #elif defined(BF538_FAMILY)
698 case IRQ_PORTF_INTA:
699 irq = IRQ_PF0;
700 break;
701 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
702 case IRQ_PORTF_INTA:
703 irq = IRQ_PF0;
704 break;
705 case IRQ_PORTG_INTA:
706 irq = IRQ_PG0;
707 break;
708 case IRQ_PORTH_INTA:
709 irq = IRQ_PH0;
710 break;
711 #elif defined(CONFIG_BF561)
712 case IRQ_PROG0_INTA:
713 irq = IRQ_PF0;
714 break;
715 case IRQ_PROG1_INTA:
716 irq = IRQ_PF16;
717 break;
718 case IRQ_PROG2_INTA:
719 irq = IRQ_PF32;
720 break;
721 #endif
722 default:
723 BUG();
724 return;
725 }
726
727 if (search) {
728 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
729 irq += i;
730
731 mask = get_gpiop_data(i) & get_gpiop_maska(i);
732
733 while (mask) {
734 if (mask & 1)
735 bfin_handle_irq(irq);
736 irq++;
737 mask >>= 1;
738 }
739 }
740 } else {
741 gpio = irq_to_gpio(irq);
742 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
743
744 do {
745 if (mask & 1)
746 bfin_handle_irq(irq);
747 irq++;
748 mask >>= 1;
749 } while (mask);
750 }
751
752 }
753
754 #else /* CONFIG_BF54x */
755
756 #define NR_PINT_SYS_IRQS 4
757 #define NR_PINT_BITS 32
758 #define NR_PINTS 160
759 #define IRQ_NOT_AVAIL 0xFF
760
761 #define PINT_2_BANK(x) ((x) >> 5)
762 #define PINT_2_BIT(x) ((x) & 0x1F)
763 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
764
765 static unsigned char irq2pint_lut[NR_PINTS];
766 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
767
768 struct pin_int_t {
769 unsigned int mask_set;
770 unsigned int mask_clear;
771 unsigned int request;
772 unsigned int assign;
773 unsigned int edge_set;
774 unsigned int edge_clear;
775 unsigned int invert_set;
776 unsigned int invert_clear;
777 unsigned int pinstate;
778 unsigned int latch;
779 };
780
781 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
782 (struct pin_int_t *)PINT0_MASK_SET,
783 (struct pin_int_t *)PINT1_MASK_SET,
784 (struct pin_int_t *)PINT2_MASK_SET,
785 (struct pin_int_t *)PINT3_MASK_SET,
786 };
787
788 inline unsigned int get_irq_base(u32 bank, u8 bmap)
789 {
790 unsigned int irq_base;
791
792 if (bank < 2) { /*PA-PB */
793 irq_base = IRQ_PA0 + bmap * 16;
794 } else { /*PC-PJ */
795 irq_base = IRQ_PC0 + bmap * 16;
796 }
797
798 return irq_base;
799 }
800
801 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
802 void init_pint_lut(void)
803 {
804 u16 bank, bit, irq_base, bit_pos;
805 u32 pint_assign;
806 u8 bmap;
807
808 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
809
810 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
811
812 pint_assign = pint[bank]->assign;
813
814 for (bit = 0; bit < NR_PINT_BITS; bit++) {
815
816 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
817
818 irq_base = get_irq_base(bank, bmap);
819
820 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
821 bit_pos = bit + bank * NR_PINT_BITS;
822
823 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
824 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
825 }
826 }
827 }
828
829 static void bfin_gpio_ack_irq(struct irq_data *d)
830 {
831 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
832 u32 pintbit = PINT_BIT(pint_val);
833 u32 bank = PINT_2_BANK(pint_val);
834
835 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
836 if (pint[bank]->invert_set & pintbit)
837 pint[bank]->invert_clear = pintbit;
838 else
839 pint[bank]->invert_set = pintbit;
840 }
841 pint[bank]->request = pintbit;
842
843 }
844
845 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
846 {
847 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
848 u32 pintbit = PINT_BIT(pint_val);
849 u32 bank = PINT_2_BANK(pint_val);
850
851 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
852 if (pint[bank]->invert_set & pintbit)
853 pint[bank]->invert_clear = pintbit;
854 else
855 pint[bank]->invert_set = pintbit;
856 }
857
858 pint[bank]->request = pintbit;
859 pint[bank]->mask_clear = pintbit;
860 }
861
862 static void bfin_gpio_mask_irq(struct irq_data *d)
863 {
864 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
865
866 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
867 }
868
869 static void bfin_gpio_unmask_irq(struct irq_data *d)
870 {
871 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
872 u32 pintbit = PINT_BIT(pint_val);
873 u32 bank = PINT_2_BANK(pint_val);
874
875 pint[bank]->mask_set = pintbit;
876 }
877
878 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
879 {
880 unsigned int irq = d->irq;
881 u32 gpionr = irq_to_gpio(irq);
882 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
883
884 if (pint_val == IRQ_NOT_AVAIL) {
885 printk(KERN_ERR
886 "GPIO IRQ %d :Not in PINT Assign table "
887 "Reconfigure Interrupt to Port Assignemt\n", irq);
888 return -ENODEV;
889 }
890
891 if (__test_and_set_bit(gpionr, gpio_enabled))
892 bfin_gpio_irq_prepare(gpionr);
893
894 bfin_gpio_unmask_irq(d);
895
896 return 0;
897 }
898
899 static void bfin_gpio_irq_shutdown(struct irq_data *d)
900 {
901 u32 gpionr = irq_to_gpio(d->irq);
902
903 bfin_gpio_mask_irq(d);
904 __clear_bit(gpionr, gpio_enabled);
905 bfin_gpio_irq_free(gpionr);
906 }
907
908 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
909 {
910 unsigned int irq = d->irq;
911 int ret;
912 char buf[16];
913 u32 gpionr = irq_to_gpio(irq);
914 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
915 u32 pintbit = PINT_BIT(pint_val);
916 u32 bank = PINT_2_BANK(pint_val);
917
918 if (pint_val == IRQ_NOT_AVAIL)
919 return -ENODEV;
920
921 if (type == IRQ_TYPE_PROBE) {
922 /* only probe unenabled GPIO interrupt lines */
923 if (test_bit(gpionr, gpio_enabled))
924 return 0;
925 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
926 }
927
928 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
929 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
930
931 snprintf(buf, 16, "gpio-irq%d", irq);
932 ret = bfin_gpio_irq_request(gpionr, buf);
933 if (ret)
934 return ret;
935
936 if (__test_and_set_bit(gpionr, gpio_enabled))
937 bfin_gpio_irq_prepare(gpionr);
938
939 } else {
940 __clear_bit(gpionr, gpio_enabled);
941 return 0;
942 }
943
944 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
945 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
946 else
947 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
948
949 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
950 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
951 if (gpio_get_value(gpionr))
952 pint[bank]->invert_set = pintbit;
953 else
954 pint[bank]->invert_clear = pintbit;
955 }
956
957 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
958 pint[bank]->edge_set = pintbit;
959 bfin_set_irq_handler(irq, handle_edge_irq);
960 } else {
961 pint[bank]->edge_clear = pintbit;
962 bfin_set_irq_handler(irq, handle_level_irq);
963 }
964
965 return 0;
966 }
967
968 #ifdef CONFIG_PM
969 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
970 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
971
972 int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
973 {
974 u32 pint_irq;
975 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
976 u32 bank = PINT_2_BANK(pint_val);
977 u32 pintbit = PINT_BIT(pint_val);
978
979 switch (bank) {
980 case 0:
981 pint_irq = IRQ_PINT0;
982 break;
983 case 2:
984 pint_irq = IRQ_PINT2;
985 break;
986 case 3:
987 pint_irq = IRQ_PINT3;
988 break;
989 case 1:
990 pint_irq = IRQ_PINT1;
991 break;
992 default:
993 return -EINVAL;
994 }
995
996 bfin_internal_set_wake(pint_irq, state);
997
998 if (state)
999 pint_wakeup_masks[bank] |= pintbit;
1000 else
1001 pint_wakeup_masks[bank] &= ~pintbit;
1002
1003 return 0;
1004 }
1005
1006 u32 bfin_pm_setup(void)
1007 {
1008 u32 val, i;
1009
1010 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1011 val = pint[i]->mask_clear;
1012 pint_saved_masks[i] = val;
1013 if (val ^ pint_wakeup_masks[i]) {
1014 pint[i]->mask_clear = val;
1015 pint[i]->mask_set = pint_wakeup_masks[i];
1016 }
1017 }
1018
1019 return 0;
1020 }
1021
1022 void bfin_pm_restore(void)
1023 {
1024 u32 i, val;
1025
1026 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1027 val = pint_saved_masks[i];
1028 if (val ^ pint_wakeup_masks[i]) {
1029 pint[i]->mask_clear = pint[i]->mask_clear;
1030 pint[i]->mask_set = val;
1031 }
1032 }
1033 }
1034 #else
1035 # define bfin_gpio_set_wake NULL
1036 #endif
1037
1038 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1039 struct irq_desc *desc)
1040 {
1041 u32 bank, pint_val;
1042 u32 request, irq;
1043
1044 switch (inta_irq) {
1045 case IRQ_PINT0:
1046 bank = 0;
1047 break;
1048 case IRQ_PINT2:
1049 bank = 2;
1050 break;
1051 case IRQ_PINT3:
1052 bank = 3;
1053 break;
1054 case IRQ_PINT1:
1055 bank = 1;
1056 break;
1057 default:
1058 return;
1059 }
1060
1061 pint_val = bank * NR_PINT_BITS;
1062
1063 request = pint[bank]->request;
1064
1065 while (request) {
1066 if (request & 1) {
1067 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1068 bfin_handle_irq(irq);
1069 }
1070 pint_val++;
1071 request >>= 1;
1072 }
1073
1074 }
1075 #endif
1076
1077 static struct irq_chip bfin_gpio_irqchip = {
1078 .name = "GPIO",
1079 .irq_ack = bfin_gpio_ack_irq,
1080 .irq_mask = bfin_gpio_mask_irq,
1081 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1082 .irq_unmask = bfin_gpio_unmask_irq,
1083 .irq_disable = bfin_gpio_mask_irq,
1084 .irq_enable = bfin_gpio_unmask_irq,
1085 .irq_set_type = bfin_gpio_irq_type,
1086 .irq_startup = bfin_gpio_irq_startup,
1087 .irq_shutdown = bfin_gpio_irq_shutdown,
1088 .irq_set_wake = bfin_gpio_set_wake,
1089 };
1090
1091 void __cpuinit init_exception_vectors(void)
1092 {
1093 /* cannot program in software:
1094 * evt0 - emulation (jtag)
1095 * evt1 - reset
1096 */
1097 bfin_write_EVT2(evt_nmi);
1098 bfin_write_EVT3(trap);
1099 bfin_write_EVT5(evt_ivhw);
1100 bfin_write_EVT6(evt_timer);
1101 bfin_write_EVT7(evt_evt7);
1102 bfin_write_EVT8(evt_evt8);
1103 bfin_write_EVT9(evt_evt9);
1104 bfin_write_EVT10(evt_evt10);
1105 bfin_write_EVT11(evt_evt11);
1106 bfin_write_EVT12(evt_evt12);
1107 bfin_write_EVT13(evt_evt13);
1108 bfin_write_EVT14(evt_evt14);
1109 bfin_write_EVT15(evt_system_call);
1110 CSYNC();
1111 }
1112
1113 /*
1114 * This function should be called during kernel startup to initialize
1115 * the BFin IRQ handling routines.
1116 */
1117
1118 int __init init_arch_irq(void)
1119 {
1120 int irq;
1121 unsigned long ilat = 0;
1122
1123 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1124 #ifdef SIC_IMASK0
1125 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1126 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1127 # ifdef SIC_IMASK2
1128 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1129 # endif
1130 # ifdef CONFIG_SMP
1131 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1132 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1133 # endif
1134 #else
1135 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1136 #endif
1137
1138 local_irq_disable();
1139
1140 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1141 /* Clear EMAC Interrupt Status bits so we can demux it later */
1142 bfin_write_EMAC_SYSTAT(-1);
1143 #endif
1144
1145 #ifdef CONFIG_BF54x
1146 # ifdef CONFIG_PINTx_REASSIGN
1147 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1148 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1149 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1150 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1151 # endif
1152 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1153 init_pint_lut();
1154 #endif
1155
1156 for (irq = 0; irq <= SYS_IRQS; irq++) {
1157 if (irq <= IRQ_CORETMR)
1158 irq_set_chip(irq, &bfin_core_irqchip);
1159 else
1160 irq_set_chip(irq, &bfin_internal_irqchip);
1161
1162 switch (irq) {
1163 #if defined(CONFIG_BF53x)
1164 case IRQ_PROG_INTA:
1165 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1166 case IRQ_MAC_RX:
1167 # endif
1168 #elif defined(CONFIG_BF54x)
1169 case IRQ_PINT0:
1170 case IRQ_PINT1:
1171 case IRQ_PINT2:
1172 case IRQ_PINT3:
1173 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1174 case IRQ_PORTF_INTA:
1175 case IRQ_PORTG_INTA:
1176 case IRQ_PORTH_INTA:
1177 #elif defined(CONFIG_BF561)
1178 case IRQ_PROG0_INTA:
1179 case IRQ_PROG1_INTA:
1180 case IRQ_PROG2_INTA:
1181 #elif defined(BF538_FAMILY)
1182 case IRQ_PORTF_INTA:
1183 #endif
1184 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1185 break;
1186 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1187 case IRQ_GENERIC_ERROR:
1188 irq_set_chained_handler(irq, bfin_demux_error_irq);
1189 break;
1190 #endif
1191 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1192 case IRQ_MAC_ERROR:
1193 irq_set_chained_handler(irq,
1194 bfin_demux_mac_status_irq);
1195 break;
1196 #endif
1197 #ifdef CONFIG_SMP
1198 case IRQ_SUPPLE_0:
1199 case IRQ_SUPPLE_1:
1200 irq_set_handler(irq, handle_percpu_irq);
1201 break;
1202 #endif
1203
1204 #ifdef CONFIG_TICKSOURCE_CORETMR
1205 case IRQ_CORETMR:
1206 # ifdef CONFIG_SMP
1207 irq_set_handler(irq, handle_percpu_irq);
1208 # else
1209 irq_set_handler(irq, handle_simple_irq);
1210 # endif
1211 break;
1212 #endif
1213
1214 #ifdef CONFIG_TICKSOURCE_GPTMR0
1215 case IRQ_TIMER0:
1216 irq_set_handler(irq, handle_simple_irq);
1217 break;
1218 #endif
1219
1220 default:
1221 #ifdef CONFIG_IPIPE
1222 irq_set_handler(irq, handle_level_irq);
1223 #else
1224 irq_set_handler(irq, handle_simple_irq);
1225 #endif
1226 break;
1227 }
1228 }
1229
1230 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1231 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1232 irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
1233 handle_level_irq);
1234 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1235 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1236 #endif
1237 #endif
1238
1239 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1240 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1241 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1242 handle_level_irq);
1243 #endif
1244 /* if configured as edge, then will be changed to do_edge_IRQ */
1245 for (irq = GPIO_IRQ_BASE;
1246 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1247 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1248 handle_level_irq);
1249
1250 bfin_write_IMASK(0);
1251 CSYNC();
1252 ilat = bfin_read_ILAT();
1253 CSYNC();
1254 bfin_write_ILAT(ilat);
1255 CSYNC();
1256
1257 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1258 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1259 * local_irq_enable()
1260 */
1261 program_IAR();
1262 /* Therefore it's better to setup IARs before interrupts enabled */
1263 search_IAR();
1264
1265 /* Enable interrupts IVG7-15 */
1266 bfin_irq_flags |= IMASK_IVG15 |
1267 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1268 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1269
1270 /* This implicitly covers ANOMALY_05000171
1271 * Boot-ROM code modifies SICA_IWRx wakeup registers
1272 */
1273 #ifdef SIC_IWR0
1274 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1275 # ifdef SIC_IWR1
1276 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1277 * will screw up the bootrom as it relies on MDMA0/1 waking it
1278 * up from IDLE instructions. See this report for more info:
1279 * http://blackfin.uclinux.org/gf/tracker/4323
1280 */
1281 if (ANOMALY_05000435)
1282 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1283 else
1284 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1285 # endif
1286 # ifdef SIC_IWR2
1287 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1288 # endif
1289 #else
1290 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1291 #endif
1292
1293 return 0;
1294 }
1295
1296 #ifdef CONFIG_DO_IRQ_L1
1297 __attribute__((l1_text))
1298 #endif
1299 static int vec_to_irq(int vec)
1300 {
1301 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1302 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1303 unsigned long sic_status[3];
1304
1305 if (likely(vec == EVT_IVTMR_P))
1306 return IRQ_CORETMR;
1307
1308 #ifdef SIC_ISR
1309 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1310 #else
1311 if (smp_processor_id()) {
1312 # ifdef SICB_ISR0
1313 /* This will be optimized out in UP mode. */
1314 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1315 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1316 # endif
1317 } else {
1318 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1319 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1320 }
1321 #endif
1322 #ifdef SIC_ISR2
1323 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1324 #endif
1325
1326 for (;; ivg++) {
1327 if (ivg >= ivg_stop)
1328 return -1;
1329 #ifdef SIC_ISR
1330 if (sic_status[0] & ivg->isrflag)
1331 #else
1332 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1333 #endif
1334 return ivg->irqno;
1335 }
1336 }
1337
1338 #ifdef CONFIG_DO_IRQ_L1
1339 __attribute__((l1_text))
1340 #endif
1341 void do_irq(int vec, struct pt_regs *fp)
1342 {
1343 int irq = vec_to_irq(vec);
1344 if (irq == -1)
1345 return;
1346 asm_do_IRQ(irq, fp);
1347 }
1348
1349 #ifdef CONFIG_IPIPE
1350
1351 int __ipipe_get_irq_priority(unsigned irq)
1352 {
1353 int ient, prio;
1354
1355 if (irq <= IRQ_CORETMR)
1356 return irq;
1357
1358 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1359 struct ivgx *ivg = ivg_table + ient;
1360 if (ivg->irqno == irq) {
1361 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1362 if (ivg7_13[prio].ifirst <= ivg &&
1363 ivg7_13[prio].istop > ivg)
1364 return IVG7 + prio;
1365 }
1366 }
1367 }
1368
1369 return IVG15;
1370 }
1371
1372 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1373 #ifdef CONFIG_DO_IRQ_L1
1374 __attribute__((l1_text))
1375 #endif
1376 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1377 {
1378 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1379 struct ipipe_domain *this_domain = __ipipe_current_domain;
1380 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1381 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1382 int irq, s = 0;
1383
1384 irq = vec_to_irq(vec);
1385 if (irq == -1)
1386 return 0;
1387
1388 if (irq == IRQ_SYSTMR) {
1389 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1390 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1391 #endif
1392 /* This is basically what we need from the register frame. */
1393 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1394 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1395 if (this_domain != ipipe_root_domain)
1396 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1397 else
1398 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1399 }
1400
1401 /*
1402 * We don't want Linux interrupt handlers to run at the
1403 * current core priority level (i.e. < EVT15), since this
1404 * might delay other interrupts handled by a high priority
1405 * domain. Here is what we do instead:
1406 *
1407 * - we raise the SYNCDEFER bit to prevent
1408 * __ipipe_handle_irq() to sync the pipeline for the root
1409 * stage for the incoming interrupt. Upon return, that IRQ is
1410 * pending in the interrupt log.
1411 *
1412 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1413 * that _schedule_and_signal_from_int will eventually sync the
1414 * pipeline from EVT15.
1415 */
1416 if (this_domain == ipipe_root_domain) {
1417 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1418 barrier();
1419 }
1420
1421 ipipe_trace_irq_entry(irq);
1422 __ipipe_handle_irq(irq, regs);
1423 ipipe_trace_irq_exit(irq);
1424
1425 if (user_mode(regs) &&
1426 !ipipe_test_foreign_stack() &&
1427 (current->ipipe_flags & PF_EVTRET) != 0) {
1428 /*
1429 * Testing for user_regs() does NOT fully eliminate
1430 * foreign stack contexts, because of the forged
1431 * interrupt returns we do through
1432 * __ipipe_call_irqtail. In that case, we might have
1433 * preempted a foreign stack context in a high
1434 * priority domain, with a single interrupt level now
1435 * pending after the irqtail unwinding is done. In
1436 * which case user_mode() is now true, and the event
1437 * gets dispatched spuriously.
1438 */
1439 current->ipipe_flags &= ~PF_EVTRET;
1440 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1441 }
1442
1443 if (this_domain == ipipe_root_domain) {
1444 set_thread_flag(TIF_IRQ_SYNC);
1445 if (!s) {
1446 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1447 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1448 }
1449 }
1450
1451 return 0;
1452 }
1453
1454 #endif /* CONFIG_IPIPE */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree