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agp/intel-agp: Clear entire GTT on startup
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / intel-agp.c
blob33b4853b1353b65639385c2543ca85f5d02c428c
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 /*
14 * If we have Intel graphics, we're not going to have anything other than
15 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
16 * on the Intel IOMMU support (CONFIG_DMAR).
17 * Only newer chipsets need to bother with this, of course.
18 */
19 #ifdef CONFIG_DMAR
20 #define USE_PCI_DMA_API 1
21 #endif
22
23 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
24 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
27 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
28 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
29 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
30 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
31 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
32 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
33 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
34 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
35 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
36 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
37 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
38 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
39 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
40 #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
41 #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
42 #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
43 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
44 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
45 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
46 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
47 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
48 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
49 #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
50 #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
51 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
52 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
53 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
54 #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
55 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
56 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
57 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
58 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
59 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
60 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
61 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
62 #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
63 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
64 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
65 #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
66
67 /* cover 915 and 945 variants */
68 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
69 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
70 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
71 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
72 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
73 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
74
75 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
76 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
77 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
78 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
81
82 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
84 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
87
88 #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
89 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
90
91 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
92 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
97 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB)
100
101 extern int agp_memory_reserved;
102
103
104 /* Intel 815 register */
105 #define INTEL_815_APCONT 0x51
106 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
107
108 /* Intel i820 registers */
109 #define INTEL_I820_RDCR 0x51
110 #define INTEL_I820_ERRSTS 0xc8
111
112 /* Intel i840 registers */
113 #define INTEL_I840_MCHCFG 0x50
114 #define INTEL_I840_ERRSTS 0xc8
115
116 /* Intel i850 registers */
117 #define INTEL_I850_MCHCFG 0x50
118 #define INTEL_I850_ERRSTS 0xc8
119
120 /* intel 915G registers */
121 #define I915_GMADDR 0x18
122 #define I915_MMADDR 0x10
123 #define I915_PTEADDR 0x1C
124 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
125 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
126 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
127 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
128 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
129 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
130 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
131 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
132
133 #define I915_IFPADDR 0x60
134
135 /* Intel 965G registers */
136 #define I965_MSAC 0x62
137 #define I965_IFPADDR 0x70
138
139 /* Intel 7505 registers */
140 #define INTEL_I7505_APSIZE 0x74
141 #define INTEL_I7505_NCAPID 0x60
142 #define INTEL_I7505_NISTAT 0x6c
143 #define INTEL_I7505_ATTBASE 0x78
144 #define INTEL_I7505_ERRSTS 0x42
145 #define INTEL_I7505_AGPCTRL 0x70
146 #define INTEL_I7505_MCHCFG 0x50
147
148 static const struct aper_size_info_fixed intel_i810_sizes[] =
149 {
150 {64, 16384, 4},
151 /* The 32M mode still requires a 64k gatt */
152 {32, 8192, 4}
153 };
154
155 #define AGP_DCACHE_MEMORY 1
156 #define AGP_PHYS_MEMORY 2
157 #define INTEL_AGP_CACHED_MEMORY 3
158
159 static struct gatt_mask intel_i810_masks[] =
160 {
161 {.mask = I810_PTE_VALID, .type = 0},
162 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
163 {.mask = I810_PTE_VALID, .type = 0},
164 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
165 .type = INTEL_AGP_CACHED_MEMORY}
166 };
167
168 static struct _intel_private {
169 struct pci_dev *pcidev; /* device one */
170 u8 __iomem *registers;
171 u32 __iomem *gtt; /* I915G */
172 int num_dcache_entries;
173 /* gtt_entries is the number of gtt entries that are already mapped
174 * to stolen memory. Stolen memory is larger than the memory mapped
175 * through gtt_entries, as it includes some reserved space for the BIOS
176 * popup and for the GTT.
177 */
178 int gtt_entries; /* i830+ */
179 int gtt_total_size;
180 union {
181 void __iomem *i9xx_flush_page;
182 void *i8xx_flush_page;
183 };
184 struct page *i8xx_page;
185 struct resource ifp_resource;
186 int resource_valid;
187 } intel_private;
188
189 #ifdef USE_PCI_DMA_API
190 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
191 {
192 *ret = pci_map_page(intel_private.pcidev, page, 0,
193 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
194 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
195 return -EINVAL;
196 return 0;
197 }
198
199 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
200 {
201 pci_unmap_page(intel_private.pcidev, dma,
202 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
203 }
204
205 static void intel_agp_free_sglist(struct agp_memory *mem)
206 {
207 struct sg_table st;
208
209 st.sgl = mem->sg_list;
210 st.orig_nents = st.nents = mem->page_count;
211
212 sg_free_table(&st);
213
214 mem->sg_list = NULL;
215 mem->num_sg = 0;
216 }
217
218 static int intel_agp_map_memory(struct agp_memory *mem)
219 {
220 struct sg_table st;
221 struct scatterlist *sg;
222 int i;
223
224 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
225
226 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
227 return -ENOMEM;
228
229 mem->sg_list = sg = st.sgl;
230
231 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
232 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
233
234 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
235 mem->page_count, PCI_DMA_BIDIRECTIONAL);
236 if (unlikely(!mem->num_sg)) {
237 intel_agp_free_sglist(mem);
238 return -ENOMEM;
239 }
240 return 0;
241 }
242
243 static void intel_agp_unmap_memory(struct agp_memory *mem)
244 {
245 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
246
247 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
248 mem->page_count, PCI_DMA_BIDIRECTIONAL);
249 intel_agp_free_sglist(mem);
250 }
251
252 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
253 off_t pg_start, int mask_type)
254 {
255 struct scatterlist *sg;
256 int i, j;
257
258 j = pg_start;
259
260 WARN_ON(!mem->num_sg);
261
262 if (mem->num_sg == mem->page_count) {
263 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
264 writel(agp_bridge->driver->mask_memory(agp_bridge,
265 sg_dma_address(sg), mask_type),
266 intel_private.gtt+j);
267 j++;
268 }
269 } else {
270 /* sg may merge pages, but we have to seperate
271 * per-page addr for GTT */
272 unsigned int len, m;
273
274 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
275 len = sg_dma_len(sg) / PAGE_SIZE;
276 for (m = 0; m < len; m++) {
277 writel(agp_bridge->driver->mask_memory(agp_bridge,
278 sg_dma_address(sg) + m * PAGE_SIZE,
279 mask_type),
280 intel_private.gtt+j);
281 j++;
282 }
283 }
284 }
285 readl(intel_private.gtt+j-1);
286 }
287
288 #else
289
290 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
291 off_t pg_start, int mask_type)
292 {
293 int i, j;
294
295 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
296 writel(agp_bridge->driver->mask_memory(agp_bridge,
297 page_to_phys(mem->pages[i]), mask_type),
298 intel_private.gtt+j);
299 }
300
301 readl(intel_private.gtt+j-1);
302 }
303
304 #endif
305
306 static int intel_i810_fetch_size(void)
307 {
308 u32 smram_miscc;
309 struct aper_size_info_fixed *values;
310
311 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
312 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
313
314 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
315 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
316 return 0;
317 }
318 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
319 agp_bridge->previous_size =
320 agp_bridge->current_size = (void *) (values + 1);
321 agp_bridge->aperture_size_idx = 1;
322 return values[1].size;
323 } else {
324 agp_bridge->previous_size =
325 agp_bridge->current_size = (void *) (values);
326 agp_bridge->aperture_size_idx = 0;
327 return values[0].size;
328 }
329
330 return 0;
331 }
332
333 static int intel_i810_configure(void)
334 {
335 struct aper_size_info_fixed *current_size;
336 u32 temp;
337 int i;
338
339 current_size = A_SIZE_FIX(agp_bridge->current_size);
340
341 if (!intel_private.registers) {
342 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
343 temp &= 0xfff80000;
344
345 intel_private.registers = ioremap(temp, 128 * 4096);
346 if (!intel_private.registers) {
347 dev_err(&intel_private.pcidev->dev,
348 "can't remap memory\n");
349 return -ENOMEM;
350 }
351 }
352
353 if ((readl(intel_private.registers+I810_DRAM_CTL)
354 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
355 /* This will need to be dynamically assigned */
356 dev_info(&intel_private.pcidev->dev,
357 "detected 4MB dedicated video ram\n");
358 intel_private.num_dcache_entries = 1024;
359 }
360 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
361 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
362 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
363 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
364
365 if (agp_bridge->driver->needs_scratch_page) {
366 for (i = 0; i < current_size->num_entries; i++) {
367 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
368 }
369 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
370 }
371 global_cache_flush();
372 return 0;
373 }
374
375 static void intel_i810_cleanup(void)
376 {
377 writel(0, intel_private.registers+I810_PGETBL_CTL);
378 readl(intel_private.registers); /* PCI Posting. */
379 iounmap(intel_private.registers);
380 }
381
382 static void intel_i810_tlbflush(struct agp_memory *mem)
383 {
384 return;
385 }
386
387 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
388 {
389 return;
390 }
391
392 /* Exists to support ARGB cursors */
393 static struct page *i8xx_alloc_pages(void)
394 {
395 struct page *page;
396
397 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
398 if (page == NULL)
399 return NULL;
400
401 if (set_pages_uc(page, 4) < 0) {
402 set_pages_wb(page, 4);
403 __free_pages(page, 2);
404 return NULL;
405 }
406 get_page(page);
407 atomic_inc(&agp_bridge->current_memory_agp);
408 return page;
409 }
410
411 static void i8xx_destroy_pages(struct page *page)
412 {
413 if (page == NULL)
414 return;
415
416 set_pages_wb(page, 4);
417 put_page(page);
418 __free_pages(page, 2);
419 atomic_dec(&agp_bridge->current_memory_agp);
420 }
421
422 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
423 int type)
424 {
425 if (type < AGP_USER_TYPES)
426 return type;
427 else if (type == AGP_USER_CACHED_MEMORY)
428 return INTEL_AGP_CACHED_MEMORY;
429 else
430 return 0;
431 }
432
433 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
434 int type)
435 {
436 int i, j, num_entries;
437 void *temp;
438 int ret = -EINVAL;
439 int mask_type;
440
441 if (mem->page_count == 0)
442 goto out;
443
444 temp = agp_bridge->current_size;
445 num_entries = A_SIZE_FIX(temp)->num_entries;
446
447 if ((pg_start + mem->page_count) > num_entries)
448 goto out_err;
449
450
451 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
452 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
453 ret = -EBUSY;
454 goto out_err;
455 }
456 }
457
458 if (type != mem->type)
459 goto out_err;
460
461 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
462
463 switch (mask_type) {
464 case AGP_DCACHE_MEMORY:
465 if (!mem->is_flushed)
466 global_cache_flush();
467 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
468 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
469 intel_private.registers+I810_PTE_BASE+(i*4));
470 }
471 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
472 break;
473 case AGP_PHYS_MEMORY:
474 case AGP_NORMAL_MEMORY:
475 if (!mem->is_flushed)
476 global_cache_flush();
477 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
478 writel(agp_bridge->driver->mask_memory(agp_bridge,
479 page_to_phys(mem->pages[i]), mask_type),
480 intel_private.registers+I810_PTE_BASE+(j*4));
481 }
482 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
483 break;
484 default:
485 goto out_err;
486 }
487
488 agp_bridge->driver->tlb_flush(mem);
489 out:
490 ret = 0;
491 out_err:
492 mem->is_flushed = true;
493 return ret;
494 }
495
496 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
497 int type)
498 {
499 int i;
500
501 if (mem->page_count == 0)
502 return 0;
503
504 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
505 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
506 }
507 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
508
509 agp_bridge->driver->tlb_flush(mem);
510 return 0;
511 }
512
513 /*
514 * The i810/i830 requires a physical address to program its mouse
515 * pointer into hardware.
516 * However the Xserver still writes to it through the agp aperture.
517 */
518 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
519 {
520 struct agp_memory *new;
521 struct page *page;
522
523 switch (pg_count) {
524 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
525 break;
526 case 4:
527 /* kludge to get 4 physical pages for ARGB cursor */
528 page = i8xx_alloc_pages();
529 break;
530 default:
531 return NULL;
532 }
533
534 if (page == NULL)
535 return NULL;
536
537 new = agp_create_memory(pg_count);
538 if (new == NULL)
539 return NULL;
540
541 new->pages[0] = page;
542 if (pg_count == 4) {
543 /* kludge to get 4 physical pages for ARGB cursor */
544 new->pages[1] = new->pages[0] + 1;
545 new->pages[2] = new->pages[1] + 1;
546 new->pages[3] = new->pages[2] + 1;
547 }
548 new->page_count = pg_count;
549 new->num_scratch_pages = pg_count;
550 new->type = AGP_PHYS_MEMORY;
551 new->physical = page_to_phys(new->pages[0]);
552 return new;
553 }
554
555 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
556 {
557 struct agp_memory *new;
558
559 if (type == AGP_DCACHE_MEMORY) {
560 if (pg_count != intel_private.num_dcache_entries)
561 return NULL;
562
563 new = agp_create_memory(1);
564 if (new == NULL)
565 return NULL;
566
567 new->type = AGP_DCACHE_MEMORY;
568 new->page_count = pg_count;
569 new->num_scratch_pages = 0;
570 agp_free_page_array(new);
571 return new;
572 }
573 if (type == AGP_PHYS_MEMORY)
574 return alloc_agpphysmem_i8xx(pg_count, type);
575 return NULL;
576 }
577
578 static void intel_i810_free_by_type(struct agp_memory *curr)
579 {
580 agp_free_key(curr->key);
581 if (curr->type == AGP_PHYS_MEMORY) {
582 if (curr->page_count == 4)
583 i8xx_destroy_pages(curr->pages[0]);
584 else {
585 agp_bridge->driver->agp_destroy_page(curr->pages[0],
586 AGP_PAGE_DESTROY_UNMAP);
587 agp_bridge->driver->agp_destroy_page(curr->pages[0],
588 AGP_PAGE_DESTROY_FREE);
589 }
590 agp_free_page_array(curr);
591 }
592 kfree(curr);
593 }
594
595 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
596 dma_addr_t addr, int type)
597 {
598 /* Type checking must be done elsewhere */
599 return addr | bridge->driver->masks[type].mask;
600 }
601
602 static struct aper_size_info_fixed intel_i830_sizes[] =
603 {
604 {128, 32768, 5},
605 /* The 64M mode still requires a 128k gatt */
606 {64, 16384, 5},
607 {256, 65536, 6},
608 {512, 131072, 7},
609 };
610
611 static void intel_i830_init_gtt_entries(void)
612 {
613 u16 gmch_ctrl;
614 int gtt_entries;
615 u8 rdct;
616 int local = 0;
617 static const int ddt[4] = { 0, 16, 32, 64 };
618 int size; /* reserved space (in kb) at the top of stolen memory */
619
620 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
621
622 if (IS_I965) {
623 u32 pgetbl_ctl;
624 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
625
626 /* The 965 has a field telling us the size of the GTT,
627 * which may be larger than what is necessary to map the
628 * aperture.
629 */
630 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
631 case I965_PGETBL_SIZE_128KB:
632 size = 128;
633 break;
634 case I965_PGETBL_SIZE_256KB:
635 size = 256;
636 break;
637 case I965_PGETBL_SIZE_512KB:
638 size = 512;
639 break;
640 case I965_PGETBL_SIZE_1MB:
641 size = 1024;
642 break;
643 case I965_PGETBL_SIZE_2MB:
644 size = 2048;
645 break;
646 case I965_PGETBL_SIZE_1_5MB:
647 size = 1024 + 512;
648 break;
649 default:
650 dev_info(&intel_private.pcidev->dev,
651 "unknown page table size, assuming 512KB\n");
652 size = 512;
653 }
654 size += 4; /* add in BIOS popup space */
655 } else if (IS_G33 && !IS_PINEVIEW) {
656 /* G33's GTT size defined in gmch_ctrl */
657 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
658 case G33_PGETBL_SIZE_1M:
659 size = 1024;
660 break;
661 case G33_PGETBL_SIZE_2M:
662 size = 2048;
663 break;
664 default:
665 dev_info(&agp_bridge->dev->dev,
666 "unknown page table size 0x%x, assuming 512KB\n",
667 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
668 size = 512;
669 }
670 size += 4;
671 } else if (IS_G4X || IS_PINEVIEW) {
672 /* On 4 series hardware, GTT stolen is separate from graphics
673 * stolen, ignore it in stolen gtt entries counting. However,
674 * 4KB of the stolen memory doesn't get mapped to the GTT.
675 */
676 size = 4;
677 } else {
678 /* On previous hardware, the GTT size was just what was
679 * required to map the aperture.
680 */
681 size = agp_bridge->driver->fetch_size() + 4;
682 }
683
684 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
685 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
686 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
687 case I830_GMCH_GMS_STOLEN_512:
688 gtt_entries = KB(512) - KB(size);
689 break;
690 case I830_GMCH_GMS_STOLEN_1024:
691 gtt_entries = MB(1) - KB(size);
692 break;
693 case I830_GMCH_GMS_STOLEN_8192:
694 gtt_entries = MB(8) - KB(size);
695 break;
696 case I830_GMCH_GMS_LOCAL:
697 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
698 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
699 MB(ddt[I830_RDRAM_DDT(rdct)]);
700 local = 1;
701 break;
702 default:
703 gtt_entries = 0;
704 break;
705 }
706 } else {
707 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
708 case I855_GMCH_GMS_STOLEN_1M:
709 gtt_entries = MB(1) - KB(size);
710 break;
711 case I855_GMCH_GMS_STOLEN_4M:
712 gtt_entries = MB(4) - KB(size);
713 break;
714 case I855_GMCH_GMS_STOLEN_8M:
715 gtt_entries = MB(8) - KB(size);
716 break;
717 case I855_GMCH_GMS_STOLEN_16M:
718 gtt_entries = MB(16) - KB(size);
719 break;
720 case I855_GMCH_GMS_STOLEN_32M:
721 gtt_entries = MB(32) - KB(size);
722 break;
723 case I915_GMCH_GMS_STOLEN_48M:
724 /* Check it's really I915G */
725 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
726 gtt_entries = MB(48) - KB(size);
727 else
728 gtt_entries = 0;
729 break;
730 case I915_GMCH_GMS_STOLEN_64M:
731 /* Check it's really I915G */
732 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
733 gtt_entries = MB(64) - KB(size);
734 else
735 gtt_entries = 0;
736 break;
737 case G33_GMCH_GMS_STOLEN_128M:
738 if (IS_G33 || IS_I965 || IS_G4X)
739 gtt_entries = MB(128) - KB(size);
740 else
741 gtt_entries = 0;
742 break;
743 case G33_GMCH_GMS_STOLEN_256M:
744 if (IS_G33 || IS_I965 || IS_G4X)
745 gtt_entries = MB(256) - KB(size);
746 else
747 gtt_entries = 0;
748 break;
749 case INTEL_GMCH_GMS_STOLEN_96M:
750 if (IS_I965 || IS_G4X)
751 gtt_entries = MB(96) - KB(size);
752 else
753 gtt_entries = 0;
754 break;
755 case INTEL_GMCH_GMS_STOLEN_160M:
756 if (IS_I965 || IS_G4X)
757 gtt_entries = MB(160) - KB(size);
758 else
759 gtt_entries = 0;
760 break;
761 case INTEL_GMCH_GMS_STOLEN_224M:
762 if (IS_I965 || IS_G4X)
763 gtt_entries = MB(224) - KB(size);
764 else
765 gtt_entries = 0;
766 break;
767 case INTEL_GMCH_GMS_STOLEN_352M:
768 if (IS_I965 || IS_G4X)
769 gtt_entries = MB(352) - KB(size);
770 else
771 gtt_entries = 0;
772 break;
773 default:
774 gtt_entries = 0;
775 break;
776 }
777 }
778 if (gtt_entries > 0) {
779 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
780 gtt_entries / KB(1), local ? "local" : "stolen");
781 gtt_entries /= KB(4);
782 } else {
783 dev_info(&agp_bridge->dev->dev,
784 "no pre-allocated video memory detected\n");
785 gtt_entries = 0;
786 }
787
788 intel_private.gtt_entries = gtt_entries;
789 }
790
791 static void intel_i830_fini_flush(void)
792 {
793 kunmap(intel_private.i8xx_page);
794 intel_private.i8xx_flush_page = NULL;
795 unmap_page_from_agp(intel_private.i8xx_page);
796
797 __free_page(intel_private.i8xx_page);
798 intel_private.i8xx_page = NULL;
799 }
800
801 static void intel_i830_setup_flush(void)
802 {
803 /* return if we've already set the flush mechanism up */
804 if (intel_private.i8xx_page)
805 return;
806
807 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
808 if (!intel_private.i8xx_page)
809 return;
810
811 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
812 if (!intel_private.i8xx_flush_page)
813 intel_i830_fini_flush();
814 }
815
816 static void
817 do_wbinvd(void *null)
818 {
819 wbinvd();
820 }
821
822 /* The chipset_flush interface needs to get data that has already been
823 * flushed out of the CPU all the way out to main memory, because the GPU
824 * doesn't snoop those buffers.
825 *
826 * The 8xx series doesn't have the same lovely interface for flushing the
827 * chipset write buffers that the later chips do. According to the 865
828 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
829 * that buffer out, we just fill 1KB and clflush it out, on the assumption
830 * that it'll push whatever was in there out. It appears to work.
831 */
832 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
833 {
834 unsigned int *pg = intel_private.i8xx_flush_page;
835
836 memset(pg, 0, 1024);
837
838 if (cpu_has_clflush) {
839 clflush_cache_range(pg, 1024);
840 } else {
841 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
842 printk(KERN_ERR "Timed out waiting for cache flush.\n");
843 }
844 }
845
846 /* The intel i830 automatically initializes the agp aperture during POST.
847 * Use the memory already set aside for in the GTT.
848 */
849 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
850 {
851 int page_order;
852 struct aper_size_info_fixed *size;
853 int num_entries;
854 u32 temp;
855
856 size = agp_bridge->current_size;
857 page_order = size->page_order;
858 num_entries = size->num_entries;
859 agp_bridge->gatt_table_real = NULL;
860
861 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
862 temp &= 0xfff80000;
863
864 intel_private.registers = ioremap(temp, 128 * 4096);
865 if (!intel_private.registers)
866 return -ENOMEM;
867
868 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
869 global_cache_flush(); /* FIXME: ?? */
870
871 /* we have to call this as early as possible after the MMIO base address is known */
872 intel_i830_init_gtt_entries();
873
874 agp_bridge->gatt_table = NULL;
875
876 agp_bridge->gatt_bus_addr = temp;
877
878 return 0;
879 }
880
881 /* Return the gatt table to a sane state. Use the top of stolen
882 * memory for the GTT.
883 */
884 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
885 {
886 return 0;
887 }
888
889 static int intel_i830_fetch_size(void)
890 {
891 u16 gmch_ctrl;
892 struct aper_size_info_fixed *values;
893
894 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
895
896 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
897 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
898 /* 855GM/852GM/865G has 128MB aperture size */
899 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
900 agp_bridge->aperture_size_idx = 0;
901 return values[0].size;
902 }
903
904 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
905
906 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
907 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
908 agp_bridge->aperture_size_idx = 0;
909 return values[0].size;
910 } else {
911 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
912 agp_bridge->aperture_size_idx = 1;
913 return values[1].size;
914 }
915
916 return 0;
917 }
918
919 static int intel_i830_configure(void)
920 {
921 struct aper_size_info_fixed *current_size;
922 u32 temp;
923 u16 gmch_ctrl;
924 int i;
925
926 current_size = A_SIZE_FIX(agp_bridge->current_size);
927
928 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
929 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
930
931 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
932 gmch_ctrl |= I830_GMCH_ENABLED;
933 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
934
935 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
936 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
937
938 if (agp_bridge->driver->needs_scratch_page) {
939 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
940 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
941 }
942 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
943 }
944
945 global_cache_flush();
946
947 intel_i830_setup_flush();
948 return 0;
949 }
950
951 static void intel_i830_cleanup(void)
952 {
953 iounmap(intel_private.registers);
954 }
955
956 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
957 int type)
958 {
959 int i, j, num_entries;
960 void *temp;
961 int ret = -EINVAL;
962 int mask_type;
963
964 if (mem->page_count == 0)
965 goto out;
966
967 temp = agp_bridge->current_size;
968 num_entries = A_SIZE_FIX(temp)->num_entries;
969
970 if (pg_start < intel_private.gtt_entries) {
971 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
972 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
973 pg_start, intel_private.gtt_entries);
974
975 dev_info(&intel_private.pcidev->dev,
976 "trying to insert into local/stolen memory\n");
977 goto out_err;
978 }
979
980 if ((pg_start + mem->page_count) > num_entries)
981 goto out_err;
982
983 /* The i830 can't check the GTT for entries since its read only,
984 * depend on the caller to make the correct offset decisions.
985 */
986
987 if (type != mem->type)
988 goto out_err;
989
990 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
991
992 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
993 mask_type != INTEL_AGP_CACHED_MEMORY)
994 goto out_err;
995
996 if (!mem->is_flushed)
997 global_cache_flush();
998
999 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1000 writel(agp_bridge->driver->mask_memory(agp_bridge,
1001 page_to_phys(mem->pages[i]), mask_type),
1002 intel_private.registers+I810_PTE_BASE+(j*4));
1003 }
1004 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1005 agp_bridge->driver->tlb_flush(mem);
1006
1007 out:
1008 ret = 0;
1009 out_err:
1010 mem->is_flushed = true;
1011 return ret;
1012 }
1013
1014 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1015 int type)
1016 {
1017 int i;
1018
1019 if (mem->page_count == 0)
1020 return 0;
1021
1022 if (pg_start < intel_private.gtt_entries) {
1023 dev_info(&intel_private.pcidev->dev,
1024 "trying to disable local/stolen memory\n");
1025 return -EINVAL;
1026 }
1027
1028 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1029 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1030 }
1031 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1032
1033 agp_bridge->driver->tlb_flush(mem);
1034 return 0;
1035 }
1036
1037 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1038 {
1039 if (type == AGP_PHYS_MEMORY)
1040 return alloc_agpphysmem_i8xx(pg_count, type);
1041 /* always return NULL for other allocation types for now */
1042 return NULL;
1043 }
1044
1045 static int intel_alloc_chipset_flush_resource(void)
1046 {
1047 int ret;
1048 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1049 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1050 pcibios_align_resource, agp_bridge->dev);
1051
1052 return ret;
1053 }
1054
1055 static void intel_i915_setup_chipset_flush(void)
1056 {
1057 int ret;
1058 u32 temp;
1059
1060 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1061 if (!(temp & 0x1)) {
1062 intel_alloc_chipset_flush_resource();
1063 intel_private.resource_valid = 1;
1064 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1065 } else {
1066 temp &= ~1;
1067
1068 intel_private.resource_valid = 1;
1069 intel_private.ifp_resource.start = temp;
1070 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1071 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1072 /* some BIOSes reserve this area in a pnp some don't */
1073 if (ret)
1074 intel_private.resource_valid = 0;
1075 }
1076 }
1077
1078 static void intel_i965_g33_setup_chipset_flush(void)
1079 {
1080 u32 temp_hi, temp_lo;
1081 int ret;
1082
1083 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1084 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1085
1086 if (!(temp_lo & 0x1)) {
1087
1088 intel_alloc_chipset_flush_resource();
1089
1090 intel_private.resource_valid = 1;
1091 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1092 upper_32_bits(intel_private.ifp_resource.start));
1093 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1094 } else {
1095 u64 l64;
1096
1097 temp_lo &= ~0x1;
1098 l64 = ((u64)temp_hi << 32) | temp_lo;
1099
1100 intel_private.resource_valid = 1;
1101 intel_private.ifp_resource.start = l64;
1102 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1103 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1104 /* some BIOSes reserve this area in a pnp some don't */
1105 if (ret)
1106 intel_private.resource_valid = 0;
1107 }
1108 }
1109
1110 static void intel_i9xx_setup_flush(void)
1111 {
1112 /* return if already configured */
1113 if (intel_private.ifp_resource.start)
1114 return;
1115
1116 /* setup a resource for this object */
1117 intel_private.ifp_resource.name = "Intel Flush Page";
1118 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1119
1120 /* Setup chipset flush for 915 */
1121 if (IS_I965 || IS_G33 || IS_G4X) {
1122 intel_i965_g33_setup_chipset_flush();
1123 } else {
1124 intel_i915_setup_chipset_flush();
1125 }
1126
1127 if (intel_private.ifp_resource.start) {
1128 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1129 if (!intel_private.i9xx_flush_page)
1130 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1131 }
1132 }
1133
1134 static int intel_i915_configure(void)
1135 {
1136 struct aper_size_info_fixed *current_size;
1137 u32 temp;
1138 u16 gmch_ctrl;
1139 int i;
1140
1141 current_size = A_SIZE_FIX(agp_bridge->current_size);
1142
1143 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1144
1145 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1146
1147 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1148 gmch_ctrl |= I830_GMCH_ENABLED;
1149 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1150
1151 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1152 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1153
1154 if (agp_bridge->driver->needs_scratch_page) {
1155 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1156 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1157 }
1158 readl(intel_private.gtt+i-1); /* PCI Posting. */
1159 }
1160
1161 global_cache_flush();
1162
1163 intel_i9xx_setup_flush();
1164
1165 #ifdef USE_PCI_DMA_API
1166 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
1167 dev_err(&intel_private.pcidev->dev,
1168 "set gfx device dma mask 36bit failed!\n");
1169 #endif
1170
1171 return 0;
1172 }
1173
1174 static void intel_i915_cleanup(void)
1175 {
1176 if (intel_private.i9xx_flush_page)
1177 iounmap(intel_private.i9xx_flush_page);
1178 if (intel_private.resource_valid)
1179 release_resource(&intel_private.ifp_resource);
1180 intel_private.ifp_resource.start = 0;
1181 intel_private.resource_valid = 0;
1182 iounmap(intel_private.gtt);
1183 iounmap(intel_private.registers);
1184 }
1185
1186 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1187 {
1188 if (intel_private.i9xx_flush_page)
1189 writel(1, intel_private.i9xx_flush_page);
1190 }
1191
1192 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1193 int type)
1194 {
1195 int num_entries;
1196 void *temp;
1197 int ret = -EINVAL;
1198 int mask_type;
1199
1200 if (mem->page_count == 0)
1201 goto out;
1202
1203 temp = agp_bridge->current_size;
1204 num_entries = A_SIZE_FIX(temp)->num_entries;
1205
1206 if (pg_start < intel_private.gtt_entries) {
1207 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1208 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1209 pg_start, intel_private.gtt_entries);
1210
1211 dev_info(&intel_private.pcidev->dev,
1212 "trying to insert into local/stolen memory\n");
1213 goto out_err;
1214 }
1215
1216 if ((pg_start + mem->page_count) > num_entries)
1217 goto out_err;
1218
1219 /* The i915 can't check the GTT for entries since it's read only;
1220 * depend on the caller to make the correct offset decisions.
1221 */
1222
1223 if (type != mem->type)
1224 goto out_err;
1225
1226 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1227
1228 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1229 mask_type != INTEL_AGP_CACHED_MEMORY)
1230 goto out_err;
1231
1232 if (!mem->is_flushed)
1233 global_cache_flush();
1234
1235 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1236 agp_bridge->driver->tlb_flush(mem);
1237
1238 out:
1239 ret = 0;
1240 out_err:
1241 mem->is_flushed = true;
1242 return ret;
1243 }
1244
1245 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1246 int type)
1247 {
1248 int i;
1249
1250 if (mem->page_count == 0)
1251 return 0;
1252
1253 if (pg_start < intel_private.gtt_entries) {
1254 dev_info(&intel_private.pcidev->dev,
1255 "trying to disable local/stolen memory\n");
1256 return -EINVAL;
1257 }
1258
1259 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1260 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1261
1262 readl(intel_private.gtt+i-1);
1263
1264 agp_bridge->driver->tlb_flush(mem);
1265 return 0;
1266 }
1267
1268 /* Return the aperture size by just checking the resource length. The effect
1269 * described in the spec of the MSAC registers is just changing of the
1270 * resource size.
1271 */
1272 static int intel_i9xx_fetch_size(void)
1273 {
1274 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1275 int aper_size; /* size in megabytes */
1276 int i;
1277
1278 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1279
1280 for (i = 0; i < num_sizes; i++) {
1281 if (aper_size == intel_i830_sizes[i].size) {
1282 agp_bridge->current_size = intel_i830_sizes + i;
1283 agp_bridge->previous_size = agp_bridge->current_size;
1284 return aper_size;
1285 }
1286 }
1287
1288 return 0;
1289 }
1290
1291 /* The intel i915 automatically initializes the agp aperture during POST.
1292 * Use the memory already set aside for in the GTT.
1293 */
1294 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1295 {
1296 int page_order;
1297 struct aper_size_info_fixed *size;
1298 int num_entries;
1299 u32 temp, temp2;
1300 int gtt_map_size = 256 * 1024;
1301
1302 size = agp_bridge->current_size;
1303 page_order = size->page_order;
1304 num_entries = size->num_entries;
1305 agp_bridge->gatt_table_real = NULL;
1306
1307 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1308 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1309
1310 if (IS_G33)
1311 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1312 intel_private.gtt = ioremap(temp2, gtt_map_size);
1313 if (!intel_private.gtt)
1314 return -ENOMEM;
1315
1316 intel_private.gtt_total_size = gtt_map_size / 4;
1317
1318 temp &= 0xfff80000;
1319
1320 intel_private.registers = ioremap(temp, 128 * 4096);
1321 if (!intel_private.registers) {
1322 iounmap(intel_private.gtt);
1323 return -ENOMEM;
1324 }
1325
1326 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1327 global_cache_flush(); /* FIXME: ? */
1328
1329 /* we have to call this as early as possible after the MMIO base address is known */
1330 intel_i830_init_gtt_entries();
1331
1332 agp_bridge->gatt_table = NULL;
1333
1334 agp_bridge->gatt_bus_addr = temp;
1335
1336 return 0;
1337 }
1338
1339 /*
1340 * The i965 supports 36-bit physical addresses, but to keep
1341 * the format of the GTT the same, the bits that don't fit
1342 * in a 32-bit word are shifted down to bits 4..7.
1343 *
1344 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1345 * is always zero on 32-bit architectures, so no need to make
1346 * this conditional.
1347 */
1348 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1349 dma_addr_t addr, int type)
1350 {
1351 /* Shift high bits down */
1352 addr |= (addr >> 28) & 0xf0;
1353
1354 /* Type checking must be done elsewhere */
1355 return addr | bridge->driver->masks[type].mask;
1356 }
1357
1358 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1359 {
1360 switch (agp_bridge->dev->device) {
1361 case PCI_DEVICE_ID_INTEL_GM45_HB:
1362 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
1363 case PCI_DEVICE_ID_INTEL_Q45_HB:
1364 case PCI_DEVICE_ID_INTEL_G45_HB:
1365 case PCI_DEVICE_ID_INTEL_G41_HB:
1366 case PCI_DEVICE_ID_INTEL_B43_HB:
1367 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
1368 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
1369 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
1370 *gtt_offset = *gtt_size = MB(2);
1371 break;
1372 default:
1373 *gtt_offset = *gtt_size = KB(512);
1374 }
1375 }
1376
1377 /* The intel i965 automatically initializes the agp aperture during POST.
1378 * Use the memory already set aside for in the GTT.
1379 */
1380 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1381 {
1382 int page_order;
1383 struct aper_size_info_fixed *size;
1384 int num_entries;
1385 u32 temp;
1386 int gtt_offset, gtt_size;
1387
1388 size = agp_bridge->current_size;
1389 page_order = size->page_order;
1390 num_entries = size->num_entries;
1391 agp_bridge->gatt_table_real = NULL;
1392
1393 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1394
1395 temp &= 0xfff00000;
1396
1397 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1398
1399 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1400
1401 if (!intel_private.gtt)
1402 return -ENOMEM;
1403
1404 intel_private.gtt_total_size = gtt_size / 4;
1405
1406 intel_private.registers = ioremap(temp, 128 * 4096);
1407 if (!intel_private.registers) {
1408 iounmap(intel_private.gtt);
1409 return -ENOMEM;
1410 }
1411
1412 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1413 global_cache_flush(); /* FIXME: ? */
1414
1415 /* we have to call this as early as possible after the MMIO base address is known */
1416 intel_i830_init_gtt_entries();
1417
1418 agp_bridge->gatt_table = NULL;
1419
1420 agp_bridge->gatt_bus_addr = temp;
1421
1422 return 0;
1423 }
1424
1425
1426 static int intel_fetch_size(void)
1427 {
1428 int i;
1429 u16 temp;
1430 struct aper_size_info_16 *values;
1431
1432 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1433 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1434
1435 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1436 if (temp == values[i].size_value) {
1437 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1438 agp_bridge->aperture_size_idx = i;
1439 return values[i].size;
1440 }
1441 }
1442
1443 return 0;
1444 }
1445
1446 static int __intel_8xx_fetch_size(u8 temp)
1447 {
1448 int i;
1449 struct aper_size_info_8 *values;
1450
1451 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1452
1453 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1454 if (temp == values[i].size_value) {
1455 agp_bridge->previous_size =
1456 agp_bridge->current_size = (void *) (values + i);
1457 agp_bridge->aperture_size_idx = i;
1458 return values[i].size;
1459 }
1460 }
1461 return 0;
1462 }
1463
1464 static int intel_8xx_fetch_size(void)
1465 {
1466 u8 temp;
1467
1468 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1469 return __intel_8xx_fetch_size(temp);
1470 }
1471
1472 static int intel_815_fetch_size(void)
1473 {
1474 u8 temp;
1475
1476 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1477 * one non-reserved bit, so mask the others out ... */
1478 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1479 temp &= (1 << 3);
1480
1481 return __intel_8xx_fetch_size(temp);
1482 }
1483
1484 static void intel_tlbflush(struct agp_memory *mem)
1485 {
1486 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1487 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1488 }
1489
1490
1491 static void intel_8xx_tlbflush(struct agp_memory *mem)
1492 {
1493 u32 temp;
1494 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1495 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1496 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1497 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1498 }
1499
1500
1501 static void intel_cleanup(void)
1502 {
1503 u16 temp;
1504 struct aper_size_info_16 *previous_size;
1505
1506 previous_size = A_SIZE_16(agp_bridge->previous_size);
1507 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1508 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1509 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1510 }
1511
1512
1513 static void intel_8xx_cleanup(void)
1514 {
1515 u16 temp;
1516 struct aper_size_info_8 *previous_size;
1517
1518 previous_size = A_SIZE_8(agp_bridge->previous_size);
1519 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1520 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1521 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1522 }
1523
1524
1525 static int intel_configure(void)
1526 {
1527 u32 temp;
1528 u16 temp2;
1529 struct aper_size_info_16 *current_size;
1530
1531 current_size = A_SIZE_16(agp_bridge->current_size);
1532
1533 /* aperture size */
1534 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1535
1536 /* address to map to */
1537 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1538 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1539
1540 /* attbase - aperture base */
1541 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1542
1543 /* agpctrl */
1544 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1545
1546 /* paccfg/nbxcfg */
1547 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1548 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1549 (temp2 & ~(1 << 10)) | (1 << 9));
1550 /* clear any possible error conditions */
1551 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1552 return 0;
1553 }
1554
1555 static int intel_815_configure(void)
1556 {
1557 u32 temp, addr;
1558 u8 temp2;
1559 struct aper_size_info_8 *current_size;
1560
1561 /* attbase - aperture base */
1562 /* the Intel 815 chipset spec. says that bits 29-31 in the
1563 * ATTBASE register are reserved -> try not to write them */
1564 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1565 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1566 return -EINVAL;
1567 }
1568
1569 current_size = A_SIZE_8(agp_bridge->current_size);
1570
1571 /* aperture size */
1572 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1573 current_size->size_value);
1574
1575 /* address to map to */
1576 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1577 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1578
1579 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1580 addr &= INTEL_815_ATTBASE_MASK;
1581 addr |= agp_bridge->gatt_bus_addr;
1582 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1583
1584 /* agpctrl */
1585 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1586
1587 /* apcont */
1588 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1589 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1590
1591 /* clear any possible error conditions */
1592 /* Oddness : this chipset seems to have no ERRSTS register ! */
1593 return 0;
1594 }
1595
1596 static void intel_820_tlbflush(struct agp_memory *mem)
1597 {
1598 return;
1599 }
1600
1601 static void intel_820_cleanup(void)
1602 {
1603 u8 temp;
1604 struct aper_size_info_8 *previous_size;
1605
1606 previous_size = A_SIZE_8(agp_bridge->previous_size);
1607 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1608 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1609 temp & ~(1 << 1));
1610 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1611 previous_size->size_value);
1612 }
1613
1614
1615 static int intel_820_configure(void)
1616 {
1617 u32 temp;
1618 u8 temp2;
1619 struct aper_size_info_8 *current_size;
1620
1621 current_size = A_SIZE_8(agp_bridge->current_size);
1622
1623 /* aperture size */
1624 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1625
1626 /* address to map to */
1627 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1628 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1629
1630 /* attbase - aperture base */
1631 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1632
1633 /* agpctrl */
1634 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1635
1636 /* global enable aperture access */
1637 /* This flag is not accessed through MCHCFG register as in */
1638 /* i850 chipset. */
1639 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1640 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1641 /* clear any possible AGP-related error conditions */
1642 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1643 return 0;
1644 }
1645
1646 static int intel_840_configure(void)
1647 {
1648 u32 temp;
1649 u16 temp2;
1650 struct aper_size_info_8 *current_size;
1651
1652 current_size = A_SIZE_8(agp_bridge->current_size);
1653
1654 /* aperture size */
1655 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1656
1657 /* address to map to */
1658 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1659 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1660
1661 /* attbase - aperture base */
1662 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1663
1664 /* agpctrl */
1665 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1666
1667 /* mcgcfg */
1668 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1669 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1670 /* clear any possible error conditions */
1671 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1672 return 0;
1673 }
1674
1675 static int intel_845_configure(void)
1676 {
1677 u32 temp;
1678 u8 temp2;
1679 struct aper_size_info_8 *current_size;
1680
1681 current_size = A_SIZE_8(agp_bridge->current_size);
1682
1683 /* aperture size */
1684 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1685
1686 if (agp_bridge->apbase_config != 0) {
1687 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1688 agp_bridge->apbase_config);
1689 } else {
1690 /* address to map to */
1691 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1692 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1693 agp_bridge->apbase_config = temp;
1694 }
1695
1696 /* attbase - aperture base */
1697 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1698
1699 /* agpctrl */
1700 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1701
1702 /* agpm */
1703 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1704 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1705 /* clear any possible error conditions */
1706 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1707
1708 intel_i830_setup_flush();
1709 return 0;
1710 }
1711
1712 static int intel_850_configure(void)
1713 {
1714 u32 temp;
1715 u16 temp2;
1716 struct aper_size_info_8 *current_size;
1717
1718 current_size = A_SIZE_8(agp_bridge->current_size);
1719
1720 /* aperture size */
1721 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1722
1723 /* address to map to */
1724 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1725 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1726
1727 /* attbase - aperture base */
1728 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1729
1730 /* agpctrl */
1731 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1732
1733 /* mcgcfg */
1734 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1735 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1736 /* clear any possible AGP-related error conditions */
1737 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1738 return 0;
1739 }
1740
1741 static int intel_860_configure(void)
1742 {
1743 u32 temp;
1744 u16 temp2;
1745 struct aper_size_info_8 *current_size;
1746
1747 current_size = A_SIZE_8(agp_bridge->current_size);
1748
1749 /* aperture size */
1750 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1751
1752 /* address to map to */
1753 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1754 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1755
1756 /* attbase - aperture base */
1757 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1758
1759 /* agpctrl */
1760 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1761
1762 /* mcgcfg */
1763 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1764 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1765 /* clear any possible AGP-related error conditions */
1766 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1767 return 0;
1768 }
1769
1770 static int intel_830mp_configure(void)
1771 {
1772 u32 temp;
1773 u16 temp2;
1774 struct aper_size_info_8 *current_size;
1775
1776 current_size = A_SIZE_8(agp_bridge->current_size);
1777
1778 /* aperture size */
1779 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1780
1781 /* address to map to */
1782 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1783 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1784
1785 /* attbase - aperture base */
1786 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1787
1788 /* agpctrl */
1789 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1790
1791 /* gmch */
1792 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1793 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1794 /* clear any possible AGP-related error conditions */
1795 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1796 return 0;
1797 }
1798
1799 static int intel_7505_configure(void)
1800 {
1801 u32 temp;
1802 u16 temp2;
1803 struct aper_size_info_8 *current_size;
1804
1805 current_size = A_SIZE_8(agp_bridge->current_size);
1806
1807 /* aperture size */
1808 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1809
1810 /* address to map to */
1811 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1812 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1813
1814 /* attbase - aperture base */
1815 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1816
1817 /* agpctrl */
1818 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1819
1820 /* mchcfg */
1821 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1822 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1823
1824 return 0;
1825 }
1826
1827 /* Setup function */
1828 static const struct gatt_mask intel_generic_masks[] =
1829 {
1830 {.mask = 0x00000017, .type = 0}
1831 };
1832
1833 static const struct aper_size_info_8 intel_815_sizes[2] =
1834 {
1835 {64, 16384, 4, 0},
1836 {32, 8192, 3, 8},
1837 };
1838
1839 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1840 {
1841 {256, 65536, 6, 0},
1842 {128, 32768, 5, 32},
1843 {64, 16384, 4, 48},
1844 {32, 8192, 3, 56},
1845 {16, 4096, 2, 60},
1846 {8, 2048, 1, 62},
1847 {4, 1024, 0, 63}
1848 };
1849
1850 static const struct aper_size_info_16 intel_generic_sizes[7] =
1851 {
1852 {256, 65536, 6, 0},
1853 {128, 32768, 5, 32},
1854 {64, 16384, 4, 48},
1855 {32, 8192, 3, 56},
1856 {16, 4096, 2, 60},
1857 {8, 2048, 1, 62},
1858 {4, 1024, 0, 63}
1859 };
1860
1861 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1862 {
1863 {256, 65536, 6, 0},
1864 {128, 32768, 5, 32},
1865 {64, 16384, 4, 48},
1866 {32, 8192, 3, 56}
1867 };
1868
1869 static const struct agp_bridge_driver intel_generic_driver = {
1870 .owner = THIS_MODULE,
1871 .aperture_sizes = intel_generic_sizes,
1872 .size_type = U16_APER_SIZE,
1873 .num_aperture_sizes = 7,
1874 .configure = intel_configure,
1875 .fetch_size = intel_fetch_size,
1876 .cleanup = intel_cleanup,
1877 .tlb_flush = intel_tlbflush,
1878 .mask_memory = agp_generic_mask_memory,
1879 .masks = intel_generic_masks,
1880 .agp_enable = agp_generic_enable,
1881 .cache_flush = global_cache_flush,
1882 .create_gatt_table = agp_generic_create_gatt_table,
1883 .free_gatt_table = agp_generic_free_gatt_table,
1884 .insert_memory = agp_generic_insert_memory,
1885 .remove_memory = agp_generic_remove_memory,
1886 .alloc_by_type = agp_generic_alloc_by_type,
1887 .free_by_type = agp_generic_free_by_type,
1888 .agp_alloc_page = agp_generic_alloc_page,
1889 .agp_alloc_pages = agp_generic_alloc_pages,
1890 .agp_destroy_page = agp_generic_destroy_page,
1891 .agp_destroy_pages = agp_generic_destroy_pages,
1892 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1893 };
1894
1895 static const struct agp_bridge_driver intel_810_driver = {
1896 .owner = THIS_MODULE,
1897 .aperture_sizes = intel_i810_sizes,
1898 .size_type = FIXED_APER_SIZE,
1899 .num_aperture_sizes = 2,
1900 .needs_scratch_page = true,
1901 .configure = intel_i810_configure,
1902 .fetch_size = intel_i810_fetch_size,
1903 .cleanup = intel_i810_cleanup,
1904 .tlb_flush = intel_i810_tlbflush,
1905 .mask_memory = intel_i810_mask_memory,
1906 .masks = intel_i810_masks,
1907 .agp_enable = intel_i810_agp_enable,
1908 .cache_flush = global_cache_flush,
1909 .create_gatt_table = agp_generic_create_gatt_table,
1910 .free_gatt_table = agp_generic_free_gatt_table,
1911 .insert_memory = intel_i810_insert_entries,
1912 .remove_memory = intel_i810_remove_entries,
1913 .alloc_by_type = intel_i810_alloc_by_type,
1914 .free_by_type = intel_i810_free_by_type,
1915 .agp_alloc_page = agp_generic_alloc_page,
1916 .agp_alloc_pages = agp_generic_alloc_pages,
1917 .agp_destroy_page = agp_generic_destroy_page,
1918 .agp_destroy_pages = agp_generic_destroy_pages,
1919 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1920 };
1921
1922 static const struct agp_bridge_driver intel_815_driver = {
1923 .owner = THIS_MODULE,
1924 .aperture_sizes = intel_815_sizes,
1925 .size_type = U8_APER_SIZE,
1926 .num_aperture_sizes = 2,
1927 .configure = intel_815_configure,
1928 .fetch_size = intel_815_fetch_size,
1929 .cleanup = intel_8xx_cleanup,
1930 .tlb_flush = intel_8xx_tlbflush,
1931 .mask_memory = agp_generic_mask_memory,
1932 .masks = intel_generic_masks,
1933 .agp_enable = agp_generic_enable,
1934 .cache_flush = global_cache_flush,
1935 .create_gatt_table = agp_generic_create_gatt_table,
1936 .free_gatt_table = agp_generic_free_gatt_table,
1937 .insert_memory = agp_generic_insert_memory,
1938 .remove_memory = agp_generic_remove_memory,
1939 .alloc_by_type = agp_generic_alloc_by_type,
1940 .free_by_type = agp_generic_free_by_type,
1941 .agp_alloc_page = agp_generic_alloc_page,
1942 .agp_alloc_pages = agp_generic_alloc_pages,
1943 .agp_destroy_page = agp_generic_destroy_page,
1944 .agp_destroy_pages = agp_generic_destroy_pages,
1945 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1946 };
1947
1948 static const struct agp_bridge_driver intel_830_driver = {
1949 .owner = THIS_MODULE,
1950 .aperture_sizes = intel_i830_sizes,
1951 .size_type = FIXED_APER_SIZE,
1952 .num_aperture_sizes = 4,
1953 .needs_scratch_page = true,
1954 .configure = intel_i830_configure,
1955 .fetch_size = intel_i830_fetch_size,
1956 .cleanup = intel_i830_cleanup,
1957 .tlb_flush = intel_i810_tlbflush,
1958 .mask_memory = intel_i810_mask_memory,
1959 .masks = intel_i810_masks,
1960 .agp_enable = intel_i810_agp_enable,
1961 .cache_flush = global_cache_flush,
1962 .create_gatt_table = intel_i830_create_gatt_table,
1963 .free_gatt_table = intel_i830_free_gatt_table,
1964 .insert_memory = intel_i830_insert_entries,
1965 .remove_memory = intel_i830_remove_entries,
1966 .alloc_by_type = intel_i830_alloc_by_type,
1967 .free_by_type = intel_i810_free_by_type,
1968 .agp_alloc_page = agp_generic_alloc_page,
1969 .agp_alloc_pages = agp_generic_alloc_pages,
1970 .agp_destroy_page = agp_generic_destroy_page,
1971 .agp_destroy_pages = agp_generic_destroy_pages,
1972 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1973 .chipset_flush = intel_i830_chipset_flush,
1974 };
1975
1976 static const struct agp_bridge_driver intel_820_driver = {
1977 .owner = THIS_MODULE,
1978 .aperture_sizes = intel_8xx_sizes,
1979 .size_type = U8_APER_SIZE,
1980 .num_aperture_sizes = 7,
1981 .configure = intel_820_configure,
1982 .fetch_size = intel_8xx_fetch_size,
1983 .cleanup = intel_820_cleanup,
1984 .tlb_flush = intel_820_tlbflush,
1985 .mask_memory = agp_generic_mask_memory,
1986 .masks = intel_generic_masks,
1987 .agp_enable = agp_generic_enable,
1988 .cache_flush = global_cache_flush,
1989 .create_gatt_table = agp_generic_create_gatt_table,
1990 .free_gatt_table = agp_generic_free_gatt_table,
1991 .insert_memory = agp_generic_insert_memory,
1992 .remove_memory = agp_generic_remove_memory,
1993 .alloc_by_type = agp_generic_alloc_by_type,
1994 .free_by_type = agp_generic_free_by_type,
1995 .agp_alloc_page = agp_generic_alloc_page,
1996 .agp_alloc_pages = agp_generic_alloc_pages,
1997 .agp_destroy_page = agp_generic_destroy_page,
1998 .agp_destroy_pages = agp_generic_destroy_pages,
1999 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2000 };
2001
2002 static const struct agp_bridge_driver intel_830mp_driver = {
2003 .owner = THIS_MODULE,
2004 .aperture_sizes = intel_830mp_sizes,
2005 .size_type = U8_APER_SIZE,
2006 .num_aperture_sizes = 4,
2007 .configure = intel_830mp_configure,
2008 .fetch_size = intel_8xx_fetch_size,
2009 .cleanup = intel_8xx_cleanup,
2010 .tlb_flush = intel_8xx_tlbflush,
2011 .mask_memory = agp_generic_mask_memory,
2012 .masks = intel_generic_masks,
2013 .agp_enable = agp_generic_enable,
2014 .cache_flush = global_cache_flush,
2015 .create_gatt_table = agp_generic_create_gatt_table,
2016 .free_gatt_table = agp_generic_free_gatt_table,
2017 .insert_memory = agp_generic_insert_memory,
2018 .remove_memory = agp_generic_remove_memory,
2019 .alloc_by_type = agp_generic_alloc_by_type,
2020 .free_by_type = agp_generic_free_by_type,
2021 .agp_alloc_page = agp_generic_alloc_page,
2022 .agp_alloc_pages = agp_generic_alloc_pages,
2023 .agp_destroy_page = agp_generic_destroy_page,
2024 .agp_destroy_pages = agp_generic_destroy_pages,
2025 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2026 };
2027
2028 static const struct agp_bridge_driver intel_840_driver = {
2029 .owner = THIS_MODULE,
2030 .aperture_sizes = intel_8xx_sizes,
2031 .size_type = U8_APER_SIZE,
2032 .num_aperture_sizes = 7,
2033 .configure = intel_840_configure,
2034 .fetch_size = intel_8xx_fetch_size,
2035 .cleanup = intel_8xx_cleanup,
2036 .tlb_flush = intel_8xx_tlbflush,
2037 .mask_memory = agp_generic_mask_memory,
2038 .masks = intel_generic_masks,
2039 .agp_enable = agp_generic_enable,
2040 .cache_flush = global_cache_flush,
2041 .create_gatt_table = agp_generic_create_gatt_table,
2042 .free_gatt_table = agp_generic_free_gatt_table,
2043 .insert_memory = agp_generic_insert_memory,
2044 .remove_memory = agp_generic_remove_memory,
2045 .alloc_by_type = agp_generic_alloc_by_type,
2046 .free_by_type = agp_generic_free_by_type,
2047 .agp_alloc_page = agp_generic_alloc_page,
2048 .agp_alloc_pages = agp_generic_alloc_pages,
2049 .agp_destroy_page = agp_generic_destroy_page,
2050 .agp_destroy_pages = agp_generic_destroy_pages,
2051 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2052 };
2053
2054 static const struct agp_bridge_driver intel_845_driver = {
2055 .owner = THIS_MODULE,
2056 .aperture_sizes = intel_8xx_sizes,
2057 .size_type = U8_APER_SIZE,
2058 .num_aperture_sizes = 7,
2059 .configure = intel_845_configure,
2060 .fetch_size = intel_8xx_fetch_size,
2061 .cleanup = intel_8xx_cleanup,
2062 .tlb_flush = intel_8xx_tlbflush,
2063 .mask_memory = agp_generic_mask_memory,
2064 .masks = intel_generic_masks,
2065 .agp_enable = agp_generic_enable,
2066 .cache_flush = global_cache_flush,
2067 .create_gatt_table = agp_generic_create_gatt_table,
2068 .free_gatt_table = agp_generic_free_gatt_table,
2069 .insert_memory = agp_generic_insert_memory,
2070 .remove_memory = agp_generic_remove_memory,
2071 .alloc_by_type = agp_generic_alloc_by_type,
2072 .free_by_type = agp_generic_free_by_type,
2073 .agp_alloc_page = agp_generic_alloc_page,
2074 .agp_alloc_pages = agp_generic_alloc_pages,
2075 .agp_destroy_page = agp_generic_destroy_page,
2076 .agp_destroy_pages = agp_generic_destroy_pages,
2077 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2078 .chipset_flush = intel_i830_chipset_flush,
2079 };
2080
2081 static const struct agp_bridge_driver intel_850_driver = {
2082 .owner = THIS_MODULE,
2083 .aperture_sizes = intel_8xx_sizes,
2084 .size_type = U8_APER_SIZE,
2085 .num_aperture_sizes = 7,
2086 .configure = intel_850_configure,
2087 .fetch_size = intel_8xx_fetch_size,
2088 .cleanup = intel_8xx_cleanup,
2089 .tlb_flush = intel_8xx_tlbflush,
2090 .mask_memory = agp_generic_mask_memory,
2091 .masks = intel_generic_masks,
2092 .agp_enable = agp_generic_enable,
2093 .cache_flush = global_cache_flush,
2094 .create_gatt_table = agp_generic_create_gatt_table,
2095 .free_gatt_table = agp_generic_free_gatt_table,
2096 .insert_memory = agp_generic_insert_memory,
2097 .remove_memory = agp_generic_remove_memory,
2098 .alloc_by_type = agp_generic_alloc_by_type,
2099 .free_by_type = agp_generic_free_by_type,
2100 .agp_alloc_page = agp_generic_alloc_page,
2101 .agp_alloc_pages = agp_generic_alloc_pages,
2102 .agp_destroy_page = agp_generic_destroy_page,
2103 .agp_destroy_pages = agp_generic_destroy_pages,
2104 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2105 };
2106
2107 static const struct agp_bridge_driver intel_860_driver = {
2108 .owner = THIS_MODULE,
2109 .aperture_sizes = intel_8xx_sizes,
2110 .size_type = U8_APER_SIZE,
2111 .num_aperture_sizes = 7,
2112 .configure = intel_860_configure,
2113 .fetch_size = intel_8xx_fetch_size,
2114 .cleanup = intel_8xx_cleanup,
2115 .tlb_flush = intel_8xx_tlbflush,
2116 .mask_memory = agp_generic_mask_memory,
2117 .masks = intel_generic_masks,
2118 .agp_enable = agp_generic_enable,
2119 .cache_flush = global_cache_flush,
2120 .create_gatt_table = agp_generic_create_gatt_table,
2121 .free_gatt_table = agp_generic_free_gatt_table,
2122 .insert_memory = agp_generic_insert_memory,
2123 .remove_memory = agp_generic_remove_memory,
2124 .alloc_by_type = agp_generic_alloc_by_type,
2125 .free_by_type = agp_generic_free_by_type,
2126 .agp_alloc_page = agp_generic_alloc_page,
2127 .agp_alloc_pages = agp_generic_alloc_pages,
2128 .agp_destroy_page = agp_generic_destroy_page,
2129 .agp_destroy_pages = agp_generic_destroy_pages,
2130 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2131 };
2132
2133 static const struct agp_bridge_driver intel_915_driver = {
2134 .owner = THIS_MODULE,
2135 .aperture_sizes = intel_i830_sizes,
2136 .size_type = FIXED_APER_SIZE,
2137 .num_aperture_sizes = 4,
2138 .needs_scratch_page = true,
2139 .configure = intel_i915_configure,
2140 .fetch_size = intel_i9xx_fetch_size,
2141 .cleanup = intel_i915_cleanup,
2142 .tlb_flush = intel_i810_tlbflush,
2143 .mask_memory = intel_i810_mask_memory,
2144 .masks = intel_i810_masks,
2145 .agp_enable = intel_i810_agp_enable,
2146 .cache_flush = global_cache_flush,
2147 .create_gatt_table = intel_i915_create_gatt_table,
2148 .free_gatt_table = intel_i830_free_gatt_table,
2149 .insert_memory = intel_i915_insert_entries,
2150 .remove_memory = intel_i915_remove_entries,
2151 .alloc_by_type = intel_i830_alloc_by_type,
2152 .free_by_type = intel_i810_free_by_type,
2153 .agp_alloc_page = agp_generic_alloc_page,
2154 .agp_alloc_pages = agp_generic_alloc_pages,
2155 .agp_destroy_page = agp_generic_destroy_page,
2156 .agp_destroy_pages = agp_generic_destroy_pages,
2157 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2158 .chipset_flush = intel_i915_chipset_flush,
2159 #ifdef USE_PCI_DMA_API
2160 .agp_map_page = intel_agp_map_page,
2161 .agp_unmap_page = intel_agp_unmap_page,
2162 .agp_map_memory = intel_agp_map_memory,
2163 .agp_unmap_memory = intel_agp_unmap_memory,
2164 #endif
2165 };
2166
2167 static const struct agp_bridge_driver intel_i965_driver = {
2168 .owner = THIS_MODULE,
2169 .aperture_sizes = intel_i830_sizes,
2170 .size_type = FIXED_APER_SIZE,
2171 .num_aperture_sizes = 4,
2172 .needs_scratch_page = true,
2173 .configure = intel_i915_configure,
2174 .fetch_size = intel_i9xx_fetch_size,
2175 .cleanup = intel_i915_cleanup,
2176 .tlb_flush = intel_i810_tlbflush,
2177 .mask_memory = intel_i965_mask_memory,
2178 .masks = intel_i810_masks,
2179 .agp_enable = intel_i810_agp_enable,
2180 .cache_flush = global_cache_flush,
2181 .create_gatt_table = intel_i965_create_gatt_table,
2182 .free_gatt_table = intel_i830_free_gatt_table,
2183 .insert_memory = intel_i915_insert_entries,
2184 .remove_memory = intel_i915_remove_entries,
2185 .alloc_by_type = intel_i830_alloc_by_type,
2186 .free_by_type = intel_i810_free_by_type,
2187 .agp_alloc_page = agp_generic_alloc_page,
2188 .agp_alloc_pages = agp_generic_alloc_pages,
2189 .agp_destroy_page = agp_generic_destroy_page,
2190 .agp_destroy_pages = agp_generic_destroy_pages,
2191 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2192 .chipset_flush = intel_i915_chipset_flush,
2193 #ifdef USE_PCI_DMA_API
2194 .agp_map_page = intel_agp_map_page,
2195 .agp_unmap_page = intel_agp_unmap_page,
2196 .agp_map_memory = intel_agp_map_memory,
2197 .agp_unmap_memory = intel_agp_unmap_memory,
2198 #endif
2199 };
2200
2201 static const struct agp_bridge_driver intel_7505_driver = {
2202 .owner = THIS_MODULE,
2203 .aperture_sizes = intel_8xx_sizes,
2204 .size_type = U8_APER_SIZE,
2205 .num_aperture_sizes = 7,
2206 .configure = intel_7505_configure,
2207 .fetch_size = intel_8xx_fetch_size,
2208 .cleanup = intel_8xx_cleanup,
2209 .tlb_flush = intel_8xx_tlbflush,
2210 .mask_memory = agp_generic_mask_memory,
2211 .masks = intel_generic_masks,
2212 .agp_enable = agp_generic_enable,
2213 .cache_flush = global_cache_flush,
2214 .create_gatt_table = agp_generic_create_gatt_table,
2215 .free_gatt_table = agp_generic_free_gatt_table,
2216 .insert_memory = agp_generic_insert_memory,
2217 .remove_memory = agp_generic_remove_memory,
2218 .alloc_by_type = agp_generic_alloc_by_type,
2219 .free_by_type = agp_generic_free_by_type,
2220 .agp_alloc_page = agp_generic_alloc_page,
2221 .agp_alloc_pages = agp_generic_alloc_pages,
2222 .agp_destroy_page = agp_generic_destroy_page,
2223 .agp_destroy_pages = agp_generic_destroy_pages,
2224 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2225 };
2226
2227 static const struct agp_bridge_driver intel_g33_driver = {
2228 .owner = THIS_MODULE,
2229 .aperture_sizes = intel_i830_sizes,
2230 .size_type = FIXED_APER_SIZE,
2231 .num_aperture_sizes = 4,
2232 .needs_scratch_page = true,
2233 .configure = intel_i915_configure,
2234 .fetch_size = intel_i9xx_fetch_size,
2235 .cleanup = intel_i915_cleanup,
2236 .tlb_flush = intel_i810_tlbflush,
2237 .mask_memory = intel_i965_mask_memory,
2238 .masks = intel_i810_masks,
2239 .agp_enable = intel_i810_agp_enable,
2240 .cache_flush = global_cache_flush,
2241 .create_gatt_table = intel_i915_create_gatt_table,
2242 .free_gatt_table = intel_i830_free_gatt_table,
2243 .insert_memory = intel_i915_insert_entries,
2244 .remove_memory = intel_i915_remove_entries,
2245 .alloc_by_type = intel_i830_alloc_by_type,
2246 .free_by_type = intel_i810_free_by_type,
2247 .agp_alloc_page = agp_generic_alloc_page,
2248 .agp_alloc_pages = agp_generic_alloc_pages,
2249 .agp_destroy_page = agp_generic_destroy_page,
2250 .agp_destroy_pages = agp_generic_destroy_pages,
2251 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2252 .chipset_flush = intel_i915_chipset_flush,
2253 #ifdef USE_PCI_DMA_API
2254 .agp_map_page = intel_agp_map_page,
2255 .agp_unmap_page = intel_agp_unmap_page,
2256 .agp_map_memory = intel_agp_map_memory,
2257 .agp_unmap_memory = intel_agp_unmap_memory,
2258 #endif
2259 };
2260
2261 static int find_gmch(u16 device)
2262 {
2263 struct pci_dev *gmch_device;
2264
2265 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2266 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2267 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2268 device, gmch_device);
2269 }
2270
2271 if (!gmch_device)
2272 return 0;
2273
2274 intel_private.pcidev = gmch_device;
2275 return 1;
2276 }
2277
2278 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2279 * driver and gmch_driver must be non-null, and find_gmch will determine
2280 * which one should be used if a gmch_chip_id is present.
2281 */
2282 static const struct intel_driver_description {
2283 unsigned int chip_id;
2284 unsigned int gmch_chip_id;
2285 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2286 char *name;
2287 const struct agp_bridge_driver *driver;
2288 const struct agp_bridge_driver *gmch_driver;
2289 } intel_agp_chipsets[] = {
2290 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2291 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2292 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2293 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2294 NULL, &intel_810_driver },
2295 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2296 NULL, &intel_810_driver },
2297 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2298 NULL, &intel_810_driver },
2299 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2300 &intel_815_driver, &intel_810_driver },
2301 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2302 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2303 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2304 &intel_830mp_driver, &intel_830_driver },
2305 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2306 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2307 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2308 &intel_845_driver, &intel_830_driver },
2309 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2310 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2311 &intel_845_driver, &intel_830_driver },
2312 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2313 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2314 &intel_845_driver, &intel_830_driver },
2315 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2316 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2317 &intel_845_driver, &intel_830_driver },
2318 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2319 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2320 NULL, &intel_915_driver },
2321 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2322 NULL, &intel_915_driver },
2323 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2324 NULL, &intel_915_driver },
2325 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2326 NULL, &intel_915_driver },
2327 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2328 NULL, &intel_915_driver },
2329 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2330 NULL, &intel_915_driver },
2331 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2332 NULL, &intel_i965_driver },
2333 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2334 NULL, &intel_i965_driver },
2335 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2336 NULL, &intel_i965_driver },
2337 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2338 NULL, &intel_i965_driver },
2339 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2340 NULL, &intel_i965_driver },
2341 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2342 NULL, &intel_i965_driver },
2343 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2344 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2345 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2346 NULL, &intel_g33_driver },
2347 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2348 NULL, &intel_g33_driver },
2349 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2350 NULL, &intel_g33_driver },
2351 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "Pineview",
2352 NULL, &intel_g33_driver },
2353 { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "Pineview",
2354 NULL, &intel_g33_driver },
2355 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2356 "GM45", NULL, &intel_i965_driver },
2357 { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0,
2358 "Eaglelake", NULL, &intel_i965_driver },
2359 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2360 "Q45/Q43", NULL, &intel_i965_driver },
2361 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2362 "G45/G43", NULL, &intel_i965_driver },
2363 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2364 "B43", NULL, &intel_i965_driver },
2365 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2366 "G41", NULL, &intel_i965_driver },
2367 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0,
2368 "Ironlake/D", NULL, &intel_i965_driver },
2369 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2370 "Ironlake/M", NULL, &intel_i965_driver },
2371 { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
2372 "Ironlake/MA", NULL, &intel_i965_driver },
2373 { 0, 0, 0, NULL, NULL, NULL }
2374 };
2375
2376 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2377 const struct pci_device_id *ent)
2378 {
2379 struct agp_bridge_data *bridge;
2380 u8 cap_ptr = 0;
2381 struct resource *r;
2382 int i;
2383
2384 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2385
2386 bridge = agp_alloc_bridge();
2387 if (!bridge)
2388 return -ENOMEM;
2389
2390 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2391 /* In case that multiple models of gfx chip may
2392 stand on same host bridge type, this can be
2393 sure we detect the right IGD. */
2394 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2395 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2396 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2397 bridge->driver =
2398 intel_agp_chipsets[i].gmch_driver;
2399 break;
2400 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2401 continue;
2402 } else {
2403 bridge->driver = intel_agp_chipsets[i].driver;
2404 break;
2405 }
2406 }
2407 }
2408
2409 if (intel_agp_chipsets[i].name == NULL) {
2410 if (cap_ptr)
2411 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2412 pdev->vendor, pdev->device);
2413 agp_put_bridge(bridge);
2414 return -ENODEV;
2415 }
2416
2417 if (bridge->driver == NULL) {
2418 /* bridge has no AGP and no IGD detected */
2419 if (cap_ptr)
2420 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2421 intel_agp_chipsets[i].gmch_chip_id);
2422 agp_put_bridge(bridge);
2423 return -ENODEV;
2424 }
2425
2426 bridge->dev = pdev;
2427 bridge->capndx = cap_ptr;
2428 bridge->dev_private_data = &intel_private;
2429
2430 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2431
2432 /*
2433 * The following fixes the case where the BIOS has "forgotten" to
2434 * provide an address range for the GART.
2435 * 20030610 - hamish@zot.org
2436 */
2437 r = &pdev->resource[0];
2438 if (!r->start && r->end) {
2439 if (pci_assign_resource(pdev, 0)) {
2440 dev_err(&pdev->dev, "can't assign resource 0\n");
2441 agp_put_bridge(bridge);
2442 return -ENODEV;
2443 }
2444 }
2445
2446 /*
2447 * If the device has not been properly setup, the following will catch
2448 * the problem and should stop the system from crashing.
2449 * 20030610 - hamish@zot.org
2450 */
2451 if (pci_enable_device(pdev)) {
2452 dev_err(&pdev->dev, "can't enable PCI device\n");
2453 agp_put_bridge(bridge);
2454 return -ENODEV;
2455 }
2456
2457 /* Fill in the mode register */
2458 if (cap_ptr) {
2459 pci_read_config_dword(pdev,
2460 bridge->capndx+PCI_AGP_STATUS,
2461 &bridge->mode);
2462 }
2463
2464 pci_set_drvdata(pdev, bridge);
2465 return agp_add_bridge(bridge);
2466 }
2467
2468 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2469 {
2470 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2471
2472 agp_remove_bridge(bridge);
2473
2474 if (intel_private.pcidev)
2475 pci_dev_put(intel_private.pcidev);
2476
2477 agp_put_bridge(bridge);
2478 }
2479
2480 #ifdef CONFIG_PM
2481 static int agp_intel_resume(struct pci_dev *pdev)
2482 {
2483 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2484 int ret_val;
2485
2486 if (bridge->driver == &intel_generic_driver)
2487 intel_configure();
2488 else if (bridge->driver == &intel_850_driver)
2489 intel_850_configure();
2490 else if (bridge->driver == &intel_845_driver)
2491 intel_845_configure();
2492 else if (bridge->driver == &intel_830mp_driver)
2493 intel_830mp_configure();
2494 else if (bridge->driver == &intel_915_driver)
2495 intel_i915_configure();
2496 else if (bridge->driver == &intel_830_driver)
2497 intel_i830_configure();
2498 else if (bridge->driver == &intel_810_driver)
2499 intel_i810_configure();
2500 else if (bridge->driver == &intel_i965_driver)
2501 intel_i915_configure();
2502
2503 ret_val = agp_rebind_memory();
2504 if (ret_val != 0)
2505 return ret_val;
2506
2507 return 0;
2508 }
2509 #endif
2510
2511 static struct pci_device_id agp_intel_pci_table[] = {
2512 #define ID(x) \
2513 { \
2514 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2515 .class_mask = ~0, \
2516 .vendor = PCI_VENDOR_ID_INTEL, \
2517 .device = x, \
2518 .subvendor = PCI_ANY_ID, \
2519 .subdevice = PCI_ANY_ID, \
2520 }
2521 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2522 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2523 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2524 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2525 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2526 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2527 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2528 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2529 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2530 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2531 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2532 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2533 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2534 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2535 ID(PCI_DEVICE_ID_INTEL_82854_HB),
2536 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2537 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2538 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2539 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2540 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2541 ID(PCI_DEVICE_ID_INTEL_7505_0),
2542 ID(PCI_DEVICE_ID_INTEL_7205_0),
2543 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2544 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2545 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2546 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2547 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2548 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2549 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
2550 ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
2551 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2552 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2553 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2554 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2555 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2556 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2557 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2558 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2559 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2560 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2561 ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
2562 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2563 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2564 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2565 ID(PCI_DEVICE_ID_INTEL_B43_HB),
2566 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
2567 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
2568 ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
2569 { }
2570 };
2571
2572 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2573
2574 static struct pci_driver agp_intel_pci_driver = {
2575 .name = "agpgart-intel",
2576 .id_table = agp_intel_pci_table,
2577 .probe = agp_intel_probe,
2578 .remove = __devexit_p(agp_intel_remove),
2579 #ifdef CONFIG_PM
2580 .resume = agp_intel_resume,
2581 #endif
2582 };
2583
2584 static int __init agp_intel_init(void)
2585 {
2586 if (agp_off)
2587 return -EINVAL;
2588 return pci_register_driver(&agp_intel_pci_driver);
2589 }
2590
2591 static void __exit agp_intel_cleanup(void)
2592 {
2593 pci_unregister_driver(&agp_intel_pci_driver);
2594 }
2595
2596 module_init(agp_intel_init);
2597 module_exit(agp_intel_cleanup);
2598
2599 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2600 MODULE_LICENSE("GPL and additional rights");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree