1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/delay.h>
4 #include <linux/errno.h>
5 #include <linux/hpet.h>
6 #include <linux/init.h>
7 #include <linux/sysdev.h>
10 #include <asm/fixmap.h>
12 #include <asm/i8253.h>
15 #define HPET_MASK CLOCKSOURCE_MASK(32)
20 #define FSEC_PER_NSEC 1000000L
23 * HPET address is set in acpi/boot.c, when an ACPI entry exists
25 unsigned long hpet_address
;
26 static void __iomem
*hpet_virt_address
;
28 unsigned long hpet_readl(unsigned long a
)
30 return readl(hpet_virt_address
+ a
);
33 static inline void hpet_writel(unsigned long d
, unsigned long a
)
35 writel(d
, hpet_virt_address
+ a
);
39 #include <asm/pgtable.h>
42 static inline void hpet_set_mapping(void)
44 hpet_virt_address
= ioremap_nocache(hpet_address
, HPET_MMAP_SIZE
);
46 __set_fixmap(VSYSCALL_HPET
, hpet_address
, PAGE_KERNEL_VSYSCALL_NOCACHE
);
50 static inline void hpet_clear_mapping(void)
52 iounmap(hpet_virt_address
);
53 hpet_virt_address
= NULL
;
57 * HPET command line enable / disable
59 static int boot_hpet_disable
;
62 static int __init
hpet_setup(char* str
)
65 if (!strncmp("disable", str
, 7))
66 boot_hpet_disable
= 1;
67 if (!strncmp("force", str
, 5))
72 __setup("hpet=", hpet_setup
);
74 static int __init
disable_hpet(char *str
)
76 boot_hpet_disable
= 1;
79 __setup("nohpet", disable_hpet
);
81 static inline int is_hpet_capable(void)
83 return (!boot_hpet_disable
&& hpet_address
);
87 * HPET timer interrupt enable / disable
89 static int hpet_legacy_int_enabled
;
92 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
94 int is_hpet_enabled(void)
96 return is_hpet_capable() && hpet_legacy_int_enabled
;
98 EXPORT_SYMBOL_GPL(is_hpet_enabled
);
101 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
102 * timer 0 and timer 1 in case of RTC emulation.
105 static void hpet_reserve_platform_timers(unsigned long id
)
107 struct hpet __iomem
*hpet
= hpet_virt_address
;
108 struct hpet_timer __iomem
*timer
= &hpet
->hpet_timers
[2];
109 unsigned int nrtimers
, i
;
112 nrtimers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
114 memset(&hd
, 0, sizeof (hd
));
115 hd
.hd_phys_address
= hpet_address
;
116 hd
.hd_address
= hpet
;
117 hd
.hd_nirqs
= nrtimers
;
118 hd
.hd_flags
= HPET_DATA_PLATFORM
;
119 hpet_reserve_timer(&hd
, 0);
121 #ifdef CONFIG_HPET_EMULATE_RTC
122 hpet_reserve_timer(&hd
, 1);
125 hd
.hd_irq
[0] = HPET_LEGACY_8254
;
126 hd
.hd_irq
[1] = HPET_LEGACY_RTC
;
128 for (i
= 2; i
< nrtimers
; timer
++, i
++) {
129 hd
.hd_irq
[i
] = (readl(&timer
->hpet_config
) & Tn_INT_ROUTE_CNF_MASK
) >>
130 Tn_INT_ROUTE_CNF_SHIFT
;
137 static void hpet_reserve_platform_timers(unsigned long id
) { }
143 static unsigned long hpet_period
;
145 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
146 struct clock_event_device
*evt
);
147 static int hpet_legacy_next_event(unsigned long delta
,
148 struct clock_event_device
*evt
);
151 * The hpet clock event device
153 static struct clock_event_device hpet_clockevent
= {
155 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
156 .set_mode
= hpet_legacy_set_mode
,
157 .set_next_event
= hpet_legacy_next_event
,
163 static void hpet_start_counter(void)
165 unsigned long cfg
= hpet_readl(HPET_CFG
);
167 cfg
&= ~HPET_CFG_ENABLE
;
168 hpet_writel(cfg
, HPET_CFG
);
169 hpet_writel(0, HPET_COUNTER
);
170 hpet_writel(0, HPET_COUNTER
+ 4);
171 cfg
|= HPET_CFG_ENABLE
;
172 hpet_writel(cfg
, HPET_CFG
);
175 static void hpet_resume_device(void)
180 static void hpet_restart_counter(void)
182 hpet_resume_device();
183 hpet_start_counter();
186 static void hpet_enable_legacy_int(void)
188 unsigned long cfg
= hpet_readl(HPET_CFG
);
190 cfg
|= HPET_CFG_LEGACY
;
191 hpet_writel(cfg
, HPET_CFG
);
192 hpet_legacy_int_enabled
= 1;
195 static void hpet_legacy_clockevent_register(void)
197 /* Start HPET legacy interrupts */
198 hpet_enable_legacy_int();
201 * The mult factor is defined as (include/linux/clockchips.h)
202 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
203 * hpet_period is in units of femtoseconds (per cycle), so
204 * mult/2^shift = cyc/ns = 10^6/hpet_period
205 * mult = (10^6 * 2^shift)/hpet_period
206 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
208 hpet_clockevent
.mult
= div_sc((unsigned long) FSEC_PER_NSEC
,
209 hpet_period
, hpet_clockevent
.shift
);
210 /* Calculate the min / max delta */
211 hpet_clockevent
.max_delta_ns
= clockevent_delta2ns(0x7FFFFFFF,
213 hpet_clockevent
.min_delta_ns
= clockevent_delta2ns(0x30,
217 * Start hpet with the boot cpu mask and make it
218 * global after the IO_APIC has been initialized.
220 hpet_clockevent
.cpumask
= cpumask_of_cpu(smp_processor_id());
221 clockevents_register_device(&hpet_clockevent
);
222 global_clock_event
= &hpet_clockevent
;
223 printk(KERN_DEBUG
"hpet clockevent registered\n");
226 static void hpet_legacy_set_mode(enum clock_event_mode mode
,
227 struct clock_event_device
*evt
)
229 unsigned long cfg
, cmp
, now
;
233 case CLOCK_EVT_MODE_PERIODIC
:
234 delta
= ((uint64_t)(NSEC_PER_SEC
/HZ
)) * hpet_clockevent
.mult
;
235 delta
>>= hpet_clockevent
.shift
;
236 now
= hpet_readl(HPET_COUNTER
);
237 cmp
= now
+ (unsigned long) delta
;
238 cfg
= hpet_readl(HPET_T0_CFG
);
239 cfg
|= HPET_TN_ENABLE
| HPET_TN_PERIODIC
|
240 HPET_TN_SETVAL
| HPET_TN_32BIT
;
241 hpet_writel(cfg
, HPET_T0_CFG
);
243 * The first write after writing TN_SETVAL to the
244 * config register sets the counter value, the second
245 * write sets the period.
247 hpet_writel(cmp
, HPET_T0_CMP
);
249 hpet_writel((unsigned long) delta
, HPET_T0_CMP
);
252 case CLOCK_EVT_MODE_ONESHOT
:
253 cfg
= hpet_readl(HPET_T0_CFG
);
254 cfg
&= ~HPET_TN_PERIODIC
;
255 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
256 hpet_writel(cfg
, HPET_T0_CFG
);
259 case CLOCK_EVT_MODE_UNUSED
:
260 case CLOCK_EVT_MODE_SHUTDOWN
:
261 cfg
= hpet_readl(HPET_T0_CFG
);
262 cfg
&= ~HPET_TN_ENABLE
;
263 hpet_writel(cfg
, HPET_T0_CFG
);
266 case CLOCK_EVT_MODE_RESUME
:
267 hpet_enable_legacy_int();
272 static int hpet_legacy_next_event(unsigned long delta
,
273 struct clock_event_device
*evt
)
277 cnt
= hpet_readl(HPET_COUNTER
);
279 hpet_writel(cnt
, HPET_T0_CMP
);
281 return ((long)(hpet_readl(HPET_COUNTER
) - cnt
) > 0) ? -ETIME
: 0;
285 * Clock source related code
287 static cycle_t
read_hpet(void)
289 return (cycle_t
)hpet_readl(HPET_COUNTER
);
293 static cycle_t __vsyscall_fn
vread_hpet(void)
295 return readl((const void __iomem
*)fix_to_virt(VSYSCALL_HPET
) + 0xf0);
299 static struct clocksource clocksource_hpet
= {
305 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
306 .resume
= hpet_restart_counter
,
312 static int hpet_clocksource_register(void)
317 /* Start the counter */
318 hpet_start_counter();
320 /* Verify whether hpet counter works */
325 * We don't know the TSC frequency yet, but waiting for
326 * 200000 TSC cycles is safe:
333 } while ((now
- start
) < 200000UL);
335 if (t1
== read_hpet()) {
337 "HPET counter not counting. HPET disabled\n");
342 * The definition of mult is (include/linux/clocksource.h)
343 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
344 * so we first need to convert hpet_period to ns/cyc units:
345 * mult/2^shift = ns/cyc = hpet_period/10^6
346 * mult = (hpet_period * 2^shift)/10^6
347 * mult = (hpet_period << shift)/FSEC_PER_NSEC
349 clocksource_hpet
.mult
= div_sc(hpet_period
, FSEC_PER_NSEC
, HPET_SHIFT
);
351 clocksource_register(&clocksource_hpet
);
357 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
359 int __init
hpet_enable(void)
364 if (!is_hpet_capable())
370 * Read the period and check for a sane value:
372 hpet_period
= hpet_readl(HPET_PERIOD
);
375 * AMD SB700 based systems with spread spectrum enabled use a
376 * SMM based HPET emulation to provide proper frequency
377 * setting. The SMM code is initialized with the first HPET
378 * register access and takes some time to complete. During
379 * this time the config register reads 0xffffffff. We check
380 * for max. 1000 loops whether the config register reads a non
381 * 0xffffffff value to make sure that HPET is up and running
382 * before we go further. A counting loop is safe, as the HPET
383 * access takes thousands of CPU cycles. On non SB700 based
384 * machines this check is only done once and has no side
387 for (i
= 0; hpet_readl(HPET_CFG
) == 0xFFFFFFFF; i
++) {
390 "HPET config register value = 0xFFFFFFFF. "
396 if (hpet_period
< HPET_MIN_PERIOD
|| hpet_period
> HPET_MAX_PERIOD
)
400 * Read the HPET ID register to retrieve the IRQ routing
401 * information and the number of channels
403 id
= hpet_readl(HPET_ID
);
405 #ifdef CONFIG_HPET_EMULATE_RTC
407 * The legacy routing mode needs at least two channels, tick timer
408 * and the rtc emulation channel.
410 if (!(id
& HPET_ID_NUMBER
))
414 if (hpet_clocksource_register())
417 if (id
& HPET_ID_LEGSUP
) {
418 hpet_legacy_clockevent_register();
424 hpet_clear_mapping();
425 boot_hpet_disable
= 1;
430 * Needs to be late, as the reserve_timer code calls kalloc !
432 * Not a problem on i386 as hpet_enable is called from late_time_init,
433 * but on x86_64 it is necessary !
435 static __init
int hpet_late_init(void)
437 if (boot_hpet_disable
)
441 if (!force_hpet_address
)
444 hpet_address
= force_hpet_address
;
446 if (!hpet_virt_address
)
450 hpet_reserve_platform_timers(hpet_readl(HPET_ID
));
454 fs_initcall(hpet_late_init
);
456 void hpet_disable(void)
458 if (is_hpet_capable()) {
459 unsigned long cfg
= hpet_readl(HPET_CFG
);
461 if (hpet_legacy_int_enabled
) {
462 cfg
&= ~HPET_CFG_LEGACY
;
463 hpet_legacy_int_enabled
= 0;
465 cfg
&= ~HPET_CFG_ENABLE
;
466 hpet_writel(cfg
, HPET_CFG
);
470 #ifdef CONFIG_HPET_EMULATE_RTC
472 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
473 * is enabled, we support RTC interrupt functionality in software.
474 * RTC has 3 kinds of interrupts:
475 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
477 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
478 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
479 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
480 * (1) and (2) above are implemented using polling at a frequency of
481 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
482 * overhead. (DEFAULT_RTC_INT_FREQ)
483 * For (3), we use interrupts at 64Hz or user specified periodic
484 * frequency, whichever is higher.
486 #include <linux/mc146818rtc.h>
487 #include <linux/rtc.h>
490 #define DEFAULT_RTC_INT_FREQ 64
491 #define DEFAULT_RTC_SHIFT 6
492 #define RTC_NUM_INTS 1
494 static unsigned long hpet_rtc_flags
;
495 static int hpet_prev_update_sec
;
496 static struct rtc_time hpet_alarm_time
;
497 static unsigned long hpet_pie_count
;
498 static unsigned long hpet_t1_cmp
;
499 static unsigned long hpet_default_delta
;
500 static unsigned long hpet_pie_delta
;
501 static unsigned long hpet_pie_limit
;
503 static rtc_irq_handler irq_handler
;
506 * Registers a IRQ handler.
508 int hpet_register_irq_handler(rtc_irq_handler handler
)
510 if (!is_hpet_enabled())
515 irq_handler
= handler
;
519 EXPORT_SYMBOL_GPL(hpet_register_irq_handler
);
522 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
525 void hpet_unregister_irq_handler(rtc_irq_handler handler
)
527 if (!is_hpet_enabled())
533 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler
);
536 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
537 * is not supported by all HPET implementations for timer 1.
539 * hpet_rtc_timer_init() is called when the rtc is initialized.
541 int hpet_rtc_timer_init(void)
543 unsigned long cfg
, cnt
, delta
, flags
;
545 if (!is_hpet_enabled())
548 if (!hpet_default_delta
) {
551 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
552 clc
>>= hpet_clockevent
.shift
+ DEFAULT_RTC_SHIFT
;
553 hpet_default_delta
= (unsigned long) clc
;
556 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
557 delta
= hpet_default_delta
;
559 delta
= hpet_pie_delta
;
561 local_irq_save(flags
);
563 cnt
= delta
+ hpet_readl(HPET_COUNTER
);
564 hpet_writel(cnt
, HPET_T1_CMP
);
567 cfg
= hpet_readl(HPET_T1_CFG
);
568 cfg
&= ~HPET_TN_PERIODIC
;
569 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
570 hpet_writel(cfg
, HPET_T1_CFG
);
572 local_irq_restore(flags
);
576 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init
);
579 * The functions below are called from rtc driver.
580 * Return 0 if HPET is not being used.
581 * Otherwise do the necessary changes and return 1.
583 int hpet_mask_rtc_irq_bit(unsigned long bit_mask
)
585 if (!is_hpet_enabled())
588 hpet_rtc_flags
&= ~bit_mask
;
591 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit
);
593 int hpet_set_rtc_irq_bit(unsigned long bit_mask
)
595 unsigned long oldbits
= hpet_rtc_flags
;
597 if (!is_hpet_enabled())
600 hpet_rtc_flags
|= bit_mask
;
602 if ((bit_mask
& RTC_UIE
) && !(oldbits
& RTC_UIE
))
603 hpet_prev_update_sec
= -1;
606 hpet_rtc_timer_init();
610 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit
);
612 int hpet_set_alarm_time(unsigned char hrs
, unsigned char min
,
615 if (!is_hpet_enabled())
618 hpet_alarm_time
.tm_hour
= hrs
;
619 hpet_alarm_time
.tm_min
= min
;
620 hpet_alarm_time
.tm_sec
= sec
;
624 EXPORT_SYMBOL_GPL(hpet_set_alarm_time
);
626 int hpet_set_periodic_freq(unsigned long freq
)
630 if (!is_hpet_enabled())
633 if (freq
<= DEFAULT_RTC_INT_FREQ
)
634 hpet_pie_limit
= DEFAULT_RTC_INT_FREQ
/ freq
;
636 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
638 clc
>>= hpet_clockevent
.shift
;
639 hpet_pie_delta
= (unsigned long) clc
;
643 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq
);
645 int hpet_rtc_dropped_irq(void)
647 return is_hpet_enabled();
649 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq
);
651 static void hpet_rtc_timer_reinit(void)
653 unsigned long cfg
, delta
;
656 if (unlikely(!hpet_rtc_flags
)) {
657 cfg
= hpet_readl(HPET_T1_CFG
);
658 cfg
&= ~HPET_TN_ENABLE
;
659 hpet_writel(cfg
, HPET_T1_CFG
);
663 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
664 delta
= hpet_default_delta
;
666 delta
= hpet_pie_delta
;
669 * Increment the comparator value until we are ahead of the
673 hpet_t1_cmp
+= delta
;
674 hpet_writel(hpet_t1_cmp
, HPET_T1_CMP
);
676 } while ((long)(hpet_readl(HPET_COUNTER
) - hpet_t1_cmp
) > 0);
679 if (hpet_rtc_flags
& RTC_PIE
)
680 hpet_pie_count
+= lost_ints
;
681 if (printk_ratelimit())
682 printk(KERN_WARNING
"hpet1: lost %d rtc interrupts\n",
687 irqreturn_t
hpet_rtc_interrupt(int irq
, void *dev_id
)
689 struct rtc_time curr_time
;
690 unsigned long rtc_int_flag
= 0;
692 hpet_rtc_timer_reinit();
693 memset(&curr_time
, 0, sizeof(struct rtc_time
));
695 if (hpet_rtc_flags
& (RTC_UIE
| RTC_AIE
))
696 get_rtc_time(&curr_time
);
698 if (hpet_rtc_flags
& RTC_UIE
&&
699 curr_time
.tm_sec
!= hpet_prev_update_sec
) {
700 if (hpet_prev_update_sec
>= 0)
701 rtc_int_flag
= RTC_UF
;
702 hpet_prev_update_sec
= curr_time
.tm_sec
;
705 if (hpet_rtc_flags
& RTC_PIE
&&
706 ++hpet_pie_count
>= hpet_pie_limit
) {
707 rtc_int_flag
|= RTC_PF
;
711 if (hpet_rtc_flags
& RTC_AIE
&&
712 (curr_time
.tm_sec
== hpet_alarm_time
.tm_sec
) &&
713 (curr_time
.tm_min
== hpet_alarm_time
.tm_min
) &&
714 (curr_time
.tm_hour
== hpet_alarm_time
.tm_hour
))
715 rtc_int_flag
|= RTC_AF
;
718 rtc_int_flag
|= (RTC_IRQF
| (RTC_NUM_INTS
<< 8));
720 irq_handler(rtc_int_flag
, dev_id
);
724 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt
);