?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/kms: disable/enable poll around switcheroo on/off
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
blobcc6e56a18edd9e8bc9ac9f11e41e9209951f0a62
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38 #include <linux/acpi.h>
39 #include <linux/pnp.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/slab.h>
42
43 /* Really want an OS-independent resettable timer. Would like to have
44 * this loop run for (eg) 3 sec, but have the timer reset every time
45 * the head pointer changes, so that EBUSY only happens if the ring
46 * actually stalls for (eg) 3 seconds.
47 */
48 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
49 {
50 drm_i915_private_t *dev_priv = dev->dev_private;
51 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
52 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
53 u32 last_acthd = I915_READ(acthd_reg);
54 u32 acthd;
55 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
56 int i;
57
58 trace_i915_ring_wait_begin (dev);
59
60 for (i = 0; i < 100000; i++) {
61 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
62 acthd = I915_READ(acthd_reg);
63 ring->space = ring->head - (ring->tail + 8);
64 if (ring->space < 0)
65 ring->space += ring->Size;
66 if (ring->space >= n) {
67 trace_i915_ring_wait_end (dev);
68 return 0;
69 }
70
71 if (dev->primary->master) {
72 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
73 if (master_priv->sarea_priv)
74 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
75 }
76
77
78 if (ring->head != last_head)
79 i = 0;
80 if (acthd != last_acthd)
81 i = 0;
82
83 last_head = ring->head;
84 last_acthd = acthd;
85 msleep_interruptible(10);
86
87 }
88
89 trace_i915_ring_wait_end (dev);
90 return -EBUSY;
91 }
92
93 /* As a ringbuffer is only allowed to wrap between instructions, fill
94 * the tail with NOOPs.
95 */
96 int i915_wrap_ring(struct drm_device *dev)
97 {
98 drm_i915_private_t *dev_priv = dev->dev_private;
99 volatile unsigned int *virt;
100 int rem;
101
102 rem = dev_priv->ring.Size - dev_priv->ring.tail;
103 if (dev_priv->ring.space < rem) {
104 int ret = i915_wait_ring(dev, rem, __func__);
105 if (ret)
106 return ret;
107 }
108 dev_priv->ring.space -= rem;
109
110 virt = (unsigned int *)
111 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
112 rem /= 4;
113 while (rem--)
114 *virt++ = MI_NOOP;
115
116 dev_priv->ring.tail = 0;
117
118 return 0;
119 }
120
121 /**
122 * Sets up the hardware status page for devices that need a physical address
123 * in the register.
124 */
125 static int i915_init_phys_hws(struct drm_device *dev)
126 {
127 drm_i915_private_t *dev_priv = dev->dev_private;
128 /* Program Hardware Status Page */
129 dev_priv->status_page_dmah =
130 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
131
132 if (!dev_priv->status_page_dmah) {
133 DRM_ERROR("Can not allocate hardware status page\n");
134 return -ENOMEM;
135 }
136 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
137 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
138
139 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
140
141 if (IS_I965G(dev))
142 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
143 0xf0;
144
145 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
146 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
147 return 0;
148 }
149
150 /**
151 * Frees the hardware status page, whether it's a physical address or a virtual
152 * address set up by the X Server.
153 */
154 static void i915_free_hws(struct drm_device *dev)
155 {
156 drm_i915_private_t *dev_priv = dev->dev_private;
157 if (dev_priv->status_page_dmah) {
158 drm_pci_free(dev, dev_priv->status_page_dmah);
159 dev_priv->status_page_dmah = NULL;
160 }
161
162 if (dev_priv->status_gfx_addr) {
163 dev_priv->status_gfx_addr = 0;
164 drm_core_ioremapfree(&dev_priv->hws_map, dev);
165 }
166
167 /* Need to rewrite hardware status page */
168 I915_WRITE(HWS_PGA, 0x1ffff000);
169 }
170
171 void i915_kernel_lost_context(struct drm_device * dev)
172 {
173 drm_i915_private_t *dev_priv = dev->dev_private;
174 struct drm_i915_master_private *master_priv;
175 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
176
177 /*
178 * We should never lose context on the ring with modesetting
179 * as we don't expose it to userspace
180 */
181 if (drm_core_check_feature(dev, DRIVER_MODESET))
182 return;
183
184 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
185 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
186 ring->space = ring->head - (ring->tail + 8);
187 if (ring->space < 0)
188 ring->space += ring->Size;
189
190 if (!dev->primary->master)
191 return;
192
193 master_priv = dev->primary->master->driver_priv;
194 if (ring->head == ring->tail && master_priv->sarea_priv)
195 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
196 }
197
198 static int i915_dma_cleanup(struct drm_device * dev)
199 {
200 drm_i915_private_t *dev_priv = dev->dev_private;
201 /* Make sure interrupts are disabled here because the uninstall ioctl
202 * may not have been called from userspace and after dev_private
203 * is freed, it's too late.
204 */
205 if (dev->irq_enabled)
206 drm_irq_uninstall(dev);
207
208 if (dev_priv->ring.virtual_start) {
209 drm_core_ioremapfree(&dev_priv->ring.map, dev);
210 dev_priv->ring.virtual_start = NULL;
211 dev_priv->ring.map.handle = NULL;
212 dev_priv->ring.map.size = 0;
213 }
214
215 /* Clear the HWS virtual address at teardown */
216 if (I915_NEED_GFX_HWS(dev))
217 i915_free_hws(dev);
218
219 return 0;
220 }
221
222 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
223 {
224 drm_i915_private_t *dev_priv = dev->dev_private;
225 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
226
227 master_priv->sarea = drm_getsarea(dev);
228 if (master_priv->sarea) {
229 master_priv->sarea_priv = (drm_i915_sarea_t *)
230 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
231 } else {
232 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
233 }
234
235 if (init->ring_size != 0) {
236 if (dev_priv->ring.ring_obj != NULL) {
237 i915_dma_cleanup(dev);
238 DRM_ERROR("Client tried to initialize ringbuffer in "
239 "GEM mode\n");
240 return -EINVAL;
241 }
242
243 dev_priv->ring.Size = init->ring_size;
244
245 dev_priv->ring.map.offset = init->ring_start;
246 dev_priv->ring.map.size = init->ring_size;
247 dev_priv->ring.map.type = 0;
248 dev_priv->ring.map.flags = 0;
249 dev_priv->ring.map.mtrr = 0;
250
251 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
252
253 if (dev_priv->ring.map.handle == NULL) {
254 i915_dma_cleanup(dev);
255 DRM_ERROR("can not ioremap virtual address for"
256 " ring buffer\n");
257 return -ENOMEM;
258 }
259 }
260
261 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
262
263 dev_priv->cpp = init->cpp;
264 dev_priv->back_offset = init->back_offset;
265 dev_priv->front_offset = init->front_offset;
266 dev_priv->current_page = 0;
267 if (master_priv->sarea_priv)
268 master_priv->sarea_priv->pf_current_page = 0;
269
270 /* Allow hardware batchbuffers unless told otherwise.
271 */
272 dev_priv->allow_batchbuffer = 1;
273
274 return 0;
275 }
276
277 static int i915_dma_resume(struct drm_device * dev)
278 {
279 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
280
281 DRM_DEBUG_DRIVER("%s\n", __func__);
282
283 if (dev_priv->ring.map.handle == NULL) {
284 DRM_ERROR("can not ioremap virtual address for"
285 " ring buffer\n");
286 return -ENOMEM;
287 }
288
289 /* Program Hardware Status Page */
290 if (!dev_priv->hw_status_page) {
291 DRM_ERROR("Can not find hardware status page\n");
292 return -EINVAL;
293 }
294 DRM_DEBUG_DRIVER("hw status page @ %p\n",
295 dev_priv->hw_status_page);
296
297 if (dev_priv->status_gfx_addr != 0)
298 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
299 else
300 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
301 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
302
303 return 0;
304 }
305
306 static int i915_dma_init(struct drm_device *dev, void *data,
307 struct drm_file *file_priv)
308 {
309 drm_i915_init_t *init = data;
310 int retcode = 0;
311
312 switch (init->func) {
313 case I915_INIT_DMA:
314 retcode = i915_initialize(dev, init);
315 break;
316 case I915_CLEANUP_DMA:
317 retcode = i915_dma_cleanup(dev);
318 break;
319 case I915_RESUME_DMA:
320 retcode = i915_dma_resume(dev);
321 break;
322 default:
323 retcode = -EINVAL;
324 break;
325 }
326
327 return retcode;
328 }
329
330 /* Implement basically the same security restrictions as hardware does
331 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
332 *
333 * Most of the calculations below involve calculating the size of a
334 * particular instruction. It's important to get the size right as
335 * that tells us where the next instruction to check is. Any illegal
336 * instruction detected will be given a size of zero, which is a
337 * signal to abort the rest of the buffer.
338 */
339 static int do_validate_cmd(int cmd)
340 {
341 switch (((cmd >> 29) & 0x7)) {
342 case 0x0:
343 switch ((cmd >> 23) & 0x3f) {
344 case 0x0:
345 return 1; /* MI_NOOP */
346 case 0x4:
347 return 1; /* MI_FLUSH */
348 default:
349 return 0; /* disallow everything else */
350 }
351 break;
352 case 0x1:
353 return 0; /* reserved */
354 case 0x2:
355 return (cmd & 0xff) + 2; /* 2d commands */
356 case 0x3:
357 if (((cmd >> 24) & 0x1f) <= 0x18)
358 return 1;
359
360 switch ((cmd >> 24) & 0x1f) {
361 case 0x1c:
362 return 1;
363 case 0x1d:
364 switch ((cmd >> 16) & 0xff) {
365 case 0x3:
366 return (cmd & 0x1f) + 2;
367 case 0x4:
368 return (cmd & 0xf) + 2;
369 default:
370 return (cmd & 0xffff) + 2;
371 }
372 case 0x1e:
373 if (cmd & (1 << 23))
374 return (cmd & 0xffff) + 1;
375 else
376 return 1;
377 case 0x1f:
378 if ((cmd & (1 << 23)) == 0) /* inline vertices */
379 return (cmd & 0x1ffff) + 2;
380 else if (cmd & (1 << 17)) /* indirect random */
381 if ((cmd & 0xffff) == 0)
382 return 0; /* unknown length, too hard */
383 else
384 return (((cmd & 0xffff) + 1) / 2) + 1;
385 else
386 return 2; /* indirect sequential */
387 default:
388 return 0;
389 }
390 default:
391 return 0;
392 }
393
394 return 0;
395 }
396
397 static int validate_cmd(int cmd)
398 {
399 int ret = do_validate_cmd(cmd);
400
401 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
402
403 return ret;
404 }
405
406 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
407 {
408 drm_i915_private_t *dev_priv = dev->dev_private;
409 int i;
410 RING_LOCALS;
411
412 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
413 return -EINVAL;
414
415 BEGIN_LP_RING((dwords+1)&~1);
416
417 for (i = 0; i < dwords;) {
418 int cmd, sz;
419
420 cmd = buffer[i];
421
422 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
423 return -EINVAL;
424
425 OUT_RING(cmd);
426
427 while (++i, --sz) {
428 OUT_RING(buffer[i]);
429 }
430 }
431
432 if (dwords & 1)
433 OUT_RING(0);
434
435 ADVANCE_LP_RING();
436
437 return 0;
438 }
439
440 int
441 i915_emit_box(struct drm_device *dev,
442 struct drm_clip_rect *boxes,
443 int i, int DR1, int DR4)
444 {
445 drm_i915_private_t *dev_priv = dev->dev_private;
446 struct drm_clip_rect box = boxes[i];
447 RING_LOCALS;
448
449 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
450 DRM_ERROR("Bad box %d,%d..%d,%d\n",
451 box.x1, box.y1, box.x2, box.y2);
452 return -EINVAL;
453 }
454
455 if (IS_I965G(dev)) {
456 BEGIN_LP_RING(4);
457 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
458 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
459 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
460 OUT_RING(DR4);
461 ADVANCE_LP_RING();
462 } else {
463 BEGIN_LP_RING(6);
464 OUT_RING(GFX_OP_DRAWRECT_INFO);
465 OUT_RING(DR1);
466 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
467 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
468 OUT_RING(DR4);
469 OUT_RING(0);
470 ADVANCE_LP_RING();
471 }
472
473 return 0;
474 }
475
476 /* XXX: Emitting the counter should really be moved to part of the IRQ
477 * emit. For now, do it in both places:
478 */
479
480 static void i915_emit_breadcrumb(struct drm_device *dev)
481 {
482 drm_i915_private_t *dev_priv = dev->dev_private;
483 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
484 RING_LOCALS;
485
486 dev_priv->counter++;
487 if (dev_priv->counter > 0x7FFFFFFFUL)
488 dev_priv->counter = 0;
489 if (master_priv->sarea_priv)
490 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
491
492 BEGIN_LP_RING(4);
493 OUT_RING(MI_STORE_DWORD_INDEX);
494 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
495 OUT_RING(dev_priv->counter);
496 OUT_RING(0);
497 ADVANCE_LP_RING();
498 }
499
500 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
501 drm_i915_cmdbuffer_t *cmd,
502 struct drm_clip_rect *cliprects,
503 void *cmdbuf)
504 {
505 int nbox = cmd->num_cliprects;
506 int i = 0, count, ret;
507
508 if (cmd->sz & 0x3) {
509 DRM_ERROR("alignment");
510 return -EINVAL;
511 }
512
513 i915_kernel_lost_context(dev);
514
515 count = nbox ? nbox : 1;
516
517 for (i = 0; i < count; i++) {
518 if (i < nbox) {
519 ret = i915_emit_box(dev, cliprects, i,
520 cmd->DR1, cmd->DR4);
521 if (ret)
522 return ret;
523 }
524
525 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
526 if (ret)
527 return ret;
528 }
529
530 i915_emit_breadcrumb(dev);
531 return 0;
532 }
533
534 static int i915_dispatch_batchbuffer(struct drm_device * dev,
535 drm_i915_batchbuffer_t * batch,
536 struct drm_clip_rect *cliprects)
537 {
538 drm_i915_private_t *dev_priv = dev->dev_private;
539 int nbox = batch->num_cliprects;
540 int i = 0, count;
541 RING_LOCALS;
542
543 if ((batch->start | batch->used) & 0x7) {
544 DRM_ERROR("alignment");
545 return -EINVAL;
546 }
547
548 i915_kernel_lost_context(dev);
549
550 count = nbox ? nbox : 1;
551
552 for (i = 0; i < count; i++) {
553 if (i < nbox) {
554 int ret = i915_emit_box(dev, cliprects, i,
555 batch->DR1, batch->DR4);
556 if (ret)
557 return ret;
558 }
559
560 if (!IS_I830(dev) && !IS_845G(dev)) {
561 BEGIN_LP_RING(2);
562 if (IS_I965G(dev)) {
563 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
564 OUT_RING(batch->start);
565 } else {
566 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
567 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
568 }
569 ADVANCE_LP_RING();
570 } else {
571 BEGIN_LP_RING(4);
572 OUT_RING(MI_BATCH_BUFFER);
573 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
574 OUT_RING(batch->start + batch->used - 4);
575 OUT_RING(0);
576 ADVANCE_LP_RING();
577 }
578 }
579
580 i915_emit_breadcrumb(dev);
581
582 return 0;
583 }
584
585 static int i915_dispatch_flip(struct drm_device * dev)
586 {
587 drm_i915_private_t *dev_priv = dev->dev_private;
588 struct drm_i915_master_private *master_priv =
589 dev->primary->master->driver_priv;
590 RING_LOCALS;
591
592 if (!master_priv->sarea_priv)
593 return -EINVAL;
594
595 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
596 __func__,
597 dev_priv->current_page,
598 master_priv->sarea_priv->pf_current_page);
599
600 i915_kernel_lost_context(dev);
601
602 BEGIN_LP_RING(2);
603 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
604 OUT_RING(0);
605 ADVANCE_LP_RING();
606
607 BEGIN_LP_RING(6);
608 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
609 OUT_RING(0);
610 if (dev_priv->current_page == 0) {
611 OUT_RING(dev_priv->back_offset);
612 dev_priv->current_page = 1;
613 } else {
614 OUT_RING(dev_priv->front_offset);
615 dev_priv->current_page = 0;
616 }
617 OUT_RING(0);
618 ADVANCE_LP_RING();
619
620 BEGIN_LP_RING(2);
621 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
622 OUT_RING(0);
623 ADVANCE_LP_RING();
624
625 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
626
627 BEGIN_LP_RING(4);
628 OUT_RING(MI_STORE_DWORD_INDEX);
629 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
630 OUT_RING(dev_priv->counter);
631 OUT_RING(0);
632 ADVANCE_LP_RING();
633
634 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
635 return 0;
636 }
637
638 static int i915_quiescent(struct drm_device * dev)
639 {
640 drm_i915_private_t *dev_priv = dev->dev_private;
641
642 i915_kernel_lost_context(dev);
643 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
644 }
645
646 static int i915_flush_ioctl(struct drm_device *dev, void *data,
647 struct drm_file *file_priv)
648 {
649 int ret;
650
651 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
652
653 mutex_lock(&dev->struct_mutex);
654 ret = i915_quiescent(dev);
655 mutex_unlock(&dev->struct_mutex);
656
657 return ret;
658 }
659
660 static int i915_batchbuffer(struct drm_device *dev, void *data,
661 struct drm_file *file_priv)
662 {
663 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
664 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
665 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
666 master_priv->sarea_priv;
667 drm_i915_batchbuffer_t *batch = data;
668 int ret;
669 struct drm_clip_rect *cliprects = NULL;
670
671 if (!dev_priv->allow_batchbuffer) {
672 DRM_ERROR("Batchbuffer ioctl disabled\n");
673 return -EINVAL;
674 }
675
676 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
677 batch->start, batch->used, batch->num_cliprects);
678
679 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
680
681 if (batch->num_cliprects < 0)
682 return -EINVAL;
683
684 if (batch->num_cliprects) {
685 cliprects = kcalloc(batch->num_cliprects,
686 sizeof(struct drm_clip_rect),
687 GFP_KERNEL);
688 if (cliprects == NULL)
689 return -ENOMEM;
690
691 ret = copy_from_user(cliprects, batch->cliprects,
692 batch->num_cliprects *
693 sizeof(struct drm_clip_rect));
694 if (ret != 0)
695 goto fail_free;
696 }
697
698 mutex_lock(&dev->struct_mutex);
699 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
700 mutex_unlock(&dev->struct_mutex);
701
702 if (sarea_priv)
703 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
704
705 fail_free:
706 kfree(cliprects);
707
708 return ret;
709 }
710
711 static int i915_cmdbuffer(struct drm_device *dev, void *data,
712 struct drm_file *file_priv)
713 {
714 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
715 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
716 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
717 master_priv->sarea_priv;
718 drm_i915_cmdbuffer_t *cmdbuf = data;
719 struct drm_clip_rect *cliprects = NULL;
720 void *batch_data;
721 int ret;
722
723 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
724 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
725
726 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
727
728 if (cmdbuf->num_cliprects < 0)
729 return -EINVAL;
730
731 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
732 if (batch_data == NULL)
733 return -ENOMEM;
734
735 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
736 if (ret != 0)
737 goto fail_batch_free;
738
739 if (cmdbuf->num_cliprects) {
740 cliprects = kcalloc(cmdbuf->num_cliprects,
741 sizeof(struct drm_clip_rect), GFP_KERNEL);
742 if (cliprects == NULL) {
743 ret = -ENOMEM;
744 goto fail_batch_free;
745 }
746
747 ret = copy_from_user(cliprects, cmdbuf->cliprects,
748 cmdbuf->num_cliprects *
749 sizeof(struct drm_clip_rect));
750 if (ret != 0)
751 goto fail_clip_free;
752 }
753
754 mutex_lock(&dev->struct_mutex);
755 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
756 mutex_unlock(&dev->struct_mutex);
757 if (ret) {
758 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
759 goto fail_clip_free;
760 }
761
762 if (sarea_priv)
763 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
764
765 fail_clip_free:
766 kfree(cliprects);
767 fail_batch_free:
768 kfree(batch_data);
769
770 return ret;
771 }
772
773 static int i915_flip_bufs(struct drm_device *dev, void *data,
774 struct drm_file *file_priv)
775 {
776 int ret;
777
778 DRM_DEBUG_DRIVER("%s\n", __func__);
779
780 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
781
782 mutex_lock(&dev->struct_mutex);
783 ret = i915_dispatch_flip(dev);
784 mutex_unlock(&dev->struct_mutex);
785
786 return ret;
787 }
788
789 static int i915_getparam(struct drm_device *dev, void *data,
790 struct drm_file *file_priv)
791 {
792 drm_i915_private_t *dev_priv = dev->dev_private;
793 drm_i915_getparam_t *param = data;
794 int value;
795
796 if (!dev_priv) {
797 DRM_ERROR("called with no initialization\n");
798 return -EINVAL;
799 }
800
801 switch (param->param) {
802 case I915_PARAM_IRQ_ACTIVE:
803 value = dev->pdev->irq ? 1 : 0;
804 break;
805 case I915_PARAM_ALLOW_BATCHBUFFER:
806 value = dev_priv->allow_batchbuffer ? 1 : 0;
807 break;
808 case I915_PARAM_LAST_DISPATCH:
809 value = READ_BREADCRUMB(dev_priv);
810 break;
811 case I915_PARAM_CHIPSET_ID:
812 value = dev->pci_device;
813 break;
814 case I915_PARAM_HAS_GEM:
815 value = dev_priv->has_gem;
816 break;
817 case I915_PARAM_NUM_FENCES_AVAIL:
818 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
819 break;
820 case I915_PARAM_HAS_OVERLAY:
821 value = dev_priv->overlay ? 1 : 0;
822 break;
823 case I915_PARAM_HAS_PAGEFLIPPING:
824 value = 1;
825 break;
826 case I915_PARAM_HAS_EXECBUF2:
827 /* depends on GEM */
828 value = dev_priv->has_gem;
829 break;
830 default:
831 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
832 param->param);
833 return -EINVAL;
834 }
835
836 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
837 DRM_ERROR("DRM_COPY_TO_USER failed\n");
838 return -EFAULT;
839 }
840
841 return 0;
842 }
843
844 static int i915_setparam(struct drm_device *dev, void *data,
845 struct drm_file *file_priv)
846 {
847 drm_i915_private_t *dev_priv = dev->dev_private;
848 drm_i915_setparam_t *param = data;
849
850 if (!dev_priv) {
851 DRM_ERROR("called with no initialization\n");
852 return -EINVAL;
853 }
854
855 switch (param->param) {
856 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
857 break;
858 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
859 dev_priv->tex_lru_log_granularity = param->value;
860 break;
861 case I915_SETPARAM_ALLOW_BATCHBUFFER:
862 dev_priv->allow_batchbuffer = param->value;
863 break;
864 case I915_SETPARAM_NUM_USED_FENCES:
865 if (param->value > dev_priv->num_fence_regs ||
866 param->value < 0)
867 return -EINVAL;
868 /* Userspace can use first N regs */
869 dev_priv->fence_reg_start = param->value;
870 break;
871 default:
872 DRM_DEBUG_DRIVER("unknown parameter %d\n",
873 param->param);
874 return -EINVAL;
875 }
876
877 return 0;
878 }
879
880 static int i915_set_status_page(struct drm_device *dev, void *data,
881 struct drm_file *file_priv)
882 {
883 drm_i915_private_t *dev_priv = dev->dev_private;
884 drm_i915_hws_addr_t *hws = data;
885
886 if (!I915_NEED_GFX_HWS(dev))
887 return -EINVAL;
888
889 if (!dev_priv) {
890 DRM_ERROR("called with no initialization\n");
891 return -EINVAL;
892 }
893
894 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
895 WARN(1, "tried to set status page when mode setting active\n");
896 return 0;
897 }
898
899 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
900
901 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
902
903 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
904 dev_priv->hws_map.size = 4*1024;
905 dev_priv->hws_map.type = 0;
906 dev_priv->hws_map.flags = 0;
907 dev_priv->hws_map.mtrr = 0;
908
909 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
910 if (dev_priv->hws_map.handle == NULL) {
911 i915_dma_cleanup(dev);
912 dev_priv->status_gfx_addr = 0;
913 DRM_ERROR("can not ioremap virtual address for"
914 " G33 hw status page\n");
915 return -ENOMEM;
916 }
917 dev_priv->hw_status_page = dev_priv->hws_map.handle;
918
919 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
920 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
921 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
922 dev_priv->status_gfx_addr);
923 DRM_DEBUG_DRIVER("load hws at %p\n",
924 dev_priv->hw_status_page);
925 return 0;
926 }
927
928 static int i915_get_bridge_dev(struct drm_device *dev)
929 {
930 struct drm_i915_private *dev_priv = dev->dev_private;
931
932 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
933 if (!dev_priv->bridge_dev) {
934 DRM_ERROR("bridge device not found\n");
935 return -1;
936 }
937 return 0;
938 }
939
940 #define MCHBAR_I915 0x44
941 #define MCHBAR_I965 0x48
942 #define MCHBAR_SIZE (4*4096)
943
944 #define DEVEN_REG 0x54
945 #define DEVEN_MCHBAR_EN (1 << 28)
946
947 /* Allocate space for the MCH regs if needed, return nonzero on error */
948 static int
949 intel_alloc_mchbar_resource(struct drm_device *dev)
950 {
951 drm_i915_private_t *dev_priv = dev->dev_private;
952 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
953 u32 temp_lo, temp_hi = 0;
954 u64 mchbar_addr;
955 int ret = 0;
956
957 if (IS_I965G(dev))
958 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
959 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
960 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
961
962 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
963 #ifdef CONFIG_PNP
964 if (mchbar_addr &&
965 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
966 ret = 0;
967 goto out;
968 }
969 #endif
970
971 /* Get some space for it */
972 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
973 MCHBAR_SIZE, MCHBAR_SIZE,
974 PCIBIOS_MIN_MEM,
975 0, pcibios_align_resource,
976 dev_priv->bridge_dev);
977 if (ret) {
978 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
979 dev_priv->mch_res.start = 0;
980 goto out;
981 }
982
983 if (IS_I965G(dev))
984 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
985 upper_32_bits(dev_priv->mch_res.start));
986
987 pci_write_config_dword(dev_priv->bridge_dev, reg,
988 lower_32_bits(dev_priv->mch_res.start));
989 out:
990 return ret;
991 }
992
993 /* Setup MCHBAR if possible, return true if we should disable it again */
994 static void
995 intel_setup_mchbar(struct drm_device *dev)
996 {
997 drm_i915_private_t *dev_priv = dev->dev_private;
998 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
999 u32 temp;
1000 bool enabled;
1001
1002 dev_priv->mchbar_need_disable = false;
1003
1004 if (IS_I915G(dev) || IS_I915GM(dev)) {
1005 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1006 enabled = !!(temp & DEVEN_MCHBAR_EN);
1007 } else {
1008 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1009 enabled = temp & 1;
1010 }
1011
1012 /* If it's already enabled, don't have to do anything */
1013 if (enabled)
1014 return;
1015
1016 if (intel_alloc_mchbar_resource(dev))
1017 return;
1018
1019 dev_priv->mchbar_need_disable = true;
1020
1021 /* Space is allocated or reserved, so enable it. */
1022 if (IS_I915G(dev) || IS_I915GM(dev)) {
1023 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1024 temp | DEVEN_MCHBAR_EN);
1025 } else {
1026 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1027 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1028 }
1029 }
1030
1031 static void
1032 intel_teardown_mchbar(struct drm_device *dev)
1033 {
1034 drm_i915_private_t *dev_priv = dev->dev_private;
1035 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
1036 u32 temp;
1037
1038 if (dev_priv->mchbar_need_disable) {
1039 if (IS_I915G(dev) || IS_I915GM(dev)) {
1040 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1041 temp &= ~DEVEN_MCHBAR_EN;
1042 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1043 } else {
1044 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1045 temp &= ~1;
1046 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1047 }
1048 }
1049
1050 if (dev_priv->mch_res.start)
1051 release_resource(&dev_priv->mch_res);
1052 }
1053
1054 /**
1055 * i915_probe_agp - get AGP bootup configuration
1056 * @pdev: PCI device
1057 * @aperture_size: returns AGP aperture configured size
1058 * @preallocated_size: returns size of BIOS preallocated AGP space
1059 *
1060 * Since Intel integrated graphics are UMA, the BIOS has to set aside
1061 * some RAM for the framebuffer at early boot. This code figures out
1062 * how much was set aside so we can use it for our own purposes.
1063 */
1064 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
1065 uint32_t *preallocated_size,
1066 uint32_t *start)
1067 {
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 u16 tmp = 0;
1070 unsigned long overhead;
1071 unsigned long stolen;
1072
1073 /* Get the fb aperture size and "stolen" memory amount. */
1074 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1075
1076 *aperture_size = 1024 * 1024;
1077 *preallocated_size = 1024 * 1024;
1078
1079 switch (dev->pdev->device) {
1080 case PCI_DEVICE_ID_INTEL_82830_CGC:
1081 case PCI_DEVICE_ID_INTEL_82845G_IG:
1082 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1083 case PCI_DEVICE_ID_INTEL_82865_IG:
1084 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1085 *aperture_size *= 64;
1086 else
1087 *aperture_size *= 128;
1088 break;
1089 default:
1090 /* 9xx supports large sizes, just look at the length */
1091 *aperture_size = pci_resource_len(dev->pdev, 2);
1092 break;
1093 }
1094
1095 /*
1096 * Some of the preallocated space is taken by the GTT
1097 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1098 */
1099 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1100 overhead = 4096;
1101 else
1102 overhead = (*aperture_size / 1024) + 4096;
1103
1104 if (IS_GEN6(dev)) {
1105 /* SNB has memory control reg at 0x50.w */
1106 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1107
1108 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1109 case INTEL_855_GMCH_GMS_DISABLED:
1110 DRM_ERROR("video memory is disabled\n");
1111 return -1;
1112 case SNB_GMCH_GMS_STOLEN_32M:
1113 stolen = 32 * 1024 * 1024;
1114 break;
1115 case SNB_GMCH_GMS_STOLEN_64M:
1116 stolen = 64 * 1024 * 1024;
1117 break;
1118 case SNB_GMCH_GMS_STOLEN_96M:
1119 stolen = 96 * 1024 * 1024;
1120 break;
1121 case SNB_GMCH_GMS_STOLEN_128M:
1122 stolen = 128 * 1024 * 1024;
1123 break;
1124 case SNB_GMCH_GMS_STOLEN_160M:
1125 stolen = 160 * 1024 * 1024;
1126 break;
1127 case SNB_GMCH_GMS_STOLEN_192M:
1128 stolen = 192 * 1024 * 1024;
1129 break;
1130 case SNB_GMCH_GMS_STOLEN_224M:
1131 stolen = 224 * 1024 * 1024;
1132 break;
1133 case SNB_GMCH_GMS_STOLEN_256M:
1134 stolen = 256 * 1024 * 1024;
1135 break;
1136 case SNB_GMCH_GMS_STOLEN_288M:
1137 stolen = 288 * 1024 * 1024;
1138 break;
1139 case SNB_GMCH_GMS_STOLEN_320M:
1140 stolen = 320 * 1024 * 1024;
1141 break;
1142 case SNB_GMCH_GMS_STOLEN_352M:
1143 stolen = 352 * 1024 * 1024;
1144 break;
1145 case SNB_GMCH_GMS_STOLEN_384M:
1146 stolen = 384 * 1024 * 1024;
1147 break;
1148 case SNB_GMCH_GMS_STOLEN_416M:
1149 stolen = 416 * 1024 * 1024;
1150 break;
1151 case SNB_GMCH_GMS_STOLEN_448M:
1152 stolen = 448 * 1024 * 1024;
1153 break;
1154 case SNB_GMCH_GMS_STOLEN_480M:
1155 stolen = 480 * 1024 * 1024;
1156 break;
1157 case SNB_GMCH_GMS_STOLEN_512M:
1158 stolen = 512 * 1024 * 1024;
1159 break;
1160 default:
1161 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1162 tmp & SNB_GMCH_GMS_STOLEN_MASK);
1163 return -1;
1164 }
1165 } else {
1166 switch (tmp & INTEL_GMCH_GMS_MASK) {
1167 case INTEL_855_GMCH_GMS_DISABLED:
1168 DRM_ERROR("video memory is disabled\n");
1169 return -1;
1170 case INTEL_855_GMCH_GMS_STOLEN_1M:
1171 stolen = 1 * 1024 * 1024;
1172 break;
1173 case INTEL_855_GMCH_GMS_STOLEN_4M:
1174 stolen = 4 * 1024 * 1024;
1175 break;
1176 case INTEL_855_GMCH_GMS_STOLEN_8M:
1177 stolen = 8 * 1024 * 1024;
1178 break;
1179 case INTEL_855_GMCH_GMS_STOLEN_16M:
1180 stolen = 16 * 1024 * 1024;
1181 break;
1182 case INTEL_855_GMCH_GMS_STOLEN_32M:
1183 stolen = 32 * 1024 * 1024;
1184 break;
1185 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1186 stolen = 48 * 1024 * 1024;
1187 break;
1188 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1189 stolen = 64 * 1024 * 1024;
1190 break;
1191 case INTEL_GMCH_GMS_STOLEN_128M:
1192 stolen = 128 * 1024 * 1024;
1193 break;
1194 case INTEL_GMCH_GMS_STOLEN_256M:
1195 stolen = 256 * 1024 * 1024;
1196 break;
1197 case INTEL_GMCH_GMS_STOLEN_96M:
1198 stolen = 96 * 1024 * 1024;
1199 break;
1200 case INTEL_GMCH_GMS_STOLEN_160M:
1201 stolen = 160 * 1024 * 1024;
1202 break;
1203 case INTEL_GMCH_GMS_STOLEN_224M:
1204 stolen = 224 * 1024 * 1024;
1205 break;
1206 case INTEL_GMCH_GMS_STOLEN_352M:
1207 stolen = 352 * 1024 * 1024;
1208 break;
1209 default:
1210 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1211 tmp & INTEL_GMCH_GMS_MASK);
1212 return -1;
1213 }
1214 }
1215
1216 *preallocated_size = stolen - overhead;
1217 *start = overhead;
1218
1219 return 0;
1220 }
1221
1222 #define PTE_ADDRESS_MASK 0xfffff000
1223 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1224 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1225 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1226 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1227 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1228 #define PTE_VALID (1 << 0)
1229
1230 /**
1231 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1232 * @dev: drm device
1233 * @gtt_addr: address to translate
1234 *
1235 * Some chip functions require allocations from stolen space but need the
1236 * physical address of the memory in question. We use this routine
1237 * to get a physical address suitable for register programming from a given
1238 * GTT address.
1239 */
1240 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1241 unsigned long gtt_addr)
1242 {
1243 unsigned long *gtt;
1244 unsigned long entry, phys;
1245 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1246 int gtt_offset, gtt_size;
1247
1248 if (IS_I965G(dev)) {
1249 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1250 gtt_offset = 2*1024*1024;
1251 gtt_size = 2*1024*1024;
1252 } else {
1253 gtt_offset = 512*1024;
1254 gtt_size = 512*1024;
1255 }
1256 } else {
1257 gtt_bar = 3;
1258 gtt_offset = 0;
1259 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1260 }
1261
1262 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1263 gtt_size);
1264 if (!gtt) {
1265 DRM_ERROR("ioremap of GTT failed\n");
1266 return 0;
1267 }
1268
1269 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1270
1271 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1272
1273 /* Mask out these reserved bits on this hardware. */
1274 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1275 IS_I945G(dev) || IS_I945GM(dev)) {
1276 entry &= ~PTE_ADDRESS_MASK_HIGH;
1277 }
1278
1279 /* If it's not a mapping type we know, then bail. */
1280 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1281 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1282 iounmap(gtt);
1283 return 0;
1284 }
1285
1286 if (!(entry & PTE_VALID)) {
1287 DRM_ERROR("bad GTT entry in stolen space\n");
1288 iounmap(gtt);
1289 return 0;
1290 }
1291
1292 iounmap(gtt);
1293
1294 phys =(entry & PTE_ADDRESS_MASK) |
1295 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1296
1297 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1298
1299 return phys;
1300 }
1301
1302 static void i915_warn_stolen(struct drm_device *dev)
1303 {
1304 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1305 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1306 }
1307
1308 static void i915_setup_compression(struct drm_device *dev, int size)
1309 {
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 struct drm_mm_node *compressed_fb, *compressed_llb;
1312 unsigned long cfb_base;
1313 unsigned long ll_base = 0;
1314
1315 /* Leave 1M for line length buffer & misc. */
1316 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1317 if (!compressed_fb) {
1318 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1319 i915_warn_stolen(dev);
1320 return;
1321 }
1322
1323 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1324 if (!compressed_fb) {
1325 i915_warn_stolen(dev);
1326 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1327 return;
1328 }
1329
1330 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1331 if (!cfb_base) {
1332 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1333 drm_mm_put_block(compressed_fb);
1334 }
1335
1336 if (!IS_GM45(dev)) {
1337 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1338 4096, 0);
1339 if (!compressed_llb) {
1340 i915_warn_stolen(dev);
1341 return;
1342 }
1343
1344 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1345 if (!compressed_llb) {
1346 i915_warn_stolen(dev);
1347 return;
1348 }
1349
1350 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1351 if (!ll_base) {
1352 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1353 drm_mm_put_block(compressed_fb);
1354 drm_mm_put_block(compressed_llb);
1355 }
1356 }
1357
1358 dev_priv->cfb_size = size;
1359
1360 intel_disable_fbc(dev);
1361 dev_priv->compressed_fb = compressed_fb;
1362
1363 if (IS_GM45(dev)) {
1364 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1365 } else {
1366 I915_WRITE(FBC_CFB_BASE, cfb_base);
1367 I915_WRITE(FBC_LL_BASE, ll_base);
1368 dev_priv->compressed_llb = compressed_llb;
1369 }
1370
1371 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1372 ll_base, size >> 20);
1373 }
1374
1375 static void i915_cleanup_compression(struct drm_device *dev)
1376 {
1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378
1379 drm_mm_put_block(dev_priv->compressed_fb);
1380 if (!IS_GM45(dev))
1381 drm_mm_put_block(dev_priv->compressed_llb);
1382 }
1383
1384 /* true = enable decode, false = disable decoder */
1385 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1386 {
1387 struct drm_device *dev = cookie;
1388
1389 intel_modeset_vga_set_state(dev, state);
1390 if (state)
1391 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1392 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1393 else
1394 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1395 }
1396
1397 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1398 {
1399 struct drm_device *dev = pci_get_drvdata(pdev);
1400 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1401 if (state == VGA_SWITCHEROO_ON) {
1402 printk(KERN_INFO "i915: switched on\n");
1403 /* i915 resume handler doesn't set to D0 */
1404 pci_set_power_state(dev->pdev, PCI_D0);
1405 i915_resume(dev);
1406 drm_kms_helper_poll_enable(dev);
1407 } else {
1408 printk(KERN_ERR "i915: switched off\n");
1409 drm_kms_helper_poll_disable(dev);
1410 i915_suspend(dev, pmm);
1411 }
1412 }
1413
1414 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1415 {
1416 struct drm_device *dev = pci_get_drvdata(pdev);
1417 bool can_switch;
1418
1419 spin_lock(&dev->count_lock);
1420 can_switch = (dev->open_count == 0);
1421 spin_unlock(&dev->count_lock);
1422 return can_switch;
1423 }
1424
1425 static int i915_load_modeset_init(struct drm_device *dev,
1426 unsigned long prealloc_start,
1427 unsigned long prealloc_size,
1428 unsigned long agp_size)
1429 {
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1432 int ret = 0;
1433
1434 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1435 0xff000000;
1436
1437 /* Basic memrange allocator for stolen space (aka vram) */
1438 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1439 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1440
1441 /* We're off and running w/KMS */
1442 dev_priv->mm.suspended = 0;
1443
1444 /* Let GEM Manage from end of prealloc space to end of aperture.
1445 *
1446 * However, leave one page at the end still bound to the scratch page.
1447 * There are a number of places where the hardware apparently
1448 * prefetches past the end of the object, and we've seen multiple
1449 * hangs with the GPU head pointer stuck in a batchbuffer bound
1450 * at the last page of the aperture. One page should be enough to
1451 * keep any prefetching inside of the aperture.
1452 */
1453 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1454
1455 mutex_lock(&dev->struct_mutex);
1456 ret = i915_gem_init_ringbuffer(dev);
1457 mutex_unlock(&dev->struct_mutex);
1458 if (ret)
1459 goto out;
1460
1461 /* Try to set up FBC with a reasonable compressed buffer size */
1462 if (I915_HAS_FBC(dev) && i915_powersave) {
1463 int cfb_size;
1464
1465 /* Try to get an 8M buffer... */
1466 if (prealloc_size > (9*1024*1024))
1467 cfb_size = 8*1024*1024;
1468 else /* fall back to 7/8 of the stolen space */
1469 cfb_size = prealloc_size * 7 / 8;
1470 i915_setup_compression(dev, cfb_size);
1471 }
1472
1473 /* Allow hardware batchbuffers unless told otherwise.
1474 */
1475 dev_priv->allow_batchbuffer = 1;
1476
1477 ret = intel_init_bios(dev);
1478 if (ret)
1479 DRM_INFO("failed to find VBIOS tables\n");
1480
1481 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1482 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1483 if (ret)
1484 goto destroy_ringbuffer;
1485
1486 ret = vga_switcheroo_register_client(dev->pdev,
1487 i915_switcheroo_set_state,
1488 i915_switcheroo_can_switch);
1489 if (ret)
1490 goto destroy_ringbuffer;
1491
1492 intel_modeset_init(dev);
1493
1494 ret = drm_irq_install(dev);
1495 if (ret)
1496 goto destroy_ringbuffer;
1497
1498 /* Always safe in the mode setting case. */
1499 /* FIXME: do pre/post-mode set stuff in core KMS code */
1500 dev->vblank_disable_allowed = 1;
1501
1502 /*
1503 * Initialize the hardware status page IRQ location.
1504 */
1505
1506 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1507
1508 intel_fbdev_init(dev);
1509 drm_kms_helper_poll_init(dev);
1510 return 0;
1511
1512 destroy_ringbuffer:
1513 mutex_lock(&dev->struct_mutex);
1514 i915_gem_cleanup_ringbuffer(dev);
1515 mutex_unlock(&dev->struct_mutex);
1516 out:
1517 return ret;
1518 }
1519
1520 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1521 {
1522 struct drm_i915_master_private *master_priv;
1523
1524 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1525 if (!master_priv)
1526 return -ENOMEM;
1527
1528 master->driver_priv = master_priv;
1529 return 0;
1530 }
1531
1532 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1533 {
1534 struct drm_i915_master_private *master_priv = master->driver_priv;
1535
1536 if (!master_priv)
1537 return;
1538
1539 kfree(master_priv);
1540
1541 master->driver_priv = NULL;
1542 }
1543
1544 static void i915_get_mem_freq(struct drm_device *dev)
1545 {
1546 drm_i915_private_t *dev_priv = dev->dev_private;
1547 u32 tmp;
1548
1549 if (!IS_PINEVIEW(dev))
1550 return;
1551
1552 tmp = I915_READ(CLKCFG);
1553
1554 switch (tmp & CLKCFG_FSB_MASK) {
1555 case CLKCFG_FSB_533:
1556 dev_priv->fsb_freq = 533; /* 133*4 */
1557 break;
1558 case CLKCFG_FSB_800:
1559 dev_priv->fsb_freq = 800; /* 200*4 */
1560 break;
1561 case CLKCFG_FSB_667:
1562 dev_priv->fsb_freq = 667; /* 167*4 */
1563 break;
1564 case CLKCFG_FSB_400:
1565 dev_priv->fsb_freq = 400; /* 100*4 */
1566 break;
1567 }
1568
1569 switch (tmp & CLKCFG_MEM_MASK) {
1570 case CLKCFG_MEM_533:
1571 dev_priv->mem_freq = 533;
1572 break;
1573 case CLKCFG_MEM_667:
1574 dev_priv->mem_freq = 667;
1575 break;
1576 case CLKCFG_MEM_800:
1577 dev_priv->mem_freq = 800;
1578 break;
1579 }
1580 }
1581
1582 /**
1583 * i915_driver_load - setup chip and create an initial config
1584 * @dev: DRM device
1585 * @flags: startup flags
1586 *
1587 * The driver load routine has to do several things:
1588 * - drive output discovery via intel_modeset_init()
1589 * - initialize the memory manager
1590 * - allocate initial config memory
1591 * - setup the DRM framebuffer with the allocated memory
1592 */
1593 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1594 {
1595 struct drm_i915_private *dev_priv;
1596 resource_size_t base, size;
1597 int ret = 0, mmio_bar;
1598 uint32_t agp_size, prealloc_size, prealloc_start;
1599
1600 /* i915 has 4 more counters */
1601 dev->counters += 4;
1602 dev->types[6] = _DRM_STAT_IRQ;
1603 dev->types[7] = _DRM_STAT_PRIMARY;
1604 dev->types[8] = _DRM_STAT_SECONDARY;
1605 dev->types[9] = _DRM_STAT_DMA;
1606
1607 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1608 if (dev_priv == NULL)
1609 return -ENOMEM;
1610
1611 dev->dev_private = (void *)dev_priv;
1612 dev_priv->dev = dev;
1613 dev_priv->info = (struct intel_device_info *) flags;
1614
1615 /* Add register map (needed for suspend/resume) */
1616 mmio_bar = IS_I9XX(dev) ? 0 : 1;
1617 base = drm_get_resource_start(dev, mmio_bar);
1618 size = drm_get_resource_len(dev, mmio_bar);
1619
1620 if (i915_get_bridge_dev(dev)) {
1621 ret = -EIO;
1622 goto free_priv;
1623 }
1624
1625 dev_priv->regs = ioremap(base, size);
1626 if (!dev_priv->regs) {
1627 DRM_ERROR("failed to map registers\n");
1628 ret = -EIO;
1629 goto put_bridge;
1630 }
1631
1632 dev_priv->mm.gtt_mapping =
1633 io_mapping_create_wc(dev->agp->base,
1634 dev->agp->agp_info.aper_size * 1024*1024);
1635 if (dev_priv->mm.gtt_mapping == NULL) {
1636 ret = -EIO;
1637 goto out_rmmap;
1638 }
1639
1640 /* Set up a WC MTRR for non-PAT systems. This is more common than
1641 * one would think, because the kernel disables PAT on first
1642 * generation Core chips because WC PAT gets overridden by a UC
1643 * MTRR if present. Even if a UC MTRR isn't present.
1644 */
1645 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1646 dev->agp->agp_info.aper_size *
1647 1024 * 1024,
1648 MTRR_TYPE_WRCOMB, 1);
1649 if (dev_priv->mm.gtt_mtrr < 0) {
1650 DRM_INFO("MTRR allocation failed. Graphics "
1651 "performance may suffer.\n");
1652 }
1653
1654 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1655 if (ret)
1656 goto out_iomapfree;
1657
1658 dev_priv->wq = create_singlethread_workqueue("i915");
1659 if (dev_priv->wq == NULL) {
1660 DRM_ERROR("Failed to create our workqueue.\n");
1661 ret = -ENOMEM;
1662 goto out_iomapfree;
1663 }
1664
1665 /* enable GEM by default */
1666 dev_priv->has_gem = 1;
1667
1668 if (prealloc_size > agp_size * 3 / 4) {
1669 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1670 "memory stolen.\n",
1671 prealloc_size / 1024, agp_size / 1024);
1672 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1673 "updating the BIOS to fix).\n");
1674 dev_priv->has_gem = 0;
1675 }
1676
1677 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1678 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1679 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1680 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1681 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1682 }
1683
1684 /* Try to make sure MCHBAR is enabled before poking at it */
1685 intel_setup_mchbar(dev);
1686
1687 i915_gem_load(dev);
1688
1689 /* Init HWS */
1690 if (!I915_NEED_GFX_HWS(dev)) {
1691 ret = i915_init_phys_hws(dev);
1692 if (ret != 0)
1693 goto out_workqueue_free;
1694 }
1695
1696 i915_get_mem_freq(dev);
1697
1698 /* On the 945G/GM, the chipset reports the MSI capability on the
1699 * integrated graphics even though the support isn't actually there
1700 * according to the published specs. It doesn't appear to function
1701 * correctly in testing on 945G.
1702 * This may be a side effect of MSI having been made available for PEG
1703 * and the registers being closely associated.
1704 *
1705 * According to chipset errata, on the 965GM, MSI interrupts may
1706 * be lost or delayed, but we use them anyways to avoid
1707 * stuck interrupts on some machines.
1708 */
1709 if (!IS_I945G(dev) && !IS_I945GM(dev))
1710 pci_enable_msi(dev->pdev);
1711
1712 spin_lock_init(&dev_priv->user_irq_lock);
1713 spin_lock_init(&dev_priv->error_lock);
1714 dev_priv->user_irq_refcount = 0;
1715 dev_priv->trace_irq_seqno = 0;
1716
1717 ret = drm_vblank_init(dev, I915_NUM_PIPE);
1718
1719 if (ret) {
1720 (void) i915_driver_unload(dev);
1721 return ret;
1722 }
1723
1724 /* Start out suspended */
1725 dev_priv->mm.suspended = 1;
1726
1727 intel_detect_pch(dev);
1728
1729 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1730 ret = i915_load_modeset_init(dev, prealloc_start,
1731 prealloc_size, agp_size);
1732 if (ret < 0) {
1733 DRM_ERROR("failed to init modeset\n");
1734 goto out_workqueue_free;
1735 }
1736 }
1737
1738 /* Must be done after probing outputs */
1739 intel_opregion_init(dev, 0);
1740
1741 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1742 (unsigned long) dev);
1743 return 0;
1744
1745 out_workqueue_free:
1746 destroy_workqueue(dev_priv->wq);
1747 out_iomapfree:
1748 io_mapping_free(dev_priv->mm.gtt_mapping);
1749 out_rmmap:
1750 iounmap(dev_priv->regs);
1751 put_bridge:
1752 pci_dev_put(dev_priv->bridge_dev);
1753 free_priv:
1754 kfree(dev_priv);
1755 return ret;
1756 }
1757
1758 int i915_driver_unload(struct drm_device *dev)
1759 {
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761
1762 i915_destroy_error_state(dev);
1763
1764 destroy_workqueue(dev_priv->wq);
1765 del_timer_sync(&dev_priv->hangcheck_timer);
1766
1767 io_mapping_free(dev_priv->mm.gtt_mapping);
1768 if (dev_priv->mm.gtt_mtrr >= 0) {
1769 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1770 dev->agp->agp_info.aper_size * 1024 * 1024);
1771 dev_priv->mm.gtt_mtrr = -1;
1772 }
1773
1774 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1775 intel_modeset_cleanup(dev);
1776
1777 /*
1778 * free the memory space allocated for the child device
1779 * config parsed from VBT
1780 */
1781 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1782 kfree(dev_priv->child_dev);
1783 dev_priv->child_dev = NULL;
1784 dev_priv->child_dev_num = 0;
1785 }
1786 drm_irq_uninstall(dev);
1787 vga_switcheroo_unregister_client(dev->pdev);
1788 vga_client_register(dev->pdev, NULL, NULL, NULL);
1789 }
1790
1791 if (dev->pdev->msi_enabled)
1792 pci_disable_msi(dev->pdev);
1793
1794 if (dev_priv->regs != NULL)
1795 iounmap(dev_priv->regs);
1796
1797 intel_opregion_free(dev, 0);
1798
1799 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1800 i915_gem_free_all_phys_object(dev);
1801
1802 mutex_lock(&dev->struct_mutex);
1803 i915_gem_cleanup_ringbuffer(dev);
1804 mutex_unlock(&dev->struct_mutex);
1805 if (I915_HAS_FBC(dev) && i915_powersave)
1806 i915_cleanup_compression(dev);
1807 drm_mm_takedown(&dev_priv->vram);
1808 i915_gem_lastclose(dev);
1809
1810 intel_cleanup_overlay(dev);
1811 }
1812
1813 intel_teardown_mchbar(dev);
1814
1815 pci_dev_put(dev_priv->bridge_dev);
1816 kfree(dev->dev_private);
1817
1818 return 0;
1819 }
1820
1821 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1822 {
1823 struct drm_i915_file_private *i915_file_priv;
1824
1825 DRM_DEBUG_DRIVER("\n");
1826 i915_file_priv = (struct drm_i915_file_private *)
1827 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1828
1829 if (!i915_file_priv)
1830 return -ENOMEM;
1831
1832 file_priv->driver_priv = i915_file_priv;
1833
1834 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1835
1836 return 0;
1837 }
1838
1839 /**
1840 * i915_driver_lastclose - clean up after all DRM clients have exited
1841 * @dev: DRM device
1842 *
1843 * Take care of cleaning up after all DRM clients have exited. In the
1844 * mode setting case, we want to restore the kernel's initial mode (just
1845 * in case the last client left us in a bad state).
1846 *
1847 * Additionally, in the non-mode setting case, we'll tear down the AGP
1848 * and DMA structures, since the kernel won't be using them, and clea
1849 * up any GEM state.
1850 */
1851 void i915_driver_lastclose(struct drm_device * dev)
1852 {
1853 drm_i915_private_t *dev_priv = dev->dev_private;
1854
1855 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1856 drm_fb_helper_restore();
1857 vga_switcheroo_process_delayed_switch();
1858 return;
1859 }
1860
1861 i915_gem_lastclose(dev);
1862
1863 if (dev_priv->agp_heap)
1864 i915_mem_takedown(&(dev_priv->agp_heap));
1865
1866 i915_dma_cleanup(dev);
1867 }
1868
1869 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1870 {
1871 drm_i915_private_t *dev_priv = dev->dev_private;
1872 i915_gem_release(dev, file_priv);
1873 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1874 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1875 }
1876
1877 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1878 {
1879 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1880
1881 kfree(i915_file_priv);
1882 }
1883
1884 struct drm_ioctl_desc i915_ioctls[] = {
1885 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1886 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1887 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1888 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1889 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1890 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1891 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1892 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1893 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1894 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1895 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1896 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1897 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1898 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1899 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1900 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1901 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1902 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1903 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1904 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1905 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1906 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1907 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1908 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1909 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1910 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1911 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1912 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1913 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1914 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1915 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1916 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1917 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1918 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1919 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1920 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1921 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1922 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1923 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1924 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1925 };
1926
1927 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1928
1929 /**
1930 * Determine if the device really is AGP or not.
1931 *
1932 * All Intel graphics chipsets are treated as AGP, even if they are really
1933 * PCI-e.
1934 *
1935 * \param dev The device to be tested.
1936 *
1937 * \returns
1938 * A value of 1 is always retured to indictate every i9x5 is AGP.
1939 */
1940 int i915_driver_device_is_agp(struct drm_device * dev)
1941 {
1942 return 1;
1943 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree