2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
31 #include <linux/spinlock.h>
32 #include <linux/workqueue.h>
34 #include <linux/delay.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/ulpi.h>
37 #include <linux/i2c/twl.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/err.h>
40 #include <linux/notifier.h>
41 #include <linux/slab.h>
43 /* Register defines */
45 #define MCPC_CTRL 0x30
46 #define MCPC_CTRL_RTSOL (1 << 7)
47 #define MCPC_CTRL_EXTSWR (1 << 6)
48 #define MCPC_CTRL_EXTSWC (1 << 5)
49 #define MCPC_CTRL_VOICESW (1 << 4)
50 #define MCPC_CTRL_OUT64K (1 << 3)
51 #define MCPC_CTRL_RTSCTSSW (1 << 2)
52 #define MCPC_CTRL_HS_UART (1 << 0)
54 #define MCPC_IO_CTRL 0x33
55 #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
56 #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
57 #define MCPC_IO_CTRL_RXD_PU (1 << 3)
58 #define MCPC_IO_CTRL_TXDTYP (1 << 2)
59 #define MCPC_IO_CTRL_CTSTYP (1 << 1)
60 #define MCPC_IO_CTRL_RTSTYP (1 << 0)
62 #define MCPC_CTRL2 0x36
63 #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
65 #define OTHER_FUNC_CTRL 0x80
66 #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
67 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
69 #define OTHER_IFC_CTRL 0x83
70 #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
71 #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
72 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
73 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
74 #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
75 #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
77 #define OTHER_INT_EN_RISE 0x86
78 #define OTHER_INT_EN_FALL 0x89
79 #define OTHER_INT_STS 0x8C
80 #define OTHER_INT_LATCH 0x8D
81 #define OTHER_INT_VB_SESS_VLD (1 << 7)
82 #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
83 #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
84 #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
85 #define OTHER_INT_MANU (1 << 1)
86 #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
88 #define ID_STATUS 0x96
89 #define ID_RES_FLOAT (1 << 4)
90 #define ID_RES_440K (1 << 3)
91 #define ID_RES_200K (1 << 2)
92 #define ID_RES_102K (1 << 1)
93 #define ID_RES_GND (1 << 0)
95 #define POWER_CTRL 0xAC
96 #define POWER_CTRL_OTG_ENAB (1 << 5)
98 #define OTHER_IFC_CTRL2 0xAF
99 #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
100 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
101 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
102 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
106 #define REG_CTRL_EN 0xB2
107 #define REG_CTRL_ERROR 0xB5
108 #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
110 #define OTHER_FUNC_CTRL2 0xB8
111 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
113 /* following registers do not have separate _clr and _set registers */
114 #define VBUS_DEBOUNCE 0xC0
115 #define ID_DEBOUNCE 0xC1
116 #define VBAT_TIMER 0xD3
117 #define PHY_PWR_CTRL 0xFD
118 #define PHY_PWR_PHYPWD (1 << 0)
119 #define PHY_CLK_CTRL 0xFE
120 #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
121 #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
122 #define REQ_PHY_DPLL_CLK (1 << 0)
123 #define PHY_CLK_CTRL_STS 0xFF
124 #define PHY_DPLL_CLK (1 << 0)
126 /* In module TWL4030_MODULE_PM_MASTER */
127 #define STS_HW_CONDITIONS 0x0F
129 /* In module TWL4030_MODULE_PM_RECEIVER */
130 #define VUSB_DEDICATED1 0x7D
131 #define VUSB_DEDICATED2 0x7E
132 #define VUSB1V5_DEV_GRP 0x71
133 #define VUSB1V5_TYPE 0x72
134 #define VUSB1V5_REMAP 0x73
135 #define VUSB1V8_DEV_GRP 0x74
136 #define VUSB1V8_TYPE 0x75
137 #define VUSB1V8_REMAP 0x76
138 #define VUSB3V1_DEV_GRP 0x77
139 #define VUSB3V1_TYPE 0x78
140 #define VUSB3V1_REMAP 0x79
142 /* In module TWL4030_MODULE_INTBR */
144 #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
147 struct otg_transceiver otg
;
150 /* TWL4030 internal USB regulator supplies */
151 struct regulator
*usb1v5
;
152 struct regulator
*usb1v8
;
153 struct regulator
*usb3v1
;
155 /* for vbus reporting with irqs disabled */
158 /* pin configuration */
159 enum twl4030_usb_mode usb_mode
;
167 /* internal define on top of container_of */
168 #define xceiv_to_twl(x) container_of((x), struct twl4030_usb, otg);
170 /*-------------------------------------------------------------------------*/
172 static int twl4030_i2c_write_u8_verify(struct twl4030_usb
*twl
,
173 u8 module
, u8 data
, u8 address
)
177 if ((twl_i2c_write_u8(module
, data
, address
) >= 0) &&
178 (twl_i2c_read_u8(module
, &check
, address
) >= 0) &&
181 dev_dbg(twl
->dev
, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
182 1, module
, address
, check
, data
);
184 /* Failed once: Try again */
185 if ((twl_i2c_write_u8(module
, data
, address
) >= 0) &&
186 (twl_i2c_read_u8(module
, &check
, address
) >= 0) &&
189 dev_dbg(twl
->dev
, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
190 2, module
, address
, check
, data
);
192 /* Failed again: Return error */
196 #define twl4030_usb_write_verify(twl, address, data) \
197 twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
199 static inline int twl4030_usb_write(struct twl4030_usb
*twl
,
204 ret
= twl_i2c_write_u8(TWL4030_MODULE_USB
, data
, address
);
207 "TWL4030:USB:Write[0x%x] Error %d\n", address
, ret
);
211 static inline int twl4030_readb(struct twl4030_usb
*twl
, u8 module
, u8 address
)
216 ret
= twl_i2c_read_u8(module
, &data
, address
);
221 "TWL4030:readb[0x%x,0x%x] Error %d\n",
222 module
, address
, ret
);
227 static inline int twl4030_usb_read(struct twl4030_usb
*twl
, u8 address
)
229 return twl4030_readb(twl
, TWL4030_MODULE_USB
, address
);
232 /*-------------------------------------------------------------------------*/
235 twl4030_usb_set_bits(struct twl4030_usb
*twl
, u8 reg
, u8 bits
)
237 return twl4030_usb_write(twl
, ULPI_SET(reg
), bits
);
241 twl4030_usb_clear_bits(struct twl4030_usb
*twl
, u8 reg
, u8 bits
)
243 return twl4030_usb_write(twl
, ULPI_CLR(reg
), bits
);
246 /*-------------------------------------------------------------------------*/
248 static enum usb_xceiv_events
twl4030_usb_linkstat(struct twl4030_usb
*twl
)
251 int linkstat
= USB_EVENT_NONE
;
254 * For ID/VBUS sensing, see manual section 15.4.8 ...
255 * except when using only battery backup power, two
256 * comparators produce VBUS_PRES and ID_PRES signals,
257 * which don't match docs elsewhere. But ... BIT(7)
258 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
259 * seem to match up. If either is true the USB_PRES
260 * signal is active, the OTG module is activated, and
261 * its interrupt may be raised (may wake the system).
263 status
= twl4030_readb(twl
, TWL4030_MODULE_PM_MASTER
,
266 dev_err(twl
->dev
, "USB link status err %d\n", status
);
267 else if (status
& (BIT(7) | BIT(2))) {
269 linkstat
= USB_EVENT_ID
;
271 linkstat
= USB_EVENT_VBUS
;
273 linkstat
= USB_EVENT_NONE
;
275 dev_dbg(twl
->dev
, "HW_CONDITIONS 0x%02x/%d; link %d\n",
276 status
, status
, linkstat
);
278 /* REVISIT this assumes host and peripheral controllers
279 * are registered, and that both are active...
282 spin_lock_irq(&twl
->lock
);
283 twl
->linkstat
= linkstat
;
284 if (linkstat
== USB_EVENT_ID
) {
285 twl
->otg
.default_a
= true;
286 twl
->otg
.state
= OTG_STATE_A_IDLE
;
288 twl
->otg
.default_a
= false;
289 twl
->otg
.state
= OTG_STATE_B_IDLE
;
291 spin_unlock_irq(&twl
->lock
);
296 static void twl4030_usb_set_mode(struct twl4030_usb
*twl
, int mode
)
298 twl
->usb_mode
= mode
;
301 case T2_USB_MODE_ULPI
:
302 twl4030_usb_clear_bits(twl
, ULPI_IFC_CTRL
,
303 ULPI_IFC_CTRL_CARKITMODE
);
304 twl4030_usb_set_bits(twl
, POWER_CTRL
, POWER_CTRL_OTG_ENAB
);
305 twl4030_usb_clear_bits(twl
, ULPI_FUNC_CTRL
,
306 ULPI_FUNC_CTRL_XCVRSEL_MASK
|
307 ULPI_FUNC_CTRL_OPMODE_MASK
);
310 /* FIXME: power on defaults */
313 dev_err(twl
->dev
, "unsupported T2 transceiver mode %d\n",
319 static void twl4030_i2c_access(struct twl4030_usb
*twl
, int on
)
321 unsigned long timeout
;
322 int val
= twl4030_usb_read(twl
, PHY_CLK_CTRL
);
326 /* enable DPLL to access PHY registers over I2C */
327 val
|= REQ_PHY_DPLL_CLK
;
328 WARN_ON(twl4030_usb_write_verify(twl
, PHY_CLK_CTRL
,
331 timeout
= jiffies
+ HZ
;
332 while (!(twl4030_usb_read(twl
, PHY_CLK_CTRL_STS
) &
334 && time_before(jiffies
, timeout
))
336 if (!(twl4030_usb_read(twl
, PHY_CLK_CTRL_STS
) &
338 dev_err(twl
->dev
, "Timeout setting T2 HSUSB "
341 /* let ULPI control the DPLL clock */
342 val
&= ~REQ_PHY_DPLL_CLK
;
343 WARN_ON(twl4030_usb_write_verify(twl
, PHY_CLK_CTRL
,
349 static void __twl4030_phy_power(struct twl4030_usb
*twl
, int on
)
351 u8 pwr
= twl4030_usb_read(twl
, PHY_PWR_CTRL
);
354 pwr
&= ~PHY_PWR_PHYPWD
;
356 pwr
|= PHY_PWR_PHYPWD
;
358 WARN_ON(twl4030_usb_write_verify(twl
, PHY_PWR_CTRL
, pwr
) < 0);
361 static void twl4030_phy_power(struct twl4030_usb
*twl
, int on
)
364 regulator_enable(twl
->usb3v1
);
365 regulator_enable(twl
->usb1v8
);
367 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
368 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
369 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
370 * SLEEP. We work around this by clearing the bit after usv3v1
371 * is re-activated. This ensures that VUSB3V1 is really active.
373 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0,
375 regulator_enable(twl
->usb1v5
);
376 __twl4030_phy_power(twl
, 1);
377 twl4030_usb_write(twl
, PHY_CLK_CTRL
,
378 twl4030_usb_read(twl
, PHY_CLK_CTRL
) |
379 (PHY_CLK_CTRL_CLOCKGATING_EN
|
380 PHY_CLK_CTRL_CLK32K_EN
));
382 __twl4030_phy_power(twl
, 0);
383 regulator_disable(twl
->usb1v5
);
384 regulator_disable(twl
->usb1v8
);
385 regulator_disable(twl
->usb3v1
);
389 static void twl4030_phy_suspend(struct twl4030_usb
*twl
, int controller_off
)
394 twl4030_phy_power(twl
, 0);
396 dev_dbg(twl
->dev
, "%s\n", __func__
);
399 static void __twl4030_phy_resume(struct twl4030_usb
*twl
)
401 twl4030_phy_power(twl
, 1);
402 twl4030_i2c_access(twl
, 1);
403 twl4030_usb_set_mode(twl
, twl
->usb_mode
);
404 if (twl
->usb_mode
== T2_USB_MODE_ULPI
)
405 twl4030_i2c_access(twl
, 0);
408 static void twl4030_phy_resume(struct twl4030_usb
*twl
)
412 __twl4030_phy_resume(twl
);
414 dev_dbg(twl
->dev
, "%s\n", __func__
);
417 static int twl4030_usb_ldo_init(struct twl4030_usb
*twl
)
419 /* Enable writing to power configuration registers */
420 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER
,
421 TWL4030_PM_MASTER_KEY_CFG1
,
422 TWL4030_PM_MASTER_PROTECT_KEY
);
424 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER
,
425 TWL4030_PM_MASTER_KEY_CFG2
,
426 TWL4030_PM_MASTER_PROTECT_KEY
);
428 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
429 /*twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
431 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
432 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0x14, VUSB_DEDICATED1
);
434 /* Initialize 3.1V regulator */
435 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0, VUSB3V1_DEV_GRP
);
437 twl
->usb3v1
= regulator_get(twl
->dev
, "usb3v1");
438 if (IS_ERR(twl
->usb3v1
))
441 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0, VUSB3V1_TYPE
);
443 /* Initialize 1.5V regulator */
444 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0, VUSB1V5_DEV_GRP
);
446 twl
->usb1v5
= regulator_get(twl
->dev
, "usb1v5");
447 if (IS_ERR(twl
->usb1v5
))
450 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0, VUSB1V5_TYPE
);
452 /* Initialize 1.8V regulator */
453 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0, VUSB1V8_DEV_GRP
);
455 twl
->usb1v8
= regulator_get(twl
->dev
, "usb1v8");
456 if (IS_ERR(twl
->usb1v8
))
459 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER
, 0, VUSB1V8_TYPE
);
461 /* disable access to power configuration registers */
462 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER
, 0,
463 TWL4030_PM_MASTER_PROTECT_KEY
);
468 regulator_put(twl
->usb1v5
);
471 regulator_put(twl
->usb3v1
);
476 static ssize_t
twl4030_usb_vbus_show(struct device
*dev
,
477 struct device_attribute
*attr
, char *buf
)
479 struct twl4030_usb
*twl
= dev_get_drvdata(dev
);
483 spin_lock_irqsave(&twl
->lock
, flags
);
484 ret
= sprintf(buf
, "%s\n",
485 (twl
->linkstat
== USB_EVENT_VBUS
) ? "on" : "off");
486 spin_unlock_irqrestore(&twl
->lock
, flags
);
490 static DEVICE_ATTR(vbus
, 0444, twl4030_usb_vbus_show
, NULL
);
492 static irqreturn_t
twl4030_usb_irq(int irq
, void *_twl
)
494 struct twl4030_usb
*twl
= _twl
;
497 status
= twl4030_usb_linkstat(twl
);
499 /* FIXME add a set_power() method so that B-devices can
500 * configure the charger appropriately. It's not always
501 * correct to consume VBUS power, and how much current to
502 * consume is a function of the USB configuration chosen
505 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
506 * its disconnect() sibling, when changing to/from the
507 * USB_LINK_VBUS state. musb_hdrc won't care until it
508 * starts to handle softconnect right.
510 if (status
== USB_EVENT_NONE
)
511 twl4030_phy_suspend(twl
, 0);
513 twl4030_phy_resume(twl
);
515 blocking_notifier_call_chain(&twl
->otg
.notifier
, status
,
518 sysfs_notify(&twl
->dev
->kobj
, NULL
, "vbus");
523 static void twl4030_usb_phy_init(struct twl4030_usb
*twl
)
527 status
= twl4030_usb_linkstat(twl
);
529 if (status
== USB_EVENT_NONE
) {
530 __twl4030_phy_power(twl
, 0);
533 __twl4030_phy_resume(twl
);
537 blocking_notifier_call_chain(&twl
->otg
.notifier
, status
,
540 sysfs_notify(&twl
->dev
->kobj
, NULL
, "vbus");
543 static int twl4030_set_suspend(struct otg_transceiver
*x
, int suspend
)
545 struct twl4030_usb
*twl
= xceiv_to_twl(x
);
548 twl4030_phy_suspend(twl
, 1);
550 twl4030_phy_resume(twl
);
555 static int twl4030_set_peripheral(struct otg_transceiver
*x
,
556 struct usb_gadget
*gadget
)
558 struct twl4030_usb
*twl
;
563 twl
= xceiv_to_twl(x
);
564 twl
->otg
.gadget
= gadget
;
566 twl
->otg
.state
= OTG_STATE_UNDEFINED
;
571 static int twl4030_set_host(struct otg_transceiver
*x
, struct usb_bus
*host
)
573 struct twl4030_usb
*twl
;
578 twl
= xceiv_to_twl(x
);
579 twl
->otg
.host
= host
;
581 twl
->otg
.state
= OTG_STATE_UNDEFINED
;
586 static int __devinit
twl4030_usb_probe(struct platform_device
*pdev
)
588 struct twl4030_usb_data
*pdata
= pdev
->dev
.platform_data
;
589 struct twl4030_usb
*twl
;
593 dev_dbg(&pdev
->dev
, "platform_data not available\n");
597 twl
= kzalloc(sizeof *twl
, GFP_KERNEL
);
601 twl
->dev
= &pdev
->dev
;
602 twl
->irq
= platform_get_irq(pdev
, 0);
603 twl
->otg
.dev
= twl
->dev
;
604 twl
->otg
.label
= "twl4030";
605 twl
->otg
.set_host
= twl4030_set_host
;
606 twl
->otg
.set_peripheral
= twl4030_set_peripheral
;
607 twl
->otg
.set_suspend
= twl4030_set_suspend
;
608 twl
->usb_mode
= pdata
->usb_mode
;
611 /* init spinlock for workqueue */
612 spin_lock_init(&twl
->lock
);
614 err
= twl4030_usb_ldo_init(twl
);
616 dev_err(&pdev
->dev
, "ldo init failed\n");
620 otg_set_transceiver(&twl
->otg
);
622 platform_set_drvdata(pdev
, twl
);
623 if (device_create_file(&pdev
->dev
, &dev_attr_vbus
))
624 dev_warn(&pdev
->dev
, "could not create sysfs file\n");
626 BLOCKING_INIT_NOTIFIER_HEAD(&twl
->otg
.notifier
);
628 /* Our job is to use irqs and status from the power module
629 * to keep the transceiver disabled when nothing's connected.
631 * FIXME we actually shouldn't start enabling it until the
632 * USB controller drivers have said they're ready, by calling
633 * set_host() and/or set_peripheral() ... OTG_capable boards
634 * need both handles, otherwise just one suffices.
636 twl
->irq_enabled
= true;
637 status
= request_threaded_irq(twl
->irq
, NULL
, twl4030_usb_irq
,
638 IRQF_TRIGGER_FALLING
| IRQF_TRIGGER_RISING
,
641 dev_dbg(&pdev
->dev
, "can't get IRQ %d, err %d\n",
647 /* Power down phy or make it work according to
648 * current link state.
650 twl4030_usb_phy_init(twl
);
652 dev_info(&pdev
->dev
, "Initialized TWL4030 USB module\n");
656 static int __exit
twl4030_usb_remove(struct platform_device
*pdev
)
658 struct twl4030_usb
*twl
= platform_get_drvdata(pdev
);
661 free_irq(twl
->irq
, twl
);
662 device_remove_file(twl
->dev
, &dev_attr_vbus
);
664 /* set transceiver mode to power on defaults */
665 twl4030_usb_set_mode(twl
, -1);
667 /* autogate 60MHz ULPI clock,
668 * clear dpll clock request for i2c access,
671 val
= twl4030_usb_read(twl
, PHY_CLK_CTRL
);
673 val
|= PHY_CLK_CTRL_CLOCKGATING_EN
;
674 val
&= ~(PHY_CLK_CTRL_CLK32K_EN
| REQ_PHY_DPLL_CLK
);
675 twl4030_usb_write(twl
, PHY_CLK_CTRL
, (u8
)val
);
678 /* disable complete OTG block */
679 twl4030_usb_clear_bits(twl
, POWER_CTRL
, POWER_CTRL_OTG_ENAB
);
681 twl4030_phy_power(twl
, 0);
682 regulator_put(twl
->usb1v5
);
683 regulator_put(twl
->usb1v8
);
684 regulator_put(twl
->usb3v1
);
691 static struct platform_driver twl4030_usb_driver
= {
692 .probe
= twl4030_usb_probe
,
693 .remove
= __exit_p(twl4030_usb_remove
),
695 .name
= "twl4030_usb",
696 .owner
= THIS_MODULE
,
700 static int __init
twl4030_usb_init(void)
702 return platform_driver_register(&twl4030_usb_driver
);
704 subsys_initcall(twl4030_usb_init
);
706 static void __exit
twl4030_usb_exit(void)
708 platform_driver_unregister(&twl4030_usb_driver
);
710 module_exit(twl4030_usb_exit
);
712 MODULE_ALIAS("platform:twl4030_usb");
713 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
714 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
715 MODULE_LICENSE("GPL");