2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
62 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
66 i915_gem_object_put_pages(struct drm_gem_object
*obj
);
68 static LIST_HEAD(shrink_list
);
69 static DEFINE_SPINLOCK(shrink_list_lock
);
71 /* some bookkeeping */
72 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
75 dev_priv
->mm
.object_count
++;
76 dev_priv
->mm
.object_memory
+= size
;
79 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
82 dev_priv
->mm
.object_count
--;
83 dev_priv
->mm
.object_memory
-= size
;
86 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 dev_priv
->mm
.gtt_count
++;
90 dev_priv
->mm
.gtt_memory
+= size
;
93 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
96 dev_priv
->mm
.gtt_count
--;
97 dev_priv
->mm
.gtt_memory
-= size
;
100 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
103 dev_priv
->mm
.pin_count
++;
104 dev_priv
->mm
.pin_memory
+= size
;
107 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
110 dev_priv
->mm
.pin_count
--;
111 dev_priv
->mm
.pin_memory
-= size
;
115 i915_gem_check_is_wedged(struct drm_device
*dev
)
117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
118 struct completion
*x
= &dev_priv
->error_completion
;
122 if (!atomic_read(&dev_priv
->mm
.wedged
))
125 ret
= wait_for_completion_interruptible(x
);
129 /* Success, we reset the GPU! */
130 if (!atomic_read(&dev_priv
->mm
.wedged
))
133 /* GPU is hung, bump the completion count to account for
134 * the token we just consumed so that we never hit zero and
135 * end up waiting upon a subsequent completion event that
138 spin_lock_irqsave(&x
->wait
.lock
, flags
);
140 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
144 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 ret
= i915_gem_check_is_wedged(dev
);
153 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
157 if (atomic_read(&dev_priv
->mm
.wedged
)) {
158 mutex_unlock(&dev
->struct_mutex
);
162 WARN_ON(i915_verify_lists(dev
));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
169 return obj_priv
->gtt_space
&&
171 obj_priv
->pin_count
== 0;
174 int i915_gem_do_init(struct drm_device
*dev
,
178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
181 (start
& (PAGE_SIZE
- 1)) != 0 ||
182 (end
& (PAGE_SIZE
- 1)) != 0) {
186 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
189 dev_priv
->mm
.gtt_total
= end
- start
;
195 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
196 struct drm_file
*file_priv
)
198 struct drm_i915_gem_init
*args
= data
;
201 mutex_lock(&dev
->struct_mutex
);
202 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
203 mutex_unlock(&dev
->struct_mutex
);
209 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
210 struct drm_file
*file_priv
)
212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 struct drm_i915_gem_get_aperture
*args
= data
;
215 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
218 mutex_lock(&dev
->struct_mutex
);
219 args
->aper_size
= dev_priv
->mm
.gtt_total
;
220 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
221 mutex_unlock(&dev
->struct_mutex
);
228 * Creates a new mm object and returns a handle to it.
231 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
232 struct drm_file
*file_priv
)
234 struct drm_i915_gem_create
*args
= data
;
235 struct drm_gem_object
*obj
;
239 args
->size
= roundup(args
->size
, PAGE_SIZE
);
241 /* Allocate the new object */
242 obj
= i915_gem_alloc_object(dev
, args
->size
);
246 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
248 drm_gem_object_release(obj
);
249 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
254 /* drop reference from allocate - handle holds it now */
255 drm_gem_object_unreference(obj
);
256 trace_i915_gem_object_create(obj
);
258 args
->handle
= handle
;
263 fast_shmem_read(struct page
**pages
,
264 loff_t page_base
, int page_offset
,
271 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
272 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
273 kunmap_atomic(vaddr
, KM_USER0
);
275 return unwritten
? -EFAULT
: 0;
278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
280 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
281 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
283 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
284 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
288 slow_shmem_copy(struct page
*dst_page
,
290 struct page
*src_page
,
294 char *dst_vaddr
, *src_vaddr
;
296 dst_vaddr
= kmap(dst_page
);
297 src_vaddr
= kmap(src_page
);
299 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
306 slow_shmem_bit17_copy(struct page
*gpu_page
,
308 struct page
*cpu_page
,
313 char *gpu_vaddr
, *cpu_vaddr
;
315 /* Use the unswizzled path if this page isn't affected. */
316 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
318 return slow_shmem_copy(cpu_page
, cpu_offset
,
319 gpu_page
, gpu_offset
, length
);
321 return slow_shmem_copy(gpu_page
, gpu_offset
,
322 cpu_page
, cpu_offset
, length
);
325 gpu_vaddr
= kmap(gpu_page
);
326 cpu_vaddr
= kmap(cpu_page
);
328 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
329 * XORing with the other bits (A9 for Y, A9 and A10 for X)
332 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
333 int this_length
= min(cacheline_end
- gpu_offset
, length
);
334 int swizzled_gpu_offset
= gpu_offset
^ 64;
337 memcpy(cpu_vaddr
+ cpu_offset
,
338 gpu_vaddr
+ swizzled_gpu_offset
,
341 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
342 cpu_vaddr
+ cpu_offset
,
345 cpu_offset
+= this_length
;
346 gpu_offset
+= this_length
;
347 length
-= this_length
;
355 * This is the fast shmem pread path, which attempts to copy_from_user directly
356 * from the backing pages of the object to the user's address space. On a
357 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
360 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
361 struct drm_i915_gem_pread
*args
,
362 struct drm_file
*file_priv
)
364 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
366 loff_t offset
, page_base
;
367 char __user
*user_data
;
368 int page_offset
, page_length
;
371 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
374 ret
= i915_mutex_lock_interruptible(dev
);
378 ret
= i915_gem_object_get_pages(obj
, 0);
382 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
387 obj_priv
= to_intel_bo(obj
);
388 offset
= args
->offset
;
391 /* Operation in this page
393 * page_base = page offset within aperture
394 * page_offset = offset within page
395 * page_length = bytes to copy for this page
397 page_base
= (offset
& ~(PAGE_SIZE
-1));
398 page_offset
= offset
& (PAGE_SIZE
-1);
399 page_length
= remain
;
400 if ((page_offset
+ remain
) > PAGE_SIZE
)
401 page_length
= PAGE_SIZE
- page_offset
;
403 ret
= fast_shmem_read(obj_priv
->pages
,
404 page_base
, page_offset
,
405 user_data
, page_length
);
409 remain
-= page_length
;
410 user_data
+= page_length
;
411 offset
+= page_length
;
415 i915_gem_object_put_pages(obj
);
417 mutex_unlock(&dev
->struct_mutex
);
423 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
427 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
429 /* If we've insufficient memory to map in the pages, attempt
430 * to make some space by throwing out some old buffers.
432 if (ret
== -ENOMEM
) {
433 struct drm_device
*dev
= obj
->dev
;
435 ret
= i915_gem_evict_something(dev
, obj
->size
,
436 i915_gem_get_gtt_alignment(obj
));
440 ret
= i915_gem_object_get_pages(obj
, 0);
447 * This is the fallback shmem pread path, which allocates temporary storage
448 * in kernel space to copy_to_user into outside of the struct_mutex, so we
449 * can copy out of the object's backing pages while holding the struct mutex
450 * and not take page faults.
453 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
454 struct drm_i915_gem_pread
*args
,
455 struct drm_file
*file_priv
)
457 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
458 struct mm_struct
*mm
= current
->mm
;
459 struct page
**user_pages
;
461 loff_t offset
, pinned_pages
, i
;
462 loff_t first_data_page
, last_data_page
, num_pages
;
463 int shmem_page_index
, shmem_page_offset
;
464 int data_page_index
, data_page_offset
;
467 uint64_t data_ptr
= args
->data_ptr
;
468 int do_bit17_swizzling
;
472 /* Pin the user pages containing the data. We can't fault while
473 * holding the struct mutex, yet we want to hold it while
474 * dereferencing the user data.
476 first_data_page
= data_ptr
/ PAGE_SIZE
;
477 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
478 num_pages
= last_data_page
- first_data_page
+ 1;
480 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
481 if (user_pages
== NULL
)
484 down_read(&mm
->mmap_sem
);
485 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
486 num_pages
, 1, 0, user_pages
, NULL
);
487 up_read(&mm
->mmap_sem
);
488 if (pinned_pages
< num_pages
) {
490 goto fail_put_user_pages
;
493 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
495 ret
= i915_mutex_lock_interruptible(dev
);
497 goto fail_put_user_pages
;
499 ret
= i915_gem_object_get_pages_or_evict(obj
);
503 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
508 obj_priv
= to_intel_bo(obj
);
509 offset
= args
->offset
;
512 /* Operation in this page
514 * shmem_page_index = page number within shmem file
515 * shmem_page_offset = offset within page in shmem file
516 * data_page_index = page number in get_user_pages return
517 * data_page_offset = offset with data_page_index page.
518 * page_length = bytes to copy for this page
520 shmem_page_index
= offset
/ PAGE_SIZE
;
521 shmem_page_offset
= offset
& ~PAGE_MASK
;
522 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
523 data_page_offset
= data_ptr
& ~PAGE_MASK
;
525 page_length
= remain
;
526 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
527 page_length
= PAGE_SIZE
- shmem_page_offset
;
528 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
529 page_length
= PAGE_SIZE
- data_page_offset
;
531 if (do_bit17_swizzling
) {
532 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
534 user_pages
[data_page_index
],
539 slow_shmem_copy(user_pages
[data_page_index
],
541 obj_priv
->pages
[shmem_page_index
],
546 remain
-= page_length
;
547 data_ptr
+= page_length
;
548 offset
+= page_length
;
552 i915_gem_object_put_pages(obj
);
554 mutex_unlock(&dev
->struct_mutex
);
556 for (i
= 0; i
< pinned_pages
; i
++) {
557 SetPageDirty(user_pages
[i
]);
558 page_cache_release(user_pages
[i
]);
560 drm_free_large(user_pages
);
566 * Reads data from the object referenced by handle.
568 * On error, the contents of *data are undefined.
571 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
572 struct drm_file
*file_priv
)
574 struct drm_i915_gem_pread
*args
= data
;
575 struct drm_gem_object
*obj
;
576 struct drm_i915_gem_object
*obj_priv
;
579 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
582 obj_priv
= to_intel_bo(obj
);
584 /* Bounds check source. */
585 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
593 if (!access_ok(VERIFY_WRITE
,
594 (char __user
*)(uintptr_t)args
->data_ptr
,
600 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
607 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
608 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
610 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
612 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
617 drm_gem_object_unreference_unlocked(obj
);
621 /* This is the fast write path which cannot handle
622 * page faults in the source data
626 fast_user_write(struct io_mapping
*mapping
,
627 loff_t page_base
, int page_offset
,
628 char __user
*user_data
,
632 unsigned long unwritten
;
634 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
635 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
637 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
641 /* Here's the write path which can sleep for
646 slow_kernel_write(struct io_mapping
*mapping
,
647 loff_t gtt_base
, int gtt_offset
,
648 struct page
*user_page
, int user_offset
,
651 char __iomem
*dst_vaddr
;
654 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
655 src_vaddr
= kmap(user_page
);
657 memcpy_toio(dst_vaddr
+ gtt_offset
,
658 src_vaddr
+ user_offset
,
662 io_mapping_unmap(dst_vaddr
);
666 fast_shmem_write(struct page
**pages
,
667 loff_t page_base
, int page_offset
,
674 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
675 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
676 kunmap_atomic(vaddr
, KM_USER0
);
682 * This is the fast pwrite path, where we copy the data directly from the
683 * user into the GTT, uncached.
686 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
687 struct drm_i915_gem_pwrite
*args
,
688 struct drm_file
*file_priv
)
690 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
691 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
693 loff_t offset
, page_base
;
694 char __user
*user_data
;
695 int page_offset
, page_length
;
697 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
700 obj_priv
= to_intel_bo(obj
);
701 offset
= obj_priv
->gtt_offset
+ args
->offset
;
704 /* Operation in this page
706 * page_base = page offset within aperture
707 * page_offset = offset within page
708 * page_length = bytes to copy for this page
710 page_base
= (offset
& ~(PAGE_SIZE
-1));
711 page_offset
= offset
& (PAGE_SIZE
-1);
712 page_length
= remain
;
713 if ((page_offset
+ remain
) > PAGE_SIZE
)
714 page_length
= PAGE_SIZE
- page_offset
;
716 /* If we get a fault while copying data, then (presumably) our
717 * source page isn't available. Return the error and we'll
718 * retry in the slow path.
720 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
721 page_offset
, user_data
, page_length
))
725 remain
-= page_length
;
726 user_data
+= page_length
;
727 offset
+= page_length
;
734 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
735 * the memory and maps it using kmap_atomic for copying.
737 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
738 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
741 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
742 struct drm_i915_gem_pwrite
*args
,
743 struct drm_file
*file_priv
)
745 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
746 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
748 loff_t gtt_page_base
, offset
;
749 loff_t first_data_page
, last_data_page
, num_pages
;
750 loff_t pinned_pages
, i
;
751 struct page
**user_pages
;
752 struct mm_struct
*mm
= current
->mm
;
753 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
755 uint64_t data_ptr
= args
->data_ptr
;
759 /* Pin the user pages containing the data. We can't fault while
760 * holding the struct mutex, and all of the pwrite implementations
761 * want to hold it while dereferencing the user data.
763 first_data_page
= data_ptr
/ PAGE_SIZE
;
764 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
765 num_pages
= last_data_page
- first_data_page
+ 1;
767 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
768 if (user_pages
== NULL
)
771 mutex_unlock(&dev
->struct_mutex
);
772 down_read(&mm
->mmap_sem
);
773 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
774 num_pages
, 0, 0, user_pages
, NULL
);
775 up_read(&mm
->mmap_sem
);
776 mutex_lock(&dev
->struct_mutex
);
777 if (pinned_pages
< num_pages
) {
779 goto out_unpin_pages
;
782 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
784 goto out_unpin_pages
;
786 obj_priv
= to_intel_bo(obj
);
787 offset
= obj_priv
->gtt_offset
+ args
->offset
;
790 /* Operation in this page
792 * gtt_page_base = page offset within aperture
793 * gtt_page_offset = offset within page in aperture
794 * data_page_index = page number in get_user_pages return
795 * data_page_offset = offset with data_page_index page.
796 * page_length = bytes to copy for this page
798 gtt_page_base
= offset
& PAGE_MASK
;
799 gtt_page_offset
= offset
& ~PAGE_MASK
;
800 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
801 data_page_offset
= data_ptr
& ~PAGE_MASK
;
803 page_length
= remain
;
804 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
805 page_length
= PAGE_SIZE
- gtt_page_offset
;
806 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
807 page_length
= PAGE_SIZE
- data_page_offset
;
809 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
810 gtt_page_base
, gtt_page_offset
,
811 user_pages
[data_page_index
],
815 remain
-= page_length
;
816 offset
+= page_length
;
817 data_ptr
+= page_length
;
821 for (i
= 0; i
< pinned_pages
; i
++)
822 page_cache_release(user_pages
[i
]);
823 drm_free_large(user_pages
);
829 * This is the fast shmem pwrite path, which attempts to directly
830 * copy_from_user into the kmapped pages backing the object.
833 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
834 struct drm_i915_gem_pwrite
*args
,
835 struct drm_file
*file_priv
)
837 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
839 loff_t offset
, page_base
;
840 char __user
*user_data
;
841 int page_offset
, page_length
;
843 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
846 obj_priv
= to_intel_bo(obj
);
847 offset
= args
->offset
;
851 /* Operation in this page
853 * page_base = page offset within aperture
854 * page_offset = offset within page
855 * page_length = bytes to copy for this page
857 page_base
= (offset
& ~(PAGE_SIZE
-1));
858 page_offset
= offset
& (PAGE_SIZE
-1);
859 page_length
= remain
;
860 if ((page_offset
+ remain
) > PAGE_SIZE
)
861 page_length
= PAGE_SIZE
- page_offset
;
863 if (fast_shmem_write(obj_priv
->pages
,
864 page_base
, page_offset
,
865 user_data
, page_length
))
868 remain
-= page_length
;
869 user_data
+= page_length
;
870 offset
+= page_length
;
877 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
878 * the memory and maps it using kmap_atomic for copying.
880 * This avoids taking mmap_sem for faulting on the user's address while the
881 * struct_mutex is held.
884 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
885 struct drm_i915_gem_pwrite
*args
,
886 struct drm_file
*file_priv
)
888 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
889 struct mm_struct
*mm
= current
->mm
;
890 struct page
**user_pages
;
892 loff_t offset
, pinned_pages
, i
;
893 loff_t first_data_page
, last_data_page
, num_pages
;
894 int shmem_page_index
, shmem_page_offset
;
895 int data_page_index
, data_page_offset
;
898 uint64_t data_ptr
= args
->data_ptr
;
899 int do_bit17_swizzling
;
903 /* Pin the user pages containing the data. We can't fault while
904 * holding the struct mutex, and all of the pwrite implementations
905 * want to hold it while dereferencing the user data.
907 first_data_page
= data_ptr
/ PAGE_SIZE
;
908 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
909 num_pages
= last_data_page
- first_data_page
+ 1;
911 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
912 if (user_pages
== NULL
)
915 mutex_unlock(&dev
->struct_mutex
);
916 down_read(&mm
->mmap_sem
);
917 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
918 num_pages
, 0, 0, user_pages
, NULL
);
919 up_read(&mm
->mmap_sem
);
920 mutex_lock(&dev
->struct_mutex
);
921 if (pinned_pages
< num_pages
) {
926 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
930 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
932 obj_priv
= to_intel_bo(obj
);
933 offset
= args
->offset
;
937 /* Operation in this page
939 * shmem_page_index = page number within shmem file
940 * shmem_page_offset = offset within page in shmem file
941 * data_page_index = page number in get_user_pages return
942 * data_page_offset = offset with data_page_index page.
943 * page_length = bytes to copy for this page
945 shmem_page_index
= offset
/ PAGE_SIZE
;
946 shmem_page_offset
= offset
& ~PAGE_MASK
;
947 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
948 data_page_offset
= data_ptr
& ~PAGE_MASK
;
950 page_length
= remain
;
951 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
952 page_length
= PAGE_SIZE
- shmem_page_offset
;
953 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
954 page_length
= PAGE_SIZE
- data_page_offset
;
956 if (do_bit17_swizzling
) {
957 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
959 user_pages
[data_page_index
],
964 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
966 user_pages
[data_page_index
],
971 remain
-= page_length
;
972 data_ptr
+= page_length
;
973 offset
+= page_length
;
977 for (i
= 0; i
< pinned_pages
; i
++)
978 page_cache_release(user_pages
[i
]);
979 drm_free_large(user_pages
);
985 * Writes data to the object referenced by handle.
987 * On error, the contents of the buffer that were to be modified are undefined.
990 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
991 struct drm_file
*file
)
993 struct drm_i915_gem_pwrite
*args
= data
;
994 struct drm_gem_object
*obj
;
995 struct drm_i915_gem_object
*obj_priv
;
998 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1001 obj_priv
= to_intel_bo(obj
);
1003 ret
= i915_mutex_lock_interruptible(dev
);
1005 drm_gem_object_unreference_unlocked(obj
);
1009 /* Bounds check destination. */
1010 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1015 if (args
->size
== 0)
1018 if (!access_ok(VERIFY_READ
,
1019 (char __user
*)(uintptr_t)args
->data_ptr
,
1025 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1032 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1033 * it would end up going through the fenced access, and we'll get
1034 * different detiling behavior between reading and writing.
1035 * pread/pwrite currently are reading and writing from the CPU
1036 * perspective, requiring manual detiling by the client.
1038 if (obj_priv
->phys_obj
)
1039 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1040 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1041 obj_priv
->gtt_space
&&
1042 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1043 ret
= i915_gem_object_pin(obj
, 0);
1047 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1051 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1053 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1056 i915_gem_object_unpin(obj
);
1058 ret
= i915_gem_object_get_pages_or_evict(obj
);
1062 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1067 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1068 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1070 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1073 i915_gem_object_put_pages(obj
);
1077 drm_gem_object_unreference(obj
);
1078 mutex_unlock(&dev
->struct_mutex
);
1083 * Called when user space prepares to use an object with the CPU, either
1084 * through the mmap ioctl's mapping or a GTT mapping.
1087 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1088 struct drm_file
*file_priv
)
1090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1091 struct drm_i915_gem_set_domain
*args
= data
;
1092 struct drm_gem_object
*obj
;
1093 struct drm_i915_gem_object
*obj_priv
;
1094 uint32_t read_domains
= args
->read_domains
;
1095 uint32_t write_domain
= args
->write_domain
;
1098 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1101 /* Only handle setting domains to types used by the CPU. */
1102 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1105 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1108 /* Having something in the write domain implies it's in the read
1109 * domain, and only that read domain. Enforce that in the request.
1111 if (write_domain
!= 0 && read_domains
!= write_domain
)
1114 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1117 obj_priv
= to_intel_bo(obj
);
1119 ret
= i915_mutex_lock_interruptible(dev
);
1121 drm_gem_object_unreference_unlocked(obj
);
1125 intel_mark_busy(dev
, obj
);
1127 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1128 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1130 /* Update the LRU on the fence for the CPU access that's
1133 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1134 struct drm_i915_fence_reg
*reg
=
1135 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1136 list_move_tail(®
->lru_list
,
1137 &dev_priv
->mm
.fence_list
);
1140 /* Silently promote "you're not bound, there was nothing to do"
1141 * to success, since the client was just asking us to
1142 * make sure everything was done.
1147 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1150 /* Maintain LRU order of "inactive" objects */
1151 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1152 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1154 drm_gem_object_unreference(obj
);
1155 mutex_unlock(&dev
->struct_mutex
);
1160 * Called when user space has done writes to this buffer
1163 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1164 struct drm_file
*file_priv
)
1166 struct drm_i915_gem_sw_finish
*args
= data
;
1167 struct drm_gem_object
*obj
;
1170 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1173 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1177 ret
= i915_mutex_lock_interruptible(dev
);
1179 drm_gem_object_unreference_unlocked(obj
);
1183 /* Pinned buffers may be scanout, so flush the cache */
1184 if (to_intel_bo(obj
)->pin_count
)
1185 i915_gem_object_flush_cpu_write_domain(obj
);
1187 drm_gem_object_unreference(obj
);
1188 mutex_unlock(&dev
->struct_mutex
);
1193 * Maps the contents of an object, returning the address it is mapped
1196 * While the mapping holds a reference on the contents of the object, it doesn't
1197 * imply a ref on the object itself.
1200 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1201 struct drm_file
*file_priv
)
1203 struct drm_i915_gem_mmap
*args
= data
;
1204 struct drm_gem_object
*obj
;
1208 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1211 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1215 offset
= args
->offset
;
1217 down_write(¤t
->mm
->mmap_sem
);
1218 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1219 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1221 up_write(¤t
->mm
->mmap_sem
);
1222 drm_gem_object_unreference_unlocked(obj
);
1223 if (IS_ERR((void *)addr
))
1226 args
->addr_ptr
= (uint64_t) addr
;
1232 * i915_gem_fault - fault a page into the GTT
1233 * vma: VMA in question
1236 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1237 * from userspace. The fault handler takes care of binding the object to
1238 * the GTT (if needed), allocating and programming a fence register (again,
1239 * only if needed based on whether the old reg is still valid or the object
1240 * is tiled) and inserting a new PTE into the faulting process.
1242 * Note that the faulting process may involve evicting existing objects
1243 * from the GTT and/or fence registers to make room. So performance may
1244 * suffer if the GTT working set is large or there are few fence registers
1247 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1249 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1250 struct drm_device
*dev
= obj
->dev
;
1251 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1252 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1253 pgoff_t page_offset
;
1256 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1258 /* We don't use vmf->pgoff since that has the fake offset */
1259 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1262 /* Now bind it into the GTT if needed */
1263 mutex_lock(&dev
->struct_mutex
);
1264 if (!obj_priv
->gtt_space
) {
1265 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1269 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1274 /* Need a new fence register? */
1275 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1276 ret
= i915_gem_object_get_fence_reg(obj
, true);
1281 if (i915_gem_object_is_inactive(obj_priv
))
1282 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1284 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1287 /* Finally, remap it using the new GTT offset */
1288 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1290 mutex_unlock(&dev
->struct_mutex
);
1295 return VM_FAULT_NOPAGE
;
1298 return VM_FAULT_OOM
;
1300 return VM_FAULT_SIGBUS
;
1305 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1306 * @obj: obj in question
1308 * GEM memory mapping works by handing back to userspace a fake mmap offset
1309 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1310 * up the object based on the offset and sets up the various memory mapping
1313 * This routine allocates and attaches a fake offset for @obj.
1316 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1318 struct drm_device
*dev
= obj
->dev
;
1319 struct drm_gem_mm
*mm
= dev
->mm_private
;
1320 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1321 struct drm_map_list
*list
;
1322 struct drm_local_map
*map
;
1325 /* Set the object up for mmap'ing */
1326 list
= &obj
->map_list
;
1327 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1332 map
->type
= _DRM_GEM
;
1333 map
->size
= obj
->size
;
1336 /* Get a DRM GEM mmap offset allocated... */
1337 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1338 obj
->size
/ PAGE_SIZE
, 0, 0);
1339 if (!list
->file_offset_node
) {
1340 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1345 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1346 obj
->size
/ PAGE_SIZE
, 0);
1347 if (!list
->file_offset_node
) {
1352 list
->hash
.key
= list
->file_offset_node
->start
;
1353 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1355 DRM_ERROR("failed to add to map hash\n");
1359 /* By now we should be all set, any drm_mmap request on the offset
1360 * below will get to our mmap & fault handler */
1361 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1366 drm_mm_put_block(list
->file_offset_node
);
1374 * i915_gem_release_mmap - remove physical page mappings
1375 * @obj: obj in question
1377 * Preserve the reservation of the mmapping with the DRM core code, but
1378 * relinquish ownership of the pages back to the system.
1380 * It is vital that we remove the page mapping if we have mapped a tiled
1381 * object through the GTT and then lose the fence register due to
1382 * resource pressure. Similarly if the object has been moved out of the
1383 * aperture, than pages mapped into userspace must be revoked. Removing the
1384 * mapping will then trigger a page fault on the next user access, allowing
1385 * fixup by i915_gem_fault().
1388 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1390 struct drm_device
*dev
= obj
->dev
;
1391 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1393 if (dev
->dev_mapping
)
1394 unmap_mapping_range(dev
->dev_mapping
,
1395 obj_priv
->mmap_offset
, obj
->size
, 1);
1399 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1401 struct drm_device
*dev
= obj
->dev
;
1402 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1403 struct drm_gem_mm
*mm
= dev
->mm_private
;
1404 struct drm_map_list
*list
;
1406 list
= &obj
->map_list
;
1407 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1409 if (list
->file_offset_node
) {
1410 drm_mm_put_block(list
->file_offset_node
);
1411 list
->file_offset_node
= NULL
;
1419 obj_priv
->mmap_offset
= 0;
1423 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1424 * @obj: object to check
1426 * Return the required GTT alignment for an object, taking into account
1427 * potential fence register mapping if needed.
1430 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1432 struct drm_device
*dev
= obj
->dev
;
1433 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1437 * Minimum alignment is 4k (GTT page size), but might be greater
1438 * if a fence register is needed for the object.
1440 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1444 * Previous chips need to be aligned to the size of the smallest
1445 * fence register that can contain the object.
1447 if (INTEL_INFO(dev
)->gen
== 3)
1452 for (i
= start
; i
< obj
->size
; i
<<= 1)
1459 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1461 * @data: GTT mapping ioctl data
1462 * @file_priv: GEM object info
1464 * Simply returns the fake offset to userspace so it can mmap it.
1465 * The mmap call will end up in drm_gem_mmap(), which will set things
1466 * up so we can get faults in the handler above.
1468 * The fault handler will take care of binding the object into the GTT
1469 * (since it may have been evicted to make room for something), allocating
1470 * a fence register, and mapping the appropriate aperture address into
1474 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1475 struct drm_file
*file_priv
)
1477 struct drm_i915_gem_mmap_gtt
*args
= data
;
1478 struct drm_gem_object
*obj
;
1479 struct drm_i915_gem_object
*obj_priv
;
1482 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1485 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1489 ret
= i915_mutex_lock_interruptible(dev
);
1491 drm_gem_object_unreference_unlocked(obj
);
1495 obj_priv
= to_intel_bo(obj
);
1497 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1498 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1499 drm_gem_object_unreference(obj
);
1500 mutex_unlock(&dev
->struct_mutex
);
1505 if (!obj_priv
->mmap_offset
) {
1506 ret
= i915_gem_create_mmap_offset(obj
);
1508 drm_gem_object_unreference(obj
);
1509 mutex_unlock(&dev
->struct_mutex
);
1514 args
->offset
= obj_priv
->mmap_offset
;
1517 * Pull it into the GTT so that we have a page list (makes the
1518 * initial fault faster and any subsequent flushing possible).
1520 if (!obj_priv
->agp_mem
) {
1521 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1523 drm_gem_object_unreference(obj
);
1524 mutex_unlock(&dev
->struct_mutex
);
1529 drm_gem_object_unreference(obj
);
1530 mutex_unlock(&dev
->struct_mutex
);
1536 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1538 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1539 int page_count
= obj
->size
/ PAGE_SIZE
;
1542 BUG_ON(obj_priv
->pages_refcount
== 0);
1543 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1545 if (--obj_priv
->pages_refcount
!= 0)
1548 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1549 i915_gem_object_save_bit_17_swizzle(obj
);
1551 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1552 obj_priv
->dirty
= 0;
1554 for (i
= 0; i
< page_count
; i
++) {
1555 if (obj_priv
->dirty
)
1556 set_page_dirty(obj_priv
->pages
[i
]);
1558 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1559 mark_page_accessed(obj_priv
->pages
[i
]);
1561 page_cache_release(obj_priv
->pages
[i
]);
1563 obj_priv
->dirty
= 0;
1565 drm_free_large(obj_priv
->pages
);
1566 obj_priv
->pages
= NULL
;
1570 i915_gem_next_request_seqno(struct drm_device
*dev
,
1571 struct intel_ring_buffer
*ring
)
1573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1575 ring
->outstanding_lazy_request
= true;
1576 return dev_priv
->next_seqno
;
1580 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1581 struct intel_ring_buffer
*ring
)
1583 struct drm_device
*dev
= obj
->dev
;
1584 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1585 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1587 BUG_ON(ring
== NULL
);
1588 obj_priv
->ring
= ring
;
1590 /* Add a reference if we're newly entering the active list. */
1591 if (!obj_priv
->active
) {
1592 drm_gem_object_reference(obj
);
1593 obj_priv
->active
= 1;
1596 /* Move from whatever list we were on to the tail of execution. */
1597 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1598 obj_priv
->last_rendering_seqno
= seqno
;
1602 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1604 struct drm_device
*dev
= obj
->dev
;
1605 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1606 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1608 BUG_ON(!obj_priv
->active
);
1609 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1610 obj_priv
->last_rendering_seqno
= 0;
1613 /* Immediately discard the backing storage */
1615 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1617 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1618 struct inode
*inode
;
1620 /* Our goal here is to return as much of the memory as
1621 * is possible back to the system as we are called from OOM.
1622 * To do this we must instruct the shmfs to drop all of its
1623 * backing pages, *now*. Here we mirror the actions taken
1624 * when by shmem_delete_inode() to release the backing store.
1626 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1627 truncate_inode_pages(inode
->i_mapping
, 0);
1628 if (inode
->i_op
->truncate_range
)
1629 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1631 obj_priv
->madv
= __I915_MADV_PURGED
;
1635 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1637 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1641 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1643 struct drm_device
*dev
= obj
->dev
;
1644 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1645 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1647 if (obj_priv
->pin_count
!= 0)
1648 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.pinned_list
);
1650 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1652 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1654 obj_priv
->last_rendering_seqno
= 0;
1655 obj_priv
->ring
= NULL
;
1656 if (obj_priv
->active
) {
1657 obj_priv
->active
= 0;
1658 drm_gem_object_unreference(obj
);
1660 WARN_ON(i915_verify_lists(dev
));
1664 i915_gem_process_flushing_list(struct drm_device
*dev
,
1665 uint32_t flush_domains
,
1666 struct intel_ring_buffer
*ring
)
1668 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1669 struct drm_i915_gem_object
*obj_priv
, *next
;
1671 list_for_each_entry_safe(obj_priv
, next
,
1672 &dev_priv
->mm
.gpu_write_list
,
1674 struct drm_gem_object
*obj
= &obj_priv
->base
;
1676 if (obj
->write_domain
& flush_domains
&&
1677 obj_priv
->ring
== ring
) {
1678 uint32_t old_write_domain
= obj
->write_domain
;
1680 obj
->write_domain
= 0;
1681 list_del_init(&obj_priv
->gpu_write_list
);
1682 i915_gem_object_move_to_active(obj
, ring
);
1684 /* update the fence lru list */
1685 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1686 struct drm_i915_fence_reg
*reg
=
1687 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1688 list_move_tail(®
->lru_list
,
1689 &dev_priv
->mm
.fence_list
);
1692 trace_i915_gem_object_change_domain(obj
,
1700 i915_add_request(struct drm_device
*dev
,
1701 struct drm_file
*file
,
1702 struct drm_i915_gem_request
*request
,
1703 struct intel_ring_buffer
*ring
)
1705 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1706 struct drm_i915_file_private
*file_priv
= NULL
;
1711 file_priv
= file
->driver_priv
;
1713 if (request
== NULL
) {
1714 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1715 if (request
== NULL
)
1719 seqno
= ring
->add_request(dev
, ring
, 0);
1720 ring
->outstanding_lazy_request
= false;
1722 request
->seqno
= seqno
;
1723 request
->ring
= ring
;
1724 request
->emitted_jiffies
= jiffies
;
1725 was_empty
= list_empty(&ring
->request_list
);
1726 list_add_tail(&request
->list
, &ring
->request_list
);
1729 spin_lock(&file_priv
->mm
.lock
);
1730 request
->file_priv
= file_priv
;
1731 list_add_tail(&request
->client_list
,
1732 &file_priv
->mm
.request_list
);
1733 spin_unlock(&file_priv
->mm
.lock
);
1736 if (!dev_priv
->mm
.suspended
) {
1737 mod_timer(&dev_priv
->hangcheck_timer
,
1738 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1740 queue_delayed_work(dev_priv
->wq
,
1741 &dev_priv
->mm
.retire_work
, HZ
);
1747 * Command execution barrier
1749 * Ensures that all commands in the ring are finished
1750 * before signalling the CPU
1753 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1755 uint32_t flush_domains
= 0;
1757 /* The sampler always gets flushed on i965 (sigh) */
1758 if (INTEL_INFO(dev
)->gen
>= 4)
1759 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1761 ring
->flush(dev
, ring
,
1762 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1766 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1768 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1773 spin_lock(&file_priv
->mm
.lock
);
1774 list_del(&request
->client_list
);
1775 request
->file_priv
= NULL
;
1776 spin_unlock(&file_priv
->mm
.lock
);
1779 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1780 struct intel_ring_buffer
*ring
)
1782 while (!list_empty(&ring
->request_list
)) {
1783 struct drm_i915_gem_request
*request
;
1785 request
= list_first_entry(&ring
->request_list
,
1786 struct drm_i915_gem_request
,
1789 list_del(&request
->list
);
1790 i915_gem_request_remove_from_client(request
);
1794 while (!list_empty(&ring
->active_list
)) {
1795 struct drm_i915_gem_object
*obj_priv
;
1797 obj_priv
= list_first_entry(&ring
->active_list
,
1798 struct drm_i915_gem_object
,
1801 obj_priv
->base
.write_domain
= 0;
1802 list_del_init(&obj_priv
->gpu_write_list
);
1803 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1807 void i915_gem_reset(struct drm_device
*dev
)
1809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1810 struct drm_i915_gem_object
*obj_priv
;
1813 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1815 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1817 /* Remove anything from the flushing lists. The GPU cache is likely
1818 * to be lost on reset along with the data, so simply move the
1819 * lost bo to the inactive list.
1821 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1822 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1823 struct drm_i915_gem_object
,
1826 obj_priv
->base
.write_domain
= 0;
1827 list_del_init(&obj_priv
->gpu_write_list
);
1828 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1831 /* Move everything out of the GPU domains to ensure we do any
1832 * necessary invalidation upon reuse.
1834 list_for_each_entry(obj_priv
,
1835 &dev_priv
->mm
.inactive_list
,
1838 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1841 /* The fence registers are invalidated so clear them out */
1842 for (i
= 0; i
< 16; i
++) {
1843 struct drm_i915_fence_reg
*reg
;
1845 reg
= &dev_priv
->fence_regs
[i
];
1849 i915_gem_clear_fence_reg(reg
->obj
);
1854 * This function clears the request list as sequence numbers are passed.
1857 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1858 struct intel_ring_buffer
*ring
)
1860 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1863 if (!ring
->status_page
.page_addr
||
1864 list_empty(&ring
->request_list
))
1867 WARN_ON(i915_verify_lists(dev
));
1869 seqno
= ring
->get_seqno(dev
, ring
);
1870 while (!list_empty(&ring
->request_list
)) {
1871 struct drm_i915_gem_request
*request
;
1873 request
= list_first_entry(&ring
->request_list
,
1874 struct drm_i915_gem_request
,
1877 if (!i915_seqno_passed(seqno
, request
->seqno
))
1880 trace_i915_gem_request_retire(dev
, request
->seqno
);
1882 list_del(&request
->list
);
1883 i915_gem_request_remove_from_client(request
);
1887 /* Move any buffers on the active list that are no longer referenced
1888 * by the ringbuffer to the flushing/inactive lists as appropriate.
1890 while (!list_empty(&ring
->active_list
)) {
1891 struct drm_gem_object
*obj
;
1892 struct drm_i915_gem_object
*obj_priv
;
1894 obj_priv
= list_first_entry(&ring
->active_list
,
1895 struct drm_i915_gem_object
,
1898 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1901 obj
= &obj_priv
->base
;
1902 if (obj
->write_domain
!= 0)
1903 i915_gem_object_move_to_flushing(obj
);
1905 i915_gem_object_move_to_inactive(obj
);
1908 if (unlikely (dev_priv
->trace_irq_seqno
&&
1909 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1910 ring
->user_irq_put(dev
, ring
);
1911 dev_priv
->trace_irq_seqno
= 0;
1914 WARN_ON(i915_verify_lists(dev
));
1918 i915_gem_retire_requests(struct drm_device
*dev
)
1920 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1922 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1923 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1925 /* We must be careful that during unbind() we do not
1926 * accidentally infinitely recurse into retire requests.
1928 * retire -> free -> unbind -> wait -> retire_ring
1930 list_for_each_entry_safe(obj_priv
, tmp
,
1931 &dev_priv
->mm
.deferred_free_list
,
1933 i915_gem_free_object_tail(&obj_priv
->base
);
1936 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1938 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1942 i915_gem_retire_work_handler(struct work_struct
*work
)
1944 drm_i915_private_t
*dev_priv
;
1945 struct drm_device
*dev
;
1947 dev_priv
= container_of(work
, drm_i915_private_t
,
1948 mm
.retire_work
.work
);
1949 dev
= dev_priv
->dev
;
1951 /* Come back later if the device is busy... */
1952 if (!mutex_trylock(&dev
->struct_mutex
)) {
1953 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1957 i915_gem_retire_requests(dev
);
1959 if (!dev_priv
->mm
.suspended
&&
1960 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1962 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1963 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1964 mutex_unlock(&dev
->struct_mutex
);
1968 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1969 bool interruptible
, struct intel_ring_buffer
*ring
)
1971 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1977 if (atomic_read(&dev_priv
->mm
.wedged
))
1980 if (ring
->outstanding_lazy_request
) {
1981 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
1985 BUG_ON(seqno
== dev_priv
->next_seqno
);
1987 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
1988 if (HAS_PCH_SPLIT(dev
))
1989 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1991 ier
= I915_READ(IER
);
1993 DRM_ERROR("something (likely vbetool) disabled "
1994 "interrupts, re-enabling\n");
1995 i915_driver_irq_preinstall(dev
);
1996 i915_driver_irq_postinstall(dev
);
1999 trace_i915_gem_request_wait_begin(dev
, seqno
);
2001 ring
->waiting_gem_seqno
= seqno
;
2002 ring
->user_irq_get(dev
, ring
);
2004 ret
= wait_event_interruptible(ring
->irq_queue
,
2006 ring
->get_seqno(dev
, ring
), seqno
)
2007 || atomic_read(&dev_priv
->mm
.wedged
));
2009 wait_event(ring
->irq_queue
,
2011 ring
->get_seqno(dev
, ring
), seqno
)
2012 || atomic_read(&dev_priv
->mm
.wedged
));
2014 ring
->user_irq_put(dev
, ring
);
2015 ring
->waiting_gem_seqno
= 0;
2017 trace_i915_gem_request_wait_end(dev
, seqno
);
2019 if (atomic_read(&dev_priv
->mm
.wedged
))
2022 if (ret
&& ret
!= -ERESTARTSYS
)
2023 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2024 __func__
, ret
, seqno
, ring
->get_seqno(dev
, ring
),
2025 dev_priv
->next_seqno
);
2027 /* Directly dispatch request retiring. While we have the work queue
2028 * to handle this, the waiter on a request often wants an associated
2029 * buffer to have made it to the inactive list, and we would need
2030 * a separate wait queue to handle that.
2033 i915_gem_retire_requests_ring(dev
, ring
);
2039 * Waits for a sequence number to be signaled, and cleans up the
2040 * request and object lists appropriately for that event.
2043 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2044 struct intel_ring_buffer
*ring
)
2046 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2050 i915_gem_flush_ring(struct drm_device
*dev
,
2051 struct drm_file
*file_priv
,
2052 struct intel_ring_buffer
*ring
,
2053 uint32_t invalidate_domains
,
2054 uint32_t flush_domains
)
2056 ring
->flush(dev
, ring
, invalidate_domains
, flush_domains
);
2057 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2061 i915_gem_flush(struct drm_device
*dev
,
2062 struct drm_file
*file_priv
,
2063 uint32_t invalidate_domains
,
2064 uint32_t flush_domains
,
2065 uint32_t flush_rings
)
2067 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2069 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2070 drm_agp_chipset_flush(dev
);
2072 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2073 if (flush_rings
& RING_RENDER
)
2074 i915_gem_flush_ring(dev
, file_priv
,
2075 &dev_priv
->render_ring
,
2076 invalidate_domains
, flush_domains
);
2077 if (flush_rings
& RING_BSD
)
2078 i915_gem_flush_ring(dev
, file_priv
,
2079 &dev_priv
->bsd_ring
,
2080 invalidate_domains
, flush_domains
);
2085 * Ensures that all rendering to the object has completed and the object is
2086 * safe to unbind from the GTT or access from the CPU.
2089 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2092 struct drm_device
*dev
= obj
->dev
;
2093 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2096 /* This function only exists to support waiting for existing rendering,
2097 * not for emitting required flushes.
2099 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2101 /* If there is rendering queued on the buffer being evicted, wait for
2104 if (obj_priv
->active
) {
2105 ret
= i915_do_wait_request(dev
,
2106 obj_priv
->last_rendering_seqno
,
2117 * Unbinds an object from the GTT aperture.
2120 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2122 struct drm_device
*dev
= obj
->dev
;
2123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2124 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2127 if (obj_priv
->gtt_space
== NULL
)
2130 if (obj_priv
->pin_count
!= 0) {
2131 DRM_ERROR("Attempting to unbind pinned buffer\n");
2135 /* blow away mappings if mapped through GTT */
2136 i915_gem_release_mmap(obj
);
2138 /* Move the object to the CPU domain to ensure that
2139 * any possible CPU writes while it's not in the GTT
2140 * are flushed when we go to remap it. This will
2141 * also ensure that all pending GPU writes are finished
2144 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2145 if (ret
== -ERESTARTSYS
)
2147 /* Continue on if we fail due to EIO, the GPU is hung so we
2148 * should be safe and we need to cleanup or else we might
2149 * cause memory corruption through use-after-free.
2152 i915_gem_clflush_object(obj
);
2153 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2156 /* release the fence reg _after_ flushing */
2157 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2158 i915_gem_clear_fence_reg(obj
);
2160 drm_unbind_agp(obj_priv
->agp_mem
);
2161 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2163 i915_gem_object_put_pages(obj
);
2164 BUG_ON(obj_priv
->pages_refcount
);
2166 i915_gem_info_remove_gtt(dev_priv
, obj
->size
);
2167 list_del_init(&obj_priv
->list
);
2169 drm_mm_put_block(obj_priv
->gtt_space
);
2170 obj_priv
->gtt_space
= NULL
;
2172 if (i915_gem_object_is_purgeable(obj_priv
))
2173 i915_gem_object_truncate(obj
);
2175 trace_i915_gem_object_unbind(obj
);
2180 static int i915_ring_idle(struct drm_device
*dev
,
2181 struct intel_ring_buffer
*ring
)
2183 i915_gem_flush_ring(dev
, NULL
, ring
,
2184 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2185 return i915_wait_request(dev
,
2186 i915_gem_next_request_seqno(dev
, ring
),
2191 i915_gpu_idle(struct drm_device
*dev
)
2193 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2197 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2198 list_empty(&dev_priv
->render_ring
.active_list
) &&
2200 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2204 /* Flush everything onto the inactive list. */
2205 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2210 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2219 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2222 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2224 struct address_space
*mapping
;
2225 struct inode
*inode
;
2228 BUG_ON(obj_priv
->pages_refcount
2229 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2231 if (obj_priv
->pages_refcount
++ != 0)
2234 /* Get the list of pages out of our struct file. They'll be pinned
2235 * at this point until we release them.
2237 page_count
= obj
->size
/ PAGE_SIZE
;
2238 BUG_ON(obj_priv
->pages
!= NULL
);
2239 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2240 if (obj_priv
->pages
== NULL
) {
2241 obj_priv
->pages_refcount
--;
2245 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2246 mapping
= inode
->i_mapping
;
2247 for (i
= 0; i
< page_count
; i
++) {
2248 page
= read_cache_page_gfp(mapping
, i
,
2256 obj_priv
->pages
[i
] = page
;
2259 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2260 i915_gem_object_do_bit_17_swizzle(obj
);
2266 page_cache_release(obj_priv
->pages
[i
]);
2268 drm_free_large(obj_priv
->pages
);
2269 obj_priv
->pages
= NULL
;
2270 obj_priv
->pages_refcount
--;
2271 return PTR_ERR(page
);
2274 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2276 struct drm_gem_object
*obj
= reg
->obj
;
2277 struct drm_device
*dev
= obj
->dev
;
2278 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2279 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2280 int regnum
= obj_priv
->fence_reg
;
2283 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2285 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2286 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2287 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2289 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2290 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2291 val
|= I965_FENCE_REG_VALID
;
2293 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2296 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2298 struct drm_gem_object
*obj
= reg
->obj
;
2299 struct drm_device
*dev
= obj
->dev
;
2300 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2301 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2302 int regnum
= obj_priv
->fence_reg
;
2305 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2307 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2308 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2309 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2310 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2311 val
|= I965_FENCE_REG_VALID
;
2313 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2316 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2318 struct drm_gem_object
*obj
= reg
->obj
;
2319 struct drm_device
*dev
= obj
->dev
;
2320 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2321 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2322 int regnum
= obj_priv
->fence_reg
;
2324 uint32_t fence_reg
, val
;
2327 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2328 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2329 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2330 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2334 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2335 HAS_128_BYTE_Y_TILING(dev
))
2340 /* Note: pitch better be a power of two tile widths */
2341 pitch_val
= obj_priv
->stride
/ tile_width
;
2342 pitch_val
= ffs(pitch_val
) - 1;
2344 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2345 HAS_128_BYTE_Y_TILING(dev
))
2346 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2348 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2350 val
= obj_priv
->gtt_offset
;
2351 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2352 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2353 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2354 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2355 val
|= I830_FENCE_REG_VALID
;
2358 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2360 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2361 I915_WRITE(fence_reg
, val
);
2364 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2366 struct drm_gem_object
*obj
= reg
->obj
;
2367 struct drm_device
*dev
= obj
->dev
;
2368 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2369 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2370 int regnum
= obj_priv
->fence_reg
;
2373 uint32_t fence_size_bits
;
2375 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2376 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2377 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2378 __func__
, obj_priv
->gtt_offset
);
2382 pitch_val
= obj_priv
->stride
/ 128;
2383 pitch_val
= ffs(pitch_val
) - 1;
2384 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2386 val
= obj_priv
->gtt_offset
;
2387 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2388 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2389 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2390 WARN_ON(fence_size_bits
& ~0x00000f00);
2391 val
|= fence_size_bits
;
2392 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2393 val
|= I830_FENCE_REG_VALID
;
2395 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2398 static int i915_find_fence_reg(struct drm_device
*dev
,
2401 struct drm_i915_fence_reg
*reg
= NULL
;
2402 struct drm_i915_gem_object
*obj_priv
= NULL
;
2403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2404 struct drm_gem_object
*obj
= NULL
;
2407 /* First try to find a free reg */
2409 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2410 reg
= &dev_priv
->fence_regs
[i
];
2414 obj_priv
= to_intel_bo(reg
->obj
);
2415 if (!obj_priv
->pin_count
)
2422 /* None available, try to steal one or wait for a user to finish */
2423 i
= I915_FENCE_REG_NONE
;
2424 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2427 obj_priv
= to_intel_bo(obj
);
2429 if (obj_priv
->pin_count
)
2433 i
= obj_priv
->fence_reg
;
2437 BUG_ON(i
== I915_FENCE_REG_NONE
);
2439 /* We only have a reference on obj from the active list. put_fence_reg
2440 * might drop that one, causing a use-after-free in it. So hold a
2441 * private reference to obj like the other callers of put_fence_reg
2442 * (set_tiling ioctl) do. */
2443 drm_gem_object_reference(obj
);
2444 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2445 drm_gem_object_unreference(obj
);
2453 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2454 * @obj: object to map through a fence reg
2456 * When mapping objects through the GTT, userspace wants to be able to write
2457 * to them without having to worry about swizzling if the object is tiled.
2459 * This function walks the fence regs looking for a free one for @obj,
2460 * stealing one if it can't find any.
2462 * It then sets up the reg based on the object's properties: address, pitch
2463 * and tiling format.
2466 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2469 struct drm_device
*dev
= obj
->dev
;
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2472 struct drm_i915_fence_reg
*reg
= NULL
;
2475 /* Just update our place in the LRU if our fence is getting used. */
2476 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2477 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2478 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2482 switch (obj_priv
->tiling_mode
) {
2483 case I915_TILING_NONE
:
2484 WARN(1, "allocating a fence for non-tiled object?\n");
2487 if (!obj_priv
->stride
)
2489 WARN((obj_priv
->stride
& (512 - 1)),
2490 "object 0x%08x is X tiled but has non-512B pitch\n",
2491 obj_priv
->gtt_offset
);
2494 if (!obj_priv
->stride
)
2496 WARN((obj_priv
->stride
& (128 - 1)),
2497 "object 0x%08x is Y tiled but has non-128B pitch\n",
2498 obj_priv
->gtt_offset
);
2502 ret
= i915_find_fence_reg(dev
, interruptible
);
2506 obj_priv
->fence_reg
= ret
;
2507 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2508 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2512 switch (INTEL_INFO(dev
)->gen
) {
2514 sandybridge_write_fence_reg(reg
);
2518 i965_write_fence_reg(reg
);
2521 i915_write_fence_reg(reg
);
2524 i830_write_fence_reg(reg
);
2528 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2529 obj_priv
->tiling_mode
);
2535 * i915_gem_clear_fence_reg - clear out fence register info
2536 * @obj: object to clear
2538 * Zeroes out the fence register itself and clears out the associated
2539 * data structures in dev_priv and obj_priv.
2542 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2544 struct drm_device
*dev
= obj
->dev
;
2545 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2546 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2547 struct drm_i915_fence_reg
*reg
=
2548 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2551 switch (INTEL_INFO(dev
)->gen
) {
2553 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2554 (obj_priv
->fence_reg
* 8), 0);
2558 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2561 if (obj_priv
->fence_reg
>= 8)
2562 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2565 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2567 I915_WRITE(fence_reg
, 0);
2572 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2573 list_del_init(®
->lru_list
);
2577 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2578 * to the buffer to finish, and then resets the fence register.
2579 * @obj: tiled object holding a fence register.
2580 * @bool: whether the wait upon the fence is interruptible
2582 * Zeroes out the fence register itself and clears out the associated
2583 * data structures in dev_priv and obj_priv.
2586 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2589 struct drm_device
*dev
= obj
->dev
;
2590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2592 struct drm_i915_fence_reg
*reg
;
2594 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2597 /* If we've changed tiling, GTT-mappings of the object
2598 * need to re-fault to ensure that the correct fence register
2599 * setup is in place.
2601 i915_gem_release_mmap(obj
);
2603 /* On the i915, GPU access to tiled buffers is via a fence,
2604 * therefore we must wait for any outstanding access to complete
2605 * before clearing the fence.
2607 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2611 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2615 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2622 i915_gem_object_flush_gtt_write_domain(obj
);
2623 i915_gem_clear_fence_reg(obj
);
2629 * Finds free space in the GTT aperture and binds the object there.
2632 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2634 struct drm_device
*dev
= obj
->dev
;
2635 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2636 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2637 struct drm_mm_node
*free_space
;
2638 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2641 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2642 DRM_ERROR("Attempting to bind a purgeable object\n");
2647 alignment
= i915_gem_get_gtt_alignment(obj
);
2648 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2649 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2653 /* If the object is bigger than the entire aperture, reject it early
2654 * before evicting everything in a vain attempt to find space.
2656 if (obj
->size
> dev_priv
->mm
.gtt_total
) {
2657 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2662 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2663 obj
->size
, alignment
, 0);
2664 if (free_space
!= NULL
) {
2665 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2667 if (obj_priv
->gtt_space
!= NULL
)
2668 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2670 if (obj_priv
->gtt_space
== NULL
) {
2671 /* If the gtt is empty and we're still having trouble
2672 * fitting our object in, we're out of memory.
2674 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2681 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2683 drm_mm_put_block(obj_priv
->gtt_space
);
2684 obj_priv
->gtt_space
= NULL
;
2686 if (ret
== -ENOMEM
) {
2687 /* first try to clear up some space from the GTT */
2688 ret
= i915_gem_evict_something(dev
, obj
->size
,
2691 /* now try to shrink everyone else */
2706 /* Create an AGP memory structure pointing at our pages, and bind it
2709 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2711 obj
->size
>> PAGE_SHIFT
,
2712 obj_priv
->gtt_offset
,
2713 obj_priv
->agp_type
);
2714 if (obj_priv
->agp_mem
== NULL
) {
2715 i915_gem_object_put_pages(obj
);
2716 drm_mm_put_block(obj_priv
->gtt_space
);
2717 obj_priv
->gtt_space
= NULL
;
2719 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2726 /* keep track of bounds object by adding it to the inactive list */
2727 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2728 i915_gem_info_add_gtt(dev_priv
, obj
->size
);
2730 /* Assert that the object is not currently in any GPU domain. As it
2731 * wasn't in the GTT, there shouldn't be any way it could have been in
2734 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2735 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2737 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2743 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2745 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2747 /* If we don't have a page list set up, then we're not pinned
2748 * to GPU, and we can ignore the cache flush because it'll happen
2749 * again at bind time.
2751 if (obj_priv
->pages
== NULL
)
2754 trace_i915_gem_object_clflush(obj
);
2756 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2759 /** Flushes any GPU write domain for the object if it's dirty. */
2761 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2764 struct drm_device
*dev
= obj
->dev
;
2765 uint32_t old_write_domain
;
2767 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2770 /* Queue the GPU write cache flushing we need. */
2771 old_write_domain
= obj
->write_domain
;
2772 i915_gem_flush_ring(dev
, NULL
,
2773 to_intel_bo(obj
)->ring
,
2774 0, obj
->write_domain
);
2775 BUG_ON(obj
->write_domain
);
2777 trace_i915_gem_object_change_domain(obj
,
2784 return i915_gem_object_wait_rendering(obj
, true);
2787 /** Flushes the GTT write domain for the object if it's dirty. */
2789 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2791 uint32_t old_write_domain
;
2793 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2796 /* No actual flushing is required for the GTT write domain. Writes
2797 * to it immediately go to main memory as far as we know, so there's
2798 * no chipset flush. It also doesn't land in render cache.
2800 old_write_domain
= obj
->write_domain
;
2801 obj
->write_domain
= 0;
2803 trace_i915_gem_object_change_domain(obj
,
2808 /** Flushes the CPU write domain for the object if it's dirty. */
2810 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2812 struct drm_device
*dev
= obj
->dev
;
2813 uint32_t old_write_domain
;
2815 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2818 i915_gem_clflush_object(obj
);
2819 drm_agp_chipset_flush(dev
);
2820 old_write_domain
= obj
->write_domain
;
2821 obj
->write_domain
= 0;
2823 trace_i915_gem_object_change_domain(obj
,
2829 * Moves a single object to the GTT read, and possibly write domain.
2831 * This function returns when the move is complete, including waiting on
2835 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2837 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2838 uint32_t old_write_domain
, old_read_domains
;
2841 /* Not valid to be called on unbound objects. */
2842 if (obj_priv
->gtt_space
== NULL
)
2845 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2849 i915_gem_object_flush_cpu_write_domain(obj
);
2852 ret
= i915_gem_object_wait_rendering(obj
, true);
2857 old_write_domain
= obj
->write_domain
;
2858 old_read_domains
= obj
->read_domains
;
2860 /* It should now be out of any other write domains, and we can update
2861 * the domain values for our changes.
2863 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2864 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2866 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2867 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2868 obj_priv
->dirty
= 1;
2871 trace_i915_gem_object_change_domain(obj
,
2879 * Prepare buffer for display plane. Use uninterruptible for possible flush
2880 * wait, as in modesetting process we're not supposed to be interrupted.
2883 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2886 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2887 uint32_t old_read_domains
;
2890 /* Not valid to be called on unbound objects. */
2891 if (obj_priv
->gtt_space
== NULL
)
2894 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2898 /* Currently, we are always called from an non-interruptible context. */
2900 ret
= i915_gem_object_wait_rendering(obj
, false);
2905 i915_gem_object_flush_cpu_write_domain(obj
);
2907 old_read_domains
= obj
->read_domains
;
2908 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2910 trace_i915_gem_object_change_domain(obj
,
2918 * Moves a single object to the CPU read, and possibly write domain.
2920 * This function returns when the move is complete, including waiting on
2924 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2926 uint32_t old_write_domain
, old_read_domains
;
2929 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2933 i915_gem_object_flush_gtt_write_domain(obj
);
2935 /* If we have a partially-valid cache of the object in the CPU,
2936 * finish invalidating it and free the per-page flags.
2938 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2941 ret
= i915_gem_object_wait_rendering(obj
, true);
2946 old_write_domain
= obj
->write_domain
;
2947 old_read_domains
= obj
->read_domains
;
2949 /* Flush the CPU cache if it's still invalid. */
2950 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2951 i915_gem_clflush_object(obj
);
2953 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2956 /* It should now be out of any other write domains, and we can update
2957 * the domain values for our changes.
2959 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2961 /* If we're writing through the CPU, then the GPU read domains will
2962 * need to be invalidated at next use.
2965 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2966 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2969 trace_i915_gem_object_change_domain(obj
,
2977 * Set the next domain for the specified object. This
2978 * may not actually perform the necessary flushing/invaliding though,
2979 * as that may want to be batched with other set_domain operations
2981 * This is (we hope) the only really tricky part of gem. The goal
2982 * is fairly simple -- track which caches hold bits of the object
2983 * and make sure they remain coherent. A few concrete examples may
2984 * help to explain how it works. For shorthand, we use the notation
2985 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2986 * a pair of read and write domain masks.
2988 * Case 1: the batch buffer
2994 * 5. Unmapped from GTT
2997 * Let's take these a step at a time
3000 * Pages allocated from the kernel may still have
3001 * cache contents, so we set them to (CPU, CPU) always.
3002 * 2. Written by CPU (using pwrite)
3003 * The pwrite function calls set_domain (CPU, CPU) and
3004 * this function does nothing (as nothing changes)
3006 * This function asserts that the object is not
3007 * currently in any GPU-based read or write domains
3009 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3010 * As write_domain is zero, this function adds in the
3011 * current read domains (CPU+COMMAND, 0).
3012 * flush_domains is set to CPU.
3013 * invalidate_domains is set to COMMAND
3014 * clflush is run to get data out of the CPU caches
3015 * then i915_dev_set_domain calls i915_gem_flush to
3016 * emit an MI_FLUSH and drm_agp_chipset_flush
3017 * 5. Unmapped from GTT
3018 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3019 * flush_domains and invalidate_domains end up both zero
3020 * so no flushing/invalidating happens
3024 * Case 2: The shared render buffer
3028 * 3. Read/written by GPU
3029 * 4. set_domain to (CPU,CPU)
3030 * 5. Read/written by CPU
3031 * 6. Read/written by GPU
3034 * Same as last example, (CPU, CPU)
3036 * Nothing changes (assertions find that it is not in the GPU)
3037 * 3. Read/written by GPU
3038 * execbuffer calls set_domain (RENDER, RENDER)
3039 * flush_domains gets CPU
3040 * invalidate_domains gets GPU
3042 * MI_FLUSH and drm_agp_chipset_flush
3043 * 4. set_domain (CPU, CPU)
3044 * flush_domains gets GPU
3045 * invalidate_domains gets CPU
3046 * wait_rendering (obj) to make sure all drawing is complete.
3047 * This will include an MI_FLUSH to get the data from GPU
3049 * clflush (obj) to invalidate the CPU cache
3050 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3051 * 5. Read/written by CPU
3052 * cache lines are loaded and dirtied
3053 * 6. Read written by GPU
3054 * Same as last GPU access
3056 * Case 3: The constant buffer
3061 * 4. Updated (written) by CPU again
3070 * flush_domains = CPU
3071 * invalidate_domains = RENDER
3074 * drm_agp_chipset_flush
3075 * 4. Updated (written) by CPU again
3077 * flush_domains = 0 (no previous write domain)
3078 * invalidate_domains = 0 (no new read domains)
3081 * flush_domains = CPU
3082 * invalidate_domains = RENDER
3085 * drm_agp_chipset_flush
3088 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3090 struct drm_device
*dev
= obj
->dev
;
3091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3092 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3093 uint32_t invalidate_domains
= 0;
3094 uint32_t flush_domains
= 0;
3095 uint32_t old_read_domains
;
3097 intel_mark_busy(dev
, obj
);
3100 * If the object isn't moving to a new write domain,
3101 * let the object stay in multiple read domains
3103 if (obj
->pending_write_domain
== 0)
3104 obj
->pending_read_domains
|= obj
->read_domains
;
3106 obj_priv
->dirty
= 1;
3109 * Flush the current write domain if
3110 * the new read domains don't match. Invalidate
3111 * any read domains which differ from the old
3114 if (obj
->write_domain
&&
3115 obj
->write_domain
!= obj
->pending_read_domains
) {
3116 flush_domains
|= obj
->write_domain
;
3117 invalidate_domains
|=
3118 obj
->pending_read_domains
& ~obj
->write_domain
;
3121 * Invalidate any read caches which may have
3122 * stale data. That is, any new read domains.
3124 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3125 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3126 i915_gem_clflush_object(obj
);
3128 old_read_domains
= obj
->read_domains
;
3130 /* The actual obj->write_domain will be updated with
3131 * pending_write_domain after we emit the accumulated flush for all
3132 * of our domain changes in execbuffers (which clears objects'
3133 * write_domains). So if we have a current write domain that we
3134 * aren't changing, set pending_write_domain to that.
3136 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3137 obj
->pending_write_domain
= obj
->write_domain
;
3138 obj
->read_domains
= obj
->pending_read_domains
;
3140 dev
->invalidate_domains
|= invalidate_domains
;
3141 dev
->flush_domains
|= flush_domains
;
3143 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3145 trace_i915_gem_object_change_domain(obj
,
3151 * Moves the object from a partially CPU read to a full one.
3153 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3154 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3157 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3159 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3161 if (!obj_priv
->page_cpu_valid
)
3164 /* If we're partially in the CPU read domain, finish moving it in.
3166 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3169 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3170 if (obj_priv
->page_cpu_valid
[i
])
3172 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3176 /* Free the page_cpu_valid mappings which are now stale, whether
3177 * or not we've got I915_GEM_DOMAIN_CPU.
3179 kfree(obj_priv
->page_cpu_valid
);
3180 obj_priv
->page_cpu_valid
= NULL
;
3184 * Set the CPU read domain on a range of the object.
3186 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3187 * not entirely valid. The page_cpu_valid member of the object flags which
3188 * pages have been flushed, and will be respected by
3189 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3190 * of the whole object.
3192 * This function returns when the move is complete, including waiting on
3196 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3197 uint64_t offset
, uint64_t size
)
3199 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3200 uint32_t old_read_domains
;
3203 if (offset
== 0 && size
== obj
->size
)
3204 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3206 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3209 i915_gem_object_flush_gtt_write_domain(obj
);
3211 /* If we're already fully in the CPU read domain, we're done. */
3212 if (obj_priv
->page_cpu_valid
== NULL
&&
3213 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3216 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3217 * newly adding I915_GEM_DOMAIN_CPU
3219 if (obj_priv
->page_cpu_valid
== NULL
) {
3220 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3222 if (obj_priv
->page_cpu_valid
== NULL
)
3224 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3225 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3227 /* Flush the cache on any pages that are still invalid from the CPU's
3230 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3232 if (obj_priv
->page_cpu_valid
[i
])
3235 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3237 obj_priv
->page_cpu_valid
[i
] = 1;
3240 /* It should now be out of any other write domains, and we can update
3241 * the domain values for our changes.
3243 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3245 old_read_domains
= obj
->read_domains
;
3246 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3248 trace_i915_gem_object_change_domain(obj
,
3256 * Pin an object to the GTT and evaluate the relocations landing in it.
3259 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3260 struct drm_file
*file_priv
,
3261 struct drm_i915_gem_exec_object2
*entry
)
3263 struct drm_device
*dev
= obj
->dev
;
3264 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3265 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3266 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3270 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3271 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3273 /* Check fence reg constraints and rebind if necessary */
3275 !i915_gem_object_fence_offset_ok(obj
,
3276 obj_priv
->tiling_mode
)) {
3277 ret
= i915_gem_object_unbind(obj
);
3282 /* Choose the GTT offset for our buffer and put it there. */
3283 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3288 * Pre-965 chips need a fence register set up in order to
3289 * properly handle blits to/from tiled surfaces.
3292 ret
= i915_gem_object_get_fence_reg(obj
, true);
3294 i915_gem_object_unpin(obj
);
3298 dev_priv
->fence_regs
[obj_priv
->fence_reg
].gpu
= true;
3301 entry
->offset
= obj_priv
->gtt_offset
;
3303 /* Apply the relocations, using the GTT aperture to avoid cache
3304 * flushing requirements.
3306 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3307 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3308 struct drm_i915_gem_relocation_entry reloc
;
3309 struct drm_gem_object
*target_obj
;
3310 struct drm_i915_gem_object
*target_obj_priv
;
3312 ret
= __copy_from_user_inatomic(&reloc
,
3316 i915_gem_object_unpin(obj
);
3320 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3321 reloc
.target_handle
);
3322 if (target_obj
== NULL
) {
3323 i915_gem_object_unpin(obj
);
3326 target_obj_priv
= to_intel_bo(target_obj
);
3329 DRM_INFO("%s: obj %p offset %08x target %d "
3330 "read %08x write %08x gtt %08x "
3331 "presumed %08x delta %08x\n",
3335 (int) reloc
.target_handle
,
3336 (int) reloc
.read_domains
,
3337 (int) reloc
.write_domain
,
3338 (int) target_obj_priv
->gtt_offset
,
3339 (int) reloc
.presumed_offset
,
3343 /* The target buffer should have appeared before us in the
3344 * exec_object list, so it should have a GTT space bound by now.
3346 if (target_obj_priv
->gtt_space
== NULL
) {
3347 DRM_ERROR("No GTT space found for object %d\n",
3348 reloc
.target_handle
);
3349 drm_gem_object_unreference(target_obj
);
3350 i915_gem_object_unpin(obj
);
3354 /* Validate that the target is in a valid r/w GPU domain */
3355 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3356 DRM_ERROR("reloc with multiple write domains: "
3357 "obj %p target %d offset %d "
3358 "read %08x write %08x",
3359 obj
, reloc
.target_handle
,
3362 reloc
.write_domain
);
3363 drm_gem_object_unreference(target_obj
);
3364 i915_gem_object_unpin(obj
);
3367 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3368 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3369 DRM_ERROR("reloc with read/write CPU domains: "
3370 "obj %p target %d offset %d "
3371 "read %08x write %08x",
3372 obj
, reloc
.target_handle
,
3375 reloc
.write_domain
);
3376 drm_gem_object_unreference(target_obj
);
3377 i915_gem_object_unpin(obj
);
3380 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3381 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3382 DRM_ERROR("Write domain conflict: "
3383 "obj %p target %d offset %d "
3384 "new %08x old %08x\n",
3385 obj
, reloc
.target_handle
,
3388 target_obj
->pending_write_domain
);
3389 drm_gem_object_unreference(target_obj
);
3390 i915_gem_object_unpin(obj
);
3394 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3395 target_obj
->pending_write_domain
|= reloc
.write_domain
;
3397 /* If the relocation already has the right value in it, no
3398 * more work needs to be done.
3400 if (target_obj_priv
->gtt_offset
== reloc
.presumed_offset
) {
3401 drm_gem_object_unreference(target_obj
);
3405 /* Check that the relocation address is valid... */
3406 if (reloc
.offset
> obj
->size
- 4) {
3407 DRM_ERROR("Relocation beyond object bounds: "
3408 "obj %p target %d offset %d size %d.\n",
3409 obj
, reloc
.target_handle
,
3410 (int) reloc
.offset
, (int) obj
->size
);
3411 drm_gem_object_unreference(target_obj
);
3412 i915_gem_object_unpin(obj
);
3415 if (reloc
.offset
& 3) {
3416 DRM_ERROR("Relocation not 4-byte aligned: "
3417 "obj %p target %d offset %d.\n",
3418 obj
, reloc
.target_handle
,
3419 (int) reloc
.offset
);
3420 drm_gem_object_unreference(target_obj
);
3421 i915_gem_object_unpin(obj
);
3425 /* and points to somewhere within the target object. */
3426 if (reloc
.delta
>= target_obj
->size
) {
3427 DRM_ERROR("Relocation beyond target object bounds: "
3428 "obj %p target %d delta %d size %d.\n",
3429 obj
, reloc
.target_handle
,
3430 (int) reloc
.delta
, (int) target_obj
->size
);
3431 drm_gem_object_unreference(target_obj
);
3432 i915_gem_object_unpin(obj
);
3436 reloc
.delta
+= target_obj_priv
->gtt_offset
;
3437 if (obj
->write_domain
== I915_GEM_DOMAIN_CPU
) {
3438 uint32_t page_offset
= reloc
.offset
& ~PAGE_MASK
;
3441 vaddr
= kmap_atomic(obj_priv
->pages
[reloc
.offset
>> PAGE_SHIFT
], KM_USER0
);
3442 *(uint32_t *)(vaddr
+ page_offset
) = reloc
.delta
;
3443 kunmap_atomic(vaddr
, KM_USER0
);
3445 uint32_t __iomem
*reloc_entry
;
3446 void __iomem
*reloc_page
;
3449 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3451 drm_gem_object_unreference(target_obj
);
3452 i915_gem_object_unpin(obj
);
3456 /* Map the page containing the relocation we're going to perform. */
3457 reloc
.offset
+= obj_priv
->gtt_offset
;
3458 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3459 reloc
.offset
& PAGE_MASK
,
3461 reloc_entry
= (uint32_t __iomem
*)
3462 (reloc_page
+ (reloc
.offset
& ~PAGE_MASK
));
3463 iowrite32(reloc
.delta
, reloc_entry
);
3464 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3467 drm_gem_object_unreference(target_obj
);
3473 /* Throttle our rendering by waiting until the ring has completed our requests
3474 * emitted over 20 msec ago.
3476 * Note that if we were to use the current jiffies each time around the loop,
3477 * we wouldn't escape the function with any frames outstanding if the time to
3478 * render a frame was over 20ms.
3480 * This should get us reasonable parallelism between CPU and GPU but also
3481 * relatively low latency when blocking on a particular request to finish.
3484 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3488 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3489 struct drm_i915_gem_request
*request
;
3490 struct intel_ring_buffer
*ring
= NULL
;
3494 spin_lock(&file_priv
->mm
.lock
);
3495 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3496 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3499 ring
= request
->ring
;
3500 seqno
= request
->seqno
;
3502 spin_unlock(&file_priv
->mm
.lock
);
3508 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
3509 /* And wait for the seqno passing without holding any locks and
3510 * causing extra latency for others. This is safe as the irq
3511 * generation is designed to be run atomically and so is
3514 ring
->user_irq_get(dev
, ring
);
3515 ret
= wait_event_interruptible(ring
->irq_queue
,
3516 i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)
3517 || atomic_read(&dev_priv
->mm
.wedged
));
3518 ring
->user_irq_put(dev
, ring
);
3520 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3525 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3531 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3532 uint64_t exec_offset
)
3534 uint32_t exec_start
, exec_len
;
3536 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3537 exec_len
= (uint32_t) exec
->batch_len
;
3539 if ((exec_start
| exec_len
) & 0x7)
3549 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3554 for (i
= 0; i
< count
; i
++) {
3555 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3556 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3558 if (!access_ok(VERIFY_READ
, ptr
, length
))
3561 if (fault_in_pages_readable(ptr
, length
))
3569 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3570 struct drm_file
*file_priv
,
3571 struct drm_i915_gem_execbuffer2
*args
,
3572 struct drm_i915_gem_exec_object2
*exec_list
)
3574 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3575 struct drm_gem_object
**object_list
= NULL
;
3576 struct drm_gem_object
*batch_obj
;
3577 struct drm_i915_gem_object
*obj_priv
;
3578 struct drm_clip_rect
*cliprects
= NULL
;
3579 struct drm_i915_gem_request
*request
= NULL
;
3580 int ret
, i
, pinned
= 0;
3581 uint64_t exec_offset
;
3582 int pin_tries
, flips
;
3584 struct intel_ring_buffer
*ring
= NULL
;
3586 ret
= i915_gem_check_is_wedged(dev
);
3590 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3595 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3596 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3598 if (args
->flags
& I915_EXEC_BSD
) {
3599 if (!HAS_BSD(dev
)) {
3600 DRM_ERROR("execbuf with wrong flag\n");
3603 ring
= &dev_priv
->bsd_ring
;
3605 ring
= &dev_priv
->render_ring
;
3608 if (args
->buffer_count
< 1) {
3609 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3612 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3613 if (object_list
== NULL
) {
3614 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3615 args
->buffer_count
);
3620 if (args
->num_cliprects
!= 0) {
3621 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3623 if (cliprects
== NULL
) {
3628 ret
= copy_from_user(cliprects
,
3629 (struct drm_clip_rect __user
*)
3630 (uintptr_t) args
->cliprects_ptr
,
3631 sizeof(*cliprects
) * args
->num_cliprects
);
3633 DRM_ERROR("copy %d cliprects failed: %d\n",
3634 args
->num_cliprects
, ret
);
3640 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3641 if (request
== NULL
) {
3646 ret
= i915_mutex_lock_interruptible(dev
);
3650 if (dev_priv
->mm
.suspended
) {
3651 mutex_unlock(&dev
->struct_mutex
);
3656 /* Look up object handles */
3657 for (i
= 0; i
< args
->buffer_count
; i
++) {
3658 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3659 exec_list
[i
].handle
);
3660 if (object_list
[i
] == NULL
) {
3661 DRM_ERROR("Invalid object handle %d at index %d\n",
3662 exec_list
[i
].handle
, i
);
3663 /* prevent error path from reading uninitialized data */
3664 args
->buffer_count
= i
+ 1;
3669 obj_priv
= to_intel_bo(object_list
[i
]);
3670 if (obj_priv
->in_execbuffer
) {
3671 DRM_ERROR("Object %p appears more than once in object list\n",
3673 /* prevent error path from reading uninitialized data */
3674 args
->buffer_count
= i
+ 1;
3678 obj_priv
->in_execbuffer
= true;
3681 /* Pin and relocate */
3682 for (pin_tries
= 0; ; pin_tries
++) {
3685 for (i
= 0; i
< args
->buffer_count
; i
++) {
3686 object_list
[i
]->pending_read_domains
= 0;
3687 object_list
[i
]->pending_write_domain
= 0;
3688 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3699 /* error other than GTT full, or we've already tried again */
3700 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3701 if (ret
!= -ERESTARTSYS
) {
3702 unsigned long long total_size
= 0;
3704 for (i
= 0; i
< args
->buffer_count
; i
++) {
3705 obj_priv
= to_intel_bo(object_list
[i
]);
3707 total_size
+= object_list
[i
]->size
;
3709 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3710 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3712 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3713 pinned
+1, args
->buffer_count
,
3714 total_size
, num_fences
,
3716 DRM_ERROR("%u objects [%u pinned, %u GTT], "
3717 "%zu object bytes [%zu pinned], "
3718 "%zu /%zu gtt bytes\n",
3719 dev_priv
->mm
.object_count
,
3720 dev_priv
->mm
.pin_count
,
3721 dev_priv
->mm
.gtt_count
,
3722 dev_priv
->mm
.object_memory
,
3723 dev_priv
->mm
.pin_memory
,
3724 dev_priv
->mm
.gtt_memory
,
3725 dev_priv
->mm
.gtt_total
);
3730 /* unpin all of our buffers */
3731 for (i
= 0; i
< pinned
; i
++)
3732 i915_gem_object_unpin(object_list
[i
]);
3735 /* evict everyone we can from the aperture */
3736 ret
= i915_gem_evict_everything(dev
);
3737 if (ret
&& ret
!= -ENOSPC
)
3741 /* Set the pending read domains for the batch buffer to COMMAND */
3742 batch_obj
= object_list
[args
->buffer_count
-1];
3743 if (batch_obj
->pending_write_domain
) {
3744 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3748 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3750 /* Sanity check the batch buffer, prior to moving objects */
3751 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3752 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3754 DRM_ERROR("execbuf with invalid offset/length\n");
3758 /* Zero the global flush/invalidate flags. These
3759 * will be modified as new domains are computed
3762 dev
->invalidate_domains
= 0;
3763 dev
->flush_domains
= 0;
3764 dev_priv
->mm
.flush_rings
= 0;
3766 for (i
= 0; i
< args
->buffer_count
; i
++) {
3767 struct drm_gem_object
*obj
= object_list
[i
];
3769 /* Compute new gpu domains and update invalidate/flush */
3770 i915_gem_object_set_to_gpu_domain(obj
);
3773 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3775 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3777 dev
->invalidate_domains
,
3778 dev
->flush_domains
);
3780 i915_gem_flush(dev
, file_priv
,
3781 dev
->invalidate_domains
,
3783 dev_priv
->mm
.flush_rings
);
3786 for (i
= 0; i
< args
->buffer_count
; i
++) {
3787 struct drm_gem_object
*obj
= object_list
[i
];
3788 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3789 uint32_t old_write_domain
= obj
->write_domain
;
3791 obj
->write_domain
= obj
->pending_write_domain
;
3792 if (obj
->write_domain
)
3793 list_move_tail(&obj_priv
->gpu_write_list
,
3794 &dev_priv
->mm
.gpu_write_list
);
3796 trace_i915_gem_object_change_domain(obj
,
3802 for (i
= 0; i
< args
->buffer_count
; i
++) {
3803 i915_gem_object_check_coherency(object_list
[i
],
3804 exec_list
[i
].handle
);
3809 i915_gem_dump_object(batch_obj
,
3815 /* Check for any pending flips. As we only maintain a flip queue depth
3816 * of 1, we can simply insert a WAIT for the next display flip prior
3817 * to executing the batch and avoid stalling the CPU.
3820 for (i
= 0; i
< args
->buffer_count
; i
++) {
3821 if (object_list
[i
]->write_domain
)
3822 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3825 int plane
, flip_mask
;
3827 for (plane
= 0; flips
>> plane
; plane
++) {
3828 if (((flips
>> plane
) & 1) == 0)
3832 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3834 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3836 intel_ring_begin(dev
, ring
, 2);
3837 intel_ring_emit(dev
, ring
,
3838 MI_WAIT_FOR_EVENT
| flip_mask
);
3839 intel_ring_emit(dev
, ring
, MI_NOOP
);
3840 intel_ring_advance(dev
, ring
);
3844 /* Exec the batchbuffer */
3845 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3846 cliprects
, exec_offset
);
3848 DRM_ERROR("dispatch failed %d\n", ret
);
3853 * Ensure that the commands in the batch buffer are
3854 * finished before the interrupt fires
3856 i915_retire_commands(dev
, ring
);
3858 for (i
= 0; i
< args
->buffer_count
; i
++) {
3859 struct drm_gem_object
*obj
= object_list
[i
];
3860 obj_priv
= to_intel_bo(obj
);
3862 i915_gem_object_move_to_active(obj
, ring
);
3865 i915_add_request(dev
, file_priv
, request
, ring
);
3869 for (i
= 0; i
< pinned
; i
++)
3870 i915_gem_object_unpin(object_list
[i
]);
3872 for (i
= 0; i
< args
->buffer_count
; i
++) {
3873 if (object_list
[i
]) {
3874 obj_priv
= to_intel_bo(object_list
[i
]);
3875 obj_priv
->in_execbuffer
= false;
3877 drm_gem_object_unreference(object_list
[i
]);
3880 mutex_unlock(&dev
->struct_mutex
);
3883 drm_free_large(object_list
);
3891 * Legacy execbuffer just creates an exec2 list from the original exec object
3892 * list array and passes it to the real function.
3895 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3896 struct drm_file
*file_priv
)
3898 struct drm_i915_gem_execbuffer
*args
= data
;
3899 struct drm_i915_gem_execbuffer2 exec2
;
3900 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3901 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3905 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3906 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3909 if (args
->buffer_count
< 1) {
3910 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3914 /* Copy in the exec list from userland */
3915 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3916 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3917 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3918 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3919 args
->buffer_count
);
3920 drm_free_large(exec_list
);
3921 drm_free_large(exec2_list
);
3924 ret
= copy_from_user(exec_list
,
3925 (struct drm_i915_relocation_entry __user
*)
3926 (uintptr_t) args
->buffers_ptr
,
3927 sizeof(*exec_list
) * args
->buffer_count
);
3929 DRM_ERROR("copy %d exec entries failed %d\n",
3930 args
->buffer_count
, ret
);
3931 drm_free_large(exec_list
);
3932 drm_free_large(exec2_list
);
3936 for (i
= 0; i
< args
->buffer_count
; i
++) {
3937 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3938 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3939 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3940 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3941 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3942 if (INTEL_INFO(dev
)->gen
< 4)
3943 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3945 exec2_list
[i
].flags
= 0;
3948 exec2
.buffers_ptr
= args
->buffers_ptr
;
3949 exec2
.buffer_count
= args
->buffer_count
;
3950 exec2
.batch_start_offset
= args
->batch_start_offset
;
3951 exec2
.batch_len
= args
->batch_len
;
3952 exec2
.DR1
= args
->DR1
;
3953 exec2
.DR4
= args
->DR4
;
3954 exec2
.num_cliprects
= args
->num_cliprects
;
3955 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3956 exec2
.flags
= I915_EXEC_RENDER
;
3958 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3960 /* Copy the new buffer offsets back to the user's exec list. */
3961 for (i
= 0; i
< args
->buffer_count
; i
++)
3962 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3963 /* ... and back out to userspace */
3964 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3965 (uintptr_t) args
->buffers_ptr
,
3967 sizeof(*exec_list
) * args
->buffer_count
);
3970 DRM_ERROR("failed to copy %d exec entries "
3971 "back to user (%d)\n",
3972 args
->buffer_count
, ret
);
3976 drm_free_large(exec_list
);
3977 drm_free_large(exec2_list
);
3982 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3983 struct drm_file
*file_priv
)
3985 struct drm_i915_gem_execbuffer2
*args
= data
;
3986 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3990 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3991 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3994 if (args
->buffer_count
< 1) {
3995 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
3999 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4000 if (exec2_list
== NULL
) {
4001 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4002 args
->buffer_count
);
4005 ret
= copy_from_user(exec2_list
,
4006 (struct drm_i915_relocation_entry __user
*)
4007 (uintptr_t) args
->buffers_ptr
,
4008 sizeof(*exec2_list
) * args
->buffer_count
);
4010 DRM_ERROR("copy %d exec entries failed %d\n",
4011 args
->buffer_count
, ret
);
4012 drm_free_large(exec2_list
);
4016 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4018 /* Copy the new buffer offsets back to the user's exec list. */
4019 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4020 (uintptr_t) args
->buffers_ptr
,
4022 sizeof(*exec2_list
) * args
->buffer_count
);
4025 DRM_ERROR("failed to copy %d exec entries "
4026 "back to user (%d)\n",
4027 args
->buffer_count
, ret
);
4031 drm_free_large(exec2_list
);
4036 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4038 struct drm_device
*dev
= obj
->dev
;
4039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4040 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4043 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4044 WARN_ON(i915_verify_lists(dev
));
4046 if (obj_priv
->gtt_space
!= NULL
) {
4048 alignment
= i915_gem_get_gtt_alignment(obj
);
4049 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4050 WARN(obj_priv
->pin_count
,
4051 "bo is already pinned with incorrect alignment:"
4052 " offset=%x, req.alignment=%x\n",
4053 obj_priv
->gtt_offset
, alignment
);
4054 ret
= i915_gem_object_unbind(obj
);
4060 if (obj_priv
->gtt_space
== NULL
) {
4061 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4066 obj_priv
->pin_count
++;
4068 /* If the object is not active and not pending a flush,
4069 * remove it from the inactive list
4071 if (obj_priv
->pin_count
== 1) {
4072 i915_gem_info_add_pin(dev_priv
, obj
->size
);
4073 if (!obj_priv
->active
)
4074 list_move_tail(&obj_priv
->list
,
4075 &dev_priv
->mm
.pinned_list
);
4078 WARN_ON(i915_verify_lists(dev
));
4083 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4085 struct drm_device
*dev
= obj
->dev
;
4086 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4087 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4089 WARN_ON(i915_verify_lists(dev
));
4090 obj_priv
->pin_count
--;
4091 BUG_ON(obj_priv
->pin_count
< 0);
4092 BUG_ON(obj_priv
->gtt_space
== NULL
);
4094 /* If the object is no longer pinned, and is
4095 * neither active nor being flushed, then stick it on
4098 if (obj_priv
->pin_count
== 0) {
4099 if (!obj_priv
->active
)
4100 list_move_tail(&obj_priv
->list
,
4101 &dev_priv
->mm
.inactive_list
);
4102 i915_gem_info_remove_pin(dev_priv
, obj
->size
);
4104 WARN_ON(i915_verify_lists(dev
));
4108 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4109 struct drm_file
*file_priv
)
4111 struct drm_i915_gem_pin
*args
= data
;
4112 struct drm_gem_object
*obj
;
4113 struct drm_i915_gem_object
*obj_priv
;
4116 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4118 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4122 obj_priv
= to_intel_bo(obj
);
4124 ret
= i915_mutex_lock_interruptible(dev
);
4126 drm_gem_object_unreference_unlocked(obj
);
4130 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4131 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4132 drm_gem_object_unreference(obj
);
4133 mutex_unlock(&dev
->struct_mutex
);
4137 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4138 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4140 drm_gem_object_unreference(obj
);
4141 mutex_unlock(&dev
->struct_mutex
);
4145 obj_priv
->user_pin_count
++;
4146 obj_priv
->pin_filp
= file_priv
;
4147 if (obj_priv
->user_pin_count
== 1) {
4148 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4150 drm_gem_object_unreference(obj
);
4151 mutex_unlock(&dev
->struct_mutex
);
4156 /* XXX - flush the CPU caches for pinned objects
4157 * as the X server doesn't manage domains yet
4159 i915_gem_object_flush_cpu_write_domain(obj
);
4160 args
->offset
= obj_priv
->gtt_offset
;
4161 drm_gem_object_unreference(obj
);
4162 mutex_unlock(&dev
->struct_mutex
);
4168 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4169 struct drm_file
*file_priv
)
4171 struct drm_i915_gem_pin
*args
= data
;
4172 struct drm_gem_object
*obj
;
4173 struct drm_i915_gem_object
*obj_priv
;
4176 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4178 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4183 obj_priv
= to_intel_bo(obj
);
4185 ret
= i915_mutex_lock_interruptible(dev
);
4187 drm_gem_object_unreference_unlocked(obj
);
4191 if (obj_priv
->pin_filp
!= file_priv
) {
4192 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4194 drm_gem_object_unreference(obj
);
4195 mutex_unlock(&dev
->struct_mutex
);
4198 obj_priv
->user_pin_count
--;
4199 if (obj_priv
->user_pin_count
== 0) {
4200 obj_priv
->pin_filp
= NULL
;
4201 i915_gem_object_unpin(obj
);
4204 drm_gem_object_unreference(obj
);
4205 mutex_unlock(&dev
->struct_mutex
);
4210 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4211 struct drm_file
*file_priv
)
4213 struct drm_i915_gem_busy
*args
= data
;
4214 struct drm_gem_object
*obj
;
4215 struct drm_i915_gem_object
*obj_priv
;
4218 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4220 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4225 ret
= i915_mutex_lock_interruptible(dev
);
4227 drm_gem_object_unreference_unlocked(obj
);
4231 /* Count all active objects as busy, even if they are currently not used
4232 * by the gpu. Users of this interface expect objects to eventually
4233 * become non-busy without any further actions, therefore emit any
4234 * necessary flushes here.
4236 obj_priv
= to_intel_bo(obj
);
4237 args
->busy
= obj_priv
->active
;
4239 /* Unconditionally flush objects, even when the gpu still uses this
4240 * object. Userspace calling this function indicates that it wants to
4241 * use this buffer rather sooner than later, so issuing the required
4242 * flush earlier is beneficial.
4244 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4245 i915_gem_flush_ring(dev
, file_priv
,
4247 0, obj
->write_domain
);
4249 /* Update the active list for the hardware's current position.
4250 * Otherwise this only updates on a delayed timer or when irqs
4251 * are actually unmasked, and our working set ends up being
4252 * larger than required.
4254 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4256 args
->busy
= obj_priv
->active
;
4259 drm_gem_object_unreference(obj
);
4260 mutex_unlock(&dev
->struct_mutex
);
4265 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4266 struct drm_file
*file_priv
)
4268 return i915_gem_ring_throttle(dev
, file_priv
);
4272 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4273 struct drm_file
*file_priv
)
4275 struct drm_i915_gem_madvise
*args
= data
;
4276 struct drm_gem_object
*obj
;
4277 struct drm_i915_gem_object
*obj_priv
;
4280 switch (args
->madv
) {
4281 case I915_MADV_DONTNEED
:
4282 case I915_MADV_WILLNEED
:
4288 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4290 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4294 obj_priv
= to_intel_bo(obj
);
4296 ret
= i915_mutex_lock_interruptible(dev
);
4298 drm_gem_object_unreference_unlocked(obj
);
4302 if (obj_priv
->pin_count
) {
4303 drm_gem_object_unreference(obj
);
4304 mutex_unlock(&dev
->struct_mutex
);
4306 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4310 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4311 obj_priv
->madv
= args
->madv
;
4313 /* if the object is no longer bound, discard its backing storage */
4314 if (i915_gem_object_is_purgeable(obj_priv
) &&
4315 obj_priv
->gtt_space
== NULL
)
4316 i915_gem_object_truncate(obj
);
4318 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4320 drm_gem_object_unreference(obj
);
4321 mutex_unlock(&dev
->struct_mutex
);
4326 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4330 struct drm_i915_gem_object
*obj
;
4332 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4336 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4341 i915_gem_info_add_obj(dev_priv
, size
);
4343 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4344 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4346 obj
->agp_type
= AGP_USER_MEMORY
;
4347 obj
->base
.driver_private
= NULL
;
4348 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4349 INIT_LIST_HEAD(&obj
->list
);
4350 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4351 obj
->madv
= I915_MADV_WILLNEED
;
4356 int i915_gem_init_object(struct drm_gem_object
*obj
)
4363 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4365 struct drm_device
*dev
= obj
->dev
;
4366 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4367 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4370 ret
= i915_gem_object_unbind(obj
);
4371 if (ret
== -ERESTARTSYS
) {
4372 list_move(&obj_priv
->list
,
4373 &dev_priv
->mm
.deferred_free_list
);
4377 if (obj_priv
->mmap_offset
)
4378 i915_gem_free_mmap_offset(obj
);
4380 drm_gem_object_release(obj
);
4381 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4383 kfree(obj_priv
->page_cpu_valid
);
4384 kfree(obj_priv
->bit_17
);
4388 void i915_gem_free_object(struct drm_gem_object
*obj
)
4390 struct drm_device
*dev
= obj
->dev
;
4391 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4393 trace_i915_gem_object_destroy(obj
);
4395 while (obj_priv
->pin_count
> 0)
4396 i915_gem_object_unpin(obj
);
4398 if (obj_priv
->phys_obj
)
4399 i915_gem_detach_phys_object(dev
, obj
);
4401 i915_gem_free_object_tail(obj
);
4405 i915_gem_idle(struct drm_device
*dev
)
4407 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4410 mutex_lock(&dev
->struct_mutex
);
4412 if (dev_priv
->mm
.suspended
||
4413 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4415 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4416 mutex_unlock(&dev
->struct_mutex
);
4420 ret
= i915_gpu_idle(dev
);
4422 mutex_unlock(&dev
->struct_mutex
);
4426 /* Under UMS, be paranoid and evict. */
4427 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4428 ret
= i915_gem_evict_inactive(dev
);
4430 mutex_unlock(&dev
->struct_mutex
);
4435 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4436 * We need to replace this with a semaphore, or something.
4437 * And not confound mm.suspended!
4439 dev_priv
->mm
.suspended
= 1;
4440 del_timer_sync(&dev_priv
->hangcheck_timer
);
4442 i915_kernel_lost_context(dev
);
4443 i915_gem_cleanup_ringbuffer(dev
);
4445 mutex_unlock(&dev
->struct_mutex
);
4447 /* Cancel the retire work handler, which should be idle now. */
4448 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4454 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4455 * over cache flushing.
4458 i915_gem_init_pipe_control(struct drm_device
*dev
)
4460 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4461 struct drm_gem_object
*obj
;
4462 struct drm_i915_gem_object
*obj_priv
;
4465 obj
= i915_gem_alloc_object(dev
, 4096);
4467 DRM_ERROR("Failed to allocate seqno page\n");
4471 obj_priv
= to_intel_bo(obj
);
4472 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4474 ret
= i915_gem_object_pin(obj
, 4096);
4478 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4479 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4480 if (dev_priv
->seqno_page
== NULL
)
4483 dev_priv
->seqno_obj
= obj
;
4484 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4489 i915_gem_object_unpin(obj
);
4491 drm_gem_object_unreference(obj
);
4498 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4500 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4501 struct drm_gem_object
*obj
;
4502 struct drm_i915_gem_object
*obj_priv
;
4504 obj
= dev_priv
->seqno_obj
;
4505 obj_priv
= to_intel_bo(obj
);
4506 kunmap(obj_priv
->pages
[0]);
4507 i915_gem_object_unpin(obj
);
4508 drm_gem_object_unreference(obj
);
4509 dev_priv
->seqno_obj
= NULL
;
4511 dev_priv
->seqno_page
= NULL
;
4515 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4517 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4520 if (HAS_PIPE_CONTROL(dev
)) {
4521 ret
= i915_gem_init_pipe_control(dev
);
4526 ret
= intel_init_render_ring_buffer(dev
);
4528 goto cleanup_pipe_control
;
4531 ret
= intel_init_bsd_ring_buffer(dev
);
4533 goto cleanup_render_ring
;
4536 dev_priv
->next_seqno
= 1;
4540 cleanup_render_ring
:
4541 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4542 cleanup_pipe_control
:
4543 if (HAS_PIPE_CONTROL(dev
))
4544 i915_gem_cleanup_pipe_control(dev
);
4549 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4551 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4553 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4555 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4556 if (HAS_PIPE_CONTROL(dev
))
4557 i915_gem_cleanup_pipe_control(dev
);
4561 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4562 struct drm_file
*file_priv
)
4564 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4567 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4570 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4571 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4572 atomic_set(&dev_priv
->mm
.wedged
, 0);
4575 mutex_lock(&dev
->struct_mutex
);
4576 dev_priv
->mm
.suspended
= 0;
4578 ret
= i915_gem_init_ringbuffer(dev
);
4580 mutex_unlock(&dev
->struct_mutex
);
4584 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4585 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4586 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4587 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4588 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4589 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4590 mutex_unlock(&dev
->struct_mutex
);
4592 ret
= drm_irq_install(dev
);
4594 goto cleanup_ringbuffer
;
4599 mutex_lock(&dev
->struct_mutex
);
4600 i915_gem_cleanup_ringbuffer(dev
);
4601 dev_priv
->mm
.suspended
= 1;
4602 mutex_unlock(&dev
->struct_mutex
);
4608 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4609 struct drm_file
*file_priv
)
4611 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4614 drm_irq_uninstall(dev
);
4615 return i915_gem_idle(dev
);
4619 i915_gem_lastclose(struct drm_device
*dev
)
4623 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4626 ret
= i915_gem_idle(dev
);
4628 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4632 i915_gem_load(struct drm_device
*dev
)
4635 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4637 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4638 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4639 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4640 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4641 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4642 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4643 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4644 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4646 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4647 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4649 for (i
= 0; i
< 16; i
++)
4650 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4651 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4652 i915_gem_retire_work_handler
);
4653 init_completion(&dev_priv
->error_completion
);
4654 spin_lock(&shrink_list_lock
);
4655 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4656 spin_unlock(&shrink_list_lock
);
4658 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4660 u32 tmp
= I915_READ(MI_ARB_STATE
);
4661 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4662 /* arb state is a masked write, so set bit + bit in mask */
4663 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4664 I915_WRITE(MI_ARB_STATE
, tmp
);
4668 /* Old X drivers will take 0-2 for front, back, depth buffers */
4669 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4670 dev_priv
->fence_reg_start
= 3;
4672 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4673 dev_priv
->num_fence_regs
= 16;
4675 dev_priv
->num_fence_regs
= 8;
4677 /* Initialize fence registers to zero */
4678 switch (INTEL_INFO(dev
)->gen
) {
4680 for (i
= 0; i
< 16; i
++)
4681 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4685 for (i
= 0; i
< 16; i
++)
4686 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4689 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4690 for (i
= 0; i
< 8; i
++)
4691 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4693 for (i
= 0; i
< 8; i
++)
4694 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4697 i915_gem_detect_bit_6_swizzle(dev
);
4698 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4702 * Create a physically contiguous memory object for this object
4703 * e.g. for cursor + overlay regs
4705 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4706 int id
, int size
, int align
)
4708 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4709 struct drm_i915_gem_phys_object
*phys_obj
;
4712 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4715 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4721 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4722 if (!phys_obj
->handle
) {
4727 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4730 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4738 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4740 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4741 struct drm_i915_gem_phys_object
*phys_obj
;
4743 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4746 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4747 if (phys_obj
->cur_obj
) {
4748 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4752 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4754 drm_pci_free(dev
, phys_obj
->handle
);
4756 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4759 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4763 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4764 i915_gem_free_phys_object(dev
, i
);
4767 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4768 struct drm_gem_object
*obj
)
4770 struct drm_i915_gem_object
*obj_priv
;
4775 obj_priv
= to_intel_bo(obj
);
4776 if (!obj_priv
->phys_obj
)
4779 ret
= i915_gem_object_get_pages(obj
, 0);
4783 page_count
= obj
->size
/ PAGE_SIZE
;
4785 for (i
= 0; i
< page_count
; i
++) {
4786 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4787 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4789 memcpy(dst
, src
, PAGE_SIZE
);
4790 kunmap_atomic(dst
, KM_USER0
);
4792 drm_clflush_pages(obj_priv
->pages
, page_count
);
4793 drm_agp_chipset_flush(dev
);
4795 i915_gem_object_put_pages(obj
);
4797 obj_priv
->phys_obj
->cur_obj
= NULL
;
4798 obj_priv
->phys_obj
= NULL
;
4802 i915_gem_attach_phys_object(struct drm_device
*dev
,
4803 struct drm_gem_object
*obj
,
4807 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4808 struct drm_i915_gem_object
*obj_priv
;
4813 if (id
> I915_MAX_PHYS_OBJECT
)
4816 obj_priv
= to_intel_bo(obj
);
4818 if (obj_priv
->phys_obj
) {
4819 if (obj_priv
->phys_obj
->id
== id
)
4821 i915_gem_detach_phys_object(dev
, obj
);
4824 /* create a new object */
4825 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4826 ret
= i915_gem_init_phys_object(dev
, id
,
4829 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4834 /* bind to the object */
4835 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4836 obj_priv
->phys_obj
->cur_obj
= obj
;
4838 ret
= i915_gem_object_get_pages(obj
, 0);
4840 DRM_ERROR("failed to get page list\n");
4844 page_count
= obj
->size
/ PAGE_SIZE
;
4846 for (i
= 0; i
< page_count
; i
++) {
4847 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4848 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4850 memcpy(dst
, src
, PAGE_SIZE
);
4851 kunmap_atomic(src
, KM_USER0
);
4854 i915_gem_object_put_pages(obj
);
4862 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4863 struct drm_i915_gem_pwrite
*args
,
4864 struct drm_file
*file_priv
)
4866 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4869 char __user
*user_data
;
4871 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4872 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4874 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4875 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4879 drm_agp_chipset_flush(dev
);
4883 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4885 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4887 /* Clean up our request list when the client is going away, so that
4888 * later retire_requests won't dereference our soon-to-be-gone
4891 spin_lock(&file_priv
->mm
.lock
);
4892 while (!list_empty(&file_priv
->mm
.request_list
)) {
4893 struct drm_i915_gem_request
*request
;
4895 request
= list_first_entry(&file_priv
->mm
.request_list
,
4896 struct drm_i915_gem_request
,
4898 list_del(&request
->client_list
);
4899 request
->file_priv
= NULL
;
4901 spin_unlock(&file_priv
->mm
.lock
);
4905 i915_gpu_is_active(struct drm_device
*dev
)
4907 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4910 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4911 list_empty(&dev_priv
->render_ring
.active_list
);
4913 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4915 return !lists_empty
;
4919 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4921 drm_i915_private_t
*dev_priv
, *next_dev
;
4922 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4924 int would_deadlock
= 1;
4926 /* "fast-path" to count number of available objects */
4927 if (nr_to_scan
== 0) {
4928 spin_lock(&shrink_list_lock
);
4929 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4930 struct drm_device
*dev
= dev_priv
->dev
;
4932 if (mutex_trylock(&dev
->struct_mutex
)) {
4933 list_for_each_entry(obj_priv
,
4934 &dev_priv
->mm
.inactive_list
,
4937 mutex_unlock(&dev
->struct_mutex
);
4940 spin_unlock(&shrink_list_lock
);
4942 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4945 spin_lock(&shrink_list_lock
);
4948 /* first scan for clean buffers */
4949 list_for_each_entry_safe(dev_priv
, next_dev
,
4950 &shrink_list
, mm
.shrink_list
) {
4951 struct drm_device
*dev
= dev_priv
->dev
;
4953 if (! mutex_trylock(&dev
->struct_mutex
))
4956 spin_unlock(&shrink_list_lock
);
4957 i915_gem_retire_requests(dev
);
4959 list_for_each_entry_safe(obj_priv
, next_obj
,
4960 &dev_priv
->mm
.inactive_list
,
4962 if (i915_gem_object_is_purgeable(obj_priv
)) {
4963 i915_gem_object_unbind(&obj_priv
->base
);
4964 if (--nr_to_scan
<= 0)
4969 spin_lock(&shrink_list_lock
);
4970 mutex_unlock(&dev
->struct_mutex
);
4974 if (nr_to_scan
<= 0)
4978 /* second pass, evict/count anything still on the inactive list */
4979 list_for_each_entry_safe(dev_priv
, next_dev
,
4980 &shrink_list
, mm
.shrink_list
) {
4981 struct drm_device
*dev
= dev_priv
->dev
;
4983 if (! mutex_trylock(&dev
->struct_mutex
))
4986 spin_unlock(&shrink_list_lock
);
4988 list_for_each_entry_safe(obj_priv
, next_obj
,
4989 &dev_priv
->mm
.inactive_list
,
4991 if (nr_to_scan
> 0) {
4992 i915_gem_object_unbind(&obj_priv
->base
);
4998 spin_lock(&shrink_list_lock
);
4999 mutex_unlock(&dev
->struct_mutex
);
5008 * We are desperate for pages, so as a last resort, wait
5009 * for the GPU to finish and discard whatever we can.
5010 * This has a dramatic impact to reduce the number of
5011 * OOM-killer events whilst running the GPU aggressively.
5013 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5014 struct drm_device
*dev
= dev_priv
->dev
;
5016 if (!mutex_trylock(&dev
->struct_mutex
))
5019 spin_unlock(&shrink_list_lock
);
5021 if (i915_gpu_is_active(dev
)) {
5026 spin_lock(&shrink_list_lock
);
5027 mutex_unlock(&dev
->struct_mutex
);
5034 spin_unlock(&shrink_list_lock
);
5039 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5044 static struct shrinker shrinker
= {
5045 .shrink
= i915_gem_shrink
,
5046 .seeks
= DEFAULT_SEEKS
,
5050 i915_gem_shrinker_init(void)
5052 register_shrinker(&shrinker
);
5056 i915_gem_shrinker_exit(void)
5058 unregister_shrinker(&shrinker
);