drivers/parisc/eisa.c

   1 /*
   2  * eisa.c - provide support for EISA adapters in PA-RISC machines
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  *
   9  * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
  10  * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
  11  *
  12  * There are two distinct EISA adapters.  Mongoose is found in machines
  13  * before the 712; then the Wax ASIC is used.  To complicate matters, the
  14  * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
  15  * dealt with elsewhere; this file is concerned only with the EISA portions
  16  * of Wax.
  17  *
  18  *
  19  * HINT:
  20  * -----
  21  * To allow an ISA card to work properly in the EISA slot you need to
  22  * set an edge trigger level. This may be done on the palo command line
  23  * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
  24  * n and n2 as the irq levels you want to use.
  25  *
  26  * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
  27  * irq levels 10 and 11.
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/ioport.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/eisa.h>
  38
  39 #include <asm/byteorder.h>
  40 #include <asm/io.h>
  41 #include <asm/hardware.h>
  42 #include <asm/processor.h>
  43 #include <asm/parisc-device.h>
  44 #include <asm/delay.h>
  45 #include <asm/eisa_bus.h>
  46 #include <asm/eisa_eeprom.h>
  47
  48 #if 0
  49 #define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
  50 #else
  51 #define EISA_DBG(msg, arg... )
  52 #endif
  53
  54 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
  55 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
  56
  57 static DEFINE_SPINLOCK(eisa_irq_lock);
  58
  59 void __iomem *eisa_eeprom_addr __read_mostly;
  60
  61 /* We can only have one EISA adapter in the system because neither
  62  * implementation can be flexed.
  63  */
  64 static struct eisa_ba {
  65         struct pci_hba_data     hba;
  66         unsigned long eeprom_addr;
  67         struct eisa_root_device root;
  68 } eisa_dev;
  69
  70 /* Port ops */
  71
  72 static inline unsigned long eisa_permute(unsigned short port)
  73 {
  74         if (port & 0x300) {
  75                 return 0xfc000000 | ((port & 0xfc00) >> 6)
  76                         | ((port & 0x3f8) << 9) | (port & 7);
  77         } else {
  78                 return 0xfc000000 | port;
  79         }
  80 }
  81
  82 unsigned char eisa_in8(unsigned short port)
  83 {
  84         if (EISA_bus)
  85                 return gsc_readb(eisa_permute(port));
  86         return 0xff;
  87 }
  88
  89 unsigned short eisa_in16(unsigned short port)
  90 {
  91         if (EISA_bus)
  92                 return le16_to_cpu(gsc_readw(eisa_permute(port)));
  93         return 0xffff;
  94 }
  95
  96 unsigned int eisa_in32(unsigned short port)
  97 {
  98         if (EISA_bus)
  99                 return le32_to_cpu(gsc_readl(eisa_permute(port)));
 100         return 0xffffffff;
 101 }
 102
 103 void eisa_out8(unsigned char data, unsigned short port)
 104 {
 105         if (EISA_bus)
 106                 gsc_writeb(data, eisa_permute(port));
 107 }
 108
 109 void eisa_out16(unsigned short data, unsigned short port)
 110 {
 111         if (EISA_bus)
 112                 gsc_writew(cpu_to_le16(data), eisa_permute(port));
 113 }
 114
 115 void eisa_out32(unsigned int data, unsigned short port)
 116 {
 117         if (EISA_bus)
 118                 gsc_writel(cpu_to_le32(data), eisa_permute(port));
 119 }
 120
 121 #ifndef CONFIG_PCI
 122 /* We call these directly without PCI.  See asm/io.h. */
 123 EXPORT_SYMBOL(eisa_in8);
 124 EXPORT_SYMBOL(eisa_in16);
 125 EXPORT_SYMBOL(eisa_in32);
 126 EXPORT_SYMBOL(eisa_out8);
 127 EXPORT_SYMBOL(eisa_out16);
 128 EXPORT_SYMBOL(eisa_out32);
 129 #endif
 130
 131 /* Interrupt handling */
 132
 133 /* cached interrupt mask registers */
 134 static int master_mask;
 135 static int slave_mask;
 136
 137 /* the trig level can be set with the
 138  * eisa_irq_edge=n,n,n commandline parameter
 139  * We should really read this from the EEPROM
 140  * in the furure.
 141  */
 142 /* irq 13,8,2,1,0 must be edge */
 143 static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
 144
 145
 146 /* called by free irq */
 147 static void eisa_mask_irq(unsigned int irq)
 148 {
 149         unsigned long flags;
 150
 151         EISA_DBG("disable irq %d\n", irq);
 152         /* just mask for now */
 153         spin_lock_irqsave(&eisa_irq_lock, flags);
 154         if (irq & 8) {
 155                 slave_mask |= (1 << (irq&7));
 156                 eisa_out8(slave_mask, 0xa1);
 157         } else {
 158                 master_mask |= (1 << (irq&7));
 159                 eisa_out8(master_mask, 0x21);
 160         }
 161         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 162         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
 163         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
 164 }
 165
 166 /* called by request irq */
 167 static void eisa_unmask_irq(unsigned int irq)
 168 {
 169         unsigned long flags;
 170         EISA_DBG("enable irq %d\n", irq);
 171
 172         spin_lock_irqsave(&eisa_irq_lock, flags);
 173         if (irq & 8) {
 174                 slave_mask &= ~(1 << (irq&7));
 175                 eisa_out8(slave_mask, 0xa1);
 176         } else {
 177                 master_mask &= ~(1 << (irq&7));
 178                 eisa_out8(master_mask, 0x21);
 179         }
 180         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 181         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
 182         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
 183 }
 184
 185 static struct irq_chip eisa_interrupt_type = {
 186         .name   =       "EISA",
 187         .unmask =       eisa_unmask_irq,
 188         .mask   =       eisa_mask_irq,
 189 };
 190
 191 static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
 192 {
 193         int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
 194         unsigned long flags;
 195
 196         spin_lock_irqsave(&eisa_irq_lock, flags);
 197         /* read IRR command */
 198         eisa_out8(0x0a, 0x20);
 199         eisa_out8(0x0a, 0xa0);
 200
 201         EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
 202                    irq, eisa_in8(0x20), eisa_in8(0xa0));
 203
 204         /* read ISR command */
 205         eisa_out8(0x0a, 0x20);
 206         eisa_out8(0x0a, 0xa0);
 207         EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
 208                  eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
 209
 210         irq &= 0xf;
 211
 212         /* mask irq and write eoi */
 213         if (irq & 8) {
 214                 slave_mask |= (1 << (irq&7));
 215                 eisa_out8(slave_mask, 0xa1);
 216                 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
 217                 eisa_out8(0x62,0x20);   /* 'Specific EOI' to master-IRQ2 */
 218
 219         } else {
 220                 master_mask |= (1 << (irq&7));
 221                 eisa_out8(master_mask, 0x21);
 222                 eisa_out8(0x60|irq,0x20);       /* 'Specific EOI' to master */
 223         }
 224         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 225
 226         generic_handle_irq(irq);
 227
 228         spin_lock_irqsave(&eisa_irq_lock, flags);
 229         /* unmask */
 230         if (irq & 8) {
 231                 slave_mask &= ~(1 << (irq&7));
 232                 eisa_out8(slave_mask, 0xa1);
 233         } else {
 234                 master_mask &= ~(1 << (irq&7));
 235                 eisa_out8(master_mask, 0x21);
 236         }
 237         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 238         return IRQ_HANDLED;
 239 }
 240
 241 static irqreturn_t dummy_irq2_handler(int _, void *dev)
 242 {
 243         printk(KERN_ALERT "eisa: uhh, irq2?\n");
 244         return IRQ_HANDLED;
 245 }
 246
 247 static struct irqaction irq2_action = {
 248         .handler = dummy_irq2_handler,
 249         .name = "cascade",
 250 };
 251
 252 static void init_eisa_pic(void)
 253 {
 254         unsigned long flags;
 255
 256         spin_lock_irqsave(&eisa_irq_lock, flags);
 257
 258         eisa_out8(0xff, 0x21); /* mask during init */
 259         eisa_out8(0xff, 0xa1); /* mask during init */
 260
 261         /* master pic */
 262         eisa_out8(0x11,0x20); /* ICW1 */
 263         eisa_out8(0x00,0x21); /* ICW2 */
 264         eisa_out8(0x04,0x21); /* ICW3 */
 265         eisa_out8(0x01,0x21); /* ICW4 */
 266         eisa_out8(0x40,0x20); /* OCW2 */
 267
 268         /* slave pic */
 269         eisa_out8(0x11,0xa0); /* ICW1 */
 270         eisa_out8(0x08,0xa1); /* ICW2 */
 271         eisa_out8(0x02,0xa1); /* ICW3 */
 272         eisa_out8(0x01,0xa1); /* ICW4 */
 273         eisa_out8(0x40,0xa0); /* OCW2 */
 274
 275         udelay(100);
 276
 277         slave_mask = 0xff;
 278         master_mask = 0xfb;
 279         eisa_out8(slave_mask, 0xa1); /* OCW1 */
 280         eisa_out8(master_mask, 0x21); /* OCW1 */
 281
 282         /* setup trig level */
 283         EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
 284
 285         eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge  */
 286         eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
 287
 288         EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
 289         EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
 290         EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
 291         EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
 292
 293         spin_unlock_irqrestore(&eisa_irq_lock, flags);
 294 }
 295
 296 /* Device initialisation */
 297
 298 #define is_mongoose(dev) (dev->id.sversion == 0x00076)
 299
 300 static int __init eisa_probe(struct parisc_device *dev)
 301 {
 302         int i, result;
 303
 304         char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
 305
 306         printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
 307                 name, (unsigned long)dev->hpa.start);
 308
 309         eisa_dev.hba.dev = dev;
 310         eisa_dev.hba.iommu = ccio_get_iommu(dev);
 311
 312         eisa_dev.hba.lmmio_space.name = "EISA";
 313         eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
 314         eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
 315         eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
 316         result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
 317         if (result < 0) {
 318                 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
 319                 return result;
 320         }
 321         eisa_dev.hba.io_space.name = "EISA";
 322         eisa_dev.hba.io_space.start = 0;
 323         eisa_dev.hba.io_space.end = 0xffff;
 324         eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
 325         result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
 326         if (result < 0) {
 327                 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
 328                 return result;
 329         }
 330         pcibios_register_hba(&eisa_dev.hba);
 331
 332         result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
 333         if (result) {
 334                 printk(KERN_ERR "EISA: request_irq failed!\n");
 335                 return result;
 336         }
 337
 338         /* Reserve IRQ2 */
 339         setup_irq(2, &irq2_action);
 340         for (i = 0; i < 16; i++) {
 341                 set_irq_chip_and_handler(i, &eisa_interrupt_type,
 342                                          handle_simple_irq);
 343         }
 344
 345         EISA_bus = 1;
 346
 347         if (dev->num_addrs) {
 348                 /* newer firmware hand out the eeprom address */
 349                 eisa_dev.eeprom_addr = dev->addr[0];
 350         } else {
 351                 /* old firmware, need to figure out the box */
 352                 if (is_mongoose(dev)) {
 353                         eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
 354                 } else {
 355                         eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
 356                 }
 357         }
 358         eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
 359         result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
 360                         &eisa_dev.hba.lmmio_space);
 361         init_eisa_pic();
 362
 363         if (result >= 0) {
 364                 /* FIXME : Don't enumerate the bus twice. */
 365                 eisa_dev.root.dev = &dev->dev;
 366                 dev_set_drvdata(&dev->dev, &eisa_dev.root);
 367                 eisa_dev.root.bus_base_addr = 0;
 368                 eisa_dev.root.res = &eisa_dev.hba.io_space;
 369                 eisa_dev.root.slots = result;
 370                 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
 371                 if (eisa_root_register (&eisa_dev.root)) {
 372                         printk(KERN_ERR "EISA: Failed to register EISA root\n");
 373                         return -1;
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379
 380 static const struct parisc_device_id eisa_tbl[] = {
 381         { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
 382         { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
 383         { 0, }
 384 };
 385
 386 MODULE_DEVICE_TABLE(parisc, eisa_tbl);
 387
 388 static struct parisc_driver eisa_driver = {
 389         .name =         "eisa_ba",
 390         .id_table =     eisa_tbl,
 391         .probe =        eisa_probe,
 392 };
 393
 394 void __init eisa_init(void)
 395 {
 396         register_parisc_driver(&eisa_driver);
 397 }
 398
 399
 400 static unsigned int eisa_irq_configured;
 401 void eisa_make_irq_level(int num)
 402 {
 403         if (eisa_irq_configured& (1<<num)) {
 404                 printk(KERN_WARNING
 405                        "IRQ %d polarity configured twice (last to level)\n",
 406                        num);
 407         }
 408         eisa_irq_level |= (1<<num); /* set the corresponding bit */
 409         eisa_irq_configured |= (1<<num); /* set the corresponding bit */
 410 }
 411
 412 void eisa_make_irq_edge(int num)
 413 {
 414         if (eisa_irq_configured& (1<<num)) {
 415                 printk(KERN_WARNING
 416                        "IRQ %d polarity configured twice (last to edge)\n",
 417                        num);
 418         }
 419         eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
 420         eisa_irq_configured |= (1<<num); /* set the corresponding bit */
 421 }
 422
 423 static int __init eisa_irq_setup(char *str)
 424 {
 425         char *cur = str;
 426         int val;
 427
 428         EISA_DBG("IRQ setup\n");
 429         while (cur != NULL) {
 430                 char *pe;
 431
 432                 val = (int) simple_strtoul(cur, &pe, 0);
 433                 if (val > 15 || val < 0) {
 434                         printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
 435                         continue;
 436                 }
 437                 if (val == 2) {
 438                         val = 9;
 439                 }
 440                 eisa_make_irq_edge(val); /* clear the corresponding bit */
 441                 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
 442
 443                 if ((cur = strchr(cur, ','))) {
 444                         cur++;
 445                 } else {
 446                         break;
 447                 }
 448         }
 449         return 1;
 450 }
 451
 452 __setup("eisa_irq_edge=", eisa_irq_setup);
 453