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drm/radeon/kms: pageflipping cleanup for avivo+
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
blob0b0cc74c08c0834359601e2ba2fe9bd2171aa983
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
45 {
46 /* enable the pflip int */
47 radeon_irq_kms_pflip_irq_get(rdev, crtc);
48 }
49
50 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
51 {
52 /* disable the pflip int */
53 radeon_irq_kms_pflip_irq_put(rdev, crtc);
54 }
55
56 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
57 {
58 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
59 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
60
61 /* Lock the graphics update lock */
62 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
63 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
64
65 /* update the scanout addresses */
66 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
67 upper_32_bits(crtc_base));
68 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
69 (u32)crtc_base);
70
71 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
72 upper_32_bits(crtc_base));
73 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
74 (u32)crtc_base);
75
76 /* Wait for update_pending to go high. */
77 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
79
80 /* Unlock the lock, so double-buffering can take place inside vblank */
81 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
82 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
83
84 /* Return current update_pending status: */
85 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
86 }
87
88 /* get temperature in millidegrees */
89 int evergreen_get_temp(struct radeon_device *rdev)
90 {
91 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
92 ASIC_T_SHIFT;
93 u32 actual_temp = 0;
94
95 if (temp & 0x400)
96 actual_temp = -256;
97 else if (temp & 0x200)
98 actual_temp = 255;
99 else if (temp & 0x100) {
100 actual_temp = temp & 0x1ff;
101 actual_temp |= ~0x1ff;
102 } else
103 actual_temp = temp & 0xff;
104
105 return (actual_temp * 1000) / 2;
106 }
107
108 int sumo_get_temp(struct radeon_device *rdev)
109 {
110 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
111 int actual_temp = temp - 49;
112
113 return actual_temp * 1000;
114 }
115
116 void evergreen_pm_misc(struct radeon_device *rdev)
117 {
118 int req_ps_idx = rdev->pm.requested_power_state_index;
119 int req_cm_idx = rdev->pm.requested_clock_mode_index;
120 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
121 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
122
123 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
124 if (voltage->voltage != rdev->pm.current_vddc) {
125 radeon_atom_set_voltage(rdev, voltage->voltage);
126 rdev->pm.current_vddc = voltage->voltage;
127 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
128 }
129 }
130 }
131
132 void evergreen_pm_prepare(struct radeon_device *rdev)
133 {
134 struct drm_device *ddev = rdev->ddev;
135 struct drm_crtc *crtc;
136 struct radeon_crtc *radeon_crtc;
137 u32 tmp;
138
139 /* disable any active CRTCs */
140 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
141 radeon_crtc = to_radeon_crtc(crtc);
142 if (radeon_crtc->enabled) {
143 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
144 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
145 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
146 }
147 }
148 }
149
150 void evergreen_pm_finish(struct radeon_device *rdev)
151 {
152 struct drm_device *ddev = rdev->ddev;
153 struct drm_crtc *crtc;
154 struct radeon_crtc *radeon_crtc;
155 u32 tmp;
156
157 /* enable any active CRTCs */
158 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
159 radeon_crtc = to_radeon_crtc(crtc);
160 if (radeon_crtc->enabled) {
161 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
162 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
163 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
164 }
165 }
166 }
167
168 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
169 {
170 bool connected = false;
171
172 switch (hpd) {
173 case RADEON_HPD_1:
174 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
175 connected = true;
176 break;
177 case RADEON_HPD_2:
178 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
179 connected = true;
180 break;
181 case RADEON_HPD_3:
182 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
183 connected = true;
184 break;
185 case RADEON_HPD_4:
186 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
187 connected = true;
188 break;
189 case RADEON_HPD_5:
190 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
191 connected = true;
192 break;
193 case RADEON_HPD_6:
194 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
195 connected = true;
196 break;
197 default:
198 break;
199 }
200
201 return connected;
202 }
203
204 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
205 enum radeon_hpd_id hpd)
206 {
207 u32 tmp;
208 bool connected = evergreen_hpd_sense(rdev, hpd);
209
210 switch (hpd) {
211 case RADEON_HPD_1:
212 tmp = RREG32(DC_HPD1_INT_CONTROL);
213 if (connected)
214 tmp &= ~DC_HPDx_INT_POLARITY;
215 else
216 tmp |= DC_HPDx_INT_POLARITY;
217 WREG32(DC_HPD1_INT_CONTROL, tmp);
218 break;
219 case RADEON_HPD_2:
220 tmp = RREG32(DC_HPD2_INT_CONTROL);
221 if (connected)
222 tmp &= ~DC_HPDx_INT_POLARITY;
223 else
224 tmp |= DC_HPDx_INT_POLARITY;
225 WREG32(DC_HPD2_INT_CONTROL, tmp);
226 break;
227 case RADEON_HPD_3:
228 tmp = RREG32(DC_HPD3_INT_CONTROL);
229 if (connected)
230 tmp &= ~DC_HPDx_INT_POLARITY;
231 else
232 tmp |= DC_HPDx_INT_POLARITY;
233 WREG32(DC_HPD3_INT_CONTROL, tmp);
234 break;
235 case RADEON_HPD_4:
236 tmp = RREG32(DC_HPD4_INT_CONTROL);
237 if (connected)
238 tmp &= ~DC_HPDx_INT_POLARITY;
239 else
240 tmp |= DC_HPDx_INT_POLARITY;
241 WREG32(DC_HPD4_INT_CONTROL, tmp);
242 break;
243 case RADEON_HPD_5:
244 tmp = RREG32(DC_HPD5_INT_CONTROL);
245 if (connected)
246 tmp &= ~DC_HPDx_INT_POLARITY;
247 else
248 tmp |= DC_HPDx_INT_POLARITY;
249 WREG32(DC_HPD5_INT_CONTROL, tmp);
250 break;
251 case RADEON_HPD_6:
252 tmp = RREG32(DC_HPD6_INT_CONTROL);
253 if (connected)
254 tmp &= ~DC_HPDx_INT_POLARITY;
255 else
256 tmp |= DC_HPDx_INT_POLARITY;
257 WREG32(DC_HPD6_INT_CONTROL, tmp);
258 break;
259 default:
260 break;
261 }
262 }
263
264 void evergreen_hpd_init(struct radeon_device *rdev)
265 {
266 struct drm_device *dev = rdev->ddev;
267 struct drm_connector *connector;
268 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
269 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
270
271 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
272 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
273 switch (radeon_connector->hpd.hpd) {
274 case RADEON_HPD_1:
275 WREG32(DC_HPD1_CONTROL, tmp);
276 rdev->irq.hpd[0] = true;
277 break;
278 case RADEON_HPD_2:
279 WREG32(DC_HPD2_CONTROL, tmp);
280 rdev->irq.hpd[1] = true;
281 break;
282 case RADEON_HPD_3:
283 WREG32(DC_HPD3_CONTROL, tmp);
284 rdev->irq.hpd[2] = true;
285 break;
286 case RADEON_HPD_4:
287 WREG32(DC_HPD4_CONTROL, tmp);
288 rdev->irq.hpd[3] = true;
289 break;
290 case RADEON_HPD_5:
291 WREG32(DC_HPD5_CONTROL, tmp);
292 rdev->irq.hpd[4] = true;
293 break;
294 case RADEON_HPD_6:
295 WREG32(DC_HPD6_CONTROL, tmp);
296 rdev->irq.hpd[5] = true;
297 break;
298 default:
299 break;
300 }
301 }
302 if (rdev->irq.installed)
303 evergreen_irq_set(rdev);
304 }
305
306 void evergreen_hpd_fini(struct radeon_device *rdev)
307 {
308 struct drm_device *dev = rdev->ddev;
309 struct drm_connector *connector;
310
311 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
312 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
313 switch (radeon_connector->hpd.hpd) {
314 case RADEON_HPD_1:
315 WREG32(DC_HPD1_CONTROL, 0);
316 rdev->irq.hpd[0] = false;
317 break;
318 case RADEON_HPD_2:
319 WREG32(DC_HPD2_CONTROL, 0);
320 rdev->irq.hpd[1] = false;
321 break;
322 case RADEON_HPD_3:
323 WREG32(DC_HPD3_CONTROL, 0);
324 rdev->irq.hpd[2] = false;
325 break;
326 case RADEON_HPD_4:
327 WREG32(DC_HPD4_CONTROL, 0);
328 rdev->irq.hpd[3] = false;
329 break;
330 case RADEON_HPD_5:
331 WREG32(DC_HPD5_CONTROL, 0);
332 rdev->irq.hpd[4] = false;
333 break;
334 case RADEON_HPD_6:
335 WREG32(DC_HPD6_CONTROL, 0);
336 rdev->irq.hpd[5] = false;
337 break;
338 default:
339 break;
340 }
341 }
342 }
343
344 /* watermark setup */
345
346 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
347 struct radeon_crtc *radeon_crtc,
348 struct drm_display_mode *mode,
349 struct drm_display_mode *other_mode)
350 {
351 u32 tmp = 0;
352 /*
353 * Line Buffer Setup
354 * There are 3 line buffers, each one shared by 2 display controllers.
355 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
356 * the display controllers. The paritioning is done via one of four
357 * preset allocations specified in bits 2:0:
358 * first display controller
359 * 0 - first half of lb (3840 * 2)
360 * 1 - first 3/4 of lb (5760 * 2)
361 * 2 - whole lb (7680 * 2)
362 * 3 - first 1/4 of lb (1920 * 2)
363 * second display controller
364 * 4 - second half of lb (3840 * 2)
365 * 5 - second 3/4 of lb (5760 * 2)
366 * 6 - whole lb (7680 * 2)
367 * 7 - last 1/4 of lb (1920 * 2)
368 */
369 if (mode && other_mode) {
370 if (mode->hdisplay > other_mode->hdisplay) {
371 if (mode->hdisplay > 2560)
372 tmp = 1; /* 3/4 */
373 else
374 tmp = 0; /* 1/2 */
375 } else if (other_mode->hdisplay > mode->hdisplay) {
376 if (other_mode->hdisplay > 2560)
377 tmp = 3; /* 1/4 */
378 else
379 tmp = 0; /* 1/2 */
380 } else
381 tmp = 0; /* 1/2 */
382 } else if (mode)
383 tmp = 2; /* whole */
384 else if (other_mode)
385 tmp = 3; /* 1/4 */
386
387 /* second controller of the pair uses second half of the lb */
388 if (radeon_crtc->crtc_id % 2)
389 tmp += 4;
390 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
391
392 switch (tmp) {
393 case 0:
394 case 4:
395 default:
396 if (ASIC_IS_DCE5(rdev))
397 return 4096 * 2;
398 else
399 return 3840 * 2;
400 case 1:
401 case 5:
402 if (ASIC_IS_DCE5(rdev))
403 return 6144 * 2;
404 else
405 return 5760 * 2;
406 case 2:
407 case 6:
408 if (ASIC_IS_DCE5(rdev))
409 return 8192 * 2;
410 else
411 return 7680 * 2;
412 case 3:
413 case 7:
414 if (ASIC_IS_DCE5(rdev))
415 return 2048 * 2;
416 else
417 return 1920 * 2;
418 }
419 }
420
421 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
422 {
423 u32 tmp = RREG32(MC_SHARED_CHMAP);
424
425 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
426 case 0:
427 default:
428 return 1;
429 case 1:
430 return 2;
431 case 2:
432 return 4;
433 case 3:
434 return 8;
435 }
436 }
437
438 struct evergreen_wm_params {
439 u32 dram_channels; /* number of dram channels */
440 u32 yclk; /* bandwidth per dram data pin in kHz */
441 u32 sclk; /* engine clock in kHz */
442 u32 disp_clk; /* display clock in kHz */
443 u32 src_width; /* viewport width */
444 u32 active_time; /* active display time in ns */
445 u32 blank_time; /* blank time in ns */
446 bool interlaced; /* mode is interlaced */
447 fixed20_12 vsc; /* vertical scale ratio */
448 u32 num_heads; /* number of active crtcs */
449 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
450 u32 lb_size; /* line buffer allocated to pipe */
451 u32 vtaps; /* vertical scaler taps */
452 };
453
454 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
455 {
456 /* Calculate DRAM Bandwidth and the part allocated to display. */
457 fixed20_12 dram_efficiency; /* 0.7 */
458 fixed20_12 yclk, dram_channels, bandwidth;
459 fixed20_12 a;
460
461 a.full = dfixed_const(1000);
462 yclk.full = dfixed_const(wm->yclk);
463 yclk.full = dfixed_div(yclk, a);
464 dram_channels.full = dfixed_const(wm->dram_channels * 4);
465 a.full = dfixed_const(10);
466 dram_efficiency.full = dfixed_const(7);
467 dram_efficiency.full = dfixed_div(dram_efficiency, a);
468 bandwidth.full = dfixed_mul(dram_channels, yclk);
469 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
470
471 return dfixed_trunc(bandwidth);
472 }
473
474 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
475 {
476 /* Calculate DRAM Bandwidth and the part allocated to display. */
477 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
478 fixed20_12 yclk, dram_channels, bandwidth;
479 fixed20_12 a;
480
481 a.full = dfixed_const(1000);
482 yclk.full = dfixed_const(wm->yclk);
483 yclk.full = dfixed_div(yclk, a);
484 dram_channels.full = dfixed_const(wm->dram_channels * 4);
485 a.full = dfixed_const(10);
486 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
487 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
488 bandwidth.full = dfixed_mul(dram_channels, yclk);
489 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
490
491 return dfixed_trunc(bandwidth);
492 }
493
494 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
495 {
496 /* Calculate the display Data return Bandwidth */
497 fixed20_12 return_efficiency; /* 0.8 */
498 fixed20_12 sclk, bandwidth;
499 fixed20_12 a;
500
501 a.full = dfixed_const(1000);
502 sclk.full = dfixed_const(wm->sclk);
503 sclk.full = dfixed_div(sclk, a);
504 a.full = dfixed_const(10);
505 return_efficiency.full = dfixed_const(8);
506 return_efficiency.full = dfixed_div(return_efficiency, a);
507 a.full = dfixed_const(32);
508 bandwidth.full = dfixed_mul(a, sclk);
509 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
510
511 return dfixed_trunc(bandwidth);
512 }
513
514 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
515 {
516 /* Calculate the DMIF Request Bandwidth */
517 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
518 fixed20_12 disp_clk, bandwidth;
519 fixed20_12 a;
520
521 a.full = dfixed_const(1000);
522 disp_clk.full = dfixed_const(wm->disp_clk);
523 disp_clk.full = dfixed_div(disp_clk, a);
524 a.full = dfixed_const(10);
525 disp_clk_request_efficiency.full = dfixed_const(8);
526 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
527 a.full = dfixed_const(32);
528 bandwidth.full = dfixed_mul(a, disp_clk);
529 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
530
531 return dfixed_trunc(bandwidth);
532 }
533
534 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
535 {
536 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
537 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
538 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
539 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
540
541 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
542 }
543
544 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
545 {
546 /* Calculate the display mode Average Bandwidth
547 * DisplayMode should contain the source and destination dimensions,
548 * timing, etc.
549 */
550 fixed20_12 bpp;
551 fixed20_12 line_time;
552 fixed20_12 src_width;
553 fixed20_12 bandwidth;
554 fixed20_12 a;
555
556 a.full = dfixed_const(1000);
557 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
558 line_time.full = dfixed_div(line_time, a);
559 bpp.full = dfixed_const(wm->bytes_per_pixel);
560 src_width.full = dfixed_const(wm->src_width);
561 bandwidth.full = dfixed_mul(src_width, bpp);
562 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
563 bandwidth.full = dfixed_div(bandwidth, line_time);
564
565 return dfixed_trunc(bandwidth);
566 }
567
568 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
569 {
570 /* First calcualte the latency in ns */
571 u32 mc_latency = 2000; /* 2000 ns. */
572 u32 available_bandwidth = evergreen_available_bandwidth(wm);
573 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
574 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
575 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
576 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
577 (wm->num_heads * cursor_line_pair_return_time);
578 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
579 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
580 fixed20_12 a, b, c;
581
582 if (wm->num_heads == 0)
583 return 0;
584
585 a.full = dfixed_const(2);
586 b.full = dfixed_const(1);
587 if ((wm->vsc.full > a.full) ||
588 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
589 (wm->vtaps >= 5) ||
590 ((wm->vsc.full >= a.full) && wm->interlaced))
591 max_src_lines_per_dst_line = 4;
592 else
593 max_src_lines_per_dst_line = 2;
594
595 a.full = dfixed_const(available_bandwidth);
596 b.full = dfixed_const(wm->num_heads);
597 a.full = dfixed_div(a, b);
598
599 b.full = dfixed_const(1000);
600 c.full = dfixed_const(wm->disp_clk);
601 b.full = dfixed_div(c, b);
602 c.full = dfixed_const(wm->bytes_per_pixel);
603 b.full = dfixed_mul(b, c);
604
605 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
606
607 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
608 b.full = dfixed_const(1000);
609 c.full = dfixed_const(lb_fill_bw);
610 b.full = dfixed_div(c, b);
611 a.full = dfixed_div(a, b);
612 line_fill_time = dfixed_trunc(a);
613
614 if (line_fill_time < wm->active_time)
615 return latency;
616 else
617 return latency + (line_fill_time - wm->active_time);
618
619 }
620
621 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
622 {
623 if (evergreen_average_bandwidth(wm) <=
624 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
625 return true;
626 else
627 return false;
628 };
629
630 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
631 {
632 if (evergreen_average_bandwidth(wm) <=
633 (evergreen_available_bandwidth(wm) / wm->num_heads))
634 return true;
635 else
636 return false;
637 };
638
639 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
640 {
641 u32 lb_partitions = wm->lb_size / wm->src_width;
642 u32 line_time = wm->active_time + wm->blank_time;
643 u32 latency_tolerant_lines;
644 u32 latency_hiding;
645 fixed20_12 a;
646
647 a.full = dfixed_const(1);
648 if (wm->vsc.full > a.full)
649 latency_tolerant_lines = 1;
650 else {
651 if (lb_partitions <= (wm->vtaps + 1))
652 latency_tolerant_lines = 1;
653 else
654 latency_tolerant_lines = 2;
655 }
656
657 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
658
659 if (evergreen_latency_watermark(wm) <= latency_hiding)
660 return true;
661 else
662 return false;
663 }
664
665 static void evergreen_program_watermarks(struct radeon_device *rdev,
666 struct radeon_crtc *radeon_crtc,
667 u32 lb_size, u32 num_heads)
668 {
669 struct drm_display_mode *mode = &radeon_crtc->base.mode;
670 struct evergreen_wm_params wm;
671 u32 pixel_period;
672 u32 line_time = 0;
673 u32 latency_watermark_a = 0, latency_watermark_b = 0;
674 u32 priority_a_mark = 0, priority_b_mark = 0;
675 u32 priority_a_cnt = PRIORITY_OFF;
676 u32 priority_b_cnt = PRIORITY_OFF;
677 u32 pipe_offset = radeon_crtc->crtc_id * 16;
678 u32 tmp, arb_control3;
679 fixed20_12 a, b, c;
680
681 if (radeon_crtc->base.enabled && num_heads && mode) {
682 pixel_period = 1000000 / (u32)mode->clock;
683 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
684 priority_a_cnt = 0;
685 priority_b_cnt = 0;
686
687 wm.yclk = rdev->pm.current_mclk * 10;
688 wm.sclk = rdev->pm.current_sclk * 10;
689 wm.disp_clk = mode->clock;
690 wm.src_width = mode->crtc_hdisplay;
691 wm.active_time = mode->crtc_hdisplay * pixel_period;
692 wm.blank_time = line_time - wm.active_time;
693 wm.interlaced = false;
694 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
695 wm.interlaced = true;
696 wm.vsc = radeon_crtc->vsc;
697 wm.vtaps = 1;
698 if (radeon_crtc->rmx_type != RMX_OFF)
699 wm.vtaps = 2;
700 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
701 wm.lb_size = lb_size;
702 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
703 wm.num_heads = num_heads;
704
705 /* set for high clocks */
706 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
707 /* set for low clocks */
708 /* wm.yclk = low clk; wm.sclk = low clk */
709 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
710
711 /* possibly force display priority to high */
712 /* should really do this at mode validation time... */
713 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
714 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
715 !evergreen_check_latency_hiding(&wm) ||
716 (rdev->disp_priority == 2)) {
717 DRM_INFO("force priority to high\n");
718 priority_a_cnt |= PRIORITY_ALWAYS_ON;
719 priority_b_cnt |= PRIORITY_ALWAYS_ON;
720 }
721
722 a.full = dfixed_const(1000);
723 b.full = dfixed_const(mode->clock);
724 b.full = dfixed_div(b, a);
725 c.full = dfixed_const(latency_watermark_a);
726 c.full = dfixed_mul(c, b);
727 c.full = dfixed_mul(c, radeon_crtc->hsc);
728 c.full = dfixed_div(c, a);
729 a.full = dfixed_const(16);
730 c.full = dfixed_div(c, a);
731 priority_a_mark = dfixed_trunc(c);
732 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
733
734 a.full = dfixed_const(1000);
735 b.full = dfixed_const(mode->clock);
736 b.full = dfixed_div(b, a);
737 c.full = dfixed_const(latency_watermark_b);
738 c.full = dfixed_mul(c, b);
739 c.full = dfixed_mul(c, radeon_crtc->hsc);
740 c.full = dfixed_div(c, a);
741 a.full = dfixed_const(16);
742 c.full = dfixed_div(c, a);
743 priority_b_mark = dfixed_trunc(c);
744 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
745 }
746
747 /* select wm A */
748 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
749 tmp = arb_control3;
750 tmp &= ~LATENCY_WATERMARK_MASK(3);
751 tmp |= LATENCY_WATERMARK_MASK(1);
752 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
753 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
754 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
755 LATENCY_HIGH_WATERMARK(line_time)));
756 /* select wm B */
757 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
758 tmp &= ~LATENCY_WATERMARK_MASK(3);
759 tmp |= LATENCY_WATERMARK_MASK(2);
760 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
761 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
762 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
763 LATENCY_HIGH_WATERMARK(line_time)));
764 /* restore original selection */
765 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
766
767 /* write the priority marks */
768 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
769 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
770
771 }
772
773 void evergreen_bandwidth_update(struct radeon_device *rdev)
774 {
775 struct drm_display_mode *mode0 = NULL;
776 struct drm_display_mode *mode1 = NULL;
777 u32 num_heads = 0, lb_size;
778 int i;
779
780 radeon_update_display_priority(rdev);
781
782 for (i = 0; i < rdev->num_crtc; i++) {
783 if (rdev->mode_info.crtcs[i]->base.enabled)
784 num_heads++;
785 }
786 for (i = 0; i < rdev->num_crtc; i += 2) {
787 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
788 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
789 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
790 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
791 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
792 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
793 }
794 }
795
796 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
797 {
798 unsigned i;
799 u32 tmp;
800
801 for (i = 0; i < rdev->usec_timeout; i++) {
802 /* read MC_STATUS */
803 tmp = RREG32(SRBM_STATUS) & 0x1F00;
804 if (!tmp)
805 return 0;
806 udelay(1);
807 }
808 return -1;
809 }
810
811 /*
812 * GART
813 */
814 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
815 {
816 unsigned i;
817 u32 tmp;
818
819 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
820
821 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
822 for (i = 0; i < rdev->usec_timeout; i++) {
823 /* read MC_STATUS */
824 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
825 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
826 if (tmp == 2) {
827 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
828 return;
829 }
830 if (tmp) {
831 return;
832 }
833 udelay(1);
834 }
835 }
836
837 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
838 {
839 u32 tmp;
840 int r;
841
842 if (rdev->gart.table.vram.robj == NULL) {
843 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
844 return -EINVAL;
845 }
846 r = radeon_gart_table_vram_pin(rdev);
847 if (r)
848 return r;
849 radeon_gart_restore(rdev);
850 /* Setup L2 cache */
851 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
852 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
853 EFFECTIVE_L2_QUEUE_SIZE(7));
854 WREG32(VM_L2_CNTL2, 0);
855 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
856 /* Setup TLB control */
857 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
858 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
859 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
860 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
861 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
862 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
863 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
864 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
865 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
866 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
867 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
868 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
869 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
870 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
871 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
872 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
873 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
874 (u32)(rdev->dummy_page.addr >> 12));
875 WREG32(VM_CONTEXT1_CNTL, 0);
876
877 evergreen_pcie_gart_tlb_flush(rdev);
878 rdev->gart.ready = true;
879 return 0;
880 }
881
882 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
883 {
884 u32 tmp;
885 int r;
886
887 /* Disable all tables */
888 WREG32(VM_CONTEXT0_CNTL, 0);
889 WREG32(VM_CONTEXT1_CNTL, 0);
890
891 /* Setup L2 cache */
892 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
893 EFFECTIVE_L2_QUEUE_SIZE(7));
894 WREG32(VM_L2_CNTL2, 0);
895 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
896 /* Setup TLB control */
897 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
898 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
899 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
900 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
901 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
902 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
903 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
904 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
905 if (rdev->gart.table.vram.robj) {
906 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
907 if (likely(r == 0)) {
908 radeon_bo_kunmap(rdev->gart.table.vram.robj);
909 radeon_bo_unpin(rdev->gart.table.vram.robj);
910 radeon_bo_unreserve(rdev->gart.table.vram.robj);
911 }
912 }
913 }
914
915 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
916 {
917 evergreen_pcie_gart_disable(rdev);
918 radeon_gart_table_vram_free(rdev);
919 radeon_gart_fini(rdev);
920 }
921
922
923 void evergreen_agp_enable(struct radeon_device *rdev)
924 {
925 u32 tmp;
926
927 /* Setup L2 cache */
928 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
929 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
930 EFFECTIVE_L2_QUEUE_SIZE(7));
931 WREG32(VM_L2_CNTL2, 0);
932 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
933 /* Setup TLB control */
934 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
935 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
936 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
937 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
938 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
939 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
940 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
941 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
942 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
943 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
944 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
945 WREG32(VM_CONTEXT0_CNTL, 0);
946 WREG32(VM_CONTEXT1_CNTL, 0);
947 }
948
949 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
950 {
951 save->vga_control[0] = RREG32(D1VGA_CONTROL);
952 save->vga_control[1] = RREG32(D2VGA_CONTROL);
953 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
954 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
955 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
956 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
957 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
958 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
959 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
960 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
961 if (!(rdev->flags & RADEON_IS_IGP)) {
962 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
963 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
964 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
965 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
966 }
967
968 /* Stop all video */
969 WREG32(VGA_RENDER_CONTROL, 0);
970 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
971 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
972 if (!(rdev->flags & RADEON_IS_IGP)) {
973 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
974 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
975 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
976 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
977 }
978 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
979 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
980 if (!(rdev->flags & RADEON_IS_IGP)) {
981 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
982 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
983 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
984 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
985 }
986 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
987 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
988 if (!(rdev->flags & RADEON_IS_IGP)) {
989 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
990 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
991 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
992 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
993 }
994
995 WREG32(D1VGA_CONTROL, 0);
996 WREG32(D2VGA_CONTROL, 0);
997 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
998 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
999 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1000 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1001 }
1002
1003 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1004 {
1005 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1006 upper_32_bits(rdev->mc.vram_start));
1007 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1008 upper_32_bits(rdev->mc.vram_start));
1009 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1010 (u32)rdev->mc.vram_start);
1011 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1012 (u32)rdev->mc.vram_start);
1013
1014 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1015 upper_32_bits(rdev->mc.vram_start));
1016 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1017 upper_32_bits(rdev->mc.vram_start));
1018 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1019 (u32)rdev->mc.vram_start);
1020 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1021 (u32)rdev->mc.vram_start);
1022
1023 if (!(rdev->flags & RADEON_IS_IGP)) {
1024 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1025 upper_32_bits(rdev->mc.vram_start));
1026 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1027 upper_32_bits(rdev->mc.vram_start));
1028 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1029 (u32)rdev->mc.vram_start);
1030 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1031 (u32)rdev->mc.vram_start);
1032
1033 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1034 upper_32_bits(rdev->mc.vram_start));
1035 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1036 upper_32_bits(rdev->mc.vram_start));
1037 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1038 (u32)rdev->mc.vram_start);
1039 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1040 (u32)rdev->mc.vram_start);
1041
1042 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1043 upper_32_bits(rdev->mc.vram_start));
1044 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1045 upper_32_bits(rdev->mc.vram_start));
1046 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1047 (u32)rdev->mc.vram_start);
1048 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1049 (u32)rdev->mc.vram_start);
1050
1051 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1052 upper_32_bits(rdev->mc.vram_start));
1053 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1054 upper_32_bits(rdev->mc.vram_start));
1055 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1056 (u32)rdev->mc.vram_start);
1057 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1058 (u32)rdev->mc.vram_start);
1059 }
1060
1061 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1062 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1063 /* Unlock host access */
1064 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1065 mdelay(1);
1066 /* Restore video state */
1067 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1068 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1069 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1070 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1071 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1072 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1073 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1074 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1075 if (!(rdev->flags & RADEON_IS_IGP)) {
1076 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1077 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1078 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1079 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1080 }
1081 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1082 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1083 if (!(rdev->flags & RADEON_IS_IGP)) {
1084 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1085 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1086 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1087 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1088 }
1089 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1090 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1091 if (!(rdev->flags & RADEON_IS_IGP)) {
1092 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1093 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1094 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1095 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1096 }
1097 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1098 }
1099
1100 void evergreen_mc_program(struct radeon_device *rdev)
1101 {
1102 struct evergreen_mc_save save;
1103 u32 tmp;
1104 int i, j;
1105
1106 /* Initialize HDP */
1107 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1108 WREG32((0x2c14 + j), 0x00000000);
1109 WREG32((0x2c18 + j), 0x00000000);
1110 WREG32((0x2c1c + j), 0x00000000);
1111 WREG32((0x2c20 + j), 0x00000000);
1112 WREG32((0x2c24 + j), 0x00000000);
1113 }
1114 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1115
1116 evergreen_mc_stop(rdev, &save);
1117 if (evergreen_mc_wait_for_idle(rdev)) {
1118 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1119 }
1120 /* Lockout access through VGA aperture*/
1121 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1122 /* Update configuration */
1123 if (rdev->flags & RADEON_IS_AGP) {
1124 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1125 /* VRAM before AGP */
1126 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1127 rdev->mc.vram_start >> 12);
1128 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1129 rdev->mc.gtt_end >> 12);
1130 } else {
1131 /* VRAM after AGP */
1132 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1133 rdev->mc.gtt_start >> 12);
1134 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1135 rdev->mc.vram_end >> 12);
1136 }
1137 } else {
1138 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1139 rdev->mc.vram_start >> 12);
1140 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1141 rdev->mc.vram_end >> 12);
1142 }
1143 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1144 if (rdev->flags & RADEON_IS_IGP) {
1145 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1146 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1147 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1148 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1149 }
1150 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1151 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1152 WREG32(MC_VM_FB_LOCATION, tmp);
1153 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1154 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1155 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1156 if (rdev->flags & RADEON_IS_AGP) {
1157 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1158 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1159 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1160 } else {
1161 WREG32(MC_VM_AGP_BASE, 0);
1162 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1163 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1164 }
1165 if (evergreen_mc_wait_for_idle(rdev)) {
1166 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1167 }
1168 evergreen_mc_resume(rdev, &save);
1169 /* we need to own VRAM, so turn off the VGA renderer here
1170 * to stop it overwriting our objects */
1171 rv515_vga_render_disable(rdev);
1172 }
1173
1174 /*
1175 * CP.
1176 */
1177 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1178 {
1179 /* set to DX10/11 mode */
1180 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1181 radeon_ring_write(rdev, 1);
1182 /* FIXME: implement */
1183 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1184 radeon_ring_write(rdev,
1185 #ifdef __BIG_ENDIAN
1186 (2 << 0) |
1187 #endif
1188 (ib->gpu_addr & 0xFFFFFFFC));
1189 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1190 radeon_ring_write(rdev, ib->length_dw);
1191 }
1192
1193
1194 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1195 {
1196 const __be32 *fw_data;
1197 int i;
1198
1199 if (!rdev->me_fw || !rdev->pfp_fw)
1200 return -EINVAL;
1201
1202 r700_cp_stop(rdev);
1203 WREG32(CP_RB_CNTL,
1204 #ifdef __BIG_ENDIAN
1205 BUF_SWAP_32BIT |
1206 #endif
1207 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1208
1209 fw_data = (const __be32 *)rdev->pfp_fw->data;
1210 WREG32(CP_PFP_UCODE_ADDR, 0);
1211 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1212 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1213 WREG32(CP_PFP_UCODE_ADDR, 0);
1214
1215 fw_data = (const __be32 *)rdev->me_fw->data;
1216 WREG32(CP_ME_RAM_WADDR, 0);
1217 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1218 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1219
1220 WREG32(CP_PFP_UCODE_ADDR, 0);
1221 WREG32(CP_ME_RAM_WADDR, 0);
1222 WREG32(CP_ME_RAM_RADDR, 0);
1223 return 0;
1224 }
1225
1226 static int evergreen_cp_start(struct radeon_device *rdev)
1227 {
1228 int r, i;
1229 uint32_t cp_me;
1230
1231 r = radeon_ring_lock(rdev, 7);
1232 if (r) {
1233 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1234 return r;
1235 }
1236 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1237 radeon_ring_write(rdev, 0x1);
1238 radeon_ring_write(rdev, 0x0);
1239 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1240 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1241 radeon_ring_write(rdev, 0);
1242 radeon_ring_write(rdev, 0);
1243 radeon_ring_unlock_commit(rdev);
1244
1245 cp_me = 0xff;
1246 WREG32(CP_ME_CNTL, cp_me);
1247
1248 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1249 if (r) {
1250 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1251 return r;
1252 }
1253
1254 /* setup clear context state */
1255 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1256 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1257
1258 for (i = 0; i < evergreen_default_size; i++)
1259 radeon_ring_write(rdev, evergreen_default_state[i]);
1260
1261 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1262 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1263
1264 /* set clear context state */
1265 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1266 radeon_ring_write(rdev, 0);
1267
1268 /* SQ_VTX_BASE_VTX_LOC */
1269 radeon_ring_write(rdev, 0xc0026f00);
1270 radeon_ring_write(rdev, 0x00000000);
1271 radeon_ring_write(rdev, 0x00000000);
1272 radeon_ring_write(rdev, 0x00000000);
1273
1274 /* Clear consts */
1275 radeon_ring_write(rdev, 0xc0036f00);
1276 radeon_ring_write(rdev, 0x00000bc4);
1277 radeon_ring_write(rdev, 0xffffffff);
1278 radeon_ring_write(rdev, 0xffffffff);
1279 radeon_ring_write(rdev, 0xffffffff);
1280
1281 radeon_ring_write(rdev, 0xc0026900);
1282 radeon_ring_write(rdev, 0x00000316);
1283 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1284 radeon_ring_write(rdev, 0x00000010); /* */
1285
1286 radeon_ring_unlock_commit(rdev);
1287
1288 return 0;
1289 }
1290
1291 int evergreen_cp_resume(struct radeon_device *rdev)
1292 {
1293 u32 tmp;
1294 u32 rb_bufsz;
1295 int r;
1296
1297 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1298 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1299 SOFT_RESET_PA |
1300 SOFT_RESET_SH |
1301 SOFT_RESET_VGT |
1302 SOFT_RESET_SX));
1303 RREG32(GRBM_SOFT_RESET);
1304 mdelay(15);
1305 WREG32(GRBM_SOFT_RESET, 0);
1306 RREG32(GRBM_SOFT_RESET);
1307
1308 /* Set ring buffer size */
1309 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1310 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1311 #ifdef __BIG_ENDIAN
1312 tmp |= BUF_SWAP_32BIT;
1313 #endif
1314 WREG32(CP_RB_CNTL, tmp);
1315 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1316
1317 /* Set the write pointer delay */
1318 WREG32(CP_RB_WPTR_DELAY, 0);
1319
1320 /* Initialize the ring buffer's read and write pointers */
1321 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1322 WREG32(CP_RB_RPTR_WR, 0);
1323 WREG32(CP_RB_WPTR, 0);
1324
1325 /* set the wb address wether it's enabled or not */
1326 WREG32(CP_RB_RPTR_ADDR,
1327 #ifdef __BIG_ENDIAN
1328 RB_RPTR_SWAP(2) |
1329 #endif
1330 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1331 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1332 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1333
1334 if (rdev->wb.enabled)
1335 WREG32(SCRATCH_UMSK, 0xff);
1336 else {
1337 tmp |= RB_NO_UPDATE;
1338 WREG32(SCRATCH_UMSK, 0);
1339 }
1340
1341 mdelay(1);
1342 WREG32(CP_RB_CNTL, tmp);
1343
1344 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1345 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1346
1347 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1348 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1349
1350 evergreen_cp_start(rdev);
1351 rdev->cp.ready = true;
1352 r = radeon_ring_test(rdev);
1353 if (r) {
1354 rdev->cp.ready = false;
1355 return r;
1356 }
1357 return 0;
1358 }
1359
1360 /*
1361 * Core functions
1362 */
1363 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1364 u32 num_tile_pipes,
1365 u32 num_backends,
1366 u32 backend_disable_mask)
1367 {
1368 u32 backend_map = 0;
1369 u32 enabled_backends_mask = 0;
1370 u32 enabled_backends_count = 0;
1371 u32 cur_pipe;
1372 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1373 u32 cur_backend = 0;
1374 u32 i;
1375 bool force_no_swizzle;
1376
1377 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1378 num_tile_pipes = EVERGREEN_MAX_PIPES;
1379 if (num_tile_pipes < 1)
1380 num_tile_pipes = 1;
1381 if (num_backends > EVERGREEN_MAX_BACKENDS)
1382 num_backends = EVERGREEN_MAX_BACKENDS;
1383 if (num_backends < 1)
1384 num_backends = 1;
1385
1386 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1387 if (((backend_disable_mask >> i) & 1) == 0) {
1388 enabled_backends_mask |= (1 << i);
1389 ++enabled_backends_count;
1390 }
1391 if (enabled_backends_count == num_backends)
1392 break;
1393 }
1394
1395 if (enabled_backends_count == 0) {
1396 enabled_backends_mask = 1;
1397 enabled_backends_count = 1;
1398 }
1399
1400 if (enabled_backends_count != num_backends)
1401 num_backends = enabled_backends_count;
1402
1403 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1404 switch (rdev->family) {
1405 case CHIP_CEDAR:
1406 case CHIP_REDWOOD:
1407 case CHIP_PALM:
1408 case CHIP_TURKS:
1409 case CHIP_CAICOS:
1410 force_no_swizzle = false;
1411 break;
1412 case CHIP_CYPRESS:
1413 case CHIP_HEMLOCK:
1414 case CHIP_JUNIPER:
1415 case CHIP_BARTS:
1416 default:
1417 force_no_swizzle = true;
1418 break;
1419 }
1420 if (force_no_swizzle) {
1421 bool last_backend_enabled = false;
1422
1423 force_no_swizzle = false;
1424 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1425 if (((enabled_backends_mask >> i) & 1) == 1) {
1426 if (last_backend_enabled)
1427 force_no_swizzle = true;
1428 last_backend_enabled = true;
1429 } else
1430 last_backend_enabled = false;
1431 }
1432 }
1433
1434 switch (num_tile_pipes) {
1435 case 1:
1436 case 3:
1437 case 5:
1438 case 7:
1439 DRM_ERROR("odd number of pipes!\n");
1440 break;
1441 case 2:
1442 swizzle_pipe[0] = 0;
1443 swizzle_pipe[1] = 1;
1444 break;
1445 case 4:
1446 if (force_no_swizzle) {
1447 swizzle_pipe[0] = 0;
1448 swizzle_pipe[1] = 1;
1449 swizzle_pipe[2] = 2;
1450 swizzle_pipe[3] = 3;
1451 } else {
1452 swizzle_pipe[0] = 0;
1453 swizzle_pipe[1] = 2;
1454 swizzle_pipe[2] = 1;
1455 swizzle_pipe[3] = 3;
1456 }
1457 break;
1458 case 6:
1459 if (force_no_swizzle) {
1460 swizzle_pipe[0] = 0;
1461 swizzle_pipe[1] = 1;
1462 swizzle_pipe[2] = 2;
1463 swizzle_pipe[3] = 3;
1464 swizzle_pipe[4] = 4;
1465 swizzle_pipe[5] = 5;
1466 } else {
1467 swizzle_pipe[0] = 0;
1468 swizzle_pipe[1] = 2;
1469 swizzle_pipe[2] = 4;
1470 swizzle_pipe[3] = 1;
1471 swizzle_pipe[4] = 3;
1472 swizzle_pipe[5] = 5;
1473 }
1474 break;
1475 case 8:
1476 if (force_no_swizzle) {
1477 swizzle_pipe[0] = 0;
1478 swizzle_pipe[1] = 1;
1479 swizzle_pipe[2] = 2;
1480 swizzle_pipe[3] = 3;
1481 swizzle_pipe[4] = 4;
1482 swizzle_pipe[5] = 5;
1483 swizzle_pipe[6] = 6;
1484 swizzle_pipe[7] = 7;
1485 } else {
1486 swizzle_pipe[0] = 0;
1487 swizzle_pipe[1] = 2;
1488 swizzle_pipe[2] = 4;
1489 swizzle_pipe[3] = 6;
1490 swizzle_pipe[4] = 1;
1491 swizzle_pipe[5] = 3;
1492 swizzle_pipe[6] = 5;
1493 swizzle_pipe[7] = 7;
1494 }
1495 break;
1496 }
1497
1498 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1499 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1500 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1501
1502 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1503
1504 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1505 }
1506
1507 return backend_map;
1508 }
1509
1510 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1511 {
1512 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1513
1514 tmp = RREG32(MC_SHARED_CHMAP);
1515 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1516 case 0:
1517 case 1:
1518 case 2:
1519 case 3:
1520 default:
1521 /* default mapping */
1522 mc_shared_chremap = 0x00fac688;
1523 break;
1524 }
1525
1526 switch (rdev->family) {
1527 case CHIP_HEMLOCK:
1528 case CHIP_CYPRESS:
1529 case CHIP_BARTS:
1530 tcp_chan_steer_lo = 0x54763210;
1531 tcp_chan_steer_hi = 0x0000ba98;
1532 break;
1533 case CHIP_JUNIPER:
1534 case CHIP_REDWOOD:
1535 case CHIP_CEDAR:
1536 case CHIP_PALM:
1537 case CHIP_TURKS:
1538 case CHIP_CAICOS:
1539 default:
1540 tcp_chan_steer_lo = 0x76543210;
1541 tcp_chan_steer_hi = 0x0000ba98;
1542 break;
1543 }
1544
1545 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1546 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1547 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1548 }
1549
1550 static void evergreen_gpu_init(struct radeon_device *rdev)
1551 {
1552 u32 cc_rb_backend_disable = 0;
1553 u32 cc_gc_shader_pipe_config;
1554 u32 gb_addr_config = 0;
1555 u32 mc_shared_chmap, mc_arb_ramcfg;
1556 u32 gb_backend_map;
1557 u32 grbm_gfx_index;
1558 u32 sx_debug_1;
1559 u32 smx_dc_ctl0;
1560 u32 sq_config;
1561 u32 sq_lds_resource_mgmt;
1562 u32 sq_gpr_resource_mgmt_1;
1563 u32 sq_gpr_resource_mgmt_2;
1564 u32 sq_gpr_resource_mgmt_3;
1565 u32 sq_thread_resource_mgmt;
1566 u32 sq_thread_resource_mgmt_2;
1567 u32 sq_stack_resource_mgmt_1;
1568 u32 sq_stack_resource_mgmt_2;
1569 u32 sq_stack_resource_mgmt_3;
1570 u32 vgt_cache_invalidation;
1571 u32 hdp_host_path_cntl;
1572 int i, j, num_shader_engines, ps_thread_count;
1573
1574 switch (rdev->family) {
1575 case CHIP_CYPRESS:
1576 case CHIP_HEMLOCK:
1577 rdev->config.evergreen.num_ses = 2;
1578 rdev->config.evergreen.max_pipes = 4;
1579 rdev->config.evergreen.max_tile_pipes = 8;
1580 rdev->config.evergreen.max_simds = 10;
1581 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1582 rdev->config.evergreen.max_gprs = 256;
1583 rdev->config.evergreen.max_threads = 248;
1584 rdev->config.evergreen.max_gs_threads = 32;
1585 rdev->config.evergreen.max_stack_entries = 512;
1586 rdev->config.evergreen.sx_num_of_sets = 4;
1587 rdev->config.evergreen.sx_max_export_size = 256;
1588 rdev->config.evergreen.sx_max_export_pos_size = 64;
1589 rdev->config.evergreen.sx_max_export_smx_size = 192;
1590 rdev->config.evergreen.max_hw_contexts = 8;
1591 rdev->config.evergreen.sq_num_cf_insts = 2;
1592
1593 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1594 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1595 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1596 break;
1597 case CHIP_JUNIPER:
1598 rdev->config.evergreen.num_ses = 1;
1599 rdev->config.evergreen.max_pipes = 4;
1600 rdev->config.evergreen.max_tile_pipes = 4;
1601 rdev->config.evergreen.max_simds = 10;
1602 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1603 rdev->config.evergreen.max_gprs = 256;
1604 rdev->config.evergreen.max_threads = 248;
1605 rdev->config.evergreen.max_gs_threads = 32;
1606 rdev->config.evergreen.max_stack_entries = 512;
1607 rdev->config.evergreen.sx_num_of_sets = 4;
1608 rdev->config.evergreen.sx_max_export_size = 256;
1609 rdev->config.evergreen.sx_max_export_pos_size = 64;
1610 rdev->config.evergreen.sx_max_export_smx_size = 192;
1611 rdev->config.evergreen.max_hw_contexts = 8;
1612 rdev->config.evergreen.sq_num_cf_insts = 2;
1613
1614 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1615 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1616 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1617 break;
1618 case CHIP_REDWOOD:
1619 rdev->config.evergreen.num_ses = 1;
1620 rdev->config.evergreen.max_pipes = 4;
1621 rdev->config.evergreen.max_tile_pipes = 4;
1622 rdev->config.evergreen.max_simds = 5;
1623 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1624 rdev->config.evergreen.max_gprs = 256;
1625 rdev->config.evergreen.max_threads = 248;
1626 rdev->config.evergreen.max_gs_threads = 32;
1627 rdev->config.evergreen.max_stack_entries = 256;
1628 rdev->config.evergreen.sx_num_of_sets = 4;
1629 rdev->config.evergreen.sx_max_export_size = 256;
1630 rdev->config.evergreen.sx_max_export_pos_size = 64;
1631 rdev->config.evergreen.sx_max_export_smx_size = 192;
1632 rdev->config.evergreen.max_hw_contexts = 8;
1633 rdev->config.evergreen.sq_num_cf_insts = 2;
1634
1635 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1636 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1637 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1638 break;
1639 case CHIP_CEDAR:
1640 default:
1641 rdev->config.evergreen.num_ses = 1;
1642 rdev->config.evergreen.max_pipes = 2;
1643 rdev->config.evergreen.max_tile_pipes = 2;
1644 rdev->config.evergreen.max_simds = 2;
1645 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1646 rdev->config.evergreen.max_gprs = 256;
1647 rdev->config.evergreen.max_threads = 192;
1648 rdev->config.evergreen.max_gs_threads = 16;
1649 rdev->config.evergreen.max_stack_entries = 256;
1650 rdev->config.evergreen.sx_num_of_sets = 4;
1651 rdev->config.evergreen.sx_max_export_size = 128;
1652 rdev->config.evergreen.sx_max_export_pos_size = 32;
1653 rdev->config.evergreen.sx_max_export_smx_size = 96;
1654 rdev->config.evergreen.max_hw_contexts = 4;
1655 rdev->config.evergreen.sq_num_cf_insts = 1;
1656
1657 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1658 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1659 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1660 break;
1661 case CHIP_PALM:
1662 rdev->config.evergreen.num_ses = 1;
1663 rdev->config.evergreen.max_pipes = 2;
1664 rdev->config.evergreen.max_tile_pipes = 2;
1665 rdev->config.evergreen.max_simds = 2;
1666 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1667 rdev->config.evergreen.max_gprs = 256;
1668 rdev->config.evergreen.max_threads = 192;
1669 rdev->config.evergreen.max_gs_threads = 16;
1670 rdev->config.evergreen.max_stack_entries = 256;
1671 rdev->config.evergreen.sx_num_of_sets = 4;
1672 rdev->config.evergreen.sx_max_export_size = 128;
1673 rdev->config.evergreen.sx_max_export_pos_size = 32;
1674 rdev->config.evergreen.sx_max_export_smx_size = 96;
1675 rdev->config.evergreen.max_hw_contexts = 4;
1676 rdev->config.evergreen.sq_num_cf_insts = 1;
1677
1678 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1679 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1680 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1681 break;
1682 case CHIP_BARTS:
1683 rdev->config.evergreen.num_ses = 2;
1684 rdev->config.evergreen.max_pipes = 4;
1685 rdev->config.evergreen.max_tile_pipes = 8;
1686 rdev->config.evergreen.max_simds = 7;
1687 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1688 rdev->config.evergreen.max_gprs = 256;
1689 rdev->config.evergreen.max_threads = 248;
1690 rdev->config.evergreen.max_gs_threads = 32;
1691 rdev->config.evergreen.max_stack_entries = 512;
1692 rdev->config.evergreen.sx_num_of_sets = 4;
1693 rdev->config.evergreen.sx_max_export_size = 256;
1694 rdev->config.evergreen.sx_max_export_pos_size = 64;
1695 rdev->config.evergreen.sx_max_export_smx_size = 192;
1696 rdev->config.evergreen.max_hw_contexts = 8;
1697 rdev->config.evergreen.sq_num_cf_insts = 2;
1698
1699 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1700 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1701 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1702 break;
1703 case CHIP_TURKS:
1704 rdev->config.evergreen.num_ses = 1;
1705 rdev->config.evergreen.max_pipes = 4;
1706 rdev->config.evergreen.max_tile_pipes = 4;
1707 rdev->config.evergreen.max_simds = 6;
1708 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1709 rdev->config.evergreen.max_gprs = 256;
1710 rdev->config.evergreen.max_threads = 248;
1711 rdev->config.evergreen.max_gs_threads = 32;
1712 rdev->config.evergreen.max_stack_entries = 256;
1713 rdev->config.evergreen.sx_num_of_sets = 4;
1714 rdev->config.evergreen.sx_max_export_size = 256;
1715 rdev->config.evergreen.sx_max_export_pos_size = 64;
1716 rdev->config.evergreen.sx_max_export_smx_size = 192;
1717 rdev->config.evergreen.max_hw_contexts = 8;
1718 rdev->config.evergreen.sq_num_cf_insts = 2;
1719
1720 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1721 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1722 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1723 break;
1724 case CHIP_CAICOS:
1725 rdev->config.evergreen.num_ses = 1;
1726 rdev->config.evergreen.max_pipes = 4;
1727 rdev->config.evergreen.max_tile_pipes = 2;
1728 rdev->config.evergreen.max_simds = 2;
1729 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1730 rdev->config.evergreen.max_gprs = 256;
1731 rdev->config.evergreen.max_threads = 192;
1732 rdev->config.evergreen.max_gs_threads = 16;
1733 rdev->config.evergreen.max_stack_entries = 256;
1734 rdev->config.evergreen.sx_num_of_sets = 4;
1735 rdev->config.evergreen.sx_max_export_size = 128;
1736 rdev->config.evergreen.sx_max_export_pos_size = 32;
1737 rdev->config.evergreen.sx_max_export_smx_size = 96;
1738 rdev->config.evergreen.max_hw_contexts = 4;
1739 rdev->config.evergreen.sq_num_cf_insts = 1;
1740
1741 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1742 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1743 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1744 break;
1745 }
1746
1747 /* Initialize HDP */
1748 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1749 WREG32((0x2c14 + j), 0x00000000);
1750 WREG32((0x2c18 + j), 0x00000000);
1751 WREG32((0x2c1c + j), 0x00000000);
1752 WREG32((0x2c20 + j), 0x00000000);
1753 WREG32((0x2c24 + j), 0x00000000);
1754 }
1755
1756 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1757
1758 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1759
1760 cc_gc_shader_pipe_config |=
1761 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1762 & EVERGREEN_MAX_PIPES_MASK);
1763 cc_gc_shader_pipe_config |=
1764 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1765 & EVERGREEN_MAX_SIMDS_MASK);
1766
1767 cc_rb_backend_disable =
1768 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1769 & EVERGREEN_MAX_BACKENDS_MASK);
1770
1771
1772 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1773 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1774
1775 switch (rdev->config.evergreen.max_tile_pipes) {
1776 case 1:
1777 default:
1778 gb_addr_config |= NUM_PIPES(0);
1779 break;
1780 case 2:
1781 gb_addr_config |= NUM_PIPES(1);
1782 break;
1783 case 4:
1784 gb_addr_config |= NUM_PIPES(2);
1785 break;
1786 case 8:
1787 gb_addr_config |= NUM_PIPES(3);
1788 break;
1789 }
1790
1791 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1792 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1793 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1794 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1795 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1796 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1797
1798 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1799 gb_addr_config |= ROW_SIZE(2);
1800 else
1801 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1802
1803 if (rdev->ddev->pdev->device == 0x689e) {
1804 u32 efuse_straps_4;
1805 u32 efuse_straps_3;
1806 u8 efuse_box_bit_131_124;
1807
1808 WREG32(RCU_IND_INDEX, 0x204);
1809 efuse_straps_4 = RREG32(RCU_IND_DATA);
1810 WREG32(RCU_IND_INDEX, 0x203);
1811 efuse_straps_3 = RREG32(RCU_IND_DATA);
1812 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1813
1814 switch(efuse_box_bit_131_124) {
1815 case 0x00:
1816 gb_backend_map = 0x76543210;
1817 break;
1818 case 0x55:
1819 gb_backend_map = 0x77553311;
1820 break;
1821 case 0x56:
1822 gb_backend_map = 0x77553300;
1823 break;
1824 case 0x59:
1825 gb_backend_map = 0x77552211;
1826 break;
1827 case 0x66:
1828 gb_backend_map = 0x77443300;
1829 break;
1830 case 0x99:
1831 gb_backend_map = 0x66552211;
1832 break;
1833 case 0x5a:
1834 gb_backend_map = 0x77552200;
1835 break;
1836 case 0xaa:
1837 gb_backend_map = 0x66442200;
1838 break;
1839 case 0x95:
1840 gb_backend_map = 0x66553311;
1841 break;
1842 default:
1843 DRM_ERROR("bad backend map, using default\n");
1844 gb_backend_map =
1845 evergreen_get_tile_pipe_to_backend_map(rdev,
1846 rdev->config.evergreen.max_tile_pipes,
1847 rdev->config.evergreen.max_backends,
1848 ((EVERGREEN_MAX_BACKENDS_MASK <<
1849 rdev->config.evergreen.max_backends) &
1850 EVERGREEN_MAX_BACKENDS_MASK));
1851 break;
1852 }
1853 } else if (rdev->ddev->pdev->device == 0x68b9) {
1854 u32 efuse_straps_3;
1855 u8 efuse_box_bit_127_124;
1856
1857 WREG32(RCU_IND_INDEX, 0x203);
1858 efuse_straps_3 = RREG32(RCU_IND_DATA);
1859 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1860
1861 switch(efuse_box_bit_127_124) {
1862 case 0x0:
1863 gb_backend_map = 0x00003210;
1864 break;
1865 case 0x5:
1866 case 0x6:
1867 case 0x9:
1868 case 0xa:
1869 gb_backend_map = 0x00003311;
1870 break;
1871 default:
1872 DRM_ERROR("bad backend map, using default\n");
1873 gb_backend_map =
1874 evergreen_get_tile_pipe_to_backend_map(rdev,
1875 rdev->config.evergreen.max_tile_pipes,
1876 rdev->config.evergreen.max_backends,
1877 ((EVERGREEN_MAX_BACKENDS_MASK <<
1878 rdev->config.evergreen.max_backends) &
1879 EVERGREEN_MAX_BACKENDS_MASK));
1880 break;
1881 }
1882 } else {
1883 switch (rdev->family) {
1884 case CHIP_CYPRESS:
1885 case CHIP_HEMLOCK:
1886 case CHIP_BARTS:
1887 gb_backend_map = 0x66442200;
1888 break;
1889 case CHIP_JUNIPER:
1890 gb_backend_map = 0x00006420;
1891 break;
1892 default:
1893 gb_backend_map =
1894 evergreen_get_tile_pipe_to_backend_map(rdev,
1895 rdev->config.evergreen.max_tile_pipes,
1896 rdev->config.evergreen.max_backends,
1897 ((EVERGREEN_MAX_BACKENDS_MASK <<
1898 rdev->config.evergreen.max_backends) &
1899 EVERGREEN_MAX_BACKENDS_MASK));
1900 }
1901 }
1902
1903 /* setup tiling info dword. gb_addr_config is not adequate since it does
1904 * not have bank info, so create a custom tiling dword.
1905 * bits 3:0 num_pipes
1906 * bits 7:4 num_banks
1907 * bits 11:8 group_size
1908 * bits 15:12 row_size
1909 */
1910 rdev->config.evergreen.tile_config = 0;
1911 switch (rdev->config.evergreen.max_tile_pipes) {
1912 case 1:
1913 default:
1914 rdev->config.evergreen.tile_config |= (0 << 0);
1915 break;
1916 case 2:
1917 rdev->config.evergreen.tile_config |= (1 << 0);
1918 break;
1919 case 4:
1920 rdev->config.evergreen.tile_config |= (2 << 0);
1921 break;
1922 case 8:
1923 rdev->config.evergreen.tile_config |= (3 << 0);
1924 break;
1925 }
1926 rdev->config.evergreen.tile_config |=
1927 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1928 rdev->config.evergreen.tile_config |=
1929 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1930 rdev->config.evergreen.tile_config |=
1931 ((gb_addr_config & 0x30000000) >> 28) << 12;
1932
1933 WREG32(GB_BACKEND_MAP, gb_backend_map);
1934 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1935 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1936 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1937
1938 evergreen_program_channel_remap(rdev);
1939
1940 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1941 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1942
1943 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1944 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1945 u32 sp = cc_gc_shader_pipe_config;
1946 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1947
1948 if (i == num_shader_engines) {
1949 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1950 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1951 }
1952
1953 WREG32(GRBM_GFX_INDEX, gfx);
1954 WREG32(RLC_GFX_INDEX, gfx);
1955
1956 WREG32(CC_RB_BACKEND_DISABLE, rb);
1957 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1958 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1959 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1960 }
1961
1962 grbm_gfx_index |= SE_BROADCAST_WRITES;
1963 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1964 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1965
1966 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1967 WREG32(CGTS_TCC_DISABLE, 0);
1968 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1969 WREG32(CGTS_USER_TCC_DISABLE, 0);
1970
1971 /* set HW defaults for 3D engine */
1972 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1973 ROQ_IB2_START(0x2b)));
1974
1975 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1976
1977 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1978 SYNC_GRADIENT |
1979 SYNC_WALKER |
1980 SYNC_ALIGNER));
1981
1982 sx_debug_1 = RREG32(SX_DEBUG_1);
1983 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1984 WREG32(SX_DEBUG_1, sx_debug_1);
1985
1986
1987 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1988 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1989 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1990 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1991
1992 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1993 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1994 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1995
1996 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1997 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1998 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1999
2000 WREG32(VGT_NUM_INSTANCES, 1);
2001 WREG32(SPI_CONFIG_CNTL, 0);
2002 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2003 WREG32(CP_PERFMON_CNTL, 0);
2004
2005 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2006 FETCH_FIFO_HIWATER(0x4) |
2007 DONE_FIFO_HIWATER(0xe0) |
2008 ALU_UPDATE_FIFO_HIWATER(0x8)));
2009
2010 sq_config = RREG32(SQ_CONFIG);
2011 sq_config &= ~(PS_PRIO(3) |
2012 VS_PRIO(3) |
2013 GS_PRIO(3) |
2014 ES_PRIO(3));
2015 sq_config |= (VC_ENABLE |
2016 EXPORT_SRC_C |
2017 PS_PRIO(0) |
2018 VS_PRIO(1) |
2019 GS_PRIO(2) |
2020 ES_PRIO(3));
2021
2022 switch (rdev->family) {
2023 case CHIP_CEDAR:
2024 case CHIP_PALM:
2025 case CHIP_CAICOS:
2026 /* no vertex cache */
2027 sq_config &= ~VC_ENABLE;
2028 break;
2029 default:
2030 break;
2031 }
2032
2033 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2034
2035 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2036 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2037 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2038 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2039 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2040 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2041 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2042
2043 switch (rdev->family) {
2044 case CHIP_CEDAR:
2045 case CHIP_PALM:
2046 ps_thread_count = 96;
2047 break;
2048 default:
2049 ps_thread_count = 128;
2050 break;
2051 }
2052
2053 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2054 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2055 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2056 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2057 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2058 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2059
2060 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2061 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2062 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2063 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2064 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2065 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2066
2067 WREG32(SQ_CONFIG, sq_config);
2068 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2069 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2070 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2071 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2072 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2073 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2074 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2075 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2076 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2077 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2078
2079 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2080 FORCE_EOV_MAX_REZ_CNT(255)));
2081
2082 switch (rdev->family) {
2083 case CHIP_CEDAR:
2084 case CHIP_PALM:
2085 case CHIP_CAICOS:
2086 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2087 break;
2088 default:
2089 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2090 break;
2091 }
2092 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2093 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2094
2095 WREG32(VGT_GS_VERTEX_REUSE, 16);
2096 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2097 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2098
2099 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2100 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2101
2102 WREG32(CB_PERF_CTR0_SEL_0, 0);
2103 WREG32(CB_PERF_CTR0_SEL_1, 0);
2104 WREG32(CB_PERF_CTR1_SEL_0, 0);
2105 WREG32(CB_PERF_CTR1_SEL_1, 0);
2106 WREG32(CB_PERF_CTR2_SEL_0, 0);
2107 WREG32(CB_PERF_CTR2_SEL_1, 0);
2108 WREG32(CB_PERF_CTR3_SEL_0, 0);
2109 WREG32(CB_PERF_CTR3_SEL_1, 0);
2110
2111 /* clear render buffer base addresses */
2112 WREG32(CB_COLOR0_BASE, 0);
2113 WREG32(CB_COLOR1_BASE, 0);
2114 WREG32(CB_COLOR2_BASE, 0);
2115 WREG32(CB_COLOR3_BASE, 0);
2116 WREG32(CB_COLOR4_BASE, 0);
2117 WREG32(CB_COLOR5_BASE, 0);
2118 WREG32(CB_COLOR6_BASE, 0);
2119 WREG32(CB_COLOR7_BASE, 0);
2120 WREG32(CB_COLOR8_BASE, 0);
2121 WREG32(CB_COLOR9_BASE, 0);
2122 WREG32(CB_COLOR10_BASE, 0);
2123 WREG32(CB_COLOR11_BASE, 0);
2124
2125 /* set the shader const cache sizes to 0 */
2126 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2127 WREG32(i, 0);
2128 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2129 WREG32(i, 0);
2130
2131 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2132 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2133
2134 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2135
2136 udelay(50);
2137
2138 }
2139
2140 int evergreen_mc_init(struct radeon_device *rdev)
2141 {
2142 u32 tmp;
2143 int chansize, numchan;
2144
2145 /* Get VRAM informations */
2146 rdev->mc.vram_is_ddr = true;
2147 tmp = RREG32(MC_ARB_RAMCFG);
2148 if (tmp & CHANSIZE_OVERRIDE) {
2149 chansize = 16;
2150 } else if (tmp & CHANSIZE_MASK) {
2151 chansize = 64;
2152 } else {
2153 chansize = 32;
2154 }
2155 tmp = RREG32(MC_SHARED_CHMAP);
2156 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2157 case 0:
2158 default:
2159 numchan = 1;
2160 break;
2161 case 1:
2162 numchan = 2;
2163 break;
2164 case 2:
2165 numchan = 4;
2166 break;
2167 case 3:
2168 numchan = 8;
2169 break;
2170 }
2171 rdev->mc.vram_width = numchan * chansize;
2172 /* Could aper size report 0 ? */
2173 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2174 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2175 /* Setup GPU memory space */
2176 if (rdev->flags & RADEON_IS_IGP) {
2177 /* size in bytes on fusion */
2178 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2179 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2180 } else {
2181 /* size in MB on evergreen */
2182 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2183 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2184 }
2185 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2186 r700_vram_gtt_location(rdev, &rdev->mc);
2187 radeon_update_bandwidth_info(rdev);
2188
2189 return 0;
2190 }
2191
2192 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2193 {
2194 u32 srbm_status;
2195 u32 grbm_status;
2196 u32 grbm_status_se0, grbm_status_se1;
2197 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2198 int r;
2199
2200 srbm_status = RREG32(SRBM_STATUS);
2201 grbm_status = RREG32(GRBM_STATUS);
2202 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2203 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2204 if (!(grbm_status & GUI_ACTIVE)) {
2205 r100_gpu_lockup_update(lockup, &rdev->cp);
2206 return false;
2207 }
2208 /* force CP activities */
2209 r = radeon_ring_lock(rdev, 2);
2210 if (!r) {
2211 /* PACKET2 NOP */
2212 radeon_ring_write(rdev, 0x80000000);
2213 radeon_ring_write(rdev, 0x80000000);
2214 radeon_ring_unlock_commit(rdev);
2215 }
2216 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2217 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2218 }
2219
2220 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2221 {
2222 struct evergreen_mc_save save;
2223 u32 grbm_reset = 0;
2224
2225 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2226 return 0;
2227
2228 dev_info(rdev->dev, "GPU softreset \n");
2229 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2230 RREG32(GRBM_STATUS));
2231 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2232 RREG32(GRBM_STATUS_SE0));
2233 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2234 RREG32(GRBM_STATUS_SE1));
2235 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2236 RREG32(SRBM_STATUS));
2237 evergreen_mc_stop(rdev, &save);
2238 if (evergreen_mc_wait_for_idle(rdev)) {
2239 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2240 }
2241 /* Disable CP parsing/prefetching */
2242 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2243
2244 /* reset all the gfx blocks */
2245 grbm_reset = (SOFT_RESET_CP |
2246 SOFT_RESET_CB |
2247 SOFT_RESET_DB |
2248 SOFT_RESET_PA |
2249 SOFT_RESET_SC |
2250 SOFT_RESET_SPI |
2251 SOFT_RESET_SH |
2252 SOFT_RESET_SX |
2253 SOFT_RESET_TC |
2254 SOFT_RESET_TA |
2255 SOFT_RESET_VC |
2256 SOFT_RESET_VGT);
2257
2258 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2259 WREG32(GRBM_SOFT_RESET, grbm_reset);
2260 (void)RREG32(GRBM_SOFT_RESET);
2261 udelay(50);
2262 WREG32(GRBM_SOFT_RESET, 0);
2263 (void)RREG32(GRBM_SOFT_RESET);
2264 /* Wait a little for things to settle down */
2265 udelay(50);
2266 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2267 RREG32(GRBM_STATUS));
2268 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2269 RREG32(GRBM_STATUS_SE0));
2270 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2271 RREG32(GRBM_STATUS_SE1));
2272 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2273 RREG32(SRBM_STATUS));
2274 evergreen_mc_resume(rdev, &save);
2275 return 0;
2276 }
2277
2278 int evergreen_asic_reset(struct radeon_device *rdev)
2279 {
2280 return evergreen_gpu_soft_reset(rdev);
2281 }
2282
2283 /* Interrupts */
2284
2285 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2286 {
2287 switch (crtc) {
2288 case 0:
2289 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2290 case 1:
2291 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2292 case 2:
2293 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2294 case 3:
2295 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2296 case 4:
2297 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2298 case 5:
2299 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2300 default:
2301 return 0;
2302 }
2303 }
2304
2305 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2306 {
2307 u32 tmp;
2308
2309 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2310 WREG32(GRBM_INT_CNTL, 0);
2311 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2312 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2313 if (!(rdev->flags & RADEON_IS_IGP)) {
2314 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2315 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2316 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2317 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2318 }
2319
2320 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2321 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2322 if (!(rdev->flags & RADEON_IS_IGP)) {
2323 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2324 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2325 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2326 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2327 }
2328
2329 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2330 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2331
2332 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2333 WREG32(DC_HPD1_INT_CONTROL, tmp);
2334 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2335 WREG32(DC_HPD2_INT_CONTROL, tmp);
2336 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2337 WREG32(DC_HPD3_INT_CONTROL, tmp);
2338 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2339 WREG32(DC_HPD4_INT_CONTROL, tmp);
2340 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2341 WREG32(DC_HPD5_INT_CONTROL, tmp);
2342 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2343 WREG32(DC_HPD6_INT_CONTROL, tmp);
2344
2345 }
2346
2347 int evergreen_irq_set(struct radeon_device *rdev)
2348 {
2349 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2350 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2351 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2352 u32 grbm_int_cntl = 0;
2353 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2354
2355 if (!rdev->irq.installed) {
2356 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2357 return -EINVAL;
2358 }
2359 /* don't enable anything if the ih is disabled */
2360 if (!rdev->ih.enabled) {
2361 r600_disable_interrupts(rdev);
2362 /* force the active interrupt state to all disabled */
2363 evergreen_disable_interrupt_state(rdev);
2364 return 0;
2365 }
2366
2367 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2368 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2369 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2370 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2371 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2372 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2373
2374 if (rdev->irq.sw_int) {
2375 DRM_DEBUG("evergreen_irq_set: sw int\n");
2376 cp_int_cntl |= RB_INT_ENABLE;
2377 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2378 }
2379 if (rdev->irq.crtc_vblank_int[0] ||
2380 rdev->irq.pflip[0]) {
2381 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2382 crtc1 |= VBLANK_INT_MASK;
2383 }
2384 if (rdev->irq.crtc_vblank_int[1] ||
2385 rdev->irq.pflip[1]) {
2386 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2387 crtc2 |= VBLANK_INT_MASK;
2388 }
2389 if (rdev->irq.crtc_vblank_int[2] ||
2390 rdev->irq.pflip[2]) {
2391 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2392 crtc3 |= VBLANK_INT_MASK;
2393 }
2394 if (rdev->irq.crtc_vblank_int[3] ||
2395 rdev->irq.pflip[3]) {
2396 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2397 crtc4 |= VBLANK_INT_MASK;
2398 }
2399 if (rdev->irq.crtc_vblank_int[4] ||
2400 rdev->irq.pflip[4]) {
2401 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2402 crtc5 |= VBLANK_INT_MASK;
2403 }
2404 if (rdev->irq.crtc_vblank_int[5] ||
2405 rdev->irq.pflip[5]) {
2406 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2407 crtc6 |= VBLANK_INT_MASK;
2408 }
2409 if (rdev->irq.hpd[0]) {
2410 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2411 hpd1 |= DC_HPDx_INT_EN;
2412 }
2413 if (rdev->irq.hpd[1]) {
2414 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2415 hpd2 |= DC_HPDx_INT_EN;
2416 }
2417 if (rdev->irq.hpd[2]) {
2418 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2419 hpd3 |= DC_HPDx_INT_EN;
2420 }
2421 if (rdev->irq.hpd[3]) {
2422 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2423 hpd4 |= DC_HPDx_INT_EN;
2424 }
2425 if (rdev->irq.hpd[4]) {
2426 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2427 hpd5 |= DC_HPDx_INT_EN;
2428 }
2429 if (rdev->irq.hpd[5]) {
2430 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2431 hpd6 |= DC_HPDx_INT_EN;
2432 }
2433 if (rdev->irq.gui_idle) {
2434 DRM_DEBUG("gui idle\n");
2435 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2436 }
2437
2438 WREG32(CP_INT_CNTL, cp_int_cntl);
2439 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2440
2441 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2442 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2443 if (!(rdev->flags & RADEON_IS_IGP)) {
2444 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2445 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2446 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2447 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2448 }
2449
2450 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2451 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2452 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2453 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2454 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2455 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2456
2457 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2458 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2459 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2460 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2461 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2462 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2463
2464 return 0;
2465 }
2466
2467 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2468 {
2469 u32 tmp;
2470
2471 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2472 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2473 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2474 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2475 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2476 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2477 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2478 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2479 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2480 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2481 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2482 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2483
2484 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2485 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2486 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2487 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2488 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2489 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2490 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2491 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2492 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2493 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2494 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2495 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2496
2497 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2498 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2499 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2500 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2501
2502 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2503 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2504 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2505 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2506
2507 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2508 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2509 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2510 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2511
2512 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2513 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2514 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2515 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2516
2517 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2518 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2519 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2520 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2521
2522 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2523 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2524 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2525 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2526
2527 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2528 tmp = RREG32(DC_HPD1_INT_CONTROL);
2529 tmp |= DC_HPDx_INT_ACK;
2530 WREG32(DC_HPD1_INT_CONTROL, tmp);
2531 }
2532 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2533 tmp = RREG32(DC_HPD2_INT_CONTROL);
2534 tmp |= DC_HPDx_INT_ACK;
2535 WREG32(DC_HPD2_INT_CONTROL, tmp);
2536 }
2537 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2538 tmp = RREG32(DC_HPD3_INT_CONTROL);
2539 tmp |= DC_HPDx_INT_ACK;
2540 WREG32(DC_HPD3_INT_CONTROL, tmp);
2541 }
2542 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2543 tmp = RREG32(DC_HPD4_INT_CONTROL);
2544 tmp |= DC_HPDx_INT_ACK;
2545 WREG32(DC_HPD4_INT_CONTROL, tmp);
2546 }
2547 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2548 tmp = RREG32(DC_HPD5_INT_CONTROL);
2549 tmp |= DC_HPDx_INT_ACK;
2550 WREG32(DC_HPD5_INT_CONTROL, tmp);
2551 }
2552 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2553 tmp = RREG32(DC_HPD5_INT_CONTROL);
2554 tmp |= DC_HPDx_INT_ACK;
2555 WREG32(DC_HPD6_INT_CONTROL, tmp);
2556 }
2557 }
2558
2559 void evergreen_irq_disable(struct radeon_device *rdev)
2560 {
2561 r600_disable_interrupts(rdev);
2562 /* Wait and acknowledge irq */
2563 mdelay(1);
2564 evergreen_irq_ack(rdev);
2565 evergreen_disable_interrupt_state(rdev);
2566 }
2567
2568 void evergreen_irq_suspend(struct radeon_device *rdev)
2569 {
2570 evergreen_irq_disable(rdev);
2571 r600_rlc_stop(rdev);
2572 }
2573
2574 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2575 {
2576 u32 wptr, tmp;
2577
2578 if (rdev->wb.enabled)
2579 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2580 else
2581 wptr = RREG32(IH_RB_WPTR);
2582
2583 if (wptr & RB_OVERFLOW) {
2584 /* When a ring buffer overflow happen start parsing interrupt
2585 * from the last not overwritten vector (wptr + 16). Hopefully
2586 * this should allow us to catchup.
2587 */
2588 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2589 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2590 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2591 tmp = RREG32(IH_RB_CNTL);
2592 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2593 WREG32(IH_RB_CNTL, tmp);
2594 }
2595 return (wptr & rdev->ih.ptr_mask);
2596 }
2597
2598 int evergreen_irq_process(struct radeon_device *rdev)
2599 {
2600 u32 wptr = evergreen_get_ih_wptr(rdev);
2601 u32 rptr = rdev->ih.rptr;
2602 u32 src_id, src_data;
2603 u32 ring_index;
2604 unsigned long flags;
2605 bool queue_hotplug = false;
2606
2607 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2608 if (!rdev->ih.enabled)
2609 return IRQ_NONE;
2610
2611 spin_lock_irqsave(&rdev->ih.lock, flags);
2612
2613 if (rptr == wptr) {
2614 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2615 return IRQ_NONE;
2616 }
2617 if (rdev->shutdown) {
2618 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2619 return IRQ_NONE;
2620 }
2621
2622 restart_ih:
2623 /* display interrupts */
2624 evergreen_irq_ack(rdev);
2625
2626 rdev->ih.wptr = wptr;
2627 while (rptr != wptr) {
2628 /* wptr/rptr are in bytes! */
2629 ring_index = rptr / 4;
2630 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2631 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2632
2633 switch (src_id) {
2634 case 1: /* D1 vblank/vline */
2635 switch (src_data) {
2636 case 0: /* D1 vblank */
2637 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2638 if (rdev->irq.crtc_vblank_int[0]) {
2639 drm_handle_vblank(rdev->ddev, 0);
2640 rdev->pm.vblank_sync = true;
2641 wake_up(&rdev->irq.vblank_queue);
2642 }
2643 if (rdev->irq.pflip[0])
2644 radeon_crtc_handle_flip(rdev, 0);
2645 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2646 DRM_DEBUG("IH: D1 vblank\n");
2647 }
2648 break;
2649 case 1: /* D1 vline */
2650 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2651 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2652 DRM_DEBUG("IH: D1 vline\n");
2653 }
2654 break;
2655 default:
2656 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2657 break;
2658 }
2659 break;
2660 case 2: /* D2 vblank/vline */
2661 switch (src_data) {
2662 case 0: /* D2 vblank */
2663 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2664 if (rdev->irq.crtc_vblank_int[1]) {
2665 drm_handle_vblank(rdev->ddev, 1);
2666 rdev->pm.vblank_sync = true;
2667 wake_up(&rdev->irq.vblank_queue);
2668 }
2669 if (rdev->irq.pflip[1])
2670 radeon_crtc_handle_flip(rdev, 1);
2671 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2672 DRM_DEBUG("IH: D2 vblank\n");
2673 }
2674 break;
2675 case 1: /* D2 vline */
2676 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2677 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2678 DRM_DEBUG("IH: D2 vline\n");
2679 }
2680 break;
2681 default:
2682 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2683 break;
2684 }
2685 break;
2686 case 3: /* D3 vblank/vline */
2687 switch (src_data) {
2688 case 0: /* D3 vblank */
2689 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2690 if (rdev->irq.crtc_vblank_int[2]) {
2691 drm_handle_vblank(rdev->ddev, 2);
2692 rdev->pm.vblank_sync = true;
2693 wake_up(&rdev->irq.vblank_queue);
2694 }
2695 if (rdev->irq.pflip[2])
2696 radeon_crtc_handle_flip(rdev, 2);
2697 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2698 DRM_DEBUG("IH: D3 vblank\n");
2699 }
2700 break;
2701 case 1: /* D3 vline */
2702 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2703 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2704 DRM_DEBUG("IH: D3 vline\n");
2705 }
2706 break;
2707 default:
2708 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2709 break;
2710 }
2711 break;
2712 case 4: /* D4 vblank/vline */
2713 switch (src_data) {
2714 case 0: /* D4 vblank */
2715 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2716 if (rdev->irq.crtc_vblank_int[3]) {
2717 drm_handle_vblank(rdev->ddev, 3);
2718 rdev->pm.vblank_sync = true;
2719 wake_up(&rdev->irq.vblank_queue);
2720 }
2721 if (rdev->irq.pflip[3])
2722 radeon_crtc_handle_flip(rdev, 3);
2723 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2724 DRM_DEBUG("IH: D4 vblank\n");
2725 }
2726 break;
2727 case 1: /* D4 vline */
2728 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2729 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2730 DRM_DEBUG("IH: D4 vline\n");
2731 }
2732 break;
2733 default:
2734 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2735 break;
2736 }
2737 break;
2738 case 5: /* D5 vblank/vline */
2739 switch (src_data) {
2740 case 0: /* D5 vblank */
2741 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2742 if (rdev->irq.crtc_vblank_int[4]) {
2743 drm_handle_vblank(rdev->ddev, 4);
2744 rdev->pm.vblank_sync = true;
2745 wake_up(&rdev->irq.vblank_queue);
2746 }
2747 if (rdev->irq.pflip[4])
2748 radeon_crtc_handle_flip(rdev, 4);
2749 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2750 DRM_DEBUG("IH: D5 vblank\n");
2751 }
2752 break;
2753 case 1: /* D5 vline */
2754 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2755 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2756 DRM_DEBUG("IH: D5 vline\n");
2757 }
2758 break;
2759 default:
2760 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2761 break;
2762 }
2763 break;
2764 case 6: /* D6 vblank/vline */
2765 switch (src_data) {
2766 case 0: /* D6 vblank */
2767 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2768 if (rdev->irq.crtc_vblank_int[5]) {
2769 drm_handle_vblank(rdev->ddev, 5);
2770 rdev->pm.vblank_sync = true;
2771 wake_up(&rdev->irq.vblank_queue);
2772 }
2773 if (rdev->irq.pflip[5])
2774 radeon_crtc_handle_flip(rdev, 5);
2775 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2776 DRM_DEBUG("IH: D6 vblank\n");
2777 }
2778 break;
2779 case 1: /* D6 vline */
2780 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2781 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2782 DRM_DEBUG("IH: D6 vline\n");
2783 }
2784 break;
2785 default:
2786 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2787 break;
2788 }
2789 break;
2790 case 42: /* HPD hotplug */
2791 switch (src_data) {
2792 case 0:
2793 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2794 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2795 queue_hotplug = true;
2796 DRM_DEBUG("IH: HPD1\n");
2797 }
2798 break;
2799 case 1:
2800 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2801 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2802 queue_hotplug = true;
2803 DRM_DEBUG("IH: HPD2\n");
2804 }
2805 break;
2806 case 2:
2807 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2808 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2809 queue_hotplug = true;
2810 DRM_DEBUG("IH: HPD3\n");
2811 }
2812 break;
2813 case 3:
2814 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2815 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2816 queue_hotplug = true;
2817 DRM_DEBUG("IH: HPD4\n");
2818 }
2819 break;
2820 case 4:
2821 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2822 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2823 queue_hotplug = true;
2824 DRM_DEBUG("IH: HPD5\n");
2825 }
2826 break;
2827 case 5:
2828 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2829 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2830 queue_hotplug = true;
2831 DRM_DEBUG("IH: HPD6\n");
2832 }
2833 break;
2834 default:
2835 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2836 break;
2837 }
2838 break;
2839 case 176: /* CP_INT in ring buffer */
2840 case 177: /* CP_INT in IB1 */
2841 case 178: /* CP_INT in IB2 */
2842 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2843 radeon_fence_process(rdev);
2844 break;
2845 case 181: /* CP EOP event */
2846 DRM_DEBUG("IH: CP EOP\n");
2847 radeon_fence_process(rdev);
2848 break;
2849 case 233: /* GUI IDLE */
2850 DRM_DEBUG("IH: CP EOP\n");
2851 rdev->pm.gui_idle = true;
2852 wake_up(&rdev->irq.idle_queue);
2853 break;
2854 default:
2855 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2856 break;
2857 }
2858
2859 /* wptr/rptr are in bytes! */
2860 rptr += 16;
2861 rptr &= rdev->ih.ptr_mask;
2862 }
2863 /* make sure wptr hasn't changed while processing */
2864 wptr = evergreen_get_ih_wptr(rdev);
2865 if (wptr != rdev->ih.wptr)
2866 goto restart_ih;
2867 if (queue_hotplug)
2868 schedule_work(&rdev->hotplug_work);
2869 rdev->ih.rptr = rptr;
2870 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2871 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2872 return IRQ_HANDLED;
2873 }
2874
2875 static int evergreen_startup(struct radeon_device *rdev)
2876 {
2877 int r;
2878
2879 /* enable pcie gen2 link */
2880 if (!ASIC_IS_DCE5(rdev))
2881 evergreen_pcie_gen2_enable(rdev);
2882
2883 if (ASIC_IS_DCE5(rdev)) {
2884 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2885 r = ni_init_microcode(rdev);
2886 if (r) {
2887 DRM_ERROR("Failed to load firmware!\n");
2888 return r;
2889 }
2890 }
2891 r = ni_mc_load_microcode(rdev);
2892 if (r) {
2893 DRM_ERROR("Failed to load MC firmware!\n");
2894 return r;
2895 }
2896 } else {
2897 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2898 r = r600_init_microcode(rdev);
2899 if (r) {
2900 DRM_ERROR("Failed to load firmware!\n");
2901 return r;
2902 }
2903 }
2904 }
2905
2906 evergreen_mc_program(rdev);
2907 if (rdev->flags & RADEON_IS_AGP) {
2908 evergreen_agp_enable(rdev);
2909 } else {
2910 r = evergreen_pcie_gart_enable(rdev);
2911 if (r)
2912 return r;
2913 }
2914 evergreen_gpu_init(rdev);
2915
2916 r = evergreen_blit_init(rdev);
2917 if (r) {
2918 evergreen_blit_fini(rdev);
2919 rdev->asic->copy = NULL;
2920 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2921 }
2922 /* XXX: ontario has problems blitting to gart at the moment */
2923 if (rdev->family == CHIP_PALM) {
2924 rdev->asic->copy = NULL;
2925 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2926 }
2927
2928 /* allocate wb buffer */
2929 r = radeon_wb_init(rdev);
2930 if (r)
2931 return r;
2932
2933 /* Enable IRQ */
2934 r = r600_irq_init(rdev);
2935 if (r) {
2936 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2937 radeon_irq_kms_fini(rdev);
2938 return r;
2939 }
2940 evergreen_irq_set(rdev);
2941
2942 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2943 if (r)
2944 return r;
2945 r = evergreen_cp_load_microcode(rdev);
2946 if (r)
2947 return r;
2948 r = evergreen_cp_resume(rdev);
2949 if (r)
2950 return r;
2951
2952 return 0;
2953 }
2954
2955 int evergreen_resume(struct radeon_device *rdev)
2956 {
2957 int r;
2958
2959 /* reset the asic, the gfx blocks are often in a bad state
2960 * after the driver is unloaded or after a resume
2961 */
2962 if (radeon_asic_reset(rdev))
2963 dev_warn(rdev->dev, "GPU reset failed !\n");
2964 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2965 * posting will perform necessary task to bring back GPU into good
2966 * shape.
2967 */
2968 /* post card */
2969 atom_asic_init(rdev->mode_info.atom_context);
2970
2971 r = evergreen_startup(rdev);
2972 if (r) {
2973 DRM_ERROR("evergreen startup failed on resume\n");
2974 return r;
2975 }
2976
2977 r = r600_ib_test(rdev);
2978 if (r) {
2979 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2980 return r;
2981 }
2982
2983 return r;
2984
2985 }
2986
2987 int evergreen_suspend(struct radeon_device *rdev)
2988 {
2989 int r;
2990
2991 /* FIXME: we should wait for ring to be empty */
2992 r700_cp_stop(rdev);
2993 rdev->cp.ready = false;
2994 evergreen_irq_suspend(rdev);
2995 radeon_wb_disable(rdev);
2996 evergreen_pcie_gart_disable(rdev);
2997
2998 /* unpin shaders bo */
2999 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3000 if (likely(r == 0)) {
3001 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3002 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3003 }
3004
3005 return 0;
3006 }
3007
3008 int evergreen_copy_blit(struct radeon_device *rdev,
3009 uint64_t src_offset, uint64_t dst_offset,
3010 unsigned num_pages, struct radeon_fence *fence)
3011 {
3012 int r;
3013
3014 mutex_lock(&rdev->r600_blit.mutex);
3015 rdev->r600_blit.vb_ib = NULL;
3016 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
3017 if (r) {
3018 if (rdev->r600_blit.vb_ib)
3019 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3020 mutex_unlock(&rdev->r600_blit.mutex);
3021 return r;
3022 }
3023 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3024 evergreen_blit_done_copy(rdev, fence);
3025 mutex_unlock(&rdev->r600_blit.mutex);
3026 return 0;
3027 }
3028
3029 /* Plan is to move initialization in that function and use
3030 * helper function so that radeon_device_init pretty much
3031 * do nothing more than calling asic specific function. This
3032 * should also allow to remove a bunch of callback function
3033 * like vram_info.
3034 */
3035 int evergreen_init(struct radeon_device *rdev)
3036 {
3037 int r;
3038
3039 r = radeon_dummy_page_init(rdev);
3040 if (r)
3041 return r;
3042 /* This don't do much */
3043 r = radeon_gem_init(rdev);
3044 if (r)
3045 return r;
3046 /* Read BIOS */
3047 if (!radeon_get_bios(rdev)) {
3048 if (ASIC_IS_AVIVO(rdev))
3049 return -EINVAL;
3050 }
3051 /* Must be an ATOMBIOS */
3052 if (!rdev->is_atom_bios) {
3053 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3054 return -EINVAL;
3055 }
3056 r = radeon_atombios_init(rdev);
3057 if (r)
3058 return r;
3059 /* reset the asic, the gfx blocks are often in a bad state
3060 * after the driver is unloaded or after a resume
3061 */
3062 if (radeon_asic_reset(rdev))
3063 dev_warn(rdev->dev, "GPU reset failed !\n");
3064 /* Post card if necessary */
3065 if (!radeon_card_posted(rdev)) {
3066 if (!rdev->bios) {
3067 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3068 return -EINVAL;
3069 }
3070 DRM_INFO("GPU not posted. posting now...\n");
3071 atom_asic_init(rdev->mode_info.atom_context);
3072 }
3073 /* Initialize scratch registers */
3074 r600_scratch_init(rdev);
3075 /* Initialize surface registers */
3076 radeon_surface_init(rdev);
3077 /* Initialize clocks */
3078 radeon_get_clock_info(rdev->ddev);
3079 /* Fence driver */
3080 r = radeon_fence_driver_init(rdev);
3081 if (r)
3082 return r;
3083 /* initialize AGP */
3084 if (rdev->flags & RADEON_IS_AGP) {
3085 r = radeon_agp_init(rdev);
3086 if (r)
3087 radeon_agp_disable(rdev);
3088 }
3089 /* initialize memory controller */
3090 r = evergreen_mc_init(rdev);
3091 if (r)
3092 return r;
3093 /* Memory manager */
3094 r = radeon_bo_init(rdev);
3095 if (r)
3096 return r;
3097
3098 r = radeon_irq_kms_init(rdev);
3099 if (r)
3100 return r;
3101
3102 rdev->cp.ring_obj = NULL;
3103 r600_ring_init(rdev, 1024 * 1024);
3104
3105 rdev->ih.ring_obj = NULL;
3106 r600_ih_ring_init(rdev, 64 * 1024);
3107
3108 r = r600_pcie_gart_init(rdev);
3109 if (r)
3110 return r;
3111
3112 rdev->accel_working = true;
3113 r = evergreen_startup(rdev);
3114 if (r) {
3115 dev_err(rdev->dev, "disabling GPU acceleration\n");
3116 r700_cp_fini(rdev);
3117 r600_irq_fini(rdev);
3118 radeon_wb_fini(rdev);
3119 radeon_irq_kms_fini(rdev);
3120 evergreen_pcie_gart_fini(rdev);
3121 rdev->accel_working = false;
3122 }
3123 if (rdev->accel_working) {
3124 r = radeon_ib_pool_init(rdev);
3125 if (r) {
3126 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3127 rdev->accel_working = false;
3128 }
3129 r = r600_ib_test(rdev);
3130 if (r) {
3131 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3132 rdev->accel_working = false;
3133 }
3134 }
3135 return 0;
3136 }
3137
3138 void evergreen_fini(struct radeon_device *rdev)
3139 {
3140 evergreen_blit_fini(rdev);
3141 r700_cp_fini(rdev);
3142 r600_irq_fini(rdev);
3143 radeon_wb_fini(rdev);
3144 radeon_irq_kms_fini(rdev);
3145 evergreen_pcie_gart_fini(rdev);
3146 radeon_gem_fini(rdev);
3147 radeon_fence_driver_fini(rdev);
3148 radeon_agp_fini(rdev);
3149 radeon_bo_fini(rdev);
3150 radeon_atombios_fini(rdev);
3151 kfree(rdev->bios);
3152 rdev->bios = NULL;
3153 radeon_dummy_page_fini(rdev);
3154 }
3155
3156 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3157 {
3158 u32 link_width_cntl, speed_cntl;
3159
3160 if (radeon_pcie_gen2 == 0)
3161 return;
3162
3163 if (rdev->flags & RADEON_IS_IGP)
3164 return;
3165
3166 if (!(rdev->flags & RADEON_IS_PCIE))
3167 return;
3168
3169 /* x2 cards have a special sequence */
3170 if (ASIC_IS_X2(rdev))
3171 return;
3172
3173 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3174 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3175 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3176
3177 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3178 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3179 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3180
3181 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3182 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3183 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3184
3185 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3186 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3187 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3188
3189 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3190 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3191 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3192
3193 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3194 speed_cntl |= LC_GEN2_EN_STRAP;
3195 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3196
3197 } else {
3198 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3199 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3200 if (1)
3201 link_width_cntl |= LC_UPCONFIGURE_DIS;
3202 else
3203 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3204 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3205 }
3206 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree