3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
12 * for processing interrupts from the device.
14 *------------------------------------------------------------------------------
18 * This software is provided subject to the following terms and conditions,
19 * which you should read carefully before using the software. Using this
20 * software indicates your acceptance of these terms and conditions. If you do
21 * not agree with these terms and conditions, do not use the software.
23 * Copyright © 2005 Agere Systems Inc.
24 * All rights reserved.
26 * Redistribution and use in source or binary forms, with or without
27 * modifications, are permitted provided that the following conditions are met:
29 * . Redistributions of source code must retain the above copyright notice, this
30 * list of conditions and the following Disclaimer as comments in the code as
31 * well as in the documentation and/or other materials provided with the
34 * . Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following Disclaimer in the documentation
36 * and/or other materials provided with the distribution.
38 * . Neither the name of Agere Systems Inc. nor the names of the contributors
39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
44 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
48 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
51 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
52 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
59 #include "et131x_version.h"
60 #include "et131x_defs.h"
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <linux/pci.h>
79 #include <asm/system.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
87 #include "et1310_phy.h"
88 #include "et1310_pm.h"
89 #include "et1310_jagcore.h"
90 #include "et1310_mac.h"
92 #include "et131x_adapter.h"
95 * et131x_enable_interrupts - enable interrupt
96 * @adapter: et131x device
98 * Enable the appropriate interrupts on the ET131x according to our
102 void et131x_enable_interrupts(struct et131x_adapter
*adapter
)
106 /* Enable all global interrupts */
107 if (adapter
->FlowControl
== TxOnly
|| adapter
->FlowControl
== Both
)
108 mask
= INT_MASK_ENABLE
;
110 mask
= INT_MASK_ENABLE_NO_FLOW
;
112 adapter
->CachedMaskValue
= mask
;
113 writel(mask
, &adapter
->regs
->global
.int_mask
);
117 * et131x_disable_interrupts - interrupt disable
118 * @adapter: et131x device
120 * Block all interrupts from the et131x device at the device itself
123 void et131x_disable_interrupts(struct et131x_adapter
*adapter
)
125 /* Disable all global interrupts */
126 adapter
->CachedMaskValue
= INT_MASK_DISABLE
;
127 writel(INT_MASK_DISABLE
, &adapter
->regs
->global
.int_mask
);
132 * et131x_isr - The Interrupt Service Routine for the driver.
133 * @irq: the IRQ on which the interrupt was received.
134 * @dev_id: device-specific info (here a pointer to a net_device struct)
136 * Returns a value indicating if the interrupt was handled.
139 irqreturn_t
et131x_isr(int irq
, void *dev_id
)
142 struct net_device
*netdev
= (struct net_device
*)dev_id
;
143 struct et131x_adapter
*adapter
= NULL
;
146 if (!netif_device_present(netdev
)) {
151 adapter
= netdev_priv(netdev
);
153 /* If the adapter is in low power state, then it should not
154 * recognize any interrupt
157 /* Disable Device Interrupts */
158 et131x_disable_interrupts(adapter
);
160 /* Get a copy of the value in the interrupt status register
161 * so we can process the interrupting section
163 status
= readl(&adapter
->regs
->global
.int_status
);
165 if (adapter
->FlowControl
== TxOnly
||
166 adapter
->FlowControl
== Both
) {
167 status
&= ~INT_MASK_ENABLE
;
169 status
&= ~INT_MASK_ENABLE_NO_FLOW
;
172 /* Make sure this is our interrupt */
175 et131x_enable_interrupts(adapter
);
179 /* This is our interrupt, so process accordingly */
181 if (status
& ET_INTR_WATCHDOG
) {
182 PMP_TCB pMpTcb
= adapter
->TxRing
.CurrSendHead
;
185 if (++pMpTcb
->PacketStaleCount
> 1)
186 status
|= ET_INTR_TXDMA_ISR
;
188 if (adapter
->RxRing
.UnfinishedReceives
)
189 status
|= ET_INTR_RXDMA_XFR_DONE
;
190 else if (pMpTcb
== NULL
)
191 writel(0, &adapter
->regs
->global
.watchdog_timer
);
193 status
&= ~ET_INTR_WATCHDOG
;
197 /* This interrupt has in some way been "handled" by
198 * the ISR. Either it was a spurious Rx interrupt, or
199 * it was a Tx interrupt that has been filtered by
202 et131x_enable_interrupts(adapter
);
206 /* We need to save the interrupt status value for use in our
207 * DPC. We will clear the software copy of that in that
210 adapter
->Stats
.InterruptStatus
= status
;
212 /* Schedule the ISR handler as a bottom-half task in the
213 * kernel's tq_immediate queue, and mark the queue for
216 schedule_work(&adapter
->task
);
218 return IRQ_RETVAL(handled
);
222 * et131x_isr_handler - The ISR handler
223 * @p_adapter, a pointer to the device's private adapter structure
225 * scheduled to run in a deferred context by the ISR. This is where the ISR's
226 * work actually gets done.
228 void et131x_isr_handler(struct work_struct
*work
)
230 struct et131x_adapter
*etdev
=
231 container_of(work
, struct et131x_adapter
, task
);
232 u32 status
= etdev
->Stats
.InterruptStatus
;
233 ADDRESS_MAP_t __iomem
*iomem
= etdev
->regs
;
236 * These first two are by far the most common. Once handled, we clear
237 * their two bits in the status word. If the word is now zero, we
240 /* Handle all the completed Transmit interrupts */
241 if (status
& ET_INTR_TXDMA_ISR
) {
242 et131x_handle_send_interrupt(etdev
);
245 /* Handle all the completed Receives interrupts */
246 if (status
& ET_INTR_RXDMA_XFR_DONE
) {
247 et131x_handle_recv_interrupt(etdev
);
250 status
&= 0xffffffd7;
253 /* Handle the TXDMA Error interrupt */
254 if (status
& ET_INTR_TXDMA_ERR
) {
257 /* Following read also clears the register (COR) */
258 txdma_err
= readl(&iomem
->txdma
.TxDmaError
);
260 dev_warn(&etdev
->pdev
->dev
,
261 "TXDMA_ERR interrupt, error = %d\n",
265 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
266 if (status
& (ET_INTR_RXDMA_FB_R0_LOW
| ET_INTR_RXDMA_FB_R1_LOW
)) {
268 * This indicates the number of unused buffers in
269 * RXDMA free buffer ring 0 is <= the limit you
270 * programmed. Free buffer resources need to be
271 * returned. Free buffers are consumed as packets
272 * are passed from the network to the host. The host
273 * becomes aware of the packets from the contents of
274 * the packet status ring. This ring is queried when
275 * the packet done interrupt occurs. Packets are then
276 * passed to the OS. When the OS is done with the
277 * packets the resources can be returned to the
278 * ET1310 for re-use. This interrupt is one method of
279 * returning resources.
282 /* If the user has flow control on, then we will
283 * send a pause packet, otherwise just exit
285 if (etdev
->FlowControl
== TxOnly
||
286 etdev
->FlowControl
== Both
) {
289 /* Tell the device to send a pause packet via
290 * the back pressure register
292 pm_csr
= readl(&iomem
->global
.pm_csr
);
293 if ((pm_csr
& ET_PM_PHY_SW_COMA
) == 0) {
294 TXMAC_BP_CTRL_t bp_ctrl
= { 0 };
296 bp_ctrl
.bits
.bp_req
= 1;
297 bp_ctrl
.bits
.bp_xonxoff
= 1;
298 writel(bp_ctrl
.value
,
299 &iomem
->txmac
.bp_ctrl
.value
);
304 /* Handle Packet Status Ring Low Interrupt */
305 if (status
& ET_INTR_RXDMA_STAT_LOW
) {
308 * Same idea as with the two Free Buffer Rings.
309 * Packets going from the network to the host each
310 * consume a free buffer resource and a packet status
311 * resource. These resoures are passed to the OS.
312 * When the OS is done with the resources, they need
313 * to be returned to the ET1310. This is one method
314 * of returning the resources.
318 /* Handle RXDMA Error Interrupt */
319 if (status
& ET_INTR_RXDMA_ERR
) {
321 * The rxdma_error interrupt is sent when a time-out
322 * on a request issued by the JAGCore has occurred or
323 * a completion is returned with an un-successful
324 * status. In both cases the request is considered
325 * complete. The JAGCore will automatically re-try the
326 * request in question. Normally information on events
327 * like these are sent to the host using the "Advanced
328 * Error Reporting" capability. This interrupt is
329 * another way of getting similar information. The
330 * only thing required is to clear the interrupt by
331 * reading the ISR in the global resources. The
332 * JAGCore will do a re-try on the request. Normally
333 * you should never see this interrupt. If you start
334 * to see this interrupt occurring frequently then
335 * something bad has occurred. A reset might be the
340 etdev
->TxMacTest
.value
=
341 readl(&iomem
->txmac
.tx_test
.value
);
342 dev_warn(&etdev
->pdev
->dev
,
343 "RxDMA_ERR interrupt, error %x\n",
344 etdev
->TxMacTest
.value
);
347 /* Handle the Wake on LAN Event */
348 if (status
& ET_INTR_WOL
) {
350 * This is a secondary interrupt for wake on LAN.
351 * The driver should never see this, if it does,
352 * something serious is wrong. We will TRAP the
353 * message when we are in DBG mode, otherwise we
356 dev_err(&etdev
->pdev
->dev
, "WAKE_ON_LAN interrupt\n");
359 /* Handle the PHY interrupt */
360 if (status
& ET_INTR_PHY
) {
362 MI_BMSR_t BmsrInts
, BmsrData
;
365 /* If we are in coma mode when we get this interrupt,
366 * we need to disable it.
368 pm_csr
= readl(&iomem
->global
.pm_csr
);
369 if (pm_csr
& ET_PM_PHY_SW_COMA
) {
371 * Check to see if we are in coma mode and if
372 * so, disable it because we will not be able
373 * to read PHY values until we are out.
375 DisablePhyComa(etdev
);
378 /* Read the PHY ISR to clear the reason for the
381 MiRead(etdev
, (uint8_t) offsetof(MI_REGS_t
, isr
),
384 if (!etdev
->ReplicaPhyLoopbk
) {
386 (uint8_t) offsetof(MI_REGS_t
, bmsr
),
390 etdev
->Bmsr
.value
^ BmsrData
.value
;
391 etdev
->Bmsr
.value
= BmsrData
.value
;
393 /* Do all the cable in / cable out stuff */
394 et131x_Mii_check(etdev
, BmsrData
, BmsrInts
);
398 /* Let's move on to the TxMac */
399 if (status
& ET_INTR_TXMAC
) {
400 etdev
->TxRing
.TxMacErr
.value
=
401 readl(&iomem
->txmac
.err
.value
);
404 * When any of the errors occur and TXMAC generates
405 * an interrupt to report these errors, it usually
406 * means that TXMAC has detected an error in the data
407 * stream retrieved from the on-chip Tx Q. All of
408 * these errors are catastrophic and TXMAC won't be
409 * able to recover data when these errors occur. In
410 * a nutshell, the whole Tx path will have to be reset
411 * and re-configured afterwards.
413 dev_warn(&etdev
->pdev
->dev
,
414 "TXMAC interrupt, error 0x%08x\n",
415 etdev
->TxRing
.TxMacErr
.value
);
417 /* If we are debugging, we want to see this error,
418 * otherwise we just want the device to be reset and
423 /* Handle RXMAC Interrupt */
424 if (status
& ET_INTR_RXMAC
) {
426 * These interrupts are catastrophic to the device,
427 * what we need to do is disable the interrupts and
428 * set the flag to cause us to reset so we can solve
431 /* MP_SET_FLAG( etdev,
432 fMP_ADAPTER_HARDWARE_ERROR); */
434 dev_warn(&etdev
->pdev
->dev
,
435 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
436 readl(&iomem
->rxmac
.err_reg
.value
));
438 dev_warn(&etdev
->pdev
->dev
,
439 "Enable 0x%08x, Diag 0x%08x\n",
440 readl(&iomem
->rxmac
.ctrl
.value
),
441 readl(&iomem
->rxmac
.rxq_diag
.value
));
444 * If we are debugging, we want to see this error,
445 * otherwise we just want the device to be reset and
450 /* Handle MAC_STAT Interrupt */
451 if (status
& ET_INTR_MAC_STAT
) {
453 * This means at least one of the un-masked counters
454 * in the MAC_STAT block has rolled over. Use this
455 * to maintain the top, software managed bits of the
458 HandleMacStatInterrupt(etdev
);
461 /* Handle SLV Timeout Interrupt */
462 if (status
& ET_INTR_SLV_TIMEOUT
) {
464 * This means a timeout has occured on a read or
465 * write request to one of the JAGCore registers. The
466 * Global Resources block has terminated the request
467 * and on a read request, returned a "fake" value.
468 * The most likely reasons are: Bad Address or the
469 * addressed module is in a power-down state and
474 et131x_enable_interrupts(etdev
);