3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_tx.c - Routines used to perform data transmission.
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et1310_pm.h"
88 #include "et1310_jagcore.h"
90 #include "et131x_adapter.h"
91 #include "et131x_initpci.h"
92 #include "et131x_isr.h"
94 #include "et1310_tx.h"
97 static void et131x_update_tcb_list(struct et131x_adapter
*etdev
);
98 static void et131x_check_send_wait_list(struct et131x_adapter
*etdev
);
99 static inline void et131x_free_send_packet(struct et131x_adapter
*etdev
,
101 static int et131x_send_packet(struct sk_buff
*skb
,
102 struct et131x_adapter
*etdev
);
103 static int nic_send_packet(struct et131x_adapter
*etdev
, PMP_TCB pMpTcb
);
106 * et131x_tx_dma_memory_alloc
107 * @adapter: pointer to our private adapter structure
109 * Returns 0 on success and errno on failure (as defined in errno.h).
111 * Allocates memory that will be visible both to the device and to the CPU.
112 * The OS will pass us packets, pointers to which we will insert in the Tx
113 * Descriptor queue. The device will read this queue to find the packets in
114 * memory. The device will update the "status" in memory each time it xmits a
117 int et131x_tx_dma_memory_alloc(struct et131x_adapter
*adapter
)
120 TX_RING_t
*tx_ring
= &adapter
->TxRing
;
122 /* Allocate memory for the TCB's (Transmit Control Block) */
123 adapter
->TxRing
.MpTcbMem
= (MP_TCB
*)kcalloc(NUM_TCB
, sizeof(MP_TCB
),
124 GFP_ATOMIC
| GFP_DMA
);
125 if (!adapter
->TxRing
.MpTcbMem
) {
126 dev_err(&adapter
->pdev
->dev
, "Cannot alloc memory for TCBs\n");
130 /* Allocate enough memory for the Tx descriptor ring, and allocate
131 * some extra so that the ring can be aligned on a 4k boundary.
133 desc_size
= (sizeof(TX_DESC_ENTRY_t
) * NUM_DESC_PER_RING_TX
) + 4096 - 1;
134 tx_ring
->pTxDescRingVa
=
135 (PTX_DESC_ENTRY_t
) pci_alloc_consistent(adapter
->pdev
, desc_size
,
136 &tx_ring
->pTxDescRingPa
);
137 if (!adapter
->TxRing
.pTxDescRingVa
) {
138 dev_err(&adapter
->pdev
->dev
, "Cannot alloc memory for Tx Ring\n");
142 /* Save physical address
144 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
145 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
146 * are ever returned, make sure the high part is retrieved here before
147 * storing the adjusted address.
149 tx_ring
->pTxDescRingAdjustedPa
= tx_ring
->pTxDescRingPa
;
151 /* Align Tx Descriptor Ring on a 4k (0x1000) byte boundary */
152 et131x_align_allocated_memory(adapter
,
153 &tx_ring
->pTxDescRingAdjustedPa
,
154 &tx_ring
->TxDescOffset
, 0x0FFF);
156 tx_ring
->pTxDescRingVa
+= tx_ring
->TxDescOffset
;
158 /* Allocate memory for the Tx status block */
159 tx_ring
->pTxStatusVa
= pci_alloc_consistent(adapter
->pdev
,
160 sizeof(TX_STATUS_BLOCK_t
),
161 &tx_ring
->pTxStatusPa
);
162 if (!adapter
->TxRing
.pTxStatusPa
) {
163 dev_err(&adapter
->pdev
->dev
,
164 "Cannot alloc memory for Tx status block\n");
168 /* Allocate memory for a dummy buffer */
169 tx_ring
->pTxDummyBlkVa
= pci_alloc_consistent(adapter
->pdev
,
171 &tx_ring
->pTxDummyBlkPa
);
172 if (!adapter
->TxRing
.pTxDummyBlkPa
) {
173 dev_err(&adapter
->pdev
->dev
,
174 "Cannot alloc memory for Tx dummy buffer\n");
182 * et131x_tx_dma_memory_free - Free all memory allocated within this module
183 * @adapter: pointer to our private adapter structure
185 * Returns 0 on success and errno on failure (as defined in errno.h).
187 void et131x_tx_dma_memory_free(struct et131x_adapter
*adapter
)
191 if (adapter
->TxRing
.pTxDescRingVa
) {
192 /* Free memory relating to Tx rings here */
193 adapter
->TxRing
.pTxDescRingVa
-= adapter
->TxRing
.TxDescOffset
;
196 (sizeof(TX_DESC_ENTRY_t
) * NUM_DESC_PER_RING_TX
) + 4096 - 1;
198 pci_free_consistent(adapter
->pdev
,
200 adapter
->TxRing
.pTxDescRingVa
,
201 adapter
->TxRing
.pTxDescRingPa
);
203 adapter
->TxRing
.pTxDescRingVa
= NULL
;
206 /* Free memory for the Tx status block */
207 if (adapter
->TxRing
.pTxStatusVa
) {
208 pci_free_consistent(adapter
->pdev
,
209 sizeof(TX_STATUS_BLOCK_t
),
210 adapter
->TxRing
.pTxStatusVa
,
211 adapter
->TxRing
.pTxStatusPa
);
213 adapter
->TxRing
.pTxStatusVa
= NULL
;
216 /* Free memory for the dummy buffer */
217 if (adapter
->TxRing
.pTxDummyBlkVa
) {
218 pci_free_consistent(adapter
->pdev
,
220 adapter
->TxRing
.pTxDummyBlkVa
,
221 adapter
->TxRing
.pTxDummyBlkPa
);
223 adapter
->TxRing
.pTxDummyBlkVa
= NULL
;
226 /* Free the memory for MP_TCB structures */
227 kfree(adapter
->TxRing
.MpTcbMem
);
231 * ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
232 * @etdev: pointer to our private adapter structure
234 void ConfigTxDmaRegs(struct et131x_adapter
*etdev
)
236 struct _TXDMA_t __iomem
*txdma
= &etdev
->regs
->txdma
;
238 /* Load the hardware with the start of the transmit descriptor ring. */
239 writel((uint32_t) (etdev
->TxRing
.pTxDescRingAdjustedPa
>> 32),
241 writel((uint32_t) etdev
->TxRing
.pTxDescRingAdjustedPa
,
244 /* Initialise the transmit DMA engine */
245 writel(NUM_DESC_PER_RING_TX
- 1, &txdma
->pr_num_des
.value
);
247 /* Load the completion writeback physical address
249 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
250 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
251 * are ever returned, make sure the high part is retrieved here before
252 * storing the adjusted address.
254 writel(0, &txdma
->dma_wb_base_hi
);
255 writel(etdev
->TxRing
.pTxStatusPa
, &txdma
->dma_wb_base_lo
);
257 memset(etdev
->TxRing
.pTxStatusVa
, 0, sizeof(TX_STATUS_BLOCK_t
));
259 writel(0, &txdma
->service_request
);
260 etdev
->TxRing
.txDmaReadyToSend
= 0;
264 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
265 * @etdev: pointer to our adapter structure
267 void et131x_tx_dma_disable(struct et131x_adapter
*etdev
)
269 /* Setup the tramsmit dma configuration register */
270 writel(ET_TXDMA_CSR_HALT
|ET_TXDMA_SNGL_EPKT
,
271 &etdev
->regs
->txdma
.csr
);
275 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
276 * @etdev: pointer to our adapter structure
278 * Mainly used after a return to the D0 (full-power) state from a lower state.
280 void et131x_tx_dma_enable(struct et131x_adapter
*etdev
)
282 /* Setup the transmit dma configuration register for normal
285 writel(ET_TXDMA_SNGL_EPKT
|(PARM_DMA_CACHE_DEF
<< ET_TXDMA_CACHE_SHIFT
),
286 &etdev
->regs
->txdma
.csr
);
290 * et131x_init_send - Initialize send data structures
291 * @adapter: pointer to our private adapter structure
293 void et131x_init_send(struct et131x_adapter
*adapter
)
299 /* Setup some convenience pointers */
300 tx_ring
= &adapter
->TxRing
;
301 pMpTcb
= adapter
->TxRing
.MpTcbMem
;
303 tx_ring
->TCBReadyQueueHead
= pMpTcb
;
305 /* Go through and set up each TCB */
306 for (TcbCount
= 0; TcbCount
< NUM_TCB
; TcbCount
++) {
307 memset(pMpTcb
, 0, sizeof(MP_TCB
));
309 /* Set the link pointer in HW TCB to the next TCB in the
310 * chain. If this is the last TCB in the chain, also set the
313 if (TcbCount
< NUM_TCB
- 1) {
314 pMpTcb
->Next
= pMpTcb
+ 1;
316 tx_ring
->TCBReadyQueueTail
= pMpTcb
;
317 pMpTcb
->Next
= (PMP_TCB
) NULL
;
323 /* Curr send queue should now be empty */
324 tx_ring
->CurrSendHead
= (PMP_TCB
) NULL
;
325 tx_ring
->CurrSendTail
= (PMP_TCB
) NULL
;
327 INIT_LIST_HEAD(&adapter
->TxRing
.SendWaitQueue
);
331 * et131x_send_packets - This function is called by the OS to send packets
332 * @skb: the packet(s) to send
333 * @netdev:device on which to TX the above packet(s)
335 * Return 0 in almost all cases; non-zero value in extreme hard failure only
337 int et131x_send_packets(struct sk_buff
*skb
, struct net_device
*netdev
)
340 struct et131x_adapter
*etdev
= NULL
;
342 etdev
= netdev_priv(netdev
);
344 /* Send these packets
346 * NOTE: The Linux Tx entry point is only given one packet at a time
347 * to Tx, so the PacketCount and it's array used makes no sense here
350 /* Queue is not empty or TCB is not available */
351 if (!list_empty(&etdev
->TxRing
.SendWaitQueue
) ||
352 MP_TCB_RESOURCES_NOT_AVAILABLE(etdev
)) {
353 /* NOTE: If there's an error on send, no need to queue the
354 * packet under Linux; if we just send an error up to the
355 * netif layer, it will resend the skb to us.
359 /* We need to see if the link is up; if it's not, make the
360 * netif layer think we're good and drop the packet
363 * if( MP_SHOULD_FAIL_SEND( etdev ) ||
364 * etdev->DriverNoPhyAccess )
366 if (MP_SHOULD_FAIL_SEND(etdev
) || !netif_carrier_ok(netdev
)) {
367 dev_kfree_skb_any(skb
);
370 etdev
->net_stats
.tx_dropped
++;
372 status
= et131x_send_packet(skb
, etdev
);
374 if (status
== -ENOMEM
) {
376 /* NOTE: If there's an error on send, no need
377 * to queue the packet under Linux; if we just
378 * send an error up to the netif layer, it
379 * will resend the skb to us.
381 } else if (status
!= 0) {
382 /* On any other error, make netif think we're
383 * OK and drop the packet
385 dev_kfree_skb_any(skb
);
387 etdev
->net_stats
.tx_dropped
++;
395 * et131x_send_packet - Do the work to send a packet
396 * @skb: the packet(s) to send
397 * @etdev: a pointer to the device's private adapter structure
399 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
401 * Assumption: Send spinlock has been acquired
403 static int et131x_send_packet(struct sk_buff
*skb
,
404 struct et131x_adapter
*etdev
)
407 PMP_TCB pMpTcb
= NULL
;
411 /* All packets must have at least a MAC address and a protocol type */
412 if (skb
->len
< ETH_HLEN
) {
416 /* Get a TCB for this packet */
417 spin_lock_irqsave(&etdev
->TCBReadyQLock
, flags
);
419 pMpTcb
= etdev
->TxRing
.TCBReadyQueueHead
;
421 if (pMpTcb
== NULL
) {
422 spin_unlock_irqrestore(&etdev
->TCBReadyQLock
, flags
);
426 etdev
->TxRing
.TCBReadyQueueHead
= pMpTcb
->Next
;
428 if (etdev
->TxRing
.TCBReadyQueueHead
== NULL
)
429 etdev
->TxRing
.TCBReadyQueueTail
= NULL
;
431 spin_unlock_irqrestore(&etdev
->TCBReadyQLock
, flags
);
433 pMpTcb
->PacketLength
= skb
->len
;
434 pMpTcb
->Packet
= skb
;
436 if ((skb
->data
!= NULL
) && ((skb
->len
- skb
->data_len
) >= 6)) {
437 shbufva
= (uint16_t *) skb
->data
;
439 if ((shbufva
[0] == 0xffff) &&
440 (shbufva
[1] == 0xffff) && (shbufva
[2] == 0xffff)) {
441 pMpTcb
->Flags
|= fMP_DEST_BROAD
;
442 } else if ((shbufva
[0] & 0x3) == 0x0001) {
443 pMpTcb
->Flags
|= fMP_DEST_MULTI
;
449 /* Call the NIC specific send handler. */
451 status
= nic_send_packet(etdev
, pMpTcb
);
454 spin_lock_irqsave(&etdev
->TCBReadyQLock
, flags
);
456 if (etdev
->TxRing
.TCBReadyQueueTail
) {
457 etdev
->TxRing
.TCBReadyQueueTail
->Next
= pMpTcb
;
459 /* Apparently ready Q is empty. */
460 etdev
->TxRing
.TCBReadyQueueHead
= pMpTcb
;
463 etdev
->TxRing
.TCBReadyQueueTail
= pMpTcb
;
464 spin_unlock_irqrestore(&etdev
->TCBReadyQLock
, flags
);
467 WARN_ON(etdev
->TxRing
.nBusySend
> NUM_TCB
);
472 * nic_send_packet - NIC specific send handler for version B silicon.
473 * @etdev: pointer to our adapter
474 * @pMpTcb: pointer to MP_TCB
476 * Returns 0 or errno.
478 static int nic_send_packet(struct et131x_adapter
*etdev
, PMP_TCB pMpTcb
)
481 TX_DESC_ENTRY_t CurDesc
[24];
482 uint32_t FragmentNumber
= 0;
483 uint32_t thiscopy
, remainder
;
484 struct sk_buff
*pPacket
= pMpTcb
->Packet
;
485 uint32_t FragListCount
= skb_shinfo(pPacket
)->nr_frags
+ 1;
486 struct skb_frag_struct
*pFragList
= &skb_shinfo(pPacket
)->frags
[0];
489 /* Part of the optimizations of this send routine restrict us to
490 * sending 24 fragments at a pass. In practice we should never see
491 * more than 5 fragments.
493 * NOTE: The older version of this function (below) can handle any
494 * number of fragments. If needed, we can call this function,
495 * although it is less efficient.
497 if (FragListCount
> 23) {
501 memset(CurDesc
, 0, sizeof(TX_DESC_ENTRY_t
) * (FragListCount
+ 1));
503 for (loopIndex
= 0; loopIndex
< FragListCount
; loopIndex
++) {
504 /* If there is something in this element, lets get a
505 * descriptor from the ring and get the necessary data
507 if (loopIndex
== 0) {
508 /* If the fragments are smaller than a standard MTU,
509 * then map them to a single descriptor in the Tx
510 * Desc ring. However, if they're larger, as is
511 * possible with support for jumbo packets, then
512 * split them each across 2 descriptors.
514 * This will work until we determine why the hardware
515 * doesn't seem to like large fragments.
517 if ((pPacket
->len
- pPacket
->data_len
) <= 1514) {
518 CurDesc
[FragmentNumber
].DataBufferPtrHigh
= 0;
519 /* Low 16bits are length, high is vlan and
520 unused currently so zero */
521 CurDesc
[FragmentNumber
].word2
=
522 pPacket
->len
- pPacket
->data_len
;
524 /* NOTE: Here, the dma_addr_t returned from
525 * pci_map_single() is implicitly cast as a
526 * uint32_t. Although dma_addr_t can be
527 * 64-bit, the address returned by
528 * pci_map_single() is always 32-bit
529 * addressable (as defined by the pci/dma
532 CurDesc
[FragmentNumber
++].DataBufferPtrLow
=
533 pci_map_single(etdev
->pdev
,
539 CurDesc
[FragmentNumber
].DataBufferPtrHigh
= 0;
540 CurDesc
[FragmentNumber
].word2
=
541 (pPacket
->len
- pPacket
->data_len
) / 2;
543 /* NOTE: Here, the dma_addr_t returned from
544 * pci_map_single() is implicitly cast as a
545 * uint32_t. Although dma_addr_t can be
546 * 64-bit, the address returned by
547 * pci_map_single() is always 32-bit
548 * addressable (as defined by the pci/dma
551 CurDesc
[FragmentNumber
++].DataBufferPtrLow
=
552 pci_map_single(etdev
->pdev
,
555 pPacket
->data_len
) / 2),
557 CurDesc
[FragmentNumber
].DataBufferPtrHigh
= 0;
559 CurDesc
[FragmentNumber
].word2
=
560 (pPacket
->len
- pPacket
->data_len
) / 2;
562 /* NOTE: Here, the dma_addr_t returned from
563 * pci_map_single() is implicitly cast as a
564 * uint32_t. Although dma_addr_t can be
565 * 64-bit, the address returned by
566 * pci_map_single() is always 32-bit
567 * addressable (as defined by the pci/dma
570 CurDesc
[FragmentNumber
++].DataBufferPtrLow
=
571 pci_map_single(etdev
->pdev
,
574 pPacket
->data_len
) / 2),
576 pPacket
->data_len
) / 2),
580 CurDesc
[FragmentNumber
].DataBufferPtrHigh
= 0;
581 CurDesc
[FragmentNumber
].word2
=
582 pFragList
[loopIndex
- 1].size
;
584 /* NOTE: Here, the dma_addr_t returned from
585 * pci_map_page() is implicitly cast as a uint32_t.
586 * Although dma_addr_t can be 64-bit, the address
587 * returned by pci_map_page() is always 32-bit
588 * addressable (as defined by the pci/dma subsystem)
590 CurDesc
[FragmentNumber
++].DataBufferPtrLow
=
591 pci_map_page(etdev
->pdev
,
592 pFragList
[loopIndex
- 1].page
,
593 pFragList
[loopIndex
- 1].page_offset
,
594 pFragList
[loopIndex
- 1].size
,
599 if (FragmentNumber
== 0)
602 if (etdev
->linkspeed
== TRUEPHY_SPEED_1000MBPS
) {
603 if (++etdev
->TxRing
.TxPacketsSinceLastinterrupt
==
604 PARM_TX_NUM_BUFS_DEF
) {
605 /* Last element & Interrupt flag */
606 CurDesc
[FragmentNumber
- 1].word3
= 0x5;
607 etdev
->TxRing
.TxPacketsSinceLastinterrupt
= 0;
608 } else { /* Last element */
609 CurDesc
[FragmentNumber
- 1].word3
= 0x1;
612 CurDesc
[FragmentNumber
- 1].word3
= 0x5;
614 CurDesc
[0].word3
|= 2; /* First element flag */
616 pMpTcb
->WrIndexStart
= etdev
->TxRing
.txDmaReadyToSend
;
617 pMpTcb
->PacketStaleCount
= 0;
619 spin_lock_irqsave(&etdev
->SendHWLock
, flags
);
621 thiscopy
= NUM_DESC_PER_RING_TX
-
622 INDEX10(etdev
->TxRing
.txDmaReadyToSend
);
624 if (thiscopy
>= FragmentNumber
) {
626 thiscopy
= FragmentNumber
;
628 remainder
= FragmentNumber
- thiscopy
;
631 memcpy(etdev
->TxRing
.pTxDescRingVa
+
632 INDEX10(etdev
->TxRing
.txDmaReadyToSend
), CurDesc
,
633 sizeof(TX_DESC_ENTRY_t
) * thiscopy
);
635 add_10bit(&etdev
->TxRing
.txDmaReadyToSend
, thiscopy
);
637 if (INDEX10(etdev
->TxRing
.txDmaReadyToSend
)== 0 ||
638 INDEX10(etdev
->TxRing
.txDmaReadyToSend
) == NUM_DESC_PER_RING_TX
) {
639 etdev
->TxRing
.txDmaReadyToSend
&= ~ET_DMA10_MASK
;
640 etdev
->TxRing
.txDmaReadyToSend
^= ET_DMA10_WRAP
;
644 memcpy(etdev
->TxRing
.pTxDescRingVa
,
646 sizeof(TX_DESC_ENTRY_t
) * remainder
);
648 add_10bit(&etdev
->TxRing
.txDmaReadyToSend
, remainder
);
651 if (INDEX10(etdev
->TxRing
.txDmaReadyToSend
) == 0) {
652 if (etdev
->TxRing
.txDmaReadyToSend
)
653 pMpTcb
->WrIndex
= NUM_DESC_PER_RING_TX
- 1;
655 pMpTcb
->WrIndex
= ET_DMA10_WRAP
| (NUM_DESC_PER_RING_TX
- 1);
657 pMpTcb
->WrIndex
= etdev
->TxRing
.txDmaReadyToSend
- 1;
659 spin_lock(&etdev
->TCBSendQLock
);
661 if (etdev
->TxRing
.CurrSendTail
)
662 etdev
->TxRing
.CurrSendTail
->Next
= pMpTcb
;
664 etdev
->TxRing
.CurrSendHead
= pMpTcb
;
666 etdev
->TxRing
.CurrSendTail
= pMpTcb
;
668 WARN_ON(pMpTcb
->Next
!= NULL
);
670 etdev
->TxRing
.nBusySend
++;
672 spin_unlock(&etdev
->TCBSendQLock
);
674 /* Write the new write pointer back to the device. */
675 writel(etdev
->TxRing
.txDmaReadyToSend
,
676 &etdev
->regs
->txdma
.service_request
);
678 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
679 * timer to wake us up if this packet isn't followed by N more.
681 if (etdev
->linkspeed
== TRUEPHY_SPEED_1000MBPS
) {
682 writel(PARM_TX_TIME_INT_DEF
* NANO_IN_A_MICRO
,
683 &etdev
->regs
->global
.watchdog_timer
);
685 spin_unlock_irqrestore(&etdev
->SendHWLock
, flags
);
692 * et131x_free_send_packet - Recycle a MP_TCB, complete the packet if necessary
693 * @etdev: pointer to our adapter
694 * @pMpTcb: pointer to MP_TCB
696 * Assumption - Send spinlock has been acquired
698 inline void et131x_free_send_packet(struct et131x_adapter
*etdev
,
702 TX_DESC_ENTRY_t
*desc
= NULL
;
703 struct net_device_stats
*stats
= &etdev
->net_stats
;
705 if (pMpTcb
->Flags
& fMP_DEST_BROAD
)
706 atomic_inc(&etdev
->Stats
.brdcstxmt
);
707 else if (pMpTcb
->Flags
& fMP_DEST_MULTI
)
708 atomic_inc(&etdev
->Stats
.multixmt
);
710 atomic_inc(&etdev
->Stats
.unixmt
);
712 if (pMpTcb
->Packet
) {
713 stats
->tx_bytes
+= pMpTcb
->Packet
->len
;
715 /* Iterate through the TX descriptors on the ring
716 * corresponding to this packet and umap the fragments
721 (TX_DESC_ENTRY_t
*) (etdev
->TxRing
.pTxDescRingVa
+
722 INDEX10(pMpTcb
->WrIndexStart
));
724 pci_unmap_single(etdev
->pdev
,
725 desc
->DataBufferPtrLow
,
726 desc
->word2
, PCI_DMA_TODEVICE
);
728 add_10bit(&pMpTcb
->WrIndexStart
, 1);
729 if (INDEX10(pMpTcb
->WrIndexStart
) >=
730 NUM_DESC_PER_RING_TX
) {
731 pMpTcb
->WrIndexStart
&= ~ET_DMA10_MASK
;
732 pMpTcb
->WrIndexStart
^= ET_DMA10_WRAP
;
734 } while (desc
!= (etdev
->TxRing
.pTxDescRingVa
+
735 INDEX10(pMpTcb
->WrIndex
)));
737 dev_kfree_skb_any(pMpTcb
->Packet
);
740 memset(pMpTcb
, 0, sizeof(MP_TCB
));
742 /* Add the TCB to the Ready Q */
743 spin_lock_irqsave(&etdev
->TCBReadyQLock
, flags
);
745 etdev
->Stats
.opackets
++;
747 if (etdev
->TxRing
.TCBReadyQueueTail
) {
748 etdev
->TxRing
.TCBReadyQueueTail
->Next
= pMpTcb
;
750 /* Apparently ready Q is empty. */
751 etdev
->TxRing
.TCBReadyQueueHead
= pMpTcb
;
754 etdev
->TxRing
.TCBReadyQueueTail
= pMpTcb
;
756 spin_unlock_irqrestore(&etdev
->TCBReadyQLock
, flags
);
757 WARN_ON(etdev
->TxRing
.nBusySend
< 0);
761 * et131x_free_busy_send_packets - Free and complete the stopped active sends
762 * @etdev: pointer to our adapter
764 * Assumption - Send spinlock has been acquired
766 void et131x_free_busy_send_packets(struct et131x_adapter
*etdev
)
769 struct list_head
*entry
;
771 uint32_t FreeCounter
= 0;
773 while (!list_empty(&etdev
->TxRing
.SendWaitQueue
)) {
774 spin_lock_irqsave(&etdev
->SendWaitLock
, flags
);
776 etdev
->TxRing
.nWaitSend
--;
777 spin_unlock_irqrestore(&etdev
->SendWaitLock
, flags
);
779 entry
= etdev
->TxRing
.SendWaitQueue
.next
;
782 etdev
->TxRing
.nWaitSend
= 0;
784 /* Any packets being sent? Check the first TCB on the send list */
785 spin_lock_irqsave(&etdev
->TCBSendQLock
, flags
);
787 pMpTcb
= etdev
->TxRing
.CurrSendHead
;
789 while ((pMpTcb
!= NULL
) && (FreeCounter
< NUM_TCB
)) {
790 PMP_TCB pNext
= pMpTcb
->Next
;
792 etdev
->TxRing
.CurrSendHead
= pNext
;
795 etdev
->TxRing
.CurrSendTail
= NULL
;
797 etdev
->TxRing
.nBusySend
--;
799 spin_unlock_irqrestore(&etdev
->TCBSendQLock
, flags
);
802 et131x_free_send_packet(etdev
, pMpTcb
);
804 spin_lock_irqsave(&etdev
->TCBSendQLock
, flags
);
806 pMpTcb
= etdev
->TxRing
.CurrSendHead
;
809 WARN_ON(FreeCounter
== NUM_TCB
);
811 spin_unlock_irqrestore(&etdev
->TCBSendQLock
, flags
);
813 etdev
->TxRing
.nBusySend
= 0;
817 * et131x_handle_send_interrupt - Interrupt handler for sending processing
818 * @etdev: pointer to our adapter
820 * Re-claim the send resources, complete sends and get more to send from
821 * the send wait queue.
823 * Assumption - Send spinlock has been acquired
825 void et131x_handle_send_interrupt(struct et131x_adapter
*etdev
)
827 /* Mark as completed any packets which have been sent by the device. */
828 et131x_update_tcb_list(etdev
);
830 /* If we queued any transmits because we didn't have any TCBs earlier,
831 * dequeue and send those packets now, as long as we have free TCBs.
833 et131x_check_send_wait_list(etdev
);
837 * et131x_update_tcb_list - Helper routine for Send Interrupt handler
838 * @etdev: pointer to our adapter
840 * Re-claims the send resources and completes sends. Can also be called as
841 * part of the NIC send routine when the "ServiceComplete" indication has
844 static void et131x_update_tcb_list(struct et131x_adapter
*etdev
)
851 ServiceComplete
= readl(&etdev
->regs
->txdma
.NewServiceComplete
);
852 index
= INDEX10(ServiceComplete
);
854 /* Has the ring wrapped? Process any descriptors that do not have
855 * the same "wrap" indicator as the current completion indicator
857 spin_lock_irqsave(&etdev
->TCBSendQLock
, flags
);
859 pMpTcb
= etdev
->TxRing
.CurrSendHead
;
862 ((ServiceComplete
^ pMpTcb
->WrIndex
) & ET_DMA10_WRAP
) &&
863 index
< INDEX10(pMpTcb
->WrIndex
)) {
864 etdev
->TxRing
.nBusySend
--;
865 etdev
->TxRing
.CurrSendHead
= pMpTcb
->Next
;
866 if (pMpTcb
->Next
== NULL
)
867 etdev
->TxRing
.CurrSendTail
= NULL
;
869 spin_unlock_irqrestore(&etdev
->TCBSendQLock
, flags
);
870 et131x_free_send_packet(etdev
, pMpTcb
);
871 spin_lock_irqsave(&etdev
->TCBSendQLock
, flags
);
873 /* Goto the next packet */
874 pMpTcb
= etdev
->TxRing
.CurrSendHead
;
877 !((ServiceComplete
^ pMpTcb
->WrIndex
) & ET_DMA10_WRAP
)
878 && index
> (pMpTcb
->WrIndex
& ET_DMA10_MASK
)) {
879 etdev
->TxRing
.nBusySend
--;
880 etdev
->TxRing
.CurrSendHead
= pMpTcb
->Next
;
881 if (pMpTcb
->Next
== NULL
)
882 etdev
->TxRing
.CurrSendTail
= NULL
;
884 spin_unlock_irqrestore(&etdev
->TCBSendQLock
, flags
);
885 et131x_free_send_packet(etdev
, pMpTcb
);
886 spin_lock_irqsave(&etdev
->TCBSendQLock
, flags
);
888 /* Goto the next packet */
889 pMpTcb
= etdev
->TxRing
.CurrSendHead
;
892 /* Wake up the queue when we hit a low-water mark */
893 if (etdev
->TxRing
.nBusySend
<= (NUM_TCB
/ 3))
894 netif_wake_queue(etdev
->netdev
);
896 spin_unlock_irqrestore(&etdev
->TCBSendQLock
, flags
);
900 * et131x_check_send_wait_list - Helper routine for the interrupt handler
901 * @etdev: pointer to our adapter
903 * Takes packets from the send wait queue and posts them to the device (if
906 static void et131x_check_send_wait_list(struct et131x_adapter
*etdev
)
910 spin_lock_irqsave(&etdev
->SendWaitLock
, flags
);
912 while (!list_empty(&etdev
->TxRing
.SendWaitQueue
) &&
913 MP_TCB_RESOURCES_AVAILABLE(etdev
)) {
914 struct list_head
*entry
;
916 entry
= etdev
->TxRing
.SendWaitQueue
.next
;
918 etdev
->TxRing
.nWaitSend
--;
921 spin_unlock_irqrestore(&etdev
->SendWaitLock
, flags
);