include/asm-x86_64/msr.h

   1 #ifndef X86_64_MSR_H
   2 #define X86_64_MSR_H 1
   3
   4 #ifndef __ASSEMBLY__
   5 /*
   6  * Access to machine-specific registers (available on 586 and better only)
   7  * Note: the rd* operations modify the parameters directly (without using
   8  * pointer indirection), this allows gcc to optimize better
   9  */
  10
  11 #define rdmsr(msr,val1,val2) \
  12        __asm__ __volatile__("rdmsr" \
  13                             : "=a" (val1), "=d" (val2) \
  14                             : "c" (msr))
  15
  16
  17 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
  18        __asm__ __volatile__("rdmsr" \
  19                             : "=a" (a__), "=d" (b__) \
  20                             : "c" (msr)); \
  21        val = a__ | (b__<<32); \
  22 } while(0)
  23
  24 #define wrmsr(msr,val1,val2) \
  25      __asm__ __volatile__("wrmsr" \
  26                           : /* no outputs */ \
  27                           : "c" (msr), "a" (val1), "d" (val2))
  28
  29 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
  30
  31 /* wrmsr with exception handling */
  32 #define wrmsr_safe(msr,a,b) ({ int ret__;                       \
  33         asm volatile("2: wrmsr ; xorl %0,%0\n"                  \
  34                      "1:\n\t"                                   \
  35                      ".section .fixup,\"ax\"\n\t"               \
  36                      "3:  movl %4,%0 ; jmp 1b\n\t"              \
  37                      ".previous\n\t"                            \
  38                      ".section __ex_table,\"a\"\n"              \
  39                      "   .align 8\n\t"                          \
  40                      "   .quad  2b,3b\n\t"                      \
  41                      ".previous"                                \
  42                      : "=a" (ret__)                             \
  43                      : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
  44         ret__; })
  45
  46 #define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
  47
  48 #define rdmsr_safe(msr,a,b) \
  49         ({ int ret__;                                           \
  50           asm volatile ("1:       rdmsr\n"                      \
  51                       "2:\n"                                    \
  52                       ".section .fixup,\"ax\"\n"                \
  53                       "3:       movl %4,%0\n"                   \
  54                       " jmp 2b\n"                               \
  55                       ".previous\n"                             \
  56                       ".section __ex_table,\"a\"\n"             \
  57                       " .align 8\n"                             \
  58                       " .quad 1b,3b\n"                          \
  59                       ".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b))\
  60                       :"c"(msr), "i"(-EIO), "0"(0));            \
  61           ret__; })
  62
  63 #define rdtsc(low,high) \
  64      __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
  65
  66 #define rdtscl(low) \
  67      __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
  68
  69 #define rdtscll(val) do { \
  70      unsigned int __a,__d; \
  71      asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
  72      (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
  73 } while(0)
  74
  75 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
  76
  77 #define rdpmc(counter,low,high) \
  78      __asm__ __volatile__("rdpmc" \
  79                           : "=a" (low), "=d" (high) \
  80                           : "c" (counter))
  81
  82 static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
  83                          unsigned int *ecx, unsigned int *edx)
  84 {
  85         __asm__("cpuid"
  86                 : "=a" (*eax),
  87                   "=b" (*ebx),
  88                   "=c" (*ecx),
  89                   "=d" (*edx)
  90                 : "0" (op));
  91 }
  92
  93 /* Some CPUID calls want 'count' to be placed in ecx */
  94 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
  95                 int *edx)
  96 {
  97         __asm__("cpuid"
  98                 : "=a" (*eax),
  99                   "=b" (*ebx),
 100                   "=c" (*ecx),
 101                   "=d" (*edx)
 102                 : "0" (op), "c" (count));
 103 }
 104
 105 /*
 106  * CPUID functions returning a single datum
 107  */
 108 static inline unsigned int cpuid_eax(unsigned int op)
 109 {
 110         unsigned int eax;
 111
 112         __asm__("cpuid"
 113                 : "=a" (eax)
 114                 : "0" (op)
 115                 : "bx", "cx", "dx");
 116         return eax;
 117 }
 118 static inline unsigned int cpuid_ebx(unsigned int op)
 119 {
 120         unsigned int eax, ebx;
 121
 122         __asm__("cpuid"
 123                 : "=a" (eax), "=b" (ebx)
 124                 : "0" (op)
 125                 : "cx", "dx" );
 126         return ebx;
 127 }
 128 static inline unsigned int cpuid_ecx(unsigned int op)
 129 {
 130         unsigned int eax, ecx;
 131
 132         __asm__("cpuid"
 133                 : "=a" (eax), "=c" (ecx)
 134                 : "0" (op)
 135                 : "bx", "dx" );
 136         return ecx;
 137 }
 138 static inline unsigned int cpuid_edx(unsigned int op)
 139 {
 140         unsigned int eax, edx;
 141
 142         __asm__("cpuid"
 143                 : "=a" (eax), "=d" (edx)
 144                 : "0" (op)
 145                 : "bx", "cx");
 146         return edx;
 147 }
 148
 149 #define MSR_IA32_UCODE_WRITE            0x79
 150 #define MSR_IA32_UCODE_REV              0x8b
 151
 152
 153 #endif
 154
 155 /* AMD/K8 specific MSRs */
 156 #define MSR_EFER 0xc0000080             /* extended feature register */
 157 #define MSR_STAR 0xc0000081             /* legacy mode SYSCALL target */
 158 #define MSR_LSTAR 0xc0000082            /* long mode SYSCALL target */
 159 #define MSR_CSTAR 0xc0000083            /* compatibility mode SYSCALL target */
 160 #define MSR_SYSCALL_MASK 0xc0000084     /* EFLAGS mask for syscall */
 161 #define MSR_FS_BASE 0xc0000100          /* 64bit GS base */
 162 #define MSR_GS_BASE 0xc0000101          /* 64bit FS base */
 163 #define MSR_KERNEL_GS_BASE  0xc0000102  /* SwapGS GS shadow (or USER_GS from kernel) */
 164 /* EFER bits: */
 165 #define _EFER_SCE 0  /* SYSCALL/SYSRET */
 166 #define _EFER_LME 8  /* Long mode enable */
 167 #define _EFER_LMA 10 /* Long mode active (read-only) */
 168 #define _EFER_NX 11  /* No execute enable */
 169
 170 #define EFER_SCE (1<<_EFER_SCE)
 171 #define EFER_LME (1<<_EFER_LME)
 172 #define EFER_LMA (1<<_EFER_LMA)
 173 #define EFER_NX (1<<_EFER_NX)
 174
 175 /* Intel MSRs. Some also available on other CPUs */
 176 #define MSR_IA32_TSC            0x10
 177 #define MSR_IA32_PLATFORM_ID    0x17
 178
 179 #define MSR_IA32_PERFCTR0      0xc1
 180 #define MSR_IA32_PERFCTR1      0xc2
 181
 182 #define MSR_MTRRcap             0x0fe
 183 #define MSR_IA32_BBL_CR_CTL        0x119
 184
 185 #define MSR_IA32_SYSENTER_CS    0x174
 186 #define MSR_IA32_SYSENTER_ESP   0x175
 187 #define MSR_IA32_SYSENTER_EIP   0x176
 188
 189 #define MSR_IA32_MCG_CAP       0x179
 190 #define MSR_IA32_MCG_STATUS        0x17a
 191 #define MSR_IA32_MCG_CTL       0x17b
 192
 193 #define MSR_IA32_EVNTSEL0      0x186
 194 #define MSR_IA32_EVNTSEL1      0x187
 195
 196 #define MSR_IA32_DEBUGCTLMSR       0x1d9
 197 #define MSR_IA32_LASTBRANCHFROMIP  0x1db
 198 #define MSR_IA32_LASTBRANCHTOIP        0x1dc
 199 #define MSR_IA32_LASTINTFROMIP     0x1dd
 200 #define MSR_IA32_LASTINTTOIP       0x1de
 201
 202 #define MSR_MTRRfix64K_00000    0x250
 203 #define MSR_MTRRfix16K_80000    0x258
 204 #define MSR_MTRRfix16K_A0000    0x259
 205 #define MSR_MTRRfix4K_C0000     0x268
 206 #define MSR_MTRRfix4K_C8000     0x269
 207 #define MSR_MTRRfix4K_D0000     0x26a
 208 #define MSR_MTRRfix4K_D8000     0x26b
 209 #define MSR_MTRRfix4K_E0000     0x26c
 210 #define MSR_MTRRfix4K_E8000     0x26d
 211 #define MSR_MTRRfix4K_F0000     0x26e
 212 #define MSR_MTRRfix4K_F8000     0x26f
 213 #define MSR_MTRRdefType         0x2ff
 214
 215 #define MSR_IA32_MC0_CTL       0x400
 216 #define MSR_IA32_MC0_STATUS        0x401
 217 #define MSR_IA32_MC0_ADDR      0x402
 218 #define MSR_IA32_MC0_MISC      0x403
 219
 220 #define MSR_P6_PERFCTR0                 0xc1
 221 #define MSR_P6_PERFCTR1                 0xc2
 222 #define MSR_P6_EVNTSEL0                 0x186
 223 #define MSR_P6_EVNTSEL1                 0x187
 224
 225 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
 226 #define MSR_K7_EVNTSEL0            0xC0010000
 227 #define MSR_K7_PERFCTR0            0xC0010004
 228 #define MSR_K7_EVNTSEL1            0xC0010001
 229 #define MSR_K7_PERFCTR1            0xC0010005
 230 #define MSR_K7_EVNTSEL2            0xC0010002
 231 #define MSR_K7_PERFCTR2            0xC0010006
 232 #define MSR_K7_EVNTSEL3            0xC0010003
 233 #define MSR_K7_PERFCTR3            0xC0010007
 234 #define MSR_K8_TOP_MEM1            0xC001001A
 235 #define MSR_K8_TOP_MEM2            0xC001001D
 236 #define MSR_K8_SYSCFG              0xC0010010
 237 #define MSR_K8_HWCR                0xC0010015
 238
 239 /* K6 MSRs */
 240 #define MSR_K6_EFER                     0xC0000080
 241 #define MSR_K6_STAR                     0xC0000081
 242 #define MSR_K6_WHCR                     0xC0000082
 243 #define MSR_K6_UWCCR                    0xC0000085
 244 #define MSR_K6_PSOR                     0xC0000087
 245 #define MSR_K6_PFIR                     0xC0000088
 246
 247 /* Centaur-Hauls/IDT defined MSRs. */
 248 #define MSR_IDT_FCR1                    0x107
 249 #define MSR_IDT_FCR2                    0x108
 250 #define MSR_IDT_FCR3                    0x109
 251 #define MSR_IDT_FCR4                    0x10a
 252
 253 #define MSR_IDT_MCR0                    0x110
 254 #define MSR_IDT_MCR1                    0x111
 255 #define MSR_IDT_MCR2                    0x112
 256 #define MSR_IDT_MCR3                    0x113
 257 #define MSR_IDT_MCR4                    0x114
 258 #define MSR_IDT_MCR5                    0x115
 259 #define MSR_IDT_MCR6                    0x116
 260 #define MSR_IDT_MCR7                    0x117
 261 #define MSR_IDT_MCR_CTRL                0x120
 262
 263 /* VIA Cyrix defined MSRs*/
 264 #define MSR_VIA_FCR                     0x1107
 265 #define MSR_VIA_LONGHAUL                0x110a
 266 #define MSR_VIA_RNG                     0x110b
 267 #define MSR_VIA_BCR2                    0x1147
 268
 269 /* Intel defined MSRs. */
 270 #define MSR_IA32_P5_MC_ADDR             0
 271 #define MSR_IA32_P5_MC_TYPE             1
 272 #define MSR_IA32_PLATFORM_ID            0x17
 273 #define MSR_IA32_EBL_CR_POWERON         0x2a
 274
 275 #define MSR_IA32_APICBASE               0x1b
 276 #define MSR_IA32_APICBASE_BSP           (1<<8)
 277 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 278 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 279
 280 /* P4/Xeon+ specific */
 281 #define MSR_IA32_MCG_EAX                0x180
 282 #define MSR_IA32_MCG_EBX                0x181
 283 #define MSR_IA32_MCG_ECX                0x182
 284 #define MSR_IA32_MCG_EDX                0x183
 285 #define MSR_IA32_MCG_ESI                0x184
 286 #define MSR_IA32_MCG_EDI                0x185
 287 #define MSR_IA32_MCG_EBP                0x186
 288 #define MSR_IA32_MCG_ESP                0x187
 289 #define MSR_IA32_MCG_EFLAGS             0x188
 290 #define MSR_IA32_MCG_EIP                0x189
 291 #define MSR_IA32_MCG_RESERVED           0x18A
 292
 293 #define MSR_P6_EVNTSEL0                 0x186
 294 #define MSR_P6_EVNTSEL1                 0x187
 295
 296 #define MSR_IA32_PERF_STATUS            0x198
 297 #define MSR_IA32_PERF_CTL               0x199
 298
 299 #define MSR_IA32_THERM_CONTROL          0x19a
 300 #define MSR_IA32_THERM_INTERRUPT        0x19b
 301 #define MSR_IA32_THERM_STATUS           0x19c
 302 #define MSR_IA32_MISC_ENABLE            0x1a0
 303
 304 #define MSR_IA32_DEBUGCTLMSR            0x1d9
 305 #define MSR_IA32_LASTBRANCHFROMIP       0x1db
 306 #define MSR_IA32_LASTBRANCHTOIP         0x1dc
 307 #define MSR_IA32_LASTINTFROMIP          0x1dd
 308 #define MSR_IA32_LASTINTTOIP            0x1de
 309
 310 #define MSR_IA32_MC0_CTL                0x400
 311 #define MSR_IA32_MC0_STATUS             0x401
 312 #define MSR_IA32_MC0_ADDR               0x402
 313 #define MSR_IA32_MC0_MISC               0x403
 314
 315 /* Pentium IV performance counter MSRs */
 316 #define MSR_P4_BPU_PERFCTR0             0x300
 317 #define MSR_P4_BPU_PERFCTR1             0x301
 318 #define MSR_P4_BPU_PERFCTR2             0x302
 319 #define MSR_P4_BPU_PERFCTR3             0x303
 320 #define MSR_P4_MS_PERFCTR0              0x304
 321 #define MSR_P4_MS_PERFCTR1              0x305
 322 #define MSR_P4_MS_PERFCTR2              0x306
 323 #define MSR_P4_MS_PERFCTR3              0x307
 324 #define MSR_P4_FLAME_PERFCTR0           0x308
 325 #define MSR_P4_FLAME_PERFCTR1           0x309
 326 #define MSR_P4_FLAME_PERFCTR2           0x30a
 327 #define MSR_P4_FLAME_PERFCTR3           0x30b
 328 #define MSR_P4_IQ_PERFCTR0              0x30c
 329 #define MSR_P4_IQ_PERFCTR1              0x30d
 330 #define MSR_P4_IQ_PERFCTR2              0x30e
 331 #define MSR_P4_IQ_PERFCTR3              0x30f
 332 #define MSR_P4_IQ_PERFCTR4              0x310
 333 #define MSR_P4_IQ_PERFCTR5              0x311
 334 #define MSR_P4_BPU_CCCR0                0x360
 335 #define MSR_P4_BPU_CCCR1                0x361
 336 #define MSR_P4_BPU_CCCR2                0x362
 337 #define MSR_P4_BPU_CCCR3                0x363
 338 #define MSR_P4_MS_CCCR0                 0x364
 339 #define MSR_P4_MS_CCCR1                 0x365
 340 #define MSR_P4_MS_CCCR2                 0x366
 341 #define MSR_P4_MS_CCCR3                 0x367
 342 #define MSR_P4_FLAME_CCCR0              0x368
 343 #define MSR_P4_FLAME_CCCR1              0x369
 344 #define MSR_P4_FLAME_CCCR2              0x36a
 345 #define MSR_P4_FLAME_CCCR3              0x36b
 346 #define MSR_P4_IQ_CCCR0                 0x36c
 347 #define MSR_P4_IQ_CCCR1                 0x36d
 348 #define MSR_P4_IQ_CCCR2                 0x36e
 349 #define MSR_P4_IQ_CCCR3                 0x36f
 350 #define MSR_P4_IQ_CCCR4                 0x370
 351 #define MSR_P4_IQ_CCCR5                 0x371
 352 #define MSR_P4_ALF_ESCR0                0x3ca
 353 #define MSR_P4_ALF_ESCR1                0x3cb
 354 #define MSR_P4_BPU_ESCR0                0x3b2
 355 #define MSR_P4_BPU_ESCR1                0x3b3
 356 #define MSR_P4_BSU_ESCR0                0x3a0
 357 #define MSR_P4_BSU_ESCR1                0x3a1
 358 #define MSR_P4_CRU_ESCR0                0x3b8
 359 #define MSR_P4_CRU_ESCR1                0x3b9
 360 #define MSR_P4_CRU_ESCR2                0x3cc
 361 #define MSR_P4_CRU_ESCR3                0x3cd
 362 #define MSR_P4_CRU_ESCR4                0x3e0
 363 #define MSR_P4_CRU_ESCR5                0x3e1
 364 #define MSR_P4_DAC_ESCR0                0x3a8
 365 #define MSR_P4_DAC_ESCR1                0x3a9
 366 #define MSR_P4_FIRM_ESCR0               0x3a4
 367 #define MSR_P4_FIRM_ESCR1               0x3a5
 368 #define MSR_P4_FLAME_ESCR0              0x3a6
 369 #define MSR_P4_FLAME_ESCR1              0x3a7
 370 #define MSR_P4_FSB_ESCR0                0x3a2
 371 #define MSR_P4_FSB_ESCR1                0x3a3
 372 #define MSR_P4_IQ_ESCR0                 0x3ba
 373 #define MSR_P4_IQ_ESCR1                 0x3bb
 374 #define MSR_P4_IS_ESCR0                 0x3b4
 375 #define MSR_P4_IS_ESCR1                 0x3b5
 376 #define MSR_P4_ITLB_ESCR0               0x3b6
 377 #define MSR_P4_ITLB_ESCR1               0x3b7
 378 #define MSR_P4_IX_ESCR0                 0x3c8
 379 #define MSR_P4_IX_ESCR1                 0x3c9
 380 #define MSR_P4_MOB_ESCR0                0x3aa
 381 #define MSR_P4_MOB_ESCR1                0x3ab
 382 #define MSR_P4_MS_ESCR0                 0x3c0
 383 #define MSR_P4_MS_ESCR1                 0x3c1
 384 #define MSR_P4_PMH_ESCR0                0x3ac
 385 #define MSR_P4_PMH_ESCR1                0x3ad
 386 #define MSR_P4_RAT_ESCR0                0x3bc
 387 #define MSR_P4_RAT_ESCR1                0x3bd
 388 #define MSR_P4_SAAT_ESCR0               0x3ae
 389 #define MSR_P4_SAAT_ESCR1               0x3af
 390 #define MSR_P4_SSU_ESCR0                0x3be
 391 #define MSR_P4_SSU_ESCR1                0x3bf    /* guess: not defined in manual */
 392 #define MSR_P4_TBPU_ESCR0               0x3c2
 393 #define MSR_P4_TBPU_ESCR1               0x3c3
 394 #define MSR_P4_TC_ESCR0                 0x3c4
 395 #define MSR_P4_TC_ESCR1                 0x3c5
 396 #define MSR_P4_U2L_ESCR0                0x3b0
 397 #define MSR_P4_U2L_ESCR1                0x3b1
 398
 399 #endif