drivers/net/smc91x.h

   1 /*------------------------------------------------------------------------
   2  . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
   3  .
   4  . Copyright (C) 1996 by Erik Stahlman
   5  . Copyright (C) 2001 Standard Microsystems Corporation
   6  .      Developed by Simple Network Magic Corporation
   7  . Copyright (C) 2003 Monta Vista Software, Inc.
   8  .      Unified SMC91x driver by Nicolas Pitre
   9  .
  10  . This program is free software; you can redistribute it and/or modify
  11  . it under the terms of the GNU General Public License as published by
  12  . the Free Software Foundation; either version 2 of the License, or
  13  . (at your option) any later version.
  14  .
  15  . This program is distributed in the hope that it will be useful,
  16  . but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  . GNU General Public License for more details.
  19  .
  20  . You should have received a copy of the GNU General Public License
  21  . along with this program; if not, write to the Free Software
  22  . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  .
  24  . Information contained in this file was obtained from the LAN91C111
  25  . manual from SMC.  To get a copy, if you really want one, you can find
  26  . information under www.smsc.com.
  27  .
  28  . Authors
  29  .      Erik Stahlman           <erik@vt.edu>
  30  .      Daris A Nevil           <dnevil@snmc.com>
  31  .      Nicolas Pitre           <nico@fluxnic.net>
  32  .
  33  ---------------------------------------------------------------------------*/
  34 #ifndef _SMC91X_H_
  35 #define _SMC91X_H_
  36
  37 #include <linux/smc91x.h>
  38
  39 /*
  40  * Define your architecture specific bus configuration parameters here.
  41  */
  42
  43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
  44     defined(CONFIG_MACH_MAINSTONE) ||\
  45     defined(CONFIG_MACH_ZYLONITE) ||\
  46     defined(CONFIG_MACH_LITTLETON) ||\
  47     defined(CONFIG_MACH_ZYLONITE2) ||\
  48     defined(CONFIG_ARCH_VIPER) ||\
  49     defined(CONFIG_MACH_STARGATE2)
  50
  51 #include <asm/mach-types.h>
  52
  53 /* Now the bus width is specified in the platform data
  54  * pretend here to support all I/O access types
  55  */
  56 #define SMC_CAN_USE_8BIT        1
  57 #define SMC_CAN_USE_16BIT       1
  58 #define SMC_CAN_USE_32BIT       1
  59 #define SMC_NOWAIT              1
  60
  61 #define SMC_IO_SHIFT            (lp->io_shift)
  62
  63 #define SMC_inb(a, r)           readb((a) + (r))
  64 #define SMC_inw(a, r)           readw((a) + (r))
  65 #define SMC_inl(a, r)           readl((a) + (r))
  66 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
  67 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
  68 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
  69 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
  70 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
  71 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
  72 #define SMC_IRQ_FLAGS           (-1)    /* from resource */
  73
  74 /* We actually can't write halfwords properly if not word aligned */
  75 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  76 {
  77         if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
  78                 unsigned int v = val << 16;
  79                 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
  80                 writel(v, ioaddr + (reg & ~2));
  81         } else {
  82                 writew(val, ioaddr + reg);
  83         }
  84 }
  85
  86 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
  87
  88 /* We can only do 16-bit reads and writes in the static memory space. */
  89 #define SMC_CAN_USE_8BIT        0
  90 #define SMC_CAN_USE_16BIT       1
  91 #define SMC_CAN_USE_32BIT       0
  92 #define SMC_NOWAIT              1
  93
  94 #define SMC_IO_SHIFT            0
  95
  96 #define SMC_inw(a, r)           in_be16((volatile u16 *)((a) + (r)))
  97 #define SMC_outw(v, a, r)       out_be16((volatile u16 *)((a) + (r)), v)
  98 #define SMC_insw(a, r, p, l)                                            \
  99         do {                                                            \
 100                 unsigned long __port = (a) + (r);                       \
 101                 u16 *__p = (u16 *)(p);                                  \
 102                 int __l = (l);                                          \
 103                 insw(__port, __p, __l);                                 \
 104                 while (__l > 0) {                                       \
 105                         *__p = swab16(*__p);                            \
 106                         __p++;                                          \
 107                         __l--;                                          \
 108                 }                                                       \
 109         } while (0)
 110 #define SMC_outsw(a, r, p, l)                                           \
 111         do {                                                            \
 112                 unsigned long __port = (a) + (r);                       \
 113                 u16 *__p = (u16 *)(p);                                  \
 114                 int __l = (l);                                          \
 115                 while (__l > 0) {                                       \
 116                         /* Believe it or not, the swab isn't needed. */ \
 117                         outw( /* swab16 */ (*__p++), __port);           \
 118                         __l--;                                          \
 119                 }                                                       \
 120         } while (0)
 121 #define SMC_IRQ_FLAGS           (0)
 122
 123 #elif defined(CONFIG_SA1100_PLEB)
 124 /* We can only do 16-bit reads and writes in the static memory space. */
 125 #define SMC_CAN_USE_8BIT        1
 126 #define SMC_CAN_USE_16BIT       1
 127 #define SMC_CAN_USE_32BIT       0
 128 #define SMC_IO_SHIFT            0
 129 #define SMC_NOWAIT              1
 130
 131 #define SMC_inb(a, r)           readb((a) + (r))
 132 #define SMC_insb(a, r, p, l)    readsb((a) + (r), p, (l))
 133 #define SMC_inw(a, r)           readw((a) + (r))
 134 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 135 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 136 #define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, (l))
 137 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 138 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 139
 140 #define SMC_IRQ_FLAGS           (-1)
 141
 142 #elif defined(CONFIG_SA1100_ASSABET)
 143
 144 #include <mach/neponset.h>
 145
 146 /* We can only do 8-bit reads and writes in the static memory space. */
 147 #define SMC_CAN_USE_8BIT        1
 148 #define SMC_CAN_USE_16BIT       0
 149 #define SMC_CAN_USE_32BIT       0
 150 #define SMC_NOWAIT              1
 151
 152 /* The first two address lines aren't connected... */
 153 #define SMC_IO_SHIFT            2
 154
 155 #define SMC_inb(a, r)           readb((a) + (r))
 156 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 157 #define SMC_insb(a, r, p, l)    readsb((a) + (r), p, (l))
 158 #define SMC_outsb(a, r, p, l)   writesb((a) + (r), p, (l))
 159 #define SMC_IRQ_FLAGS           (-1)    /* from resource */
 160
 161 #elif   defined(CONFIG_MACH_LOGICPD_PXA270) ||  \
 162         defined(CONFIG_MACH_NOMADIK_8815NHK)
 163
 164 #define SMC_CAN_USE_8BIT        0
 165 #define SMC_CAN_USE_16BIT       1
 166 #define SMC_CAN_USE_32BIT       0
 167 #define SMC_IO_SHIFT            0
 168 #define SMC_NOWAIT              1
 169
 170 #define SMC_inw(a, r)           readw((a) + (r))
 171 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 172 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 173 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 174
 175 #elif   defined(CONFIG_ARCH_INNOKOM) || \
 176         defined(CONFIG_ARCH_PXA_IDP) || \
 177         defined(CONFIG_ARCH_RAMSES) || \
 178         defined(CONFIG_ARCH_PCM027)
 179
 180 #define SMC_CAN_USE_8BIT        1
 181 #define SMC_CAN_USE_16BIT       1
 182 #define SMC_CAN_USE_32BIT       1
 183 #define SMC_IO_SHIFT            0
 184 #define SMC_NOWAIT              1
 185 #define SMC_USE_PXA_DMA         1
 186
 187 #define SMC_inb(a, r)           readb((a) + (r))
 188 #define SMC_inw(a, r)           readw((a) + (r))
 189 #define SMC_inl(a, r)           readl((a) + (r))
 190 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 191 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
 192 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 193 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 194 #define SMC_IRQ_FLAGS           (-1)    /* from resource */
 195
 196 /* We actually can't write halfwords properly if not word aligned */
 197 static inline void
 198 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 199 {
 200         if (reg & 2) {
 201                 unsigned int v = val << 16;
 202                 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
 203                 writel(v, ioaddr + (reg & ~2));
 204         } else {
 205                 writew(val, ioaddr + reg);
 206         }
 207 }
 208
 209 #elif   defined(CONFIG_SH_SH4202_MICRODEV)
 210
 211 #define SMC_CAN_USE_8BIT        0
 212 #define SMC_CAN_USE_16BIT       1
 213 #define SMC_CAN_USE_32BIT       0
 214
 215 #define SMC_inb(a, r)           inb((a) + (r) - 0xa0000000)
 216 #define SMC_inw(a, r)           inw((a) + (r) - 0xa0000000)
 217 #define SMC_inl(a, r)           inl((a) + (r) - 0xa0000000)
 218 #define SMC_outb(v, a, r)       outb(v, (a) + (r) - 0xa0000000)
 219 #define SMC_outw(v, a, r)       outw(v, (a) + (r) - 0xa0000000)
 220 #define SMC_outl(v, a, r)       outl(v, (a) + (r) - 0xa0000000)
 221 #define SMC_insl(a, r, p, l)    insl((a) + (r) - 0xa0000000, p, l)
 222 #define SMC_outsl(a, r, p, l)   outsl((a) + (r) - 0xa0000000, p, l)
 223 #define SMC_insw(a, r, p, l)    insw((a) + (r) - 0xa0000000, p, l)
 224 #define SMC_outsw(a, r, p, l)   outsw((a) + (r) - 0xa0000000, p, l)
 225
 226 #define SMC_IRQ_FLAGS           (0)
 227
 228 #elif   defined(CONFIG_M32R)
 229
 230 #define SMC_CAN_USE_8BIT        0
 231 #define SMC_CAN_USE_16BIT       1
 232 #define SMC_CAN_USE_32BIT       0
 233
 234 #define SMC_inb(a, r)           inb(((u32)a) + (r))
 235 #define SMC_inw(a, r)           inw(((u32)a) + (r))
 236 #define SMC_outb(v, a, r)       outb(v, ((u32)a) + (r))
 237 #define SMC_outw(v, a, r)       outw(v, ((u32)a) + (r))
 238 #define SMC_insw(a, r, p, l)    insw(((u32)a) + (r), p, l)
 239 #define SMC_outsw(a, r, p, l)   outsw(((u32)a) + (r), p, l)
 240
 241 #define SMC_IRQ_FLAGS           (0)
 242
 243 #define RPC_LSA_DEFAULT         RPC_LED_TX_RX
 244 #define RPC_LSB_DEFAULT         RPC_LED_100_10
 245
 246 #elif   defined(CONFIG_MACH_LPD79520) ||        \
 247         defined(CONFIG_MACH_LPD7A400) ||        \
 248         defined(CONFIG_MACH_LPD7A404)
 249
 250 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
 251  * way that the CPU handles chip selects and the way that the SMC chip
 252  * expects the chip select to operate.  Refer to
 253  * Documentation/arm/Sharp-LH/IOBarrier for details.  The read from
 254  * IOBARRIER is a byte, in order that we read the least-common
 255  * denominator.  It would be wasteful to read 32 bits from an 8-bit
 256  * accessible region.
 257  *
 258  * There is no explicit protection against interrupts intervening
 259  * between the writew and the IOBARRIER.  In SMC ISR there is a
 260  * preamble that performs an IOBARRIER in the extremely unlikely event
 261  * that the driver interrupts itself between a writew to the chip an
 262  * the IOBARRIER that follows *and* the cache is large enough that the
 263  * first off-chip access while handing the interrupt is to the SMC
 264  * chip.  Other devices in the same address space as the SMC chip must
 265  * be aware of the potential for trouble and perform a similar
 266  * IOBARRIER on entry to their ISR.
 267  */
 268
 269 #include <mach/constants.h>     /* IOBARRIER_VIRT */
 270
 271 #define SMC_CAN_USE_8BIT        0
 272 #define SMC_CAN_USE_16BIT       1
 273 #define SMC_CAN_USE_32BIT       0
 274 #define SMC_NOWAIT              0
 275 #define LPD7X_IOBARRIER         readb (IOBARRIER_VIRT)
 276
 277 #define SMC_inw(a,r)\
 278    ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
 279 #define SMC_outw(v,a,r)   ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
 280
 281 #define SMC_insw                LPD7_SMC_insw
 282 static inline void LPD7_SMC_insw (unsigned char* a, int r,
 283                                   unsigned char* p, int l)
 284 {
 285         unsigned short* ps = (unsigned short*) p;
 286         while (l-- > 0) {
 287                 *ps++ = readw (a + r);
 288                 LPD7X_IOBARRIER;
 289         }
 290 }
 291
 292 #define SMC_outsw               LPD7_SMC_outsw
 293 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 294                                    unsigned char* p, int l)
 295 {
 296         unsigned short* ps = (unsigned short*) p;
 297         while (l-- > 0) {
 298                 writew (*ps++, a + r);
 299                 LPD7X_IOBARRIER;
 300         }
 301 }
 302
 303 #define SMC_INTERRUPT_PREAMBLE  LPD7X_IOBARRIER
 304
 305 #define RPC_LSA_DEFAULT         RPC_LED_TX_RX
 306 #define RPC_LSB_DEFAULT         RPC_LED_100_10
 307
 308 #elif   defined(CONFIG_ARCH_VERSATILE)
 309
 310 #define SMC_CAN_USE_8BIT        1
 311 #define SMC_CAN_USE_16BIT       1
 312 #define SMC_CAN_USE_32BIT       1
 313 #define SMC_NOWAIT              1
 314
 315 #define SMC_inb(a, r)           readb((a) + (r))
 316 #define SMC_inw(a, r)           readw((a) + (r))
 317 #define SMC_inl(a, r)           readl((a) + (r))
 318 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 319 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 320 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
 321 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 322 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 323 #define SMC_IRQ_FLAGS           (-1)    /* from resource */
 324
 325 #elif defined(CONFIG_MN10300)
 326
 327 /*
 328  * MN10300/AM33 configuration
 329  */
 330
 331 #include <unit/smc91111.h>
 332
 333 #else
 334
 335 /*
 336  * Default configuration
 337  */
 338
 339 #define SMC_CAN_USE_8BIT        1
 340 #define SMC_CAN_USE_16BIT       1
 341 #define SMC_CAN_USE_32BIT       1
 342 #define SMC_NOWAIT              1
 343
 344 #define SMC_IO_SHIFT            (lp->io_shift)
 345
 346 #define SMC_inb(a, r)           readb((a) + (r))
 347 #define SMC_inw(a, r)           readw((a) + (r))
 348 #define SMC_inl(a, r)           readl((a) + (r))
 349 #define SMC_outb(v, a, r)       writeb(v, (a) + (r))
 350 #define SMC_outw(v, a, r)       writew(v, (a) + (r))
 351 #define SMC_outl(v, a, r)       writel(v, (a) + (r))
 352 #define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
 353 #define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
 354 #define SMC_insl(a, r, p, l)    readsl((a) + (r), p, l)
 355 #define SMC_outsl(a, r, p, l)   writesl((a) + (r), p, l)
 356
 357 #define RPC_LSA_DEFAULT         RPC_LED_100_10
 358 #define RPC_LSB_DEFAULT         RPC_LED_TX_RX
 359
 360 #endif
 361
 362
 363 /* store this information for the driver.. */
 364 struct smc_local {
 365         /*
 366          * If I have to wait until memory is available to send a
 367          * packet, I will store the skbuff here, until I get the
 368          * desired memory.  Then, I'll send it out and free it.
 369          */
 370         struct sk_buff *pending_tx_skb;
 371         struct tasklet_struct tx_task;
 372
 373         /* version/revision of the SMC91x chip */
 374         int     version;
 375
 376         /* Contains the current active transmission mode */
 377         int     tcr_cur_mode;
 378
 379         /* Contains the current active receive mode */
 380         int     rcr_cur_mode;
 381
 382         /* Contains the current active receive/phy mode */
 383         int     rpc_cur_mode;
 384         int     ctl_rfduplx;
 385         int     ctl_rspeed;
 386
 387         u32     msg_enable;
 388         u32     phy_type;
 389         struct mii_if_info mii;
 390
 391         /* work queue */
 392         struct work_struct phy_configure;
 393         struct net_device *dev;
 394         int     work_pending;
 395
 396         spinlock_t lock;
 397
 398 #ifdef CONFIG_ARCH_PXA
 399         /* DMA needs the physical address of the chip */
 400         u_long physaddr;
 401         struct device *device;
 402 #endif
 403         void __iomem *base;
 404         void __iomem *datacs;
 405
 406         /* the low address lines on some platforms aren't connected... */
 407         int     io_shift;
 408
 409         struct smc91x_platdata cfg;
 410 };
 411
 412 #define SMC_8BIT(p)     ((p)->cfg.flags & SMC91X_USE_8BIT)
 413 #define SMC_16BIT(p)    ((p)->cfg.flags & SMC91X_USE_16BIT)
 414 #define SMC_32BIT(p)    ((p)->cfg.flags & SMC91X_USE_32BIT)
 415
 416 #ifdef CONFIG_ARCH_PXA
 417 /*
 418  * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
 419  * always happening in irq context so no need to worry about races.  TX is
 420  * different and probably not worth it for that reason, and not as critical
 421  * as RX which can overrun memory and lose packets.
 422  */
 423 #include <linux/dma-mapping.h>
 424 #include <mach/dma.h>
 425
 426 #ifdef SMC_insl
 427 #undef SMC_insl
 428 #define SMC_insl(a, r, p, l) \
 429         smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
 430 static inline void
 431 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 432                  u_char *buf, int len)
 433 {
 434         u_long physaddr = lp->physaddr;
 435         dma_addr_t dmabuf;
 436
 437         /* fallback if no DMA available */
 438         if (dma == (unsigned char)-1) {
 439                 readsl(ioaddr + reg, buf, len);
 440                 return;
 441         }
 442
 443         /* 64 bit alignment is required for memory to memory DMA */
 444         if ((long)buf & 4) {
 445                 *((u32 *)buf) = SMC_inl(ioaddr, reg);
 446                 buf += 4;
 447                 len--;
 448         }
 449
 450         len *= 4;
 451         dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 452         DCSR(dma) = DCSR_NODESC;
 453         DTADR(dma) = dmabuf;
 454         DSADR(dma) = physaddr + reg;
 455         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 456                      DCMD_WIDTH4 | (DCMD_LENGTH & len));
 457         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 458         while (!(DCSR(dma) & DCSR_STOPSTATE))
 459                 cpu_relax();
 460         DCSR(dma) = 0;
 461         dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 462 }
 463 #endif
 464
 465 #ifdef SMC_insw
 466 #undef SMC_insw
 467 #define SMC_insw(a, r, p, l) \
 468         smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
 469 static inline void
 470 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
 471                  u_char *buf, int len)
 472 {
 473         u_long physaddr = lp->physaddr;
 474         dma_addr_t dmabuf;
 475
 476         /* fallback if no DMA available */
 477         if (dma == (unsigned char)-1) {
 478                 readsw(ioaddr + reg, buf, len);
 479                 return;
 480         }
 481
 482         /* 64 bit alignment is required for memory to memory DMA */
 483         while ((long)buf & 6) {
 484                 *((u16 *)buf) = SMC_inw(ioaddr, reg);
 485                 buf += 2;
 486                 len--;
 487         }
 488
 489         len *= 2;
 490         dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
 491         DCSR(dma) = DCSR_NODESC;
 492         DTADR(dma) = dmabuf;
 493         DSADR(dma) = physaddr + reg;
 494         DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
 495                      DCMD_WIDTH2 | (DCMD_LENGTH & len));
 496         DCSR(dma) = DCSR_NODESC | DCSR_RUN;
 497         while (!(DCSR(dma) & DCSR_STOPSTATE))
 498                 cpu_relax();
 499         DCSR(dma) = 0;
 500         dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 501 }
 502 #endif
 503
 504 static void
 505 smc_pxa_dma_irq(int dma, void *dummy)
 506 {
 507         DCSR(dma) = 0;
 508 }
 509 #endif  /* CONFIG_ARCH_PXA */
 510
 511
 512 /*
 513  * Everything a particular hardware setup needs should have been defined
 514  * at this point.  Add stubs for the undefined cases, mainly to avoid
 515  * compilation warnings since they'll be optimized away, or to prevent buggy
 516  * use of them.
 517  */
 518
 519 #if ! SMC_CAN_USE_32BIT
 520 #define SMC_inl(ioaddr, reg)            ({ BUG(); 0; })
 521 #define SMC_outl(x, ioaddr, reg)        BUG()
 522 #define SMC_insl(a, r, p, l)            BUG()
 523 #define SMC_outsl(a, r, p, l)           BUG()
 524 #endif
 525
 526 #if !defined(SMC_insl) || !defined(SMC_outsl)
 527 #define SMC_insl(a, r, p, l)            BUG()
 528 #define SMC_outsl(a, r, p, l)           BUG()
 529 #endif
 530
 531 #if ! SMC_CAN_USE_16BIT
 532
 533 /*
 534  * Any 16-bit access is performed with two 8-bit accesses if the hardware
 535  * can't do it directly. Most registers are 16-bit so those are mandatory.
 536  */
 537 #define SMC_outw(x, ioaddr, reg)                                        \
 538         do {                                                            \
 539                 unsigned int __val16 = (x);                             \
 540                 SMC_outb( __val16, ioaddr, reg );                       \
 541                 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
 542         } while (0)
 543 #define SMC_inw(ioaddr, reg)                                            \
 544         ({                                                              \
 545                 unsigned int __val16;                                   \
 546                 __val16 =  SMC_inb( ioaddr, reg );                      \
 547                 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
 548                 __val16;                                                \
 549         })
 550
 551 #define SMC_insw(a, r, p, l)            BUG()
 552 #define SMC_outsw(a, r, p, l)           BUG()
 553
 554 #endif
 555
 556 #if !defined(SMC_insw) || !defined(SMC_outsw)
 557 #define SMC_insw(a, r, p, l)            BUG()
 558 #define SMC_outsw(a, r, p, l)           BUG()
 559 #endif
 560
 561 #if ! SMC_CAN_USE_8BIT
 562 #define SMC_inb(ioaddr, reg)            ({ BUG(); 0; })
 563 #define SMC_outb(x, ioaddr, reg)        BUG()
 564 #define SMC_insb(a, r, p, l)            BUG()
 565 #define SMC_outsb(a, r, p, l)           BUG()
 566 #endif
 567
 568 #if !defined(SMC_insb) || !defined(SMC_outsb)
 569 #define SMC_insb(a, r, p, l)            BUG()
 570 #define SMC_outsb(a, r, p, l)           BUG()
 571 #endif
 572
 573 #ifndef SMC_CAN_USE_DATACS
 574 #define SMC_CAN_USE_DATACS      0
 575 #endif
 576
 577 #ifndef SMC_IO_SHIFT
 578 #define SMC_IO_SHIFT    0
 579 #endif
 580
 581 #ifndef SMC_IRQ_FLAGS
 582 #define SMC_IRQ_FLAGS           IRQF_TRIGGER_RISING
 583 #endif
 584
 585 #ifndef SMC_INTERRUPT_PREAMBLE
 586 #define SMC_INTERRUPT_PREAMBLE
 587 #endif
 588
 589
 590 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
 591 #define SMC_IO_EXTENT   (16 << SMC_IO_SHIFT)
 592 #define SMC_DATA_EXTENT (4)
 593
 594 /*
 595  . Bank Select Register:
 596  .
 597  .              yyyy yyyy 0000 00xx
 598  .              xx              = bank number
 599  .              yyyy yyyy       = 0x33, for identification purposes.
 600 */
 601 #define BANK_SELECT             (14 << SMC_IO_SHIFT)
 602
 603
 604 // Transmit Control Register
 605 /* BANK 0  */
 606 #define TCR_REG(lp)     SMC_REG(lp, 0x0000, 0)
 607 #define TCR_ENABLE      0x0001  // When 1 we can transmit
 608 #define TCR_LOOP        0x0002  // Controls output pin LBK
 609 #define TCR_FORCOL      0x0004  // When 1 will force a collision
 610 #define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
 611 #define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames
 612 #define TCR_MON_CSN     0x0400  // When 1 tx monitors carrier
 613 #define TCR_FDUPLX      0x0800  // When 1 enables full duplex operation
 614 #define TCR_STP_SQET    0x1000  // When 1 stops tx if Signal Quality Error
 615 #define TCR_EPH_LOOP    0x2000  // When 1 enables EPH block loopback
 616 #define TCR_SWFDUP      0x8000  // When 1 enables Switched Full Duplex mode
 617
 618 #define TCR_CLEAR       0       /* do NOTHING */
 619 /* the default settings for the TCR register : */
 620 #define TCR_DEFAULT     (TCR_ENABLE | TCR_PAD_EN)
 621
 622
 623 // EPH Status Register
 624 /* BANK 0  */
 625 #define EPH_STATUS_REG(lp)      SMC_REG(lp, 0x0002, 0)
 626 #define ES_TX_SUC       0x0001  // Last TX was successful
 627 #define ES_SNGL_COL     0x0002  // Single collision detected for last tx
 628 #define ES_MUL_COL      0x0004  // Multiple collisions detected for last tx
 629 #define ES_LTX_MULT     0x0008  // Last tx was a multicast
 630 #define ES_16COL        0x0010  // 16 Collisions Reached
 631 #define ES_SQET         0x0020  // Signal Quality Error Test
 632 #define ES_LTXBRD       0x0040  // Last tx was a broadcast
 633 #define ES_TXDEFR       0x0080  // Transmit Deferred
 634 #define ES_LATCOL       0x0200  // Late collision detected on last tx
 635 #define ES_LOSTCARR     0x0400  // Lost Carrier Sense
 636 #define ES_EXC_DEF      0x0800  // Excessive Deferral
 637 #define ES_CTR_ROL      0x1000  // Counter Roll Over indication
 638 #define ES_LINK_OK      0x4000  // Driven by inverted value of nLNK pin
 639 #define ES_TXUNRN       0x8000  // Tx Underrun
 640
 641
 642 // Receive Control Register
 643 /* BANK 0  */
 644 #define RCR_REG(lp)             SMC_REG(lp, 0x0004, 0)
 645 #define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
 646 #define RCR_PRMS        0x0002  // Enable promiscuous mode
 647 #define RCR_ALMUL       0x0004  // When set accepts all multicast frames
 648 #define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
 649 #define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
 650 #define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
 651 #define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
 652 #define RCR_SOFTRST     0x8000  // resets the chip
 653
 654 /* the normal settings for the RCR register : */
 655 #define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
 656 #define RCR_CLEAR       0x0     // set it to a base state
 657
 658
 659 // Counter Register
 660 /* BANK 0  */
 661 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
 662
 663
 664 // Memory Information Register
 665 /* BANK 0  */
 666 #define MIR_REG(lp)             SMC_REG(lp, 0x0008, 0)
 667
 668
 669 // Receive/Phy Control Register
 670 /* BANK 0  */
 671 #define RPC_REG(lp)             SMC_REG(lp, 0x000A, 0)
 672 #define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
 673 #define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
 674 #define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
 675 #define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
 676 #define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
 677
 678 #ifndef RPC_LSA_DEFAULT
 679 #define RPC_LSA_DEFAULT RPC_LED_100
 680 #endif
 681 #ifndef RPC_LSB_DEFAULT
 682 #define RPC_LSB_DEFAULT RPC_LED_FD
 683 #endif
 684
 685 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
 686
 687
 688 /* Bank 0 0x0C is reserved */
 689
 690 // Bank Select Register
 691 /* All Banks */
 692 #define BSR_REG         0x000E
 693
 694
 695 // Configuration Reg
 696 /* BANK 1 */
 697 #define CONFIG_REG(lp)  SMC_REG(lp, 0x0000,     1)
 698 #define CONFIG_EXT_PHY  0x0200  // 1=external MII, 0=internal Phy
 699 #define CONFIG_GPCNTRL  0x0400  // Inverse value drives pin nCNTRL
 700 #define CONFIG_NO_WAIT  0x1000  // When 1 no extra wait states on ISA bus
 701 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
 702
 703 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
 704 #define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)
 705
 706
 707 // Base Address Register
 708 /* BANK 1 */
 709 #define BASE_REG(lp)    SMC_REG(lp, 0x0002, 1)
 710
 711
 712 // Individual Address Registers
 713 /* BANK 1 */
 714 #define ADDR0_REG(lp)   SMC_REG(lp, 0x0004, 1)
 715 #define ADDR1_REG(lp)   SMC_REG(lp, 0x0006, 1)
 716 #define ADDR2_REG(lp)   SMC_REG(lp, 0x0008, 1)
 717
 718
 719 // General Purpose Register
 720 /* BANK 1 */
 721 #define GP_REG(lp)              SMC_REG(lp, 0x000A, 1)
 722
 723
 724 // Control Register
 725 /* BANK 1 */
 726 #define CTL_REG(lp)             SMC_REG(lp, 0x000C, 1)
 727 #define CTL_RCV_BAD     0x4000 // When 1 bad CRC packets are received
 728 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
 729 #define CTL_LE_ENABLE   0x0080 // When 1 enables Link Error interrupt
 730 #define CTL_CR_ENABLE   0x0040 // When 1 enables Counter Rollover interrupt
 731 #define CTL_TE_ENABLE   0x0020 // When 1 enables Transmit Error interrupt
 732 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
 733 #define CTL_RELOAD      0x0002 // When set reads EEPROM into registers
 734 #define CTL_STORE       0x0001 // When set stores registers into EEPROM
 735
 736
 737 // MMU Command Register
 738 /* BANK 2 */
 739 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
 740 #define MC_BUSY         1       // When 1 the last release has not completed
 741 #define MC_NOP          (0<<5)  // No Op
 742 #define MC_ALLOC        (1<<5)  // OR with number of 256 byte packets
 743 #define MC_RESET        (2<<5)  // Reset MMU to initial state
 744 #define MC_REMOVE       (3<<5)  // Remove the current rx packet
 745 #define MC_RELEASE      (4<<5)  // Remove and release the current rx packet
 746 #define MC_FREEPKT      (5<<5)  // Release packet in PNR register
 747 #define MC_ENQUEUE      (6<<5)  // Enqueue the packet for transmit
 748 #define MC_RSTTXFIFO    (7<<5)  // Reset the TX FIFOs
 749
 750
 751 // Packet Number Register
 752 /* BANK 2 */
 753 #define PN_REG(lp)              SMC_REG(lp, 0x0002, 2)
 754
 755
 756 // Allocation Result Register
 757 /* BANK 2 */
 758 #define AR_REG(lp)              SMC_REG(lp, 0x0003, 2)
 759 #define AR_FAILED       0x80    // Alocation Failed
 760
 761
 762 // TX FIFO Ports Register
 763 /* BANK 2 */
 764 #define TXFIFO_REG(lp)  SMC_REG(lp, 0x0004, 2)
 765 #define TXFIFO_TEMPTY   0x80    // TX FIFO Empty
 766
 767 // RX FIFO Ports Register
 768 /* BANK 2 */
 769 #define RXFIFO_REG(lp)  SMC_REG(lp, 0x0005, 2)
 770 #define RXFIFO_REMPTY   0x80    // RX FIFO Empty
 771
 772 #define FIFO_REG(lp)    SMC_REG(lp, 0x0004, 2)
 773
 774 // Pointer Register
 775 /* BANK 2 */
 776 #define PTR_REG(lp)             SMC_REG(lp, 0x0006, 2)
 777 #define PTR_RCV         0x8000 // 1=Receive area, 0=Transmit area
 778 #define PTR_AUTOINC     0x4000 // Auto increment the pointer on each access
 779 #define PTR_READ        0x2000 // When 1 the operation is a read
 780
 781
 782 // Data Register
 783 /* BANK 2 */
 784 #define DATA_REG(lp)    SMC_REG(lp, 0x0008, 2)
 785
 786
 787 // Interrupt Status/Acknowledge Register
 788 /* BANK 2 */
 789 #define INT_REG(lp)             SMC_REG(lp, 0x000C, 2)
 790
 791
 792 // Interrupt Mask Register
 793 /* BANK 2 */
 794 #define IM_REG(lp)              SMC_REG(lp, 0x000D, 2)
 795 #define IM_MDINT        0x80 // PHY MI Register 18 Interrupt
 796 #define IM_ERCV_INT     0x40 // Early Receive Interrupt
 797 #define IM_EPH_INT      0x20 // Set by Ethernet Protocol Handler section
 798 #define IM_RX_OVRN_INT  0x10 // Set by Receiver Overruns
 799 #define IM_ALLOC_INT    0x08 // Set when allocation request is completed
 800 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
 801 #define IM_TX_INT       0x02 // Transmit Interrupt
 802 #define IM_RCV_INT      0x01 // Receive Interrupt
 803
 804
 805 // Multicast Table Registers
 806 /* BANK 3 */
 807 #define MCAST_REG1(lp)  SMC_REG(lp, 0x0000, 3)
 808 #define MCAST_REG2(lp)  SMC_REG(lp, 0x0002, 3)
 809 #define MCAST_REG3(lp)  SMC_REG(lp, 0x0004, 3)
 810 #define MCAST_REG4(lp)  SMC_REG(lp, 0x0006, 3)
 811
 812
 813 // Management Interface Register (MII)
 814 /* BANK 3 */
 815 #define MII_REG(lp)             SMC_REG(lp, 0x0008, 3)
 816 #define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
 817 #define MII_MDOE        0x0008 // MII Output Enable
 818 #define MII_MCLK        0x0004 // MII Clock, pin MDCLK
 819 #define MII_MDI         0x0002 // MII Input, pin MDI
 820 #define MII_MDO         0x0001 // MII Output, pin MDO
 821
 822
 823 // Revision Register
 824 /* BANK 3 */
 825 /* ( hi: chip id   low: rev # ) */
 826 #define REV_REG(lp)             SMC_REG(lp, 0x000A, 3)
 827
 828
 829 // Early RCV Register
 830 /* BANK 3 */
 831 /* this is NOT on SMC9192 */
 832 #define ERCV_REG(lp)    SMC_REG(lp, 0x000C, 3)
 833 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
 834 #define ERCV_THRESHOLD  0x001F // ERCV Threshold Mask
 835
 836
 837 // External Register
 838 /* BANK 7 */
 839 #define EXT_REG(lp)             SMC_REG(lp, 0x0000, 7)
 840
 841
 842 #define CHIP_9192       3
 843 #define CHIP_9194       4
 844 #define CHIP_9195       5
 845 #define CHIP_9196       6
 846 #define CHIP_91100      7
 847 #define CHIP_91100FD    8
 848 #define CHIP_91111FD    9
 849
 850 static const char * chip_ids[ 16 ] =  {
 851         NULL, NULL, NULL,
 852         /* 3 */ "SMC91C90/91C92",
 853         /* 4 */ "SMC91C94",
 854         /* 5 */ "SMC91C95",
 855         /* 6 */ "SMC91C96",
 856         /* 7 */ "SMC91C100",
 857         /* 8 */ "SMC91C100FD",
 858         /* 9 */ "SMC91C11xFD",
 859         NULL, NULL, NULL,
 860         NULL, NULL, NULL};
 861
 862
 863 /*
 864  . Receive status bits
 865 */
 866 #define RS_ALGNERR      0x8000
 867 #define RS_BRODCAST     0x4000
 868 #define RS_BADCRC       0x2000
 869 #define RS_ODDFRAME     0x1000
 870 #define RS_TOOLONG      0x0800
 871 #define RS_TOOSHORT     0x0400
 872 #define RS_MULTICAST    0x0001
 873 #define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 874
 875
 876 /*
 877  * PHY IDs
 878  *  LAN83C183 == LAN91C111 Internal PHY
 879  */
 880 #define PHY_LAN83C183   0x0016f840
 881 #define PHY_LAN83C180   0x02821c50
 882
 883 /*
 884  * PHY Register Addresses (LAN91C111 Internal PHY)
 885  *
 886  * Generic PHY registers can be found in <linux/mii.h>
 887  *
 888  * These phy registers are specific to our on-board phy.
 889  */
 890
 891 // PHY Configuration Register 1
 892 #define PHY_CFG1_REG            0x10
 893 #define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
 894 #define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
 895 #define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
 896 #define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
 897 #define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
 898 #define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
 899 #define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
 900 #define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
 901 #define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
 902 #define PHY_CFG1_TLVL_MASK      0x003C
 903 #define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
 904
 905
 906 // PHY Configuration Register 2
 907 #define PHY_CFG2_REG            0x11
 908 #define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
 909 #define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
 910 #define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
 911 #define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
 912
 913 // PHY Status Output (and Interrupt status) Register
 914 #define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
 915 #define PHY_INT_INT             0x8000  // 1=bits have changed since last read
 916 #define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
 917 #define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
 918 #define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
 919 #define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
 920 #define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
 921 #define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
 922 #define PHY_INT_JAB             0x0100  // 1=Jabber detected
 923 #define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
 924 #define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
 925
 926 // PHY Interrupt/Status Mask Register
 927 #define PHY_MASK_REG            0x13    // Interrupt Mask
 928 // Uses the same bit definitions as PHY_INT_REG
 929
 930
 931 /*
 932  * SMC91C96 ethernet config and status registers.
 933  * These are in the "attribute" space.
 934  */
 935 #define ECOR                    0x8000
 936 #define ECOR_RESET              0x80
 937 #define ECOR_LEVEL_IRQ          0x40
 938 #define ECOR_WR_ATTRIB          0x04
 939 #define ECOR_ENABLE             0x01
 940
 941 #define ECSR                    0x8002
 942 #define ECSR_IOIS8              0x20
 943 #define ECSR_PWRDWN             0x04
 944 #define ECSR_INT                0x02
 945
 946 #define ATTRIB_SIZE             ((64*1024) << SMC_IO_SHIFT)
 947
 948
 949 /*
 950  * Macros to abstract register access according to the data bus
 951  * capabilities.  Please use those and not the in/out primitives.
 952  * Note: the following macros do *not* select the bank -- this must
 953  * be done separately as needed in the main code.  The SMC_REG() macro
 954  * only uses the bank argument for debugging purposes (when enabled).
 955  *
 956  * Note: despite inline functions being safer, everything leading to this
 957  * should preferably be macros to let BUG() display the line number in
 958  * the core source code since we're interested in the top call site
 959  * not in any inline function location.
 960  */
 961
 962 #if SMC_DEBUG > 0
 963 #define SMC_REG(lp, reg, bank)                                  \
 964         ({                                                              \
 965                 int __b = SMC_CURRENT_BANK(lp);                 \
 966                 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {       \
 967                         printk( "%s: bank reg screwed (0x%04x)\n",      \
 968                                 CARDNAME, __b );                        \
 969                         BUG();                                          \
 970                 }                                                       \
 971                 reg<<SMC_IO_SHIFT;                                      \
 972         })
 973 #else
 974 #define SMC_REG(lp, reg, bank)  (reg<<SMC_IO_SHIFT)
 975 #endif
 976
 977 /*
 978  * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
 979  * aligned to a 32 bit boundary.  I tell you that does exist!
 980  * Fortunately the affected register accesses can be easily worked around
 981  * since we can write zeroes to the preceeding 16 bits without adverse
 982  * effects and use a 32-bit access.
 983  *
 984  * Enforce it on any 32-bit capable setup for now.
 985  */
 986 #define SMC_MUST_ALIGN_WRITE(lp)        SMC_32BIT(lp)
 987
 988 #define SMC_GET_PN(lp)                                          \
 989         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, PN_REG(lp))) \
 990                                 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
 991
 992 #define SMC_SET_PN(lp, x)                                               \
 993         do {                                                            \
 994                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
 995                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));   \
 996                 else if (SMC_8BIT(lp))                          \
 997                         SMC_outb(x, ioaddr, PN_REG(lp));                \
 998                 else                                                    \
 999                         SMC_outw(x, ioaddr, PN_REG(lp));                \
1000         } while (0)
1001
1002 #define SMC_GET_AR(lp)                                          \
1003         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, AR_REG(lp))) \
1004                                 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1005
1006 #define SMC_GET_TXFIFO(lp)                                              \
1007         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, TXFIFO_REG(lp)))     \
1008                                 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1009
1010 #define SMC_GET_RXFIFO(lp)                                              \
1011         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, RXFIFO_REG(lp)))     \
1012                                 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1013
1014 #define SMC_GET_INT(lp)                                         \
1015         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, INT_REG(lp)))        \
1016                                 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1017
1018 #define SMC_ACK_INT(lp, x)                                              \
1019         do {                                                            \
1020                 if (SMC_8BIT(lp))                                       \
1021                         SMC_outb(x, ioaddr, INT_REG(lp));               \
1022                 else {                                                  \
1023                         unsigned long __flags;                          \
1024                         int __mask;                                     \
1025                         local_irq_save(__flags);                        \
1026                         __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1027                         SMC_outw(__mask | (x), ioaddr, INT_REG(lp));    \
1028                         local_irq_restore(__flags);                     \
1029                 }                                                       \
1030         } while (0)
1031
1032 #define SMC_GET_INT_MASK(lp)                                            \
1033         (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, IM_REG(lp))) \
1034                                 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1035
1036 #define SMC_SET_INT_MASK(lp, x)                                 \
1037         do {                                                            \
1038                 if (SMC_8BIT(lp))                                       \
1039                         SMC_outb(x, ioaddr, IM_REG(lp));                \
1040                 else                                                    \
1041                         SMC_outw((x) << 8, ioaddr, INT_REG(lp));        \
1042         } while (0)
1043
1044 #define SMC_CURRENT_BANK(lp)    SMC_inw(ioaddr, BANK_SELECT)
1045
1046 #define SMC_SELECT_BANK(lp, x)                                  \
1047         do {                                                            \
1048                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
1049                         SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);    \
1050                 else                                                    \
1051                         SMC_outw(x, ioaddr, BANK_SELECT);               \
1052         } while (0)
1053
1054 #define SMC_GET_BASE(lp)                SMC_inw(ioaddr, BASE_REG(lp))
1055
1056 #define SMC_SET_BASE(lp, x)             SMC_outw(x, ioaddr, BASE_REG(lp))
1057
1058 #define SMC_GET_CONFIG(lp)      SMC_inw(ioaddr, CONFIG_REG(lp))
1059
1060 #define SMC_SET_CONFIG(lp, x)   SMC_outw(x, ioaddr, CONFIG_REG(lp))
1061
1062 #define SMC_GET_COUNTER(lp)     SMC_inw(ioaddr, COUNTER_REG(lp))
1063
1064 #define SMC_GET_CTL(lp)         SMC_inw(ioaddr, CTL_REG(lp))
1065
1066 #define SMC_SET_CTL(lp, x)              SMC_outw(x, ioaddr, CTL_REG(lp))
1067
1068 #define SMC_GET_MII(lp)         SMC_inw(ioaddr, MII_REG(lp))
1069
1070 #define SMC_GET_GP(lp)          SMC_inw(ioaddr, GP_REG(lp))
1071
1072 #define SMC_SET_GP(lp, x)                                               \
1073         do {                                                            \
1074                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
1075                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));   \
1076                 else                                                    \
1077                         SMC_outw(x, ioaddr, GP_REG(lp));                \
1078         } while (0)
1079
1080 #define SMC_SET_MII(lp, x)              SMC_outw(x, ioaddr, MII_REG(lp))
1081
1082 #define SMC_GET_MIR(lp)         SMC_inw(ioaddr, MIR_REG(lp))
1083
1084 #define SMC_SET_MIR(lp, x)              SMC_outw(x, ioaddr, MIR_REG(lp))
1085
1086 #define SMC_GET_MMU_CMD(lp)     SMC_inw(ioaddr, MMU_CMD_REG(lp))
1087
1088 #define SMC_SET_MMU_CMD(lp, x)  SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1089
1090 #define SMC_GET_FIFO(lp)                SMC_inw(ioaddr, FIFO_REG(lp))
1091
1092 #define SMC_GET_PTR(lp)         SMC_inw(ioaddr, PTR_REG(lp))
1093
1094 #define SMC_SET_PTR(lp, x)                                              \
1095         do {                                                            \
1096                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
1097                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));   \
1098                 else                                                    \
1099                         SMC_outw(x, ioaddr, PTR_REG(lp));               \
1100         } while (0)
1101
1102 #define SMC_GET_EPH_STATUS(lp)  SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1103
1104 #define SMC_GET_RCR(lp)         SMC_inw(ioaddr, RCR_REG(lp))
1105
1106 #define SMC_SET_RCR(lp, x)              SMC_outw(x, ioaddr, RCR_REG(lp))
1107
1108 #define SMC_GET_REV(lp)         SMC_inw(ioaddr, REV_REG(lp))
1109
1110 #define SMC_GET_RPC(lp)         SMC_inw(ioaddr, RPC_REG(lp))
1111
1112 #define SMC_SET_RPC(lp, x)                                              \
1113         do {                                                            \
1114                 if (SMC_MUST_ALIGN_WRITE(lp))                           \
1115                         SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));   \
1116                 else                                                    \
1117                         SMC_outw(x, ioaddr, RPC_REG(lp));               \
1118         } while (0)
1119
1120 #define SMC_GET_TCR(lp)         SMC_inw(ioaddr, TCR_REG(lp))
1121
1122 #define SMC_SET_TCR(lp, x)              SMC_outw(x, ioaddr, TCR_REG(lp))
1123
1124 #ifndef SMC_GET_MAC_ADDR
1125 #define SMC_GET_MAC_ADDR(lp, addr)                                      \
1126         do {                                                            \
1127                 unsigned int __v;                                       \
1128                 __v = SMC_inw(ioaddr, ADDR0_REG(lp));                   \
1129                 addr[0] = __v; addr[1] = __v >> 8;                      \
1130                 __v = SMC_inw(ioaddr, ADDR1_REG(lp));                   \
1131                 addr[2] = __v; addr[3] = __v >> 8;                      \
1132                 __v = SMC_inw(ioaddr, ADDR2_REG(lp));                   \
1133                 addr[4] = __v; addr[5] = __v >> 8;                      \
1134         } while (0)
1135 #endif
1136
1137 #define SMC_SET_MAC_ADDR(lp, addr)                                      \
1138         do {                                                            \
1139                 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1140                 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1141                 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1142         } while (0)
1143
1144 #define SMC_SET_MCAST(lp, x)                                            \
1145         do {                                                            \
1146                 const unsigned char *mt = (x);                          \
1147                 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1148                 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1149                 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1150                 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1151         } while (0)
1152
1153 #define SMC_PUT_PKT_HDR(lp, status, length)                             \
1154         do {                                                            \
1155                 if (SMC_32BIT(lp))                                      \
1156                         SMC_outl((status) | (length)<<16, ioaddr,       \
1157                                  DATA_REG(lp));                 \
1158                 else {                                                  \
1159                         SMC_outw(status, ioaddr, DATA_REG(lp)); \
1160                         SMC_outw(length, ioaddr, DATA_REG(lp)); \
1161                 }                                                       \
1162         } while (0)
1163
1164 #define SMC_GET_PKT_HDR(lp, status, length)                             \
1165         do {                                                            \
1166                 if (SMC_32BIT(lp)) {                            \
1167                         unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1168                         (status) = __val & 0xffff;                      \
1169                         (length) = __val >> 16;                         \
1170                 } else {                                                \
1171                         (status) = SMC_inw(ioaddr, DATA_REG(lp));       \
1172                         (length) = SMC_inw(ioaddr, DATA_REG(lp));       \
1173                 }                                                       \
1174         } while (0)
1175
1176 #define SMC_PUSH_DATA(lp, p, l)                                 \
1177         do {                                                            \
1178                 if (SMC_32BIT(lp)) {                            \
1179                         void *__ptr = (p);                              \
1180                         int __len = (l);                                \
1181                         void __iomem *__ioaddr = ioaddr;                \
1182                         if (__len >= 2 && (unsigned long)__ptr & 2) {   \
1183                                 __len -= 2;                             \
1184                                 SMC_outw(*(u16 *)__ptr, ioaddr,         \
1185                                         DATA_REG(lp));          \
1186                                 __ptr += 2;                             \
1187                         }                                               \
1188                         if (SMC_CAN_USE_DATACS && lp->datacs)           \
1189                                 __ioaddr = lp->datacs;                  \
1190                         SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1191                         if (__len & 2) {                                \
1192                                 __ptr += (__len & ~3);                  \
1193                                 SMC_outw(*((u16 *)__ptr), ioaddr,       \
1194                                          DATA_REG(lp));         \
1195                         }                                               \
1196                 } else if (SMC_16BIT(lp))                               \
1197                         SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);   \
1198                 else if (SMC_8BIT(lp))                          \
1199                         SMC_outsb(ioaddr, DATA_REG(lp), p, l);  \
1200         } while (0)
1201
1202 #define SMC_PULL_DATA(lp, p, l)                                 \
1203         do {                                                            \
1204                 if (SMC_32BIT(lp)) {                            \
1205                         void *__ptr = (p);                              \
1206                         int __len = (l);                                \
1207                         void __iomem *__ioaddr = ioaddr;                \
1208                         if ((unsigned long)__ptr & 2) {                 \
1209                                 /*                                      \
1210                                  * We want 32bit alignment here.        \
1211                                  * Since some buses perform a full      \
1212                                  * 32bit fetch even for 16bit data      \
1213                                  * we can't use SMC_inw() here.         \
1214                                  * Back both source (on-chip) and       \
1215                                  * destination pointers of 2 bytes.     \
1216                                  * This is possible since the call to   \
1217                                  * SMC_GET_PKT_HDR() already advanced   \
1218                                  * the source pointer of 4 bytes, and   \
1219                                  * the skb_reserve(skb, 2) advanced     \
1220                                  * the destination pointer of 2 bytes.  \
1221                                  */                                     \
1222                                 __ptr -= 2;                             \
1223                                 __len += 2;                             \
1224                                 SMC_SET_PTR(lp,                 \
1225                                         2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1226                         }                                               \
1227                         if (SMC_CAN_USE_DATACS && lp->datacs)           \
1228                                 __ioaddr = lp->datacs;                  \
1229                         __len += 2;                                     \
1230                         SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1231                 } else if (SMC_16BIT(lp))                               \
1232                         SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);    \
1233                 else if (SMC_8BIT(lp))                          \
1234                         SMC_insb(ioaddr, DATA_REG(lp), p, l);           \
1235         } while (0)
1236
1237 #endif  /* _SMC91X_H_ */