2 * Copyright (C) 2006, 2007 Eugene Konev
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/phy_fixed.h>
37 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/clk.h>
41 #include <asm/atomic.h>
43 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
44 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:cpmac");
48 static int debug_level
= 8;
49 static int dumb_switch
;
51 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
52 module_param(debug_level
, int, 0444);
53 module_param(dumb_switch
, int, 0444);
55 MODULE_PARM_DESC(debug_level
, "Number of NETIF_MSG bits to enable");
56 MODULE_PARM_DESC(dumb_switch
, "Assume switch is not connected to MDIO bus");
58 #define CPMAC_VERSION "0.5.1"
59 /* frame size + 802.1q tag */
60 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
61 #define CPMAC_QUEUES 8
63 /* Ethernet registers */
64 #define CPMAC_TX_CONTROL 0x0004
65 #define CPMAC_TX_TEARDOWN 0x0008
66 #define CPMAC_RX_CONTROL 0x0014
67 #define CPMAC_RX_TEARDOWN 0x0018
68 #define CPMAC_MBP 0x0100
69 # define MBP_RXPASSCRC 0x40000000
70 # define MBP_RXQOS 0x20000000
71 # define MBP_RXNOCHAIN 0x10000000
72 # define MBP_RXCMF 0x01000000
73 # define MBP_RXSHORT 0x00800000
74 # define MBP_RXCEF 0x00400000
75 # define MBP_RXPROMISC 0x00200000
76 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
77 # define MBP_RXBCAST 0x00002000
78 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
79 # define MBP_RXMCAST 0x00000020
80 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
81 #define CPMAC_UNICAST_ENABLE 0x0104
82 #define CPMAC_UNICAST_CLEAR 0x0108
83 #define CPMAC_MAX_LENGTH 0x010c
84 #define CPMAC_BUFFER_OFFSET 0x0110
85 #define CPMAC_MAC_CONTROL 0x0160
86 # define MAC_TXPTYPE 0x00000200
87 # define MAC_TXPACE 0x00000040
88 # define MAC_MII 0x00000020
89 # define MAC_TXFLOW 0x00000010
90 # define MAC_RXFLOW 0x00000008
91 # define MAC_MTEST 0x00000004
92 # define MAC_LOOPBACK 0x00000002
93 # define MAC_FDX 0x00000001
94 #define CPMAC_MAC_STATUS 0x0164
95 # define MAC_STATUS_QOS 0x00000004
96 # define MAC_STATUS_RXFLOW 0x00000002
97 # define MAC_STATUS_TXFLOW 0x00000001
98 #define CPMAC_TX_INT_ENABLE 0x0178
99 #define CPMAC_TX_INT_CLEAR 0x017c
100 #define CPMAC_MAC_INT_VECTOR 0x0180
101 # define MAC_INT_STATUS 0x00080000
102 # define MAC_INT_HOST 0x00040000
103 # define MAC_INT_RX 0x00020000
104 # define MAC_INT_TX 0x00010000
105 #define CPMAC_MAC_EOI_VECTOR 0x0184
106 #define CPMAC_RX_INT_ENABLE 0x0198
107 #define CPMAC_RX_INT_CLEAR 0x019c
108 #define CPMAC_MAC_INT_ENABLE 0x01a8
109 #define CPMAC_MAC_INT_CLEAR 0x01ac
110 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
111 #define CPMAC_MAC_ADDR_MID 0x01d0
112 #define CPMAC_MAC_ADDR_HI 0x01d4
113 #define CPMAC_MAC_HASH_LO 0x01d8
114 #define CPMAC_MAC_HASH_HI 0x01dc
115 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
116 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
117 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
118 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
119 #define CPMAC_REG_END 0x0680
122 * TODO: use some of them to fill stats in cpmac_stats()
124 #define CPMAC_STATS_RX_GOOD 0x0200
125 #define CPMAC_STATS_RX_BCAST 0x0204
126 #define CPMAC_STATS_RX_MCAST 0x0208
127 #define CPMAC_STATS_RX_PAUSE 0x020c
128 #define CPMAC_STATS_RX_CRC 0x0210
129 #define CPMAC_STATS_RX_ALIGN 0x0214
130 #define CPMAC_STATS_RX_OVER 0x0218
131 #define CPMAC_STATS_RX_JABBER 0x021c
132 #define CPMAC_STATS_RX_UNDER 0x0220
133 #define CPMAC_STATS_RX_FRAG 0x0224
134 #define CPMAC_STATS_RX_FILTER 0x0228
135 #define CPMAC_STATS_RX_QOSFILTER 0x022c
136 #define CPMAC_STATS_RX_OCTETS 0x0230
138 #define CPMAC_STATS_TX_GOOD 0x0234
139 #define CPMAC_STATS_TX_BCAST 0x0238
140 #define CPMAC_STATS_TX_MCAST 0x023c
141 #define CPMAC_STATS_TX_PAUSE 0x0240
142 #define CPMAC_STATS_TX_DEFER 0x0244
143 #define CPMAC_STATS_TX_COLLISION 0x0248
144 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
145 #define CPMAC_STATS_TX_MULTICOLL 0x0250
146 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
147 #define CPMAC_STATS_TX_LATECOLL 0x0258
148 #define CPMAC_STATS_TX_UNDERRUN 0x025c
149 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
150 #define CPMAC_STATS_TX_OCTETS 0x0264
152 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
153 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
157 #define CPMAC_MDIO_VERSION 0x0000
158 #define CPMAC_MDIO_CONTROL 0x0004
159 # define MDIOC_IDLE 0x80000000
160 # define MDIOC_ENABLE 0x40000000
161 # define MDIOC_PREAMBLE 0x00100000
162 # define MDIOC_FAULT 0x00080000
163 # define MDIOC_FAULTDETECT 0x00040000
164 # define MDIOC_INTTEST 0x00020000
165 # define MDIOC_CLKDIV(div) ((div) & 0xff)
166 #define CPMAC_MDIO_ALIVE 0x0008
167 #define CPMAC_MDIO_LINK 0x000c
168 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
169 # define MDIO_BUSY 0x80000000
170 # define MDIO_WRITE 0x40000000
171 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
172 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
173 # define MDIO_DATA(data) ((data) & 0xffff)
174 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
175 # define PHYSEL_LINKSEL 0x00000040
176 # define PHYSEL_LINKINT 0x00000020
185 #define CPMAC_SOP 0x8000
186 #define CPMAC_EOP 0x4000
187 #define CPMAC_OWN 0x2000
188 #define CPMAC_EOQ 0x1000
190 struct cpmac_desc
*next
;
191 struct cpmac_desc
*prev
;
193 dma_addr_t data_mapping
;
199 struct cpmac_desc
*rx_head
;
201 struct cpmac_desc
*desc_ring
;
204 struct mii_bus
*mii_bus
;
205 struct phy_device
*phy
;
206 char phy_name
[MII_BUS_ID_SIZE
+ 3];
207 int oldlink
, oldspeed
, oldduplex
;
209 struct net_device
*dev
;
210 struct work_struct reset_work
;
211 struct platform_device
*pdev
;
212 struct napi_struct napi
;
213 atomic_t reset_pending
;
216 static irqreturn_t
cpmac_irq(int, void *);
217 static void cpmac_hw_start(struct net_device
*dev
);
218 static void cpmac_hw_stop(struct net_device
*dev
);
219 static int cpmac_stop(struct net_device
*dev
);
220 static int cpmac_open(struct net_device
*dev
);
222 static void cpmac_dump_regs(struct net_device
*dev
)
225 struct cpmac_priv
*priv
= netdev_priv(dev
);
226 for (i
= 0; i
< CPMAC_REG_END
; i
+= 4) {
230 printk(KERN_DEBUG
"%s: reg[%p]:", dev
->name
,
233 printk(" %08x", cpmac_read(priv
->regs
, i
));
238 static void cpmac_dump_desc(struct net_device
*dev
, struct cpmac_desc
*desc
)
241 printk(KERN_DEBUG
"%s: desc[%p]:", dev
->name
, desc
);
242 for (i
= 0; i
< sizeof(*desc
) / 4; i
++)
243 printk(" %08x", ((u32
*)desc
)[i
]);
247 static void cpmac_dump_all_desc(struct net_device
*dev
)
249 struct cpmac_priv
*priv
= netdev_priv(dev
);
250 struct cpmac_desc
*dump
= priv
->rx_head
;
252 cpmac_dump_desc(dev
, dump
);
254 } while (dump
!= priv
->rx_head
);
257 static void cpmac_dump_skb(struct net_device
*dev
, struct sk_buff
*skb
)
260 printk(KERN_DEBUG
"%s: skb 0x%p, len=%d\n", dev
->name
, skb
, skb
->len
);
261 for (i
= 0; i
< skb
->len
; i
++) {
265 printk(KERN_DEBUG
"%s: data[%p]:", dev
->name
,
268 printk(" %02x", ((u8
*)skb
->data
)[i
]);
273 static int cpmac_mdio_read(struct mii_bus
*bus
, int phy_id
, int reg
)
277 while (cpmac_read(bus
->priv
, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY
)
279 cpmac_write(bus
->priv
, CPMAC_MDIO_ACCESS(0), MDIO_BUSY
| MDIO_REG(reg
) |
281 while ((val
= cpmac_read(bus
->priv
, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY
)
283 return MDIO_DATA(val
);
286 static int cpmac_mdio_write(struct mii_bus
*bus
, int phy_id
,
289 while (cpmac_read(bus
->priv
, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY
)
291 cpmac_write(bus
->priv
, CPMAC_MDIO_ACCESS(0), MDIO_BUSY
| MDIO_WRITE
|
292 MDIO_REG(reg
) | MDIO_PHY(phy_id
) | MDIO_DATA(val
));
296 static int cpmac_mdio_reset(struct mii_bus
*bus
)
298 struct clk
*cpmac_clk
;
300 cpmac_clk
= clk_get(&bus
->dev
, "cpmac");
301 if (IS_ERR(cpmac_clk
)) {
302 printk(KERN_ERR
"unable to get cpmac clock\n");
305 ar7_device_reset(AR7_RESET_BIT_MDIO
);
306 cpmac_write(bus
->priv
, CPMAC_MDIO_CONTROL
, MDIOC_ENABLE
|
307 MDIOC_CLKDIV(clk_get_rate(cpmac_clk
) / 2200000 - 1));
311 static int mii_irqs
[PHY_MAX_ADDR
] = { PHY_POLL
, };
313 static struct mii_bus
*cpmac_mii
;
315 static int cpmac_config(struct net_device
*dev
, struct ifmap
*map
)
317 if (dev
->flags
& IFF_UP
)
320 /* Don't allow changing the I/O address */
321 if (map
->base_addr
!= dev
->base_addr
)
324 /* ignore other fields */
328 static void cpmac_set_multicast_list(struct net_device
*dev
)
330 struct dev_mc_list
*iter
;
332 u32 mbp
, bit
, hash
[2] = { 0, };
333 struct cpmac_priv
*priv
= netdev_priv(dev
);
335 mbp
= cpmac_read(priv
->regs
, CPMAC_MBP
);
336 if (dev
->flags
& IFF_PROMISC
) {
337 cpmac_write(priv
->regs
, CPMAC_MBP
, (mbp
& ~MBP_PROMISCCHAN(0)) |
340 cpmac_write(priv
->regs
, CPMAC_MBP
, mbp
& ~MBP_RXPROMISC
);
341 if (dev
->flags
& IFF_ALLMULTI
) {
342 /* enable all multicast mode */
343 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_LO
, 0xffffffff);
344 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_HI
, 0xffffffff);
347 * cpmac uses some strange mac address hashing
350 netdev_for_each_mc_addr(iter
, dev
) {
352 tmp
= iter
->dmi_addr
[0];
353 bit
^= (tmp
>> 2) ^ (tmp
<< 4);
354 tmp
= iter
->dmi_addr
[1];
355 bit
^= (tmp
>> 4) ^ (tmp
<< 2);
356 tmp
= iter
->dmi_addr
[2];
357 bit
^= (tmp
>> 6) ^ tmp
;
358 tmp
= iter
->dmi_addr
[3];
359 bit
^= (tmp
>> 2) ^ (tmp
<< 4);
360 tmp
= iter
->dmi_addr
[4];
361 bit
^= (tmp
>> 4) ^ (tmp
<< 2);
362 tmp
= iter
->dmi_addr
[5];
363 bit
^= (tmp
>> 6) ^ tmp
;
365 hash
[bit
/ 32] |= 1 << (bit
% 32);
368 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_LO
, hash
[0]);
369 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_HI
, hash
[1]);
374 static struct sk_buff
*cpmac_rx_one(struct cpmac_priv
*priv
,
375 struct cpmac_desc
*desc
)
377 struct sk_buff
*skb
, *result
= NULL
;
379 if (unlikely(netif_msg_hw(priv
)))
380 cpmac_dump_desc(priv
->dev
, desc
);
381 cpmac_write(priv
->regs
, CPMAC_RX_ACK(0), (u32
)desc
->mapping
);
382 if (unlikely(!desc
->datalen
)) {
383 if (netif_msg_rx_err(priv
) && net_ratelimit())
384 printk(KERN_WARNING
"%s: rx: spurious interrupt\n",
389 skb
= netdev_alloc_skb_ip_align(priv
->dev
, CPMAC_SKB_SIZE
);
391 skb_put(desc
->skb
, desc
->datalen
);
392 desc
->skb
->protocol
= eth_type_trans(desc
->skb
, priv
->dev
);
393 desc
->skb
->ip_summed
= CHECKSUM_NONE
;
394 priv
->dev
->stats
.rx_packets
++;
395 priv
->dev
->stats
.rx_bytes
+= desc
->datalen
;
397 dma_unmap_single(&priv
->dev
->dev
, desc
->data_mapping
,
398 CPMAC_SKB_SIZE
, DMA_FROM_DEVICE
);
400 desc
->data_mapping
= dma_map_single(&priv
->dev
->dev
, skb
->data
,
403 desc
->hw_data
= (u32
)desc
->data_mapping
;
404 if (unlikely(netif_msg_pktdata(priv
))) {
405 printk(KERN_DEBUG
"%s: received packet:\n",
407 cpmac_dump_skb(priv
->dev
, result
);
410 if (netif_msg_rx_err(priv
) && net_ratelimit())
412 "%s: low on skbs, dropping packet\n",
414 priv
->dev
->stats
.rx_dropped
++;
417 desc
->buflen
= CPMAC_SKB_SIZE
;
418 desc
->dataflags
= CPMAC_OWN
;
423 static int cpmac_poll(struct napi_struct
*napi
, int budget
)
426 struct cpmac_desc
*desc
, *restart
;
427 struct cpmac_priv
*priv
= container_of(napi
, struct cpmac_priv
, napi
);
428 int received
= 0, processed
= 0;
430 spin_lock(&priv
->rx_lock
);
431 if (unlikely(!priv
->rx_head
)) {
432 if (netif_msg_rx_err(priv
) && net_ratelimit())
433 printk(KERN_WARNING
"%s: rx: polling, but no queue\n",
435 spin_unlock(&priv
->rx_lock
);
440 desc
= priv
->rx_head
;
442 while (((desc
->dataflags
& CPMAC_OWN
) == 0) && (received
< budget
)) {
445 if ((desc
->dataflags
& CPMAC_EOQ
) != 0) {
446 /* The last update to eoq->hw_next didn't happen
447 * soon enough, and the receiver stopped here.
448 *Remember this descriptor so we can restart
449 * the receiver after freeing some space.
451 if (unlikely(restart
)) {
452 if (netif_msg_rx_err(priv
))
453 printk(KERN_ERR
"%s: poll found a"
454 " duplicate EOQ: %p and %p\n",
455 priv
->dev
->name
, restart
, desc
);
459 restart
= desc
->next
;
462 skb
= cpmac_rx_one(priv
, desc
);
464 netif_receive_skb(skb
);
470 if (desc
!= priv
->rx_head
) {
471 /* We freed some buffers, but not the whole ring,
472 * add what we did free to the rx list */
473 desc
->prev
->hw_next
= (u32
)0;
474 priv
->rx_head
->prev
->hw_next
= priv
->rx_head
->mapping
;
477 /* Optimization: If we did not actually process an EOQ (perhaps because
478 * of quota limits), check to see if the tail of the queue has EOQ set.
479 * We should immediately restart in that case so that the receiver can
480 * restart and run in parallel with more packet processing.
481 * This lets us handle slightly larger bursts before running
482 * out of ring space (assuming dev->weight < ring_size) */
485 (priv
->rx_head
->prev
->dataflags
& (CPMAC_OWN
|CPMAC_EOQ
))
487 (priv
->rx_head
->dataflags
& CPMAC_OWN
) != 0) {
488 /* reset EOQ so the poll loop (above) doesn't try to
489 * restart this when it eventually gets to this descriptor.
491 priv
->rx_head
->prev
->dataflags
&= ~CPMAC_EOQ
;
492 restart
= priv
->rx_head
;
496 priv
->dev
->stats
.rx_errors
++;
497 priv
->dev
->stats
.rx_fifo_errors
++;
498 if (netif_msg_rx_err(priv
) && net_ratelimit())
499 printk(KERN_WARNING
"%s: rx dma ring overrun\n",
502 if (unlikely((restart
->dataflags
& CPMAC_OWN
) == 0)) {
503 if (netif_msg_drv(priv
))
504 printk(KERN_ERR
"%s: cpmac_poll is trying to "
505 "restart rx from a descriptor that's "
507 priv
->dev
->name
, restart
);
511 cpmac_write(priv
->regs
, CPMAC_RX_PTR(0), restart
->mapping
);
514 priv
->rx_head
= desc
;
515 spin_unlock(&priv
->rx_lock
);
516 if (unlikely(netif_msg_rx_status(priv
)))
517 printk(KERN_DEBUG
"%s: poll processed %d packets\n",
518 priv
->dev
->name
, received
);
519 if (processed
== 0) {
520 /* we ran out of packets to read,
521 * revert to interrupt-driven mode */
523 cpmac_write(priv
->regs
, CPMAC_RX_INT_ENABLE
, 1);
530 /* Something went horribly wrong.
531 * Reset hardware to try to recover rather than wedging. */
533 if (netif_msg_drv(priv
)) {
534 printk(KERN_ERR
"%s: cpmac_poll is confused. "
535 "Resetting hardware\n", priv
->dev
->name
);
536 cpmac_dump_all_desc(priv
->dev
);
537 printk(KERN_DEBUG
"%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
539 cpmac_read(priv
->regs
, CPMAC_RX_PTR(0)),
540 cpmac_read(priv
->regs
, CPMAC_RX_ACK(0)));
543 spin_unlock(&priv
->rx_lock
);
545 netif_tx_stop_all_queues(priv
->dev
);
546 napi_disable(&priv
->napi
);
548 atomic_inc(&priv
->reset_pending
);
549 cpmac_hw_stop(priv
->dev
);
550 if (!schedule_work(&priv
->reset_work
))
551 atomic_dec(&priv
->reset_pending
);
556 static int cpmac_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
559 struct cpmac_desc
*desc
;
560 struct cpmac_priv
*priv
= netdev_priv(dev
);
562 if (unlikely(atomic_read(&priv
->reset_pending
)))
563 return NETDEV_TX_BUSY
;
565 if (unlikely(skb_padto(skb
, ETH_ZLEN
)))
568 len
= max(skb
->len
, ETH_ZLEN
);
569 queue
= skb_get_queue_mapping(skb
);
570 netif_stop_subqueue(dev
, queue
);
572 desc
= &priv
->desc_ring
[queue
];
573 if (unlikely(desc
->dataflags
& CPMAC_OWN
)) {
574 if (netif_msg_tx_err(priv
) && net_ratelimit())
575 printk(KERN_WARNING
"%s: tx dma ring full\n",
577 return NETDEV_TX_BUSY
;
580 spin_lock(&priv
->lock
);
581 dev
->trans_start
= jiffies
;
582 spin_unlock(&priv
->lock
);
583 desc
->dataflags
= CPMAC_SOP
| CPMAC_EOP
| CPMAC_OWN
;
585 desc
->data_mapping
= dma_map_single(&dev
->dev
, skb
->data
, len
,
587 desc
->hw_data
= (u32
)desc
->data_mapping
;
590 if (unlikely(netif_msg_tx_queued(priv
)))
591 printk(KERN_DEBUG
"%s: sending 0x%p, len=%d\n", dev
->name
, skb
,
593 if (unlikely(netif_msg_hw(priv
)))
594 cpmac_dump_desc(dev
, desc
);
595 if (unlikely(netif_msg_pktdata(priv
)))
596 cpmac_dump_skb(dev
, skb
);
597 cpmac_write(priv
->regs
, CPMAC_TX_PTR(queue
), (u32
)desc
->mapping
);
602 static void cpmac_end_xmit(struct net_device
*dev
, int queue
)
604 struct cpmac_desc
*desc
;
605 struct cpmac_priv
*priv
= netdev_priv(dev
);
607 desc
= &priv
->desc_ring
[queue
];
608 cpmac_write(priv
->regs
, CPMAC_TX_ACK(queue
), (u32
)desc
->mapping
);
609 if (likely(desc
->skb
)) {
610 spin_lock(&priv
->lock
);
611 dev
->stats
.tx_packets
++;
612 dev
->stats
.tx_bytes
+= desc
->skb
->len
;
613 spin_unlock(&priv
->lock
);
614 dma_unmap_single(&dev
->dev
, desc
->data_mapping
, desc
->skb
->len
,
617 if (unlikely(netif_msg_tx_done(priv
)))
618 printk(KERN_DEBUG
"%s: sent 0x%p, len=%d\n", dev
->name
,
619 desc
->skb
, desc
->skb
->len
);
621 dev_kfree_skb_irq(desc
->skb
);
623 if (__netif_subqueue_stopped(dev
, queue
))
624 netif_wake_subqueue(dev
, queue
);
626 if (netif_msg_tx_err(priv
) && net_ratelimit())
628 "%s: end_xmit: spurious interrupt\n", dev
->name
);
629 if (__netif_subqueue_stopped(dev
, queue
))
630 netif_wake_subqueue(dev
, queue
);
634 static void cpmac_hw_stop(struct net_device
*dev
)
637 struct cpmac_priv
*priv
= netdev_priv(dev
);
638 struct plat_cpmac_data
*pdata
= priv
->pdev
->dev
.platform_data
;
640 ar7_device_reset(pdata
->reset_bit
);
641 cpmac_write(priv
->regs
, CPMAC_RX_CONTROL
,
642 cpmac_read(priv
->regs
, CPMAC_RX_CONTROL
) & ~1);
643 cpmac_write(priv
->regs
, CPMAC_TX_CONTROL
,
644 cpmac_read(priv
->regs
, CPMAC_TX_CONTROL
) & ~1);
645 for (i
= 0; i
< 8; i
++) {
646 cpmac_write(priv
->regs
, CPMAC_TX_PTR(i
), 0);
647 cpmac_write(priv
->regs
, CPMAC_RX_PTR(i
), 0);
649 cpmac_write(priv
->regs
, CPMAC_UNICAST_CLEAR
, 0xff);
650 cpmac_write(priv
->regs
, CPMAC_RX_INT_CLEAR
, 0xff);
651 cpmac_write(priv
->regs
, CPMAC_TX_INT_CLEAR
, 0xff);
652 cpmac_write(priv
->regs
, CPMAC_MAC_INT_CLEAR
, 0xff);
653 cpmac_write(priv
->regs
, CPMAC_MAC_CONTROL
,
654 cpmac_read(priv
->regs
, CPMAC_MAC_CONTROL
) & ~MAC_MII
);
657 static void cpmac_hw_start(struct net_device
*dev
)
660 struct cpmac_priv
*priv
= netdev_priv(dev
);
661 struct plat_cpmac_data
*pdata
= priv
->pdev
->dev
.platform_data
;
663 ar7_device_reset(pdata
->reset_bit
);
664 for (i
= 0; i
< 8; i
++) {
665 cpmac_write(priv
->regs
, CPMAC_TX_PTR(i
), 0);
666 cpmac_write(priv
->regs
, CPMAC_RX_PTR(i
), 0);
668 cpmac_write(priv
->regs
, CPMAC_RX_PTR(0), priv
->rx_head
->mapping
);
670 cpmac_write(priv
->regs
, CPMAC_MBP
, MBP_RXSHORT
| MBP_RXBCAST
|
672 cpmac_write(priv
->regs
, CPMAC_BUFFER_OFFSET
, 0);
673 for (i
= 0; i
< 8; i
++)
674 cpmac_write(priv
->regs
, CPMAC_MAC_ADDR_LO(i
), dev
->dev_addr
[5]);
675 cpmac_write(priv
->regs
, CPMAC_MAC_ADDR_MID
, dev
->dev_addr
[4]);
676 cpmac_write(priv
->regs
, CPMAC_MAC_ADDR_HI
, dev
->dev_addr
[0] |
677 (dev
->dev_addr
[1] << 8) | (dev
->dev_addr
[2] << 16) |
678 (dev
->dev_addr
[3] << 24));
679 cpmac_write(priv
->regs
, CPMAC_MAX_LENGTH
, CPMAC_SKB_SIZE
);
680 cpmac_write(priv
->regs
, CPMAC_UNICAST_CLEAR
, 0xff);
681 cpmac_write(priv
->regs
, CPMAC_RX_INT_CLEAR
, 0xff);
682 cpmac_write(priv
->regs
, CPMAC_TX_INT_CLEAR
, 0xff);
683 cpmac_write(priv
->regs
, CPMAC_MAC_INT_CLEAR
, 0xff);
684 cpmac_write(priv
->regs
, CPMAC_UNICAST_ENABLE
, 1);
685 cpmac_write(priv
->regs
, CPMAC_RX_INT_ENABLE
, 1);
686 cpmac_write(priv
->regs
, CPMAC_TX_INT_ENABLE
, 0xff);
687 cpmac_write(priv
->regs
, CPMAC_MAC_INT_ENABLE
, 3);
689 cpmac_write(priv
->regs
, CPMAC_RX_CONTROL
,
690 cpmac_read(priv
->regs
, CPMAC_RX_CONTROL
) | 1);
691 cpmac_write(priv
->regs
, CPMAC_TX_CONTROL
,
692 cpmac_read(priv
->regs
, CPMAC_TX_CONTROL
) | 1);
693 cpmac_write(priv
->regs
, CPMAC_MAC_CONTROL
,
694 cpmac_read(priv
->regs
, CPMAC_MAC_CONTROL
) | MAC_MII
|
698 static void cpmac_clear_rx(struct net_device
*dev
)
700 struct cpmac_priv
*priv
= netdev_priv(dev
);
701 struct cpmac_desc
*desc
;
703 if (unlikely(!priv
->rx_head
))
705 desc
= priv
->rx_head
;
706 for (i
= 0; i
< priv
->ring_size
; i
++) {
707 if ((desc
->dataflags
& CPMAC_OWN
) == 0) {
708 if (netif_msg_rx_err(priv
) && net_ratelimit())
709 printk(KERN_WARNING
"%s: packet dropped\n",
711 if (unlikely(netif_msg_hw(priv
)))
712 cpmac_dump_desc(dev
, desc
);
713 desc
->dataflags
= CPMAC_OWN
;
714 dev
->stats
.rx_dropped
++;
716 desc
->hw_next
= desc
->next
->mapping
;
719 priv
->rx_head
->prev
->hw_next
= 0;
722 static void cpmac_clear_tx(struct net_device
*dev
)
724 struct cpmac_priv
*priv
= netdev_priv(dev
);
726 if (unlikely(!priv
->desc_ring
))
728 for (i
= 0; i
< CPMAC_QUEUES
; i
++) {
729 priv
->desc_ring
[i
].dataflags
= 0;
730 if (priv
->desc_ring
[i
].skb
) {
731 dev_kfree_skb_any(priv
->desc_ring
[i
].skb
);
732 priv
->desc_ring
[i
].skb
= NULL
;
737 static void cpmac_hw_error(struct work_struct
*work
)
739 struct cpmac_priv
*priv
=
740 container_of(work
, struct cpmac_priv
, reset_work
);
742 spin_lock(&priv
->rx_lock
);
743 cpmac_clear_rx(priv
->dev
);
744 spin_unlock(&priv
->rx_lock
);
745 cpmac_clear_tx(priv
->dev
);
746 cpmac_hw_start(priv
->dev
);
748 atomic_dec(&priv
->reset_pending
);
750 netif_tx_wake_all_queues(priv
->dev
);
751 cpmac_write(priv
->regs
, CPMAC_MAC_INT_ENABLE
, 3);
754 static void cpmac_check_status(struct net_device
*dev
)
756 struct cpmac_priv
*priv
= netdev_priv(dev
);
758 u32 macstatus
= cpmac_read(priv
->regs
, CPMAC_MAC_STATUS
);
759 int rx_channel
= (macstatus
>> 8) & 7;
760 int rx_code
= (macstatus
>> 12) & 15;
761 int tx_channel
= (macstatus
>> 16) & 7;
762 int tx_code
= (macstatus
>> 20) & 15;
764 if (rx_code
|| tx_code
) {
765 if (netif_msg_drv(priv
) && net_ratelimit()) {
766 /* Can't find any documentation on what these
767 *error codes actually are. So just log them and hope..
770 printk(KERN_WARNING
"%s: host error %d on rx "
771 "channel %d (macstatus %08x), resetting\n",
772 dev
->name
, rx_code
, rx_channel
, macstatus
);
774 printk(KERN_WARNING
"%s: host error %d on tx "
775 "channel %d (macstatus %08x), resetting\n",
776 dev
->name
, tx_code
, tx_channel
, macstatus
);
779 netif_tx_stop_all_queues(dev
);
781 if (schedule_work(&priv
->reset_work
))
782 atomic_inc(&priv
->reset_pending
);
783 if (unlikely(netif_msg_hw(priv
)))
784 cpmac_dump_regs(dev
);
786 cpmac_write(priv
->regs
, CPMAC_MAC_INT_CLEAR
, 0xff);
789 static irqreturn_t
cpmac_irq(int irq
, void *dev_id
)
791 struct net_device
*dev
= dev_id
;
792 struct cpmac_priv
*priv
;
796 priv
= netdev_priv(dev
);
798 status
= cpmac_read(priv
->regs
, CPMAC_MAC_INT_VECTOR
);
800 if (unlikely(netif_msg_intr(priv
)))
801 printk(KERN_DEBUG
"%s: interrupt status: 0x%08x\n", dev
->name
,
804 if (status
& MAC_INT_TX
)
805 cpmac_end_xmit(dev
, (status
& 7));
807 if (status
& MAC_INT_RX
) {
808 queue
= (status
>> 8) & 7;
809 if (napi_schedule_prep(&priv
->napi
)) {
810 cpmac_write(priv
->regs
, CPMAC_RX_INT_CLEAR
, 1 << queue
);
811 __napi_schedule(&priv
->napi
);
815 cpmac_write(priv
->regs
, CPMAC_MAC_EOI_VECTOR
, 0);
817 if (unlikely(status
& (MAC_INT_HOST
| MAC_INT_STATUS
)))
818 cpmac_check_status(dev
);
823 static void cpmac_tx_timeout(struct net_device
*dev
)
825 struct cpmac_priv
*priv
= netdev_priv(dev
);
827 spin_lock(&priv
->lock
);
828 dev
->stats
.tx_errors
++;
829 spin_unlock(&priv
->lock
);
830 if (netif_msg_tx_err(priv
) && net_ratelimit())
831 printk(KERN_WARNING
"%s: transmit timeout\n", dev
->name
);
833 atomic_inc(&priv
->reset_pending
);
837 atomic_dec(&priv
->reset_pending
);
839 netif_tx_wake_all_queues(priv
->dev
);
842 static int cpmac_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
844 struct cpmac_priv
*priv
= netdev_priv(dev
);
845 if (!(netif_running(dev
)))
849 if ((cmd
== SIOCGMIIPHY
) || (cmd
== SIOCGMIIREG
) ||
850 (cmd
== SIOCSMIIREG
))
851 return phy_mii_ioctl(priv
->phy
, if_mii(ifr
), cmd
);
856 static int cpmac_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
858 struct cpmac_priv
*priv
= netdev_priv(dev
);
861 return phy_ethtool_gset(priv
->phy
, cmd
);
866 static int cpmac_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
868 struct cpmac_priv
*priv
= netdev_priv(dev
);
870 if (!capable(CAP_NET_ADMIN
))
874 return phy_ethtool_sset(priv
->phy
, cmd
);
879 static void cpmac_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
881 struct cpmac_priv
*priv
= netdev_priv(dev
);
883 ring
->rx_max_pending
= 1024;
884 ring
->rx_mini_max_pending
= 1;
885 ring
->rx_jumbo_max_pending
= 1;
886 ring
->tx_max_pending
= 1;
888 ring
->rx_pending
= priv
->ring_size
;
889 ring
->rx_mini_pending
= 1;
890 ring
->rx_jumbo_pending
= 1;
891 ring
->tx_pending
= 1;
894 static int cpmac_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
896 struct cpmac_priv
*priv
= netdev_priv(dev
);
898 if (netif_running(dev
))
900 priv
->ring_size
= ring
->rx_pending
;
904 static void cpmac_get_drvinfo(struct net_device
*dev
,
905 struct ethtool_drvinfo
*info
)
907 strcpy(info
->driver
, "cpmac");
908 strcpy(info
->version
, CPMAC_VERSION
);
909 info
->fw_version
[0] = '\0';
910 sprintf(info
->bus_info
, "%s", "cpmac");
911 info
->regdump_len
= 0;
914 static const struct ethtool_ops cpmac_ethtool_ops
= {
915 .get_settings
= cpmac_get_settings
,
916 .set_settings
= cpmac_set_settings
,
917 .get_drvinfo
= cpmac_get_drvinfo
,
918 .get_link
= ethtool_op_get_link
,
919 .get_ringparam
= cpmac_get_ringparam
,
920 .set_ringparam
= cpmac_set_ringparam
,
923 static void cpmac_adjust_link(struct net_device
*dev
)
925 struct cpmac_priv
*priv
= netdev_priv(dev
);
928 spin_lock(&priv
->lock
);
929 if (priv
->phy
->link
) {
930 netif_tx_start_all_queues(dev
);
931 if (priv
->phy
->duplex
!= priv
->oldduplex
) {
933 priv
->oldduplex
= priv
->phy
->duplex
;
936 if (priv
->phy
->speed
!= priv
->oldspeed
) {
938 priv
->oldspeed
= priv
->phy
->speed
;
941 if (!priv
->oldlink
) {
945 } else if (priv
->oldlink
) {
949 priv
->oldduplex
= -1;
952 if (new_state
&& netif_msg_link(priv
) && net_ratelimit())
953 phy_print_status(priv
->phy
);
955 spin_unlock(&priv
->lock
);
958 static int cpmac_open(struct net_device
*dev
)
961 struct cpmac_priv
*priv
= netdev_priv(dev
);
962 struct resource
*mem
;
963 struct cpmac_desc
*desc
;
966 mem
= platform_get_resource_byname(priv
->pdev
, IORESOURCE_MEM
, "regs");
967 if (!request_mem_region(mem
->start
, mem
->end
- mem
->start
, dev
->name
)) {
968 if (netif_msg_drv(priv
))
969 printk(KERN_ERR
"%s: failed to request registers\n",
975 priv
->regs
= ioremap(mem
->start
, mem
->end
- mem
->start
);
977 if (netif_msg_drv(priv
))
978 printk(KERN_ERR
"%s: failed to remap registers\n",
984 size
= priv
->ring_size
+ CPMAC_QUEUES
;
985 priv
->desc_ring
= dma_alloc_coherent(&dev
->dev
,
986 sizeof(struct cpmac_desc
) * size
,
989 if (!priv
->desc_ring
) {
994 for (i
= 0; i
< size
; i
++)
995 priv
->desc_ring
[i
].mapping
= priv
->dma_ring
+ sizeof(*desc
) * i
;
997 priv
->rx_head
= &priv
->desc_ring
[CPMAC_QUEUES
];
998 for (i
= 0, desc
= priv
->rx_head
; i
< priv
->ring_size
; i
++, desc
++) {
999 skb
= netdev_alloc_skb_ip_align(dev
, CPMAC_SKB_SIZE
);
1000 if (unlikely(!skb
)) {
1005 desc
->data_mapping
= dma_map_single(&dev
->dev
, skb
->data
,
1008 desc
->hw_data
= (u32
)desc
->data_mapping
;
1009 desc
->buflen
= CPMAC_SKB_SIZE
;
1010 desc
->dataflags
= CPMAC_OWN
;
1011 desc
->next
= &priv
->rx_head
[(i
+ 1) % priv
->ring_size
];
1012 desc
->next
->prev
= desc
;
1013 desc
->hw_next
= (u32
)desc
->next
->mapping
;
1016 priv
->rx_head
->prev
->hw_next
= (u32
)0;
1018 if ((res
= request_irq(dev
->irq
, cpmac_irq
, IRQF_SHARED
,
1020 if (netif_msg_drv(priv
))
1021 printk(KERN_ERR
"%s: failed to obtain irq\n",
1026 atomic_set(&priv
->reset_pending
, 0);
1027 INIT_WORK(&priv
->reset_work
, cpmac_hw_error
);
1028 cpmac_hw_start(dev
);
1030 napi_enable(&priv
->napi
);
1031 priv
->phy
->state
= PHY_CHANGELINK
;
1032 phy_start(priv
->phy
);
1038 for (i
= 0; i
< priv
->ring_size
; i
++) {
1039 if (priv
->rx_head
[i
].skb
) {
1040 dma_unmap_single(&dev
->dev
,
1041 priv
->rx_head
[i
].data_mapping
,
1044 kfree_skb(priv
->rx_head
[i
].skb
);
1048 kfree(priv
->desc_ring
);
1049 iounmap(priv
->regs
);
1052 release_mem_region(mem
->start
, mem
->end
- mem
->start
);
1058 static int cpmac_stop(struct net_device
*dev
)
1061 struct cpmac_priv
*priv
= netdev_priv(dev
);
1062 struct resource
*mem
;
1064 netif_tx_stop_all_queues(dev
);
1066 cancel_work_sync(&priv
->reset_work
);
1067 napi_disable(&priv
->napi
);
1068 phy_stop(priv
->phy
);
1072 for (i
= 0; i
< 8; i
++)
1073 cpmac_write(priv
->regs
, CPMAC_TX_PTR(i
), 0);
1074 cpmac_write(priv
->regs
, CPMAC_RX_PTR(0), 0);
1075 cpmac_write(priv
->regs
, CPMAC_MBP
, 0);
1077 free_irq(dev
->irq
, dev
);
1078 iounmap(priv
->regs
);
1079 mem
= platform_get_resource_byname(priv
->pdev
, IORESOURCE_MEM
, "regs");
1080 release_mem_region(mem
->start
, mem
->end
- mem
->start
);
1081 priv
->rx_head
= &priv
->desc_ring
[CPMAC_QUEUES
];
1082 for (i
= 0; i
< priv
->ring_size
; i
++) {
1083 if (priv
->rx_head
[i
].skb
) {
1084 dma_unmap_single(&dev
->dev
,
1085 priv
->rx_head
[i
].data_mapping
,
1088 kfree_skb(priv
->rx_head
[i
].skb
);
1092 dma_free_coherent(&dev
->dev
, sizeof(struct cpmac_desc
) *
1093 (CPMAC_QUEUES
+ priv
->ring_size
),
1094 priv
->desc_ring
, priv
->dma_ring
);
1098 static const struct net_device_ops cpmac_netdev_ops
= {
1099 .ndo_open
= cpmac_open
,
1100 .ndo_stop
= cpmac_stop
,
1101 .ndo_start_xmit
= cpmac_start_xmit
,
1102 .ndo_tx_timeout
= cpmac_tx_timeout
,
1103 .ndo_set_multicast_list
= cpmac_set_multicast_list
,
1104 .ndo_do_ioctl
= cpmac_ioctl
,
1105 .ndo_set_config
= cpmac_config
,
1106 .ndo_change_mtu
= eth_change_mtu
,
1107 .ndo_validate_addr
= eth_validate_addr
,
1108 .ndo_set_mac_address
= eth_mac_addr
,
1111 static int external_switch
;
1113 static int __devinit
cpmac_probe(struct platform_device
*pdev
)
1116 char mdio_bus_id
[MII_BUS_ID_SIZE
];
1117 struct resource
*mem
;
1118 struct cpmac_priv
*priv
;
1119 struct net_device
*dev
;
1120 struct plat_cpmac_data
*pdata
;
1122 pdata
= pdev
->dev
.platform_data
;
1124 if (external_switch
|| dumb_switch
) {
1125 strncpy(mdio_bus_id
, "0", MII_BUS_ID_SIZE
); /* fixed phys bus */
1128 for (phy_id
= 0; phy_id
< PHY_MAX_ADDR
; phy_id
++) {
1129 if (!(pdata
->phy_mask
& (1 << phy_id
)))
1131 if (!cpmac_mii
->phy_map
[phy_id
])
1133 strncpy(mdio_bus_id
, cpmac_mii
->id
, MII_BUS_ID_SIZE
);
1138 if (phy_id
== PHY_MAX_ADDR
) {
1139 dev_err(&pdev
->dev
, "no PHY present\n");
1143 dev
= alloc_etherdev_mq(sizeof(*priv
), CPMAC_QUEUES
);
1146 printk(KERN_ERR
"cpmac: Unable to allocate net_device\n");
1150 platform_set_drvdata(pdev
, dev
);
1151 priv
= netdev_priv(dev
);
1154 mem
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "regs");
1160 dev
->irq
= platform_get_irq_byname(pdev
, "irq");
1162 dev
->netdev_ops
= &cpmac_netdev_ops
;
1163 dev
->ethtool_ops
= &cpmac_ethtool_ops
;
1165 netif_napi_add(dev
, &priv
->napi
, cpmac_poll
, 64);
1167 spin_lock_init(&priv
->lock
);
1168 spin_lock_init(&priv
->rx_lock
);
1170 priv
->ring_size
= 64;
1171 priv
->msg_enable
= netif_msg_init(debug_level
, 0xff);
1172 memcpy(dev
->dev_addr
, pdata
->dev_addr
, sizeof(pdata
->dev_addr
));
1174 snprintf(priv
->phy_name
, MII_BUS_ID_SIZE
, PHY_ID_FMT
, mdio_bus_id
, phy_id
);
1176 priv
->phy
= phy_connect(dev
, priv
->phy_name
, &cpmac_adjust_link
, 0,
1177 PHY_INTERFACE_MODE_MII
);
1179 if (IS_ERR(priv
->phy
)) {
1180 if (netif_msg_drv(priv
))
1181 printk(KERN_ERR
"%s: Could not attach to PHY\n",
1183 return PTR_ERR(priv
->phy
);
1186 if ((rc
= register_netdev(dev
))) {
1187 printk(KERN_ERR
"cpmac: error %i registering device %s\n", rc
,
1192 if (netif_msg_probe(priv
)) {
1194 "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1195 "mac: %pM)\n", dev
->name
, (void *)mem
->start
, dev
->irq
,
1196 priv
->phy_name
, dev
->dev_addr
);
1205 static int __devexit
cpmac_remove(struct platform_device
*pdev
)
1207 struct net_device
*dev
= platform_get_drvdata(pdev
);
1208 unregister_netdev(dev
);
1213 static struct platform_driver cpmac_driver
= {
1214 .driver
.name
= "cpmac",
1215 .driver
.owner
= THIS_MODULE
,
1216 .probe
= cpmac_probe
,
1217 .remove
= __devexit_p(cpmac_remove
),
1220 int __devinit
cpmac_init(void)
1225 cpmac_mii
= mdiobus_alloc();
1226 if (cpmac_mii
== NULL
)
1229 cpmac_mii
->name
= "cpmac-mii";
1230 cpmac_mii
->read
= cpmac_mdio_read
;
1231 cpmac_mii
->write
= cpmac_mdio_write
;
1232 cpmac_mii
->reset
= cpmac_mdio_reset
;
1233 cpmac_mii
->irq
= mii_irqs
;
1235 cpmac_mii
->priv
= ioremap(AR7_REGS_MDIO
, 256);
1237 if (!cpmac_mii
->priv
) {
1238 printk(KERN_ERR
"Can't ioremap mdio registers\n");
1243 #warning FIXME: unhardcode gpio&reset bits
1244 ar7_gpio_disable(26);
1245 ar7_gpio_disable(27);
1246 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO
);
1247 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI
);
1248 ar7_device_reset(AR7_RESET_BIT_EPHY
);
1250 cpmac_mii
->reset(cpmac_mii
);
1252 for (i
= 0; i
< 300; i
++)
1253 if ((mask
= cpmac_read(cpmac_mii
->priv
, CPMAC_MDIO_ALIVE
)))
1259 if (mask
& (mask
- 1)) {
1260 external_switch
= 1;
1264 cpmac_mii
->phy_mask
= ~(mask
| 0x80000000);
1265 snprintf(cpmac_mii
->id
, MII_BUS_ID_SIZE
, "1");
1267 res
= mdiobus_register(cpmac_mii
);
1271 res
= platform_driver_register(&cpmac_driver
);
1278 mdiobus_unregister(cpmac_mii
);
1281 iounmap(cpmac_mii
->priv
);
1284 mdiobus_free(cpmac_mii
);
1289 void __devexit
cpmac_exit(void)
1291 platform_driver_unregister(&cpmac_driver
);
1292 mdiobus_unregister(cpmac_mii
);
1293 mdiobus_free(cpmac_mii
);
1294 iounmap(cpmac_mii
->priv
);
1297 module_init(cpmac_init
);
1298 module_exit(cpmac_exit
);