2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
34 * definitions for the ACPI scanning code
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed
));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed
));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed
));
118 static int __initdata amd_iommu_detected
;
120 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
122 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
124 unsigned amd_iommu_aperture_order
= 26; /* size of aperture in power of 2 */
125 bool amd_iommu_isolate
= true; /* if true, device isolation is
127 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
129 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
133 * Pointer to the device table which is shared by all AMD IOMMUs
134 * it is indexed by the PCI device id or the HT unit id and contains
135 * information about the domain the device belongs to as well as the
136 * page table root pointer.
138 struct dev_table_entry
*amd_iommu_dev_table
;
141 * The alias table is a driver specific data structure which contains the
142 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
143 * More than one device can share the same requestor id.
145 u16
*amd_iommu_alias_table
;
148 * The rlookup table is used to find the IOMMU which is responsible
149 * for a specific device. It is also indexed by the PCI device id.
151 struct amd_iommu
**amd_iommu_rlookup_table
;
154 * The pd table (protection domain table) is used to find the protection domain
155 * data structure a device belongs to. Indexed with the PCI device id too.
157 struct protection_domain
**amd_iommu_pd_table
;
160 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
161 * to know which ones are already in use.
163 unsigned long *amd_iommu_pd_alloc_bitmap
;
165 static u32 dev_table_size
; /* size of the device table */
166 static u32 alias_table_size
; /* size of the alias table */
167 static u32 rlookup_table_size
; /* size if the rlookup table */
169 static inline void update_last_devid(u16 devid
)
171 if (devid
> amd_iommu_last_bdf
)
172 amd_iommu_last_bdf
= devid
;
175 static inline unsigned long tbl_size(int entry_size
)
177 unsigned shift
= PAGE_SHIFT
+
178 get_order(amd_iommu_last_bdf
* entry_size
);
183 /****************************************************************************
185 * AMD IOMMU MMIO register space handling functions
187 * These functions are used to program the IOMMU device registers in
188 * MMIO space required for that driver.
190 ****************************************************************************/
193 * This function set the exclusion range in the IOMMU. DMA accesses to the
194 * exclusion range are passed through untranslated
196 static void __init
iommu_set_exclusion_range(struct amd_iommu
*iommu
)
198 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
199 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
202 if (!iommu
->exclusion_start
)
205 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
206 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
207 &entry
, sizeof(entry
));
210 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
211 &entry
, sizeof(entry
));
214 /* Programs the physical address of the device table into the IOMMU hardware */
215 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
219 BUG_ON(iommu
->mmio_base
== NULL
);
221 entry
= virt_to_phys(amd_iommu_dev_table
);
222 entry
|= (dev_table_size
>> 12) - 1;
223 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
224 &entry
, sizeof(entry
));
227 /* Generic functions to enable/disable certain features of the IOMMU. */
228 static void __init
iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
232 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
234 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
237 static void __init
iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
241 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
243 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
246 /* Function to enable the hardware */
247 static void __init
iommu_enable(struct amd_iommu
*iommu
)
249 printk(KERN_INFO
"AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
250 dev_name(&iommu
->dev
->dev
), iommu
->cap_ptr
);
252 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
256 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
257 * the system has one.
259 static u8
* __init
iommu_map_mmio_space(u64 address
)
263 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
266 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
270 release_mem_region(address
, MMIO_REGION_LENGTH
);
275 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
277 if (iommu
->mmio_base
)
278 iounmap(iommu
->mmio_base
);
279 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
282 /****************************************************************************
284 * The functions below belong to the first pass of AMD IOMMU ACPI table
285 * parsing. In this pass we try to find out the highest device id this
286 * code has to handle. Upon this information the size of the shared data
287 * structures is determined later.
289 ****************************************************************************/
292 * This function calculates the length of a given IVHD entry
294 static inline int ivhd_entry_length(u8
*ivhd
)
296 return 0x04 << (*ivhd
>> 6);
300 * This function reads the last device id the IOMMU has to handle from the PCI
301 * capability header for this IOMMU
303 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
307 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
308 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
314 * After reading the highest device id from the IOMMU PCI capability header
315 * this function looks if there is a higher device id defined in the ACPI table
317 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
319 u8
*p
= (void *)h
, *end
= (void *)h
;
320 struct ivhd_entry
*dev
;
325 find_last_devid_on_pci(PCI_BUS(h
->devid
),
331 dev
= (struct ivhd_entry
*)p
;
333 case IVHD_DEV_SELECT
:
334 case IVHD_DEV_RANGE_END
:
336 case IVHD_DEV_EXT_SELECT
:
337 /* all the above subfield types refer to device ids */
338 update_last_devid(dev
->devid
);
343 p
+= ivhd_entry_length(p
);
352 * Iterate over all IVHD entries in the ACPI table and find the highest device
353 * id which we need to handle. This is the first of three functions which parse
354 * the ACPI table. So we check the checksum here.
356 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
359 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
360 struct ivhd_header
*h
;
363 * Validate checksum here so we don't need to do it when
364 * we actually parse the table
366 for (i
= 0; i
< table
->length
; ++i
)
369 /* ACPI table corrupt */
372 p
+= IVRS_HEADER_LENGTH
;
374 end
+= table
->length
;
376 h
= (struct ivhd_header
*)p
;
379 find_last_devid_from_ivhd(h
);
391 /****************************************************************************
393 * The following functions belong the the code path which parses the ACPI table
394 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
395 * data structures, initialize the device/alias/rlookup table and also
396 * basically initialize the hardware.
398 ****************************************************************************/
401 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
402 * write commands to that buffer later and the IOMMU will execute them
405 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
407 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
408 get_order(CMD_BUFFER_SIZE
));
413 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
419 * This function writes the command buffer address to the hardware and
422 static void iommu_enable_command_buffer(struct amd_iommu
*iommu
)
426 BUG_ON(iommu
->cmd_buf
== NULL
);
428 entry
= (u64
)virt_to_phys(iommu
->cmd_buf
);
429 entry
|= MMIO_CMD_SIZE_512
;
431 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
432 &entry
, sizeof(entry
));
434 /* set head and tail to zero manually */
435 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
436 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
438 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
441 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
443 free_pages((unsigned long)iommu
->cmd_buf
,
444 get_order(iommu
->cmd_buf_size
));
447 /* allocates the memory where the IOMMU will log its events to */
448 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
450 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
451 get_order(EVT_BUFFER_SIZE
));
453 if (iommu
->evt_buf
== NULL
)
456 return iommu
->evt_buf
;
459 static void iommu_enable_event_buffer(struct amd_iommu
*iommu
)
463 BUG_ON(iommu
->evt_buf
== NULL
);
465 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
467 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
468 &entry
, sizeof(entry
));
470 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
473 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
475 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
478 /* sets a specific bit in the device table entry. */
479 static void set_dev_entry_bit(u16 devid
, u8 bit
)
481 int i
= (bit
>> 5) & 0x07;
482 int _bit
= bit
& 0x1f;
484 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
487 /* Writes the specific IOMMU for a device into the rlookup table */
488 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
490 amd_iommu_rlookup_table
[devid
] = iommu
;
494 * This function takes the device specific flags read from the ACPI
495 * table and sets up the device table entry with that information
497 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
498 u16 devid
, u32 flags
, u32 ext_flags
)
500 if (flags
& ACPI_DEVFLAG_INITPASS
)
501 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
502 if (flags
& ACPI_DEVFLAG_EXTINT
)
503 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
504 if (flags
& ACPI_DEVFLAG_NMI
)
505 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
506 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
507 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
508 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
509 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
510 if (flags
& ACPI_DEVFLAG_LINT0
)
511 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
512 if (flags
& ACPI_DEVFLAG_LINT1
)
513 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
515 set_iommu_for_device(iommu
, devid
);
519 * Reads the device exclusion range from ACPI and initialize IOMMU with
522 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
524 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
526 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
531 * We only can configure exclusion ranges per IOMMU, not
532 * per device. But we can enable the exclusion range per
533 * device. This is done here
535 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
536 iommu
->exclusion_start
= m
->range_start
;
537 iommu
->exclusion_length
= m
->range_length
;
542 * This function reads some important data from the IOMMU PCI space and
543 * initializes the driver data structure with it. It reads the hardware
544 * capabilities and the first/last device entries
546 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
548 int cap_ptr
= iommu
->cap_ptr
;
551 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
553 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
555 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
558 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
560 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
562 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
566 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
567 * initializes the hardware and our data structures with it.
569 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
570 struct ivhd_header
*h
)
573 u8
*end
= p
, flags
= 0;
574 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
577 struct ivhd_entry
*e
;
580 * First set the recommended feature enable bits from ACPI
581 * into the IOMMU control registers
583 h
->flags
& IVHD_FLAG_HT_TUN_EN_MASK
?
584 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
585 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
587 h
->flags
& IVHD_FLAG_PASSPW_EN_MASK
?
588 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
589 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
591 h
->flags
& IVHD_FLAG_RESPASSPW_EN_MASK
?
592 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
593 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
595 h
->flags
& IVHD_FLAG_ISOC_EN_MASK
?
596 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
597 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
600 * make IOMMU memory accesses cache coherent
602 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
605 * Done. Now parse the device entries
607 p
+= sizeof(struct ivhd_header
);
611 e
= (struct ivhd_entry
*)p
;
614 for (dev_i
= iommu
->first_device
;
615 dev_i
<= iommu
->last_device
; ++dev_i
)
616 set_dev_entry_from_acpi(iommu
, dev_i
,
619 case IVHD_DEV_SELECT
:
621 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
623 case IVHD_DEV_SELECT_RANGE_START
:
624 devid_start
= e
->devid
;
631 devid_to
= e
->ext
>> 8;
632 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
633 amd_iommu_alias_table
[devid
] = devid_to
;
635 case IVHD_DEV_ALIAS_RANGE
:
636 devid_start
= e
->devid
;
638 devid_to
= e
->ext
>> 8;
642 case IVHD_DEV_EXT_SELECT
:
644 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
647 case IVHD_DEV_EXT_SELECT_RANGE
:
648 devid_start
= e
->devid
;
653 case IVHD_DEV_RANGE_END
:
655 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
657 amd_iommu_alias_table
[dev_i
] = devid_to
;
658 set_dev_entry_from_acpi(iommu
,
659 amd_iommu_alias_table
[dev_i
],
667 p
+= ivhd_entry_length(p
);
671 /* Initializes the device->iommu mapping for the driver */
672 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
676 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
677 set_iommu_for_device(iommu
, i
);
682 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
684 free_command_buffer(iommu
);
685 free_event_buffer(iommu
);
686 iommu_unmap_mmio_space(iommu
);
689 static void __init
free_iommu_all(void)
691 struct amd_iommu
*iommu
, *next
;
693 for_each_iommu_safe(iommu
, next
) {
694 list_del(&iommu
->list
);
695 free_iommu_one(iommu
);
701 * This function clues the initialization function for one IOMMU
702 * together and also allocates the command buffer and programs the
703 * hardware. It does NOT enable the IOMMU. This is done afterwards.
705 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
707 spin_lock_init(&iommu
->lock
);
708 list_add_tail(&iommu
->list
, &amd_iommu_list
);
711 * Copy data from ACPI table entry to the iommu struct
713 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
717 iommu
->cap_ptr
= h
->cap_ptr
;
718 iommu
->pci_seg
= h
->pci_seg
;
719 iommu
->mmio_phys
= h
->mmio_phys
;
720 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
721 if (!iommu
->mmio_base
)
724 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
728 iommu
->evt_buf
= alloc_event_buffer(iommu
);
732 iommu
->int_enabled
= false;
734 init_iommu_from_pci(iommu
);
735 init_iommu_from_acpi(iommu
, h
);
736 init_iommu_devices(iommu
);
738 return pci_enable_device(iommu
->dev
);
742 * Iterates over all IOMMU entries in the ACPI table, allocates the
743 * IOMMU structure and initializes it with init_iommu_one()
745 static int __init
init_iommu_all(struct acpi_table_header
*table
)
747 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
748 struct ivhd_header
*h
;
749 struct amd_iommu
*iommu
;
752 end
+= table
->length
;
753 p
+= IVRS_HEADER_LENGTH
;
756 h
= (struct ivhd_header
*)p
;
759 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
762 ret
= init_iommu_one(iommu
, h
);
777 /****************************************************************************
779 * The following functions initialize the MSI interrupts for all IOMMUs
780 * in the system. Its a bit challenging because there could be multiple
781 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
784 ****************************************************************************/
786 static int __init
iommu_setup_msix(struct amd_iommu
*iommu
)
788 struct amd_iommu
*curr
;
789 struct msix_entry entries
[32]; /* only 32 supported by AMD IOMMU */
792 for_each_iommu(curr
) {
793 if (curr
->dev
== iommu
->dev
) {
794 entries
[nvec
].entry
= curr
->evt_msi_num
;
795 entries
[nvec
].vector
= 0;
796 curr
->int_enabled
= true;
801 if (pci_enable_msix(iommu
->dev
, entries
, nvec
)) {
802 pci_disable_msix(iommu
->dev
);
806 for (i
= 0; i
< nvec
; ++i
) {
807 int r
= request_irq(entries
->vector
, amd_iommu_int_handler
,
818 for (i
-= 1; i
>= 0; --i
)
819 free_irq(entries
->vector
, NULL
);
821 pci_disable_msix(iommu
->dev
);
826 static int __init
iommu_setup_msi(struct amd_iommu
*iommu
)
830 if (pci_enable_msi(iommu
->dev
))
833 r
= request_irq(iommu
->dev
->irq
, amd_iommu_int_handler
,
839 pci_disable_msi(iommu
->dev
);
843 iommu
->int_enabled
= true;
844 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
849 static int __init
iommu_init_msi(struct amd_iommu
*iommu
)
851 if (iommu
->int_enabled
)
854 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSIX
))
855 return iommu_setup_msix(iommu
);
856 else if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
857 return iommu_setup_msi(iommu
);
862 /****************************************************************************
864 * The next functions belong to the third pass of parsing the ACPI
865 * table. In this last pass the memory mapping requirements are
866 * gathered (like exclusion and unity mapping reanges).
868 ****************************************************************************/
870 static void __init
free_unity_maps(void)
872 struct unity_map_entry
*entry
, *next
;
874 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
875 list_del(&entry
->list
);
880 /* called when we find an exclusion range definition in ACPI */
881 static int __init
init_exclusion_range(struct ivmd_header
*m
)
887 set_device_exclusion_range(m
->devid
, m
);
889 case ACPI_IVMD_TYPE_ALL
:
890 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
891 set_device_exclusion_range(i
, m
);
893 case ACPI_IVMD_TYPE_RANGE
:
894 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
895 set_device_exclusion_range(i
, m
);
904 /* called for unity map ACPI definition */
905 static int __init
init_unity_map_range(struct ivmd_header
*m
)
907 struct unity_map_entry
*e
= 0;
909 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
916 e
->devid_start
= e
->devid_end
= m
->devid
;
918 case ACPI_IVMD_TYPE_ALL
:
920 e
->devid_end
= amd_iommu_last_bdf
;
922 case ACPI_IVMD_TYPE_RANGE
:
923 e
->devid_start
= m
->devid
;
924 e
->devid_end
= m
->aux
;
927 e
->address_start
= PAGE_ALIGN(m
->range_start
);
928 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
929 e
->prot
= m
->flags
>> 1;
931 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
936 /* iterates over all memory definitions we find in the ACPI table */
937 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
939 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
940 struct ivmd_header
*m
;
942 end
+= table
->length
;
943 p
+= IVRS_HEADER_LENGTH
;
946 m
= (struct ivmd_header
*)p
;
947 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
948 init_exclusion_range(m
);
949 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
950 init_unity_map_range(m
);
959 * Init the device table to not allow DMA access for devices and
960 * suppress all page faults
962 static void init_device_table(void)
966 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
967 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
968 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
973 * This function finally enables all IOMMUs found in the system after
974 * they have been initialized
976 static void __init
enable_iommus(void)
978 struct amd_iommu
*iommu
;
980 for_each_iommu(iommu
) {
981 iommu_set_device_table(iommu
);
982 iommu_enable_command_buffer(iommu
);
983 iommu_enable_event_buffer(iommu
);
984 iommu_set_exclusion_range(iommu
);
985 iommu_init_msi(iommu
);
991 * Suspend/Resume support
992 * disable suspend until real resume implemented
995 static int amd_iommu_resume(struct sys_device
*dev
)
1000 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
1005 static struct sysdev_class amd_iommu_sysdev_class
= {
1006 .name
= "amd_iommu",
1007 .suspend
= amd_iommu_suspend
,
1008 .resume
= amd_iommu_resume
,
1011 static struct sys_device device_amd_iommu
= {
1013 .cls
= &amd_iommu_sysdev_class
,
1017 * This is the core init function for AMD IOMMU hardware in the system.
1018 * This function is called from the generic x86 DMA layer initialization
1021 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1024 * 1 pass) Find the highest PCI device id the driver has to handle.
1025 * Upon this information the size of the data structures is
1026 * determined that needs to be allocated.
1028 * 2 pass) Initialize the data structures just allocated with the
1029 * information in the ACPI table about available AMD IOMMUs
1030 * in the system. It also maps the PCI devices in the
1031 * system to specific IOMMUs
1033 * 3 pass) After the basic data structures are allocated and
1034 * initialized we update them with information about memory
1035 * remapping requirements parsed out of the ACPI table in
1038 * After that the hardware is initialized and ready to go. In the last
1039 * step we do some Linux specific things like registering the driver in
1040 * the dma_ops interface and initializing the suspend/resume support
1041 * functions. Finally it prints some information about AMD IOMMUs and
1042 * the driver state and enables the hardware.
1044 int __init
amd_iommu_init(void)
1050 printk(KERN_INFO
"AMD IOMMU disabled by kernel command line\n");
1054 if (!amd_iommu_detected
)
1058 * First parse ACPI tables to find the largest Bus/Dev/Func
1059 * we need to handle. Upon this information the shared data
1060 * structures for the IOMMUs in the system will be allocated
1062 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1065 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1066 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1067 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1071 /* Device table - directly used by all IOMMUs */
1072 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1073 get_order(dev_table_size
));
1074 if (amd_iommu_dev_table
== NULL
)
1078 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1079 * IOMMU see for that device
1081 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1082 get_order(alias_table_size
));
1083 if (amd_iommu_alias_table
== NULL
)
1086 /* IOMMU rlookup table - find the IOMMU for a specific device */
1087 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1088 GFP_KERNEL
| __GFP_ZERO
,
1089 get_order(rlookup_table_size
));
1090 if (amd_iommu_rlookup_table
== NULL
)
1094 * Protection Domain table - maps devices to protection domains
1095 * This table has the same size as the rlookup_table
1097 amd_iommu_pd_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1098 get_order(rlookup_table_size
));
1099 if (amd_iommu_pd_table
== NULL
)
1102 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1103 GFP_KERNEL
| __GFP_ZERO
,
1104 get_order(MAX_DOMAIN_ID
/8));
1105 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1108 /* init the device table */
1109 init_device_table();
1112 * let all alias entries point to itself
1114 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1115 amd_iommu_alias_table
[i
] = i
;
1118 * never allocate domain 0 because its used as the non-allocated and
1119 * error value placeholder
1121 amd_iommu_pd_alloc_bitmap
[0] = 1;
1124 * now the data structures are allocated and basically initialized
1125 * start the real acpi table scan
1128 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1131 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1134 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
1138 ret
= sysdev_register(&device_amd_iommu
);
1142 ret
= amd_iommu_init_dma_ops();
1148 printk(KERN_INFO
"AMD IOMMU: aperture size is %d MB\n",
1149 (1 << (amd_iommu_aperture_order
-20)));
1151 printk(KERN_INFO
"AMD IOMMU: device isolation ");
1152 if (amd_iommu_isolate
)
1153 printk("enabled\n");
1155 printk("disabled\n");
1157 if (amd_iommu_unmap_flush
)
1158 printk(KERN_INFO
"AMD IOMMU: IO/TLB flush on unmap enabled\n");
1160 printk(KERN_INFO
"AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1166 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1167 get_order(MAX_DOMAIN_ID
/8));
1169 free_pages((unsigned long)amd_iommu_pd_table
,
1170 get_order(rlookup_table_size
));
1172 free_pages((unsigned long)amd_iommu_rlookup_table
,
1173 get_order(rlookup_table_size
));
1175 free_pages((unsigned long)amd_iommu_alias_table
,
1176 get_order(alias_table_size
));
1178 free_pages((unsigned long)amd_iommu_dev_table
,
1179 get_order(dev_table_size
));
1188 /****************************************************************************
1190 * Early detect code. This code runs at IOMMU detection time in the DMA
1191 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1194 ****************************************************************************/
1195 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1200 void __init
amd_iommu_detect(void)
1202 if (swiotlb
|| no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1205 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1207 amd_iommu_detected
= 1;
1208 #ifdef CONFIG_GART_IOMMU
1209 gart_iommu_aperture_disabled
= 1;
1210 gart_iommu_aperture
= 0;
1215 /****************************************************************************
1217 * Parsing functions for the AMD IOMMU specific kernel command line
1220 ****************************************************************************/
1222 static int __init
parse_amd_iommu_options(char *str
)
1224 for (; *str
; ++str
) {
1225 if (strncmp(str
, "isolate", 7) == 0)
1226 amd_iommu_isolate
= true;
1227 if (strncmp(str
, "share", 5) == 0)
1228 amd_iommu_isolate
= false;
1229 if (strncmp(str
, "fullflush", 9) == 0)
1230 amd_iommu_unmap_flush
= true;
1236 static int __init
parse_amd_iommu_size_options(char *str
)
1238 unsigned order
= PAGE_SHIFT
+ get_order(memparse(str
, &str
));
1240 if ((order
> 24) && (order
< 31))
1241 amd_iommu_aperture_order
= order
;
1246 __setup("amd_iommu=", parse_amd_iommu_options
);
1247 __setup("amd_iommu_size=", parse_amd_iommu_size_options
);