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bnx2x: (NPAR mode) Fix FW initialization
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / bnx2x / bnx2x_ethtool.c
blobb3da295c453ce0a3bcb1d82a84a381709b09e633
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #include <linux/ethtool.h>
18 #include <linux/netdevice.h>
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/crc32.h>
22
23
24 #include "bnx2x.h"
25 #include "bnx2x_cmn.h"
26 #include "bnx2x_dump.h"
27 #include "bnx2x_init.h"
28
29 /* Note: in the format strings below %s is replaced by the queue-name which is
30 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
31 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
32 */
33 #define MAX_QUEUE_NAME_LEN 4
34 static const struct {
35 long offset;
36 int size;
37 char string[ETH_GSTRING_LEN];
38 } bnx2x_q_stats_arr[] = {
39 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
40 { Q_STATS_OFFSET32(error_bytes_received_hi),
41 8, "[%s]: rx_error_bytes" },
42 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
43 8, "[%s]: rx_ucast_packets" },
44 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
45 8, "[%s]: rx_mcast_packets" },
46 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
47 8, "[%s]: rx_bcast_packets" },
48 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
49 { Q_STATS_OFFSET32(rx_err_discard_pkt),
50 4, "[%s]: rx_phy_ip_err_discards"},
51 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
52 4, "[%s]: rx_skb_alloc_discard" },
53 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
54
55 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
56 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
57 8, "[%s]: tx_ucast_packets" },
58 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
59 8, "[%s]: tx_mcast_packets" },
60 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
61 8, "[%s]: tx_bcast_packets" }
62 };
63
64 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
65
66 static const struct {
67 long offset;
68 int size;
69 u32 flags;
70 #define STATS_FLAGS_PORT 1
71 #define STATS_FLAGS_FUNC 2
72 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
73 char string[ETH_GSTRING_LEN];
74 } bnx2x_stats_arr[] = {
75 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
76 8, STATS_FLAGS_BOTH, "rx_bytes" },
77 { STATS_OFFSET32(error_bytes_received_hi),
78 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
79 { STATS_OFFSET32(total_unicast_packets_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
81 { STATS_OFFSET32(total_multicast_packets_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
83 { STATS_OFFSET32(total_broadcast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
85 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
86 8, STATS_FLAGS_PORT, "rx_crc_errors" },
87 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
88 8, STATS_FLAGS_PORT, "rx_align_errors" },
89 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
90 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
91 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
92 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
93 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
94 8, STATS_FLAGS_PORT, "rx_fragments" },
95 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
96 8, STATS_FLAGS_PORT, "rx_jabbers" },
97 { STATS_OFFSET32(no_buff_discard_hi),
98 8, STATS_FLAGS_BOTH, "rx_discards" },
99 { STATS_OFFSET32(mac_filter_discard),
100 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
101 { STATS_OFFSET32(xxoverflow_discard),
102 4, STATS_FLAGS_PORT, "rx_fw_discards" },
103 { STATS_OFFSET32(brb_drop_hi),
104 8, STATS_FLAGS_PORT, "rx_brb_discard" },
105 { STATS_OFFSET32(brb_truncate_hi),
106 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
107 { STATS_OFFSET32(pause_frames_received_hi),
108 8, STATS_FLAGS_PORT, "rx_pause_frames" },
109 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
110 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
111 { STATS_OFFSET32(nig_timer_max),
112 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
113 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
114 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
115 { STATS_OFFSET32(rx_skb_alloc_failed),
116 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
117 { STATS_OFFSET32(hw_csum_err),
118 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
119
120 { STATS_OFFSET32(total_bytes_transmitted_hi),
121 8, STATS_FLAGS_BOTH, "tx_bytes" },
122 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
123 8, STATS_FLAGS_PORT, "tx_error_bytes" },
124 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
126 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
127 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
128 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
130 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
131 8, STATS_FLAGS_PORT, "tx_mac_errors" },
132 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
133 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
134 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
135 8, STATS_FLAGS_PORT, "tx_single_collisions" },
136 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
137 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
138 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
139 8, STATS_FLAGS_PORT, "tx_deferred" },
140 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
141 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
143 8, STATS_FLAGS_PORT, "tx_late_collisions" },
144 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_total_collisions" },
146 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
147 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
148 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
149 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
151 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
153 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
154 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
155 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
156 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
157 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
158 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
159 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
160 { STATS_OFFSET32(pause_frames_sent_hi),
161 8, STATS_FLAGS_PORT, "tx_pause_frames" }
162 };
163
164 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
165
166 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
167 {
168 struct bnx2x *bp = netdev_priv(dev);
169 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
170 /* Dual Media boards present all available port types */
171 cmd->supported = bp->port.supported[cfg_idx] |
172 (bp->port.supported[cfg_idx ^ 1] &
173 (SUPPORTED_TP | SUPPORTED_FIBRE));
174 cmd->advertising = bp->port.advertising[cfg_idx];
175
176 if ((bp->state == BNX2X_STATE_OPEN) &&
177 !(bp->flags & MF_FUNC_DIS) &&
178 (bp->link_vars.link_up)) {
179 cmd->speed = bp->link_vars.line_speed;
180 cmd->duplex = bp->link_vars.duplex;
181 } else {
182
183 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
184 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
185 }
186
187 if (IS_MF(bp))
188 cmd->speed = bnx2x_get_mf_speed(bp);
189
190 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
191 cmd->port = PORT_TP;
192 else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
193 cmd->port = PORT_FIBRE;
194 else
195 BNX2X_ERR("XGXS PHY Failure detected\n");
196
197 cmd->phy_address = bp->mdio.prtad;
198 cmd->transceiver = XCVR_INTERNAL;
199
200 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
201 cmd->autoneg = AUTONEG_ENABLE;
202 else
203 cmd->autoneg = AUTONEG_DISABLE;
204
205 cmd->maxtxpkt = 0;
206 cmd->maxrxpkt = 0;
207
208 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
209 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
210 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
211 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
212 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
213 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
214 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
215
216 return 0;
217 }
218
219 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
220 {
221 struct bnx2x *bp = netdev_priv(dev);
222 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
223 u32 speed;
224
225 if (IS_MF_SD(bp))
226 return 0;
227
228 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
229 " supported 0x%x advertising 0x%x speed %d speed_hi %d\n"
230 " duplex %d port %d phy_address %d transceiver %d\n"
231 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
232 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
233 cmd->speed_hi,
234 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
235 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
236
237 speed = cmd->speed;
238 speed |= (cmd->speed_hi << 16);
239
240 if (IS_MF_SI(bp)) {
241 u32 param = 0, part;
242 u32 line_speed = bp->link_vars.line_speed;
243
244 /* use 10G if no link detected */
245 if (!line_speed)
246 line_speed = 10000;
247
248 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
249 BNX2X_DEV_INFO("To set speed BC %X or higher "
250 "is required, please upgrade BC\n",
251 REQ_BC_VER_4_SET_MF_BW);
252 return -EINVAL;
253 }
254 part = (speed * 100) / line_speed;
255 if (line_speed < speed || !part) {
256 BNX2X_DEV_INFO("Speed setting should be in a range "
257 "from 1%% to 100%% "
258 "of actual line speed\n");
259 return -EINVAL;
260 }
261 /* load old values */
262 param = bp->mf_config[BP_VN(bp)];
263
264 /* leave only MIN value */
265 param &= FUNC_MF_CFG_MIN_BW_MASK;
266
267 /* set new MAX value */
268 param |= (part << FUNC_MF_CFG_MAX_BW_SHIFT)
269 & FUNC_MF_CFG_MAX_BW_MASK;
270
271 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, param);
272 return 0;
273 }
274
275 cfg_idx = bnx2x_get_link_cfg_idx(bp);
276 old_multi_phy_config = bp->link_params.multi_phy_config;
277 switch (cmd->port) {
278 case PORT_TP:
279 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
280 break; /* no port change */
281
282 if (!(bp->port.supported[0] & SUPPORTED_TP ||
283 bp->port.supported[1] & SUPPORTED_TP)) {
284 DP(NETIF_MSG_LINK, "Unsupported port type\n");
285 return -EINVAL;
286 }
287 bp->link_params.multi_phy_config &=
288 ~PORT_HW_CFG_PHY_SELECTION_MASK;
289 if (bp->link_params.multi_phy_config &
290 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
291 bp->link_params.multi_phy_config |=
292 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
293 else
294 bp->link_params.multi_phy_config |=
295 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
296 break;
297 case PORT_FIBRE:
298 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
299 break; /* no port change */
300
301 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
302 bp->port.supported[1] & SUPPORTED_FIBRE)) {
303 DP(NETIF_MSG_LINK, "Unsupported port type\n");
304 return -EINVAL;
305 }
306 bp->link_params.multi_phy_config &=
307 ~PORT_HW_CFG_PHY_SELECTION_MASK;
308 if (bp->link_params.multi_phy_config &
309 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
310 bp->link_params.multi_phy_config |=
311 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
312 else
313 bp->link_params.multi_phy_config |=
314 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
315 break;
316 default:
317 DP(NETIF_MSG_LINK, "Unsupported port type\n");
318 return -EINVAL;
319 }
320 /* Save new config in case command complete successuly */
321 new_multi_phy_config = bp->link_params.multi_phy_config;
322 /* Get the new cfg_idx */
323 cfg_idx = bnx2x_get_link_cfg_idx(bp);
324 /* Restore old config in case command failed */
325 bp->link_params.multi_phy_config = old_multi_phy_config;
326 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
327
328 if (cmd->autoneg == AUTONEG_ENABLE) {
329 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
330 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
331 return -EINVAL;
332 }
333
334 /* advertise the requested speed and duplex if supported */
335 cmd->advertising &= bp->port.supported[cfg_idx];
336
337 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
338 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
339 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
340 cmd->advertising);
341
342 } else { /* forced speed */
343 /* advertise the requested speed and duplex if supported */
344 switch (speed) {
345 case SPEED_10:
346 if (cmd->duplex == DUPLEX_FULL) {
347 if (!(bp->port.supported[cfg_idx] &
348 SUPPORTED_10baseT_Full)) {
349 DP(NETIF_MSG_LINK,
350 "10M full not supported\n");
351 return -EINVAL;
352 }
353
354 advertising = (ADVERTISED_10baseT_Full |
355 ADVERTISED_TP);
356 } else {
357 if (!(bp->port.supported[cfg_idx] &
358 SUPPORTED_10baseT_Half)) {
359 DP(NETIF_MSG_LINK,
360 "10M half not supported\n");
361 return -EINVAL;
362 }
363
364 advertising = (ADVERTISED_10baseT_Half |
365 ADVERTISED_TP);
366 }
367 break;
368
369 case SPEED_100:
370 if (cmd->duplex == DUPLEX_FULL) {
371 if (!(bp->port.supported[cfg_idx] &
372 SUPPORTED_100baseT_Full)) {
373 DP(NETIF_MSG_LINK,
374 "100M full not supported\n");
375 return -EINVAL;
376 }
377
378 advertising = (ADVERTISED_100baseT_Full |
379 ADVERTISED_TP);
380 } else {
381 if (!(bp->port.supported[cfg_idx] &
382 SUPPORTED_100baseT_Half)) {
383 DP(NETIF_MSG_LINK,
384 "100M half not supported\n");
385 return -EINVAL;
386 }
387
388 advertising = (ADVERTISED_100baseT_Half |
389 ADVERTISED_TP);
390 }
391 break;
392
393 case SPEED_1000:
394 if (cmd->duplex != DUPLEX_FULL) {
395 DP(NETIF_MSG_LINK, "1G half not supported\n");
396 return -EINVAL;
397 }
398
399 if (!(bp->port.supported[cfg_idx] &
400 SUPPORTED_1000baseT_Full)) {
401 DP(NETIF_MSG_LINK, "1G full not supported\n");
402 return -EINVAL;
403 }
404
405 advertising = (ADVERTISED_1000baseT_Full |
406 ADVERTISED_TP);
407 break;
408
409 case SPEED_2500:
410 if (cmd->duplex != DUPLEX_FULL) {
411 DP(NETIF_MSG_LINK,
412 "2.5G half not supported\n");
413 return -EINVAL;
414 }
415
416 if (!(bp->port.supported[cfg_idx]
417 & SUPPORTED_2500baseX_Full)) {
418 DP(NETIF_MSG_LINK,
419 "2.5G full not supported\n");
420 return -EINVAL;
421 }
422
423 advertising = (ADVERTISED_2500baseX_Full |
424 ADVERTISED_TP);
425 break;
426
427 case SPEED_10000:
428 if (cmd->duplex != DUPLEX_FULL) {
429 DP(NETIF_MSG_LINK, "10G half not supported\n");
430 return -EINVAL;
431 }
432
433 if (!(bp->port.supported[cfg_idx]
434 & SUPPORTED_10000baseT_Full)) {
435 DP(NETIF_MSG_LINK, "10G full not supported\n");
436 return -EINVAL;
437 }
438
439 advertising = (ADVERTISED_10000baseT_Full |
440 ADVERTISED_FIBRE);
441 break;
442
443 default:
444 DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
445 return -EINVAL;
446 }
447
448 bp->link_params.req_line_speed[cfg_idx] = speed;
449 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
450 bp->port.advertising[cfg_idx] = advertising;
451 }
452
453 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
454 DP_LEVEL " req_duplex %d advertising 0x%x\n",
455 bp->link_params.req_line_speed[cfg_idx],
456 bp->link_params.req_duplex[cfg_idx],
457 bp->port.advertising[cfg_idx]);
458
459 /* Set new config */
460 bp->link_params.multi_phy_config = new_multi_phy_config;
461 if (netif_running(dev)) {
462 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
463 bnx2x_link_set(bp);
464 }
465
466 return 0;
467 }
468
469 #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
470 #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
471 #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
472
473 static int bnx2x_get_regs_len(struct net_device *dev)
474 {
475 struct bnx2x *bp = netdev_priv(dev);
476 int regdump_len = 0;
477 int i, j, k;
478
479 if (CHIP_IS_E1(bp)) {
480 for (i = 0; i < REGS_COUNT; i++)
481 if (IS_E1_ONLINE(reg_addrs[i].info))
482 regdump_len += reg_addrs[i].size;
483
484 for (i = 0; i < WREGS_COUNT_E1; i++)
485 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
486 regdump_len += wreg_addrs_e1[i].size *
487 (1 + wreg_addrs_e1[i].read_regs_count);
488
489 } else if (CHIP_IS_E1H(bp)) {
490 for (i = 0; i < REGS_COUNT; i++)
491 if (IS_E1H_ONLINE(reg_addrs[i].info))
492 regdump_len += reg_addrs[i].size;
493
494 for (i = 0; i < WREGS_COUNT_E1H; i++)
495 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
496 regdump_len += wreg_addrs_e1h[i].size *
497 (1 + wreg_addrs_e1h[i].read_regs_count);
498 } else if (CHIP_IS_E2(bp)) {
499 for (i = 0; i < REGS_COUNT; i++)
500 if (IS_E2_ONLINE(reg_addrs[i].info))
501 regdump_len += reg_addrs[i].size;
502
503 for (i = 0; i < WREGS_COUNT_E2; i++)
504 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
505 regdump_len += wreg_addrs_e2[i].size *
506 (1 + wreg_addrs_e2[i].read_regs_count);
507
508 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
509 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
510 for (k = 0; k < PAGE_READ_REGS_E2; k++)
511 if (IS_E2_ONLINE(page_read_regs_e2[k].
512 info))
513 regdump_len +=
514 page_read_regs_e2[k].size;
515 }
516 }
517 regdump_len *= 4;
518 regdump_len += sizeof(struct dump_hdr);
519
520 return regdump_len;
521 }
522
523 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
524 {
525 u32 i, j, k, n;
526
527 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
528 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
529 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
530 for (k = 0; k < PAGE_READ_REGS_E2; k++)
531 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
532 for (n = 0; n <
533 page_read_regs_e2[k].size; n++)
534 *p++ = REG_RD(bp,
535 page_read_regs_e2[k].addr + n*4);
536 }
537 }
538 }
539
540 static void bnx2x_get_regs(struct net_device *dev,
541 struct ethtool_regs *regs, void *_p)
542 {
543 u32 *p = _p, i, j;
544 struct bnx2x *bp = netdev_priv(dev);
545 struct dump_hdr dump_hdr = {0};
546
547 regs->version = 0;
548 memset(p, 0, regs->len);
549
550 if (!netif_running(bp->dev))
551 return;
552
553 /* Disable parity attentions as long as following dump may
554 * cause false alarms by reading never written registers. We
555 * will re-enable parity attentions right after the dump.
556 */
557 bnx2x_disable_blocks_parity(bp);
558
559 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
560 dump_hdr.dump_sign = dump_sign_all;
561 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
562 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
563 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
564 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
565
566 if (CHIP_IS_E1(bp))
567 dump_hdr.info = RI_E1_ONLINE;
568 else if (CHIP_IS_E1H(bp))
569 dump_hdr.info = RI_E1H_ONLINE;
570 else if (CHIP_IS_E2(bp))
571 dump_hdr.info = RI_E2_ONLINE |
572 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
573
574 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
575 p += dump_hdr.hdr_size + 1;
576
577 if (CHIP_IS_E1(bp)) {
578 for (i = 0; i < REGS_COUNT; i++)
579 if (IS_E1_ONLINE(reg_addrs[i].info))
580 for (j = 0; j < reg_addrs[i].size; j++)
581 *p++ = REG_RD(bp,
582 reg_addrs[i].addr + j*4);
583
584 } else if (CHIP_IS_E1H(bp)) {
585 for (i = 0; i < REGS_COUNT; i++)
586 if (IS_E1H_ONLINE(reg_addrs[i].info))
587 for (j = 0; j < reg_addrs[i].size; j++)
588 *p++ = REG_RD(bp,
589 reg_addrs[i].addr + j*4);
590
591 } else if (CHIP_IS_E2(bp)) {
592 for (i = 0; i < REGS_COUNT; i++)
593 if (IS_E2_ONLINE(reg_addrs[i].info))
594 for (j = 0; j < reg_addrs[i].size; j++)
595 *p++ = REG_RD(bp,
596 reg_addrs[i].addr + j*4);
597
598 bnx2x_read_pages_regs_e2(bp, p);
599 }
600 /* Re-enable parity attentions */
601 bnx2x_clear_blocks_parity(bp);
602 if (CHIP_PARITY_ENABLED(bp))
603 bnx2x_enable_blocks_parity(bp);
604 }
605
606 #define PHY_FW_VER_LEN 20
607
608 static void bnx2x_get_drvinfo(struct net_device *dev,
609 struct ethtool_drvinfo *info)
610 {
611 struct bnx2x *bp = netdev_priv(dev);
612 u8 phy_fw_ver[PHY_FW_VER_LEN];
613
614 strcpy(info->driver, DRV_MODULE_NAME);
615 strcpy(info->version, DRV_MODULE_VERSION);
616
617 phy_fw_ver[0] = '\0';
618 if (bp->port.pmf) {
619 bnx2x_acquire_phy_lock(bp);
620 bnx2x_get_ext_phy_fw_version(&bp->link_params,
621 (bp->state != BNX2X_STATE_CLOSED),
622 phy_fw_ver, PHY_FW_VER_LEN);
623 bnx2x_release_phy_lock(bp);
624 }
625
626 strncpy(info->fw_version, bp->fw_ver, 32);
627 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
628 "bc %d.%d.%d%s%s",
629 (bp->common.bc_ver & 0xff0000) >> 16,
630 (bp->common.bc_ver & 0xff00) >> 8,
631 (bp->common.bc_ver & 0xff),
632 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
633 strcpy(info->bus_info, pci_name(bp->pdev));
634 info->n_stats = BNX2X_NUM_STATS;
635 info->testinfo_len = BNX2X_NUM_TESTS;
636 info->eedump_len = bp->common.flash_size;
637 info->regdump_len = bnx2x_get_regs_len(dev);
638 }
639
640 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
641 {
642 struct bnx2x *bp = netdev_priv(dev);
643
644 if (bp->flags & NO_WOL_FLAG) {
645 wol->supported = 0;
646 wol->wolopts = 0;
647 } else {
648 wol->supported = WAKE_MAGIC;
649 if (bp->wol)
650 wol->wolopts = WAKE_MAGIC;
651 else
652 wol->wolopts = 0;
653 }
654 memset(&wol->sopass, 0, sizeof(wol->sopass));
655 }
656
657 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
658 {
659 struct bnx2x *bp = netdev_priv(dev);
660
661 if (wol->wolopts & ~WAKE_MAGIC)
662 return -EINVAL;
663
664 if (wol->wolopts & WAKE_MAGIC) {
665 if (bp->flags & NO_WOL_FLAG)
666 return -EINVAL;
667
668 bp->wol = 1;
669 } else
670 bp->wol = 0;
671
672 return 0;
673 }
674
675 static u32 bnx2x_get_msglevel(struct net_device *dev)
676 {
677 struct bnx2x *bp = netdev_priv(dev);
678
679 return bp->msg_enable;
680 }
681
682 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
683 {
684 struct bnx2x *bp = netdev_priv(dev);
685
686 if (capable(CAP_NET_ADMIN))
687 bp->msg_enable = level;
688 }
689
690 static int bnx2x_nway_reset(struct net_device *dev)
691 {
692 struct bnx2x *bp = netdev_priv(dev);
693
694 if (!bp->port.pmf)
695 return 0;
696
697 if (netif_running(dev)) {
698 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
699 bnx2x_link_set(bp);
700 }
701
702 return 0;
703 }
704
705 static u32 bnx2x_get_link(struct net_device *dev)
706 {
707 struct bnx2x *bp = netdev_priv(dev);
708
709 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
710 return 0;
711
712 return bp->link_vars.link_up;
713 }
714
715 static int bnx2x_get_eeprom_len(struct net_device *dev)
716 {
717 struct bnx2x *bp = netdev_priv(dev);
718
719 return bp->common.flash_size;
720 }
721
722 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
723 {
724 int port = BP_PORT(bp);
725 int count, i;
726 u32 val = 0;
727
728 /* adjust timeout for emulation/FPGA */
729 count = NVRAM_TIMEOUT_COUNT;
730 if (CHIP_REV_IS_SLOW(bp))
731 count *= 100;
732
733 /* request access to nvram interface */
734 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
735 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
736
737 for (i = 0; i < count*10; i++) {
738 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
739 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
740 break;
741
742 udelay(5);
743 }
744
745 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
746 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
747 return -EBUSY;
748 }
749
750 return 0;
751 }
752
753 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
754 {
755 int port = BP_PORT(bp);
756 int count, i;
757 u32 val = 0;
758
759 /* adjust timeout for emulation/FPGA */
760 count = NVRAM_TIMEOUT_COUNT;
761 if (CHIP_REV_IS_SLOW(bp))
762 count *= 100;
763
764 /* relinquish nvram interface */
765 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
766 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
767
768 for (i = 0; i < count*10; i++) {
769 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
770 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
771 break;
772
773 udelay(5);
774 }
775
776 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
777 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
778 return -EBUSY;
779 }
780
781 return 0;
782 }
783
784 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
785 {
786 u32 val;
787
788 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
789
790 /* enable both bits, even on read */
791 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
792 (val | MCPR_NVM_ACCESS_ENABLE_EN |
793 MCPR_NVM_ACCESS_ENABLE_WR_EN));
794 }
795
796 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
797 {
798 u32 val;
799
800 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
801
802 /* disable both bits, even after read */
803 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
804 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
805 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
806 }
807
808 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
809 u32 cmd_flags)
810 {
811 int count, i, rc;
812 u32 val;
813
814 /* build the command word */
815 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
816
817 /* need to clear DONE bit separately */
818 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
819
820 /* address of the NVRAM to read from */
821 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
822 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
823
824 /* issue a read command */
825 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
826
827 /* adjust timeout for emulation/FPGA */
828 count = NVRAM_TIMEOUT_COUNT;
829 if (CHIP_REV_IS_SLOW(bp))
830 count *= 100;
831
832 /* wait for completion */
833 *ret_val = 0;
834 rc = -EBUSY;
835 for (i = 0; i < count; i++) {
836 udelay(5);
837 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
838
839 if (val & MCPR_NVM_COMMAND_DONE) {
840 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
841 /* we read nvram data in cpu order
842 * but ethtool sees it as an array of bytes
843 * converting to big-endian will do the work */
844 *ret_val = cpu_to_be32(val);
845 rc = 0;
846 break;
847 }
848 }
849
850 return rc;
851 }
852
853 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
854 int buf_size)
855 {
856 int rc;
857 u32 cmd_flags;
858 __be32 val;
859
860 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
861 DP(BNX2X_MSG_NVM,
862 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
863 offset, buf_size);
864 return -EINVAL;
865 }
866
867 if (offset + buf_size > bp->common.flash_size) {
868 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
869 " buf_size (0x%x) > flash_size (0x%x)\n",
870 offset, buf_size, bp->common.flash_size);
871 return -EINVAL;
872 }
873
874 /* request access to nvram interface */
875 rc = bnx2x_acquire_nvram_lock(bp);
876 if (rc)
877 return rc;
878
879 /* enable access to nvram interface */
880 bnx2x_enable_nvram_access(bp);
881
882 /* read the first word(s) */
883 cmd_flags = MCPR_NVM_COMMAND_FIRST;
884 while ((buf_size > sizeof(u32)) && (rc == 0)) {
885 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
886 memcpy(ret_buf, &val, 4);
887
888 /* advance to the next dword */
889 offset += sizeof(u32);
890 ret_buf += sizeof(u32);
891 buf_size -= sizeof(u32);
892 cmd_flags = 0;
893 }
894
895 if (rc == 0) {
896 cmd_flags |= MCPR_NVM_COMMAND_LAST;
897 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
898 memcpy(ret_buf, &val, 4);
899 }
900
901 /* disable access to nvram interface */
902 bnx2x_disable_nvram_access(bp);
903 bnx2x_release_nvram_lock(bp);
904
905 return rc;
906 }
907
908 static int bnx2x_get_eeprom(struct net_device *dev,
909 struct ethtool_eeprom *eeprom, u8 *eebuf)
910 {
911 struct bnx2x *bp = netdev_priv(dev);
912 int rc;
913
914 if (!netif_running(dev))
915 return -EAGAIN;
916
917 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
918 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
919 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
920 eeprom->len, eeprom->len);
921
922 /* parameters already validated in ethtool_get_eeprom */
923
924 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
925
926 return rc;
927 }
928
929 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
930 u32 cmd_flags)
931 {
932 int count, i, rc;
933
934 /* build the command word */
935 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
936
937 /* need to clear DONE bit separately */
938 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
939
940 /* write the data */
941 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
942
943 /* address of the NVRAM to write to */
944 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
945 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
946
947 /* issue the write command */
948 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
949
950 /* adjust timeout for emulation/FPGA */
951 count = NVRAM_TIMEOUT_COUNT;
952 if (CHIP_REV_IS_SLOW(bp))
953 count *= 100;
954
955 /* wait for completion */
956 rc = -EBUSY;
957 for (i = 0; i < count; i++) {
958 udelay(5);
959 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
960 if (val & MCPR_NVM_COMMAND_DONE) {
961 rc = 0;
962 break;
963 }
964 }
965
966 return rc;
967 }
968
969 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
970
971 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
972 int buf_size)
973 {
974 int rc;
975 u32 cmd_flags;
976 u32 align_offset;
977 __be32 val;
978
979 if (offset + buf_size > bp->common.flash_size) {
980 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
981 " buf_size (0x%x) > flash_size (0x%x)\n",
982 offset, buf_size, bp->common.flash_size);
983 return -EINVAL;
984 }
985
986 /* request access to nvram interface */
987 rc = bnx2x_acquire_nvram_lock(bp);
988 if (rc)
989 return rc;
990
991 /* enable access to nvram interface */
992 bnx2x_enable_nvram_access(bp);
993
994 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
995 align_offset = (offset & ~0x03);
996 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
997
998 if (rc == 0) {
999 val &= ~(0xff << BYTE_OFFSET(offset));
1000 val |= (*data_buf << BYTE_OFFSET(offset));
1001
1002 /* nvram data is returned as an array of bytes
1003 * convert it back to cpu order */
1004 val = be32_to_cpu(val);
1005
1006 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1007 cmd_flags);
1008 }
1009
1010 /* disable access to nvram interface */
1011 bnx2x_disable_nvram_access(bp);
1012 bnx2x_release_nvram_lock(bp);
1013
1014 return rc;
1015 }
1016
1017 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1018 int buf_size)
1019 {
1020 int rc;
1021 u32 cmd_flags;
1022 u32 val;
1023 u32 written_so_far;
1024
1025 if (buf_size == 1) /* ethtool */
1026 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1027
1028 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1029 DP(BNX2X_MSG_NVM,
1030 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1031 offset, buf_size);
1032 return -EINVAL;
1033 }
1034
1035 if (offset + buf_size > bp->common.flash_size) {
1036 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1037 " buf_size (0x%x) > flash_size (0x%x)\n",
1038 offset, buf_size, bp->common.flash_size);
1039 return -EINVAL;
1040 }
1041
1042 /* request access to nvram interface */
1043 rc = bnx2x_acquire_nvram_lock(bp);
1044 if (rc)
1045 return rc;
1046
1047 /* enable access to nvram interface */
1048 bnx2x_enable_nvram_access(bp);
1049
1050 written_so_far = 0;
1051 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1052 while ((written_so_far < buf_size) && (rc == 0)) {
1053 if (written_so_far == (buf_size - sizeof(u32)))
1054 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1055 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1056 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1057 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1058 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1059
1060 memcpy(&val, data_buf, 4);
1061
1062 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1063
1064 /* advance to the next dword */
1065 offset += sizeof(u32);
1066 data_buf += sizeof(u32);
1067 written_so_far += sizeof(u32);
1068 cmd_flags = 0;
1069 }
1070
1071 /* disable access to nvram interface */
1072 bnx2x_disable_nvram_access(bp);
1073 bnx2x_release_nvram_lock(bp);
1074
1075 return rc;
1076 }
1077
1078 static int bnx2x_set_eeprom(struct net_device *dev,
1079 struct ethtool_eeprom *eeprom, u8 *eebuf)
1080 {
1081 struct bnx2x *bp = netdev_priv(dev);
1082 int port = BP_PORT(bp);
1083 int rc = 0;
1084 u32 ext_phy_config;
1085 if (!netif_running(dev))
1086 return -EAGAIN;
1087
1088 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1089 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1090 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1091 eeprom->len, eeprom->len);
1092
1093 /* parameters already validated in ethtool_set_eeprom */
1094
1095 /* PHY eeprom can be accessed only by the PMF */
1096 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1097 !bp->port.pmf)
1098 return -EINVAL;
1099
1100 ext_phy_config =
1101 SHMEM_RD(bp,
1102 dev_info.port_hw_config[port].external_phy_config);
1103
1104 if (eeprom->magic == 0x50485950) {
1105 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1106 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1107
1108 bnx2x_acquire_phy_lock(bp);
1109 rc |= bnx2x_link_reset(&bp->link_params,
1110 &bp->link_vars, 0);
1111 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1112 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1113 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1114 MISC_REGISTERS_GPIO_HIGH, port);
1115 bnx2x_release_phy_lock(bp);
1116 bnx2x_link_report(bp);
1117
1118 } else if (eeprom->magic == 0x50485952) {
1119 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1120 if (bp->state == BNX2X_STATE_OPEN) {
1121 bnx2x_acquire_phy_lock(bp);
1122 rc |= bnx2x_link_reset(&bp->link_params,
1123 &bp->link_vars, 1);
1124
1125 rc |= bnx2x_phy_init(&bp->link_params,
1126 &bp->link_vars);
1127 bnx2x_release_phy_lock(bp);
1128 bnx2x_calc_fc_adv(bp);
1129 }
1130 } else if (eeprom->magic == 0x53985943) {
1131 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1132 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1133 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1134
1135 /* DSP Remove Download Mode */
1136 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1137 MISC_REGISTERS_GPIO_LOW, port);
1138
1139 bnx2x_acquire_phy_lock(bp);
1140
1141 bnx2x_sfx7101_sp_sw_reset(bp,
1142 &bp->link_params.phy[EXT_PHY1]);
1143
1144 /* wait 0.5 sec to allow it to run */
1145 msleep(500);
1146 bnx2x_ext_phy_hw_reset(bp, port);
1147 msleep(500);
1148 bnx2x_release_phy_lock(bp);
1149 }
1150 } else
1151 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1152
1153 return rc;
1154 }
1155
1156 static int bnx2x_get_coalesce(struct net_device *dev,
1157 struct ethtool_coalesce *coal)
1158 {
1159 struct bnx2x *bp = netdev_priv(dev);
1160
1161 memset(coal, 0, sizeof(struct ethtool_coalesce));
1162
1163 coal->rx_coalesce_usecs = bp->rx_ticks;
1164 coal->tx_coalesce_usecs = bp->tx_ticks;
1165
1166 return 0;
1167 }
1168
1169 static int bnx2x_set_coalesce(struct net_device *dev,
1170 struct ethtool_coalesce *coal)
1171 {
1172 struct bnx2x *bp = netdev_priv(dev);
1173
1174 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1175 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1176 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1177
1178 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1179 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1180 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1181
1182 if (netif_running(dev))
1183 bnx2x_update_coalesce(bp);
1184
1185 return 0;
1186 }
1187
1188 static void bnx2x_get_ringparam(struct net_device *dev,
1189 struct ethtool_ringparam *ering)
1190 {
1191 struct bnx2x *bp = netdev_priv(dev);
1192
1193 ering->rx_max_pending = MAX_RX_AVAIL;
1194 ering->rx_mini_max_pending = 0;
1195 ering->rx_jumbo_max_pending = 0;
1196
1197 if (bp->rx_ring_size)
1198 ering->rx_pending = bp->rx_ring_size;
1199 else
1200 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1201 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1202 else
1203 ering->rx_pending = MAX_RX_AVAIL;
1204
1205 ering->rx_mini_pending = 0;
1206 ering->rx_jumbo_pending = 0;
1207
1208 ering->tx_max_pending = MAX_TX_AVAIL;
1209 ering->tx_pending = bp->tx_ring_size;
1210 }
1211
1212 static int bnx2x_set_ringparam(struct net_device *dev,
1213 struct ethtool_ringparam *ering)
1214 {
1215 struct bnx2x *bp = netdev_priv(dev);
1216 int rc = 0;
1217
1218 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1219 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1220 return -EAGAIN;
1221 }
1222
1223 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1224 (ering->rx_pending < MIN_RX_AVAIL) ||
1225 (ering->tx_pending > MAX_TX_AVAIL) ||
1226 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1227 return -EINVAL;
1228
1229 bp->rx_ring_size = ering->rx_pending;
1230 bp->tx_ring_size = ering->tx_pending;
1231
1232 if (netif_running(dev)) {
1233 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1234 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1235 }
1236
1237 return rc;
1238 }
1239
1240 static void bnx2x_get_pauseparam(struct net_device *dev,
1241 struct ethtool_pauseparam *epause)
1242 {
1243 struct bnx2x *bp = netdev_priv(dev);
1244 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1245 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1246 BNX2X_FLOW_CTRL_AUTO);
1247
1248 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1249 BNX2X_FLOW_CTRL_RX);
1250 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1251 BNX2X_FLOW_CTRL_TX);
1252
1253 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1254 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1255 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1256 }
1257
1258 static int bnx2x_set_pauseparam(struct net_device *dev,
1259 struct ethtool_pauseparam *epause)
1260 {
1261 struct bnx2x *bp = netdev_priv(dev);
1262 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1263 if (IS_MF(bp))
1264 return 0;
1265
1266 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1267 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1268 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1269
1270 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1271
1272 if (epause->rx_pause)
1273 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1274
1275 if (epause->tx_pause)
1276 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1277
1278 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1279 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1280
1281 if (epause->autoneg) {
1282 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1283 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1284 return -EINVAL;
1285 }
1286
1287 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1288 bp->link_params.req_flow_ctrl[cfg_idx] =
1289 BNX2X_FLOW_CTRL_AUTO;
1290 }
1291 }
1292
1293 DP(NETIF_MSG_LINK,
1294 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1295
1296 if (netif_running(dev)) {
1297 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1298 bnx2x_link_set(bp);
1299 }
1300
1301 return 0;
1302 }
1303
1304 static int bnx2x_set_flags(struct net_device *dev, u32 data)
1305 {
1306 struct bnx2x *bp = netdev_priv(dev);
1307 int changed = 0;
1308 int rc = 0;
1309
1310 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1311 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1312 return -EAGAIN;
1313 }
1314
1315 if (!(data & ETH_FLAG_RXVLAN))
1316 return -EINVAL;
1317
1318 if ((data & ETH_FLAG_LRO) && bp->rx_csum && bp->disable_tpa)
1319 return -EINVAL;
1320
1321 rc = ethtool_op_set_flags(dev, data, ETH_FLAG_LRO | ETH_FLAG_RXVLAN |
1322 ETH_FLAG_TXVLAN | ETH_FLAG_RXHASH);
1323 if (rc)
1324 return rc;
1325
1326 /* TPA requires Rx CSUM offloading */
1327 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
1328 if (!(bp->flags & TPA_ENABLE_FLAG)) {
1329 bp->flags |= TPA_ENABLE_FLAG;
1330 changed = 1;
1331 }
1332 } else if (bp->flags & TPA_ENABLE_FLAG) {
1333 dev->features &= ~NETIF_F_LRO;
1334 bp->flags &= ~TPA_ENABLE_FLAG;
1335 changed = 1;
1336 }
1337
1338 if (changed && netif_running(dev)) {
1339 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1340 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1341 }
1342
1343 return rc;
1344 }
1345
1346 static u32 bnx2x_get_rx_csum(struct net_device *dev)
1347 {
1348 struct bnx2x *bp = netdev_priv(dev);
1349
1350 return bp->rx_csum;
1351 }
1352
1353 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1354 {
1355 struct bnx2x *bp = netdev_priv(dev);
1356 int rc = 0;
1357
1358 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1359 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1360 return -EAGAIN;
1361 }
1362
1363 bp->rx_csum = data;
1364
1365 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1366 TPA'ed packets will be discarded due to wrong TCP CSUM */
1367 if (!data) {
1368 u32 flags = ethtool_op_get_flags(dev);
1369
1370 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1371 }
1372
1373 return rc;
1374 }
1375
1376 static int bnx2x_set_tso(struct net_device *dev, u32 data)
1377 {
1378 if (data) {
1379 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1380 dev->features |= NETIF_F_TSO6;
1381 } else {
1382 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1383 dev->features &= ~NETIF_F_TSO6;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static const struct {
1390 char string[ETH_GSTRING_LEN];
1391 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1392 { "register_test (offline)" },
1393 { "memory_test (offline)" },
1394 { "loopback_test (offline)" },
1395 { "nvram_test (online)" },
1396 { "interrupt_test (online)" },
1397 { "link_test (online)" },
1398 { "idle check (online)" }
1399 };
1400
1401 static int bnx2x_test_registers(struct bnx2x *bp)
1402 {
1403 int idx, i, rc = -ENODEV;
1404 u32 wr_val = 0;
1405 int port = BP_PORT(bp);
1406 static const struct {
1407 u32 offset0;
1408 u32 offset1;
1409 u32 mask;
1410 } reg_tbl[] = {
1411 /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1412 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1413 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1414 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1415 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1416 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1417 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1418 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1419 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1420 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1421 /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1422 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1423 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1424 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1425 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1426 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1427 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1428 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1429 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1430 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1431 /* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1432 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1433 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1434 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1435 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1436 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1437 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1438 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1439 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1440 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1441 /* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1442 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1443 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1444 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1445 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1446 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1447 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1448
1449 { 0xffffffff, 0, 0x00000000 }
1450 };
1451
1452 if (!netif_running(bp->dev))
1453 return rc;
1454
1455 /* Repeat the test twice:
1456 First by writing 0x00000000, second by writing 0xffffffff */
1457 for (idx = 0; idx < 2; idx++) {
1458
1459 switch (idx) {
1460 case 0:
1461 wr_val = 0;
1462 break;
1463 case 1:
1464 wr_val = 0xffffffff;
1465 break;
1466 }
1467
1468 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1469 u32 offset, mask, save_val, val;
1470 if (CHIP_IS_E2(bp) &&
1471 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1472 continue;
1473
1474 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1475 mask = reg_tbl[i].mask;
1476
1477 save_val = REG_RD(bp, offset);
1478
1479 REG_WR(bp, offset, wr_val & mask);
1480
1481 val = REG_RD(bp, offset);
1482
1483 /* Restore the original register's value */
1484 REG_WR(bp, offset, save_val);
1485
1486 /* verify value is as expected */
1487 if ((val & mask) != (wr_val & mask)) {
1488 DP(NETIF_MSG_PROBE,
1489 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1490 offset, val, wr_val, mask);
1491 goto test_reg_exit;
1492 }
1493 }
1494 }
1495
1496 rc = 0;
1497
1498 test_reg_exit:
1499 return rc;
1500 }
1501
1502 static int bnx2x_test_memory(struct bnx2x *bp)
1503 {
1504 int i, j, rc = -ENODEV;
1505 u32 val;
1506 static const struct {
1507 u32 offset;
1508 int size;
1509 } mem_tbl[] = {
1510 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1511 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1512 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1513 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1514 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1515 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1516 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1517
1518 { 0xffffffff, 0 }
1519 };
1520 static const struct {
1521 char *name;
1522 u32 offset;
1523 u32 e1_mask;
1524 u32 e1h_mask;
1525 u32 e2_mask;
1526 } prty_tbl[] = {
1527 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1528 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1529 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1530 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1531 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1532 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1533
1534 { NULL, 0xffffffff, 0, 0, 0 }
1535 };
1536
1537 if (!netif_running(bp->dev))
1538 return rc;
1539
1540 /* pre-Check the parity status */
1541 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1542 val = REG_RD(bp, prty_tbl[i].offset);
1543 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1544 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1545 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1546 DP(NETIF_MSG_HW,
1547 "%s is 0x%x\n", prty_tbl[i].name, val);
1548 goto test_mem_exit;
1549 }
1550 }
1551
1552 /* Go through all the memories */
1553 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1554 for (j = 0; j < mem_tbl[i].size; j++)
1555 REG_RD(bp, mem_tbl[i].offset + j*4);
1556
1557 /* Check the parity status */
1558 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1559 val = REG_RD(bp, prty_tbl[i].offset);
1560 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1561 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1562 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1563 DP(NETIF_MSG_HW,
1564 "%s is 0x%x\n", prty_tbl[i].name, val);
1565 goto test_mem_exit;
1566 }
1567 }
1568
1569 rc = 0;
1570
1571 test_mem_exit:
1572 return rc;
1573 }
1574
1575 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1576 {
1577 int cnt = 1400;
1578
1579 if (link_up)
1580 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1581 msleep(10);
1582 }
1583
1584 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1585 {
1586 unsigned int pkt_size, num_pkts, i;
1587 struct sk_buff *skb;
1588 unsigned char *packet;
1589 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1590 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1591 u16 tx_start_idx, tx_idx;
1592 u16 rx_start_idx, rx_idx;
1593 u16 pkt_prod, bd_prod;
1594 struct sw_tx_bd *tx_buf;
1595 struct eth_tx_start_bd *tx_start_bd;
1596 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1597 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
1598 dma_addr_t mapping;
1599 union eth_rx_cqe *cqe;
1600 u8 cqe_fp_flags;
1601 struct sw_rx_bd *rx_buf;
1602 u16 len;
1603 int rc = -ENODEV;
1604
1605 /* check the loopback mode */
1606 switch (loopback_mode) {
1607 case BNX2X_PHY_LOOPBACK:
1608 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1609 return -EINVAL;
1610 break;
1611 case BNX2X_MAC_LOOPBACK:
1612 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1613 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1614 break;
1615 default:
1616 return -EINVAL;
1617 }
1618
1619 /* prepare the loopback packet */
1620 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1621 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1622 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1623 if (!skb) {
1624 rc = -ENOMEM;
1625 goto test_loopback_exit;
1626 }
1627 packet = skb_put(skb, pkt_size);
1628 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1629 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1630 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1631 for (i = ETH_HLEN; i < pkt_size; i++)
1632 packet[i] = (unsigned char) (i & 0xff);
1633
1634 /* send the loopback packet */
1635 num_pkts = 0;
1636 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1637 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1638
1639 pkt_prod = fp_tx->tx_pkt_prod++;
1640 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1641 tx_buf->first_bd = fp_tx->tx_bd_prod;
1642 tx_buf->skb = skb;
1643 tx_buf->flags = 0;
1644
1645 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1646 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1647 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1648 skb_headlen(skb), DMA_TO_DEVICE);
1649 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1650 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1651 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1652 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1653 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1654 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1655 SET_FLAG(tx_start_bd->general_data,
1656 ETH_TX_START_BD_ETH_ADDR_TYPE,
1657 UNICAST_ADDRESS);
1658 SET_FLAG(tx_start_bd->general_data,
1659 ETH_TX_START_BD_HDR_NBDS,
1660 1);
1661
1662 /* turn on parsing and get a BD */
1663 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1664
1665 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1666 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1667
1668 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1669 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1670
1671 wmb();
1672
1673 fp_tx->tx_db.data.prod += 2;
1674 barrier();
1675 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1676
1677 mmiowb();
1678
1679 num_pkts++;
1680 fp_tx->tx_bd_prod += 2; /* start + pbd */
1681
1682 udelay(100);
1683
1684 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1685 if (tx_idx != tx_start_idx + num_pkts)
1686 goto test_loopback_exit;
1687
1688 /* Unlike HC IGU won't generate an interrupt for status block
1689 * updates that have been performed while interrupts were
1690 * disabled.
1691 */
1692 if (bp->common.int_block == INT_BLOCK_IGU) {
1693 /* Disable local BHes to prevent a dead-lock situation between
1694 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1695 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1696 */
1697 local_bh_disable();
1698 bnx2x_tx_int(fp_tx);
1699 local_bh_enable();
1700 }
1701
1702 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1703 if (rx_idx != rx_start_idx + num_pkts)
1704 goto test_loopback_exit;
1705
1706 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1707 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1708 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1709 goto test_loopback_rx_exit;
1710
1711 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1712 if (len != pkt_size)
1713 goto test_loopback_rx_exit;
1714
1715 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1716 skb = rx_buf->skb;
1717 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1718 for (i = ETH_HLEN; i < pkt_size; i++)
1719 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1720 goto test_loopback_rx_exit;
1721
1722 rc = 0;
1723
1724 test_loopback_rx_exit:
1725
1726 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1727 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1728 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1729 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1730
1731 /* Update producers */
1732 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1733 fp_rx->rx_sge_prod);
1734
1735 test_loopback_exit:
1736 bp->link_params.loopback_mode = LOOPBACK_NONE;
1737
1738 return rc;
1739 }
1740
1741 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1742 {
1743 int rc = 0, res;
1744
1745 if (BP_NOMCP(bp))
1746 return rc;
1747
1748 if (!netif_running(bp->dev))
1749 return BNX2X_LOOPBACK_FAILED;
1750
1751 bnx2x_netif_stop(bp, 1);
1752 bnx2x_acquire_phy_lock(bp);
1753
1754 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1755 if (res) {
1756 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1757 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1758 }
1759
1760 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1761 if (res) {
1762 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1763 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1764 }
1765
1766 bnx2x_release_phy_lock(bp);
1767 bnx2x_netif_start(bp);
1768
1769 return rc;
1770 }
1771
1772 #define CRC32_RESIDUAL 0xdebb20e3
1773
1774 static int bnx2x_test_nvram(struct bnx2x *bp)
1775 {
1776 static const struct {
1777 int offset;
1778 int size;
1779 } nvram_tbl[] = {
1780 { 0, 0x14 }, /* bootstrap */
1781 { 0x14, 0xec }, /* dir */
1782 { 0x100, 0x350 }, /* manuf_info */
1783 { 0x450, 0xf0 }, /* feature_info */
1784 { 0x640, 0x64 }, /* upgrade_key_info */
1785 { 0x6a4, 0x64 },
1786 { 0x708, 0x70 }, /* manuf_key_info */
1787 { 0x778, 0x70 },
1788 { 0, 0 }
1789 };
1790 __be32 buf[0x350 / 4];
1791 u8 *data = (u8 *)buf;
1792 int i, rc;
1793 u32 magic, crc;
1794
1795 if (BP_NOMCP(bp))
1796 return 0;
1797
1798 rc = bnx2x_nvram_read(bp, 0, data, 4);
1799 if (rc) {
1800 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1801 goto test_nvram_exit;
1802 }
1803
1804 magic = be32_to_cpu(buf[0]);
1805 if (magic != 0x669955aa) {
1806 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1807 rc = -ENODEV;
1808 goto test_nvram_exit;
1809 }
1810
1811 for (i = 0; nvram_tbl[i].size; i++) {
1812
1813 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1814 nvram_tbl[i].size);
1815 if (rc) {
1816 DP(NETIF_MSG_PROBE,
1817 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1818 goto test_nvram_exit;
1819 }
1820
1821 crc = ether_crc_le(nvram_tbl[i].size, data);
1822 if (crc != CRC32_RESIDUAL) {
1823 DP(NETIF_MSG_PROBE,
1824 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1825 rc = -ENODEV;
1826 goto test_nvram_exit;
1827 }
1828 }
1829
1830 test_nvram_exit:
1831 return rc;
1832 }
1833
1834 static int bnx2x_test_intr(struct bnx2x *bp)
1835 {
1836 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1837 int i, rc;
1838
1839 if (!netif_running(bp->dev))
1840 return -ENODEV;
1841
1842 config->hdr.length = 0;
1843 if (CHIP_IS_E1(bp))
1844 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1845 else
1846 config->hdr.offset = BP_FUNC(bp);
1847 config->hdr.client_id = bp->fp->cl_id;
1848 config->hdr.reserved1 = 0;
1849
1850 bp->set_mac_pending = 1;
1851 smp_wmb();
1852 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1853 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1854 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1855 if (rc == 0) {
1856 for (i = 0; i < 10; i++) {
1857 if (!bp->set_mac_pending)
1858 break;
1859 smp_rmb();
1860 msleep_interruptible(10);
1861 }
1862 if (i == 10)
1863 rc = -ENODEV;
1864 }
1865
1866 return rc;
1867 }
1868
1869 static void bnx2x_self_test(struct net_device *dev,
1870 struct ethtool_test *etest, u64 *buf)
1871 {
1872 struct bnx2x *bp = netdev_priv(dev);
1873 u8 is_serdes;
1874 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1875 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1876 etest->flags |= ETH_TEST_FL_FAILED;
1877 return;
1878 }
1879
1880 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1881
1882 if (!netif_running(dev))
1883 return;
1884
1885 /* offline tests are not supported in MF mode */
1886 if (IS_MF(bp))
1887 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1888 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1889
1890 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1891 int port = BP_PORT(bp);
1892 u32 val;
1893 u8 link_up;
1894
1895 /* save current value of input enable for TX port IF */
1896 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1897 /* disable input for TX port IF */
1898 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1899
1900 link_up = bp->link_vars.link_up;
1901
1902 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1903 bnx2x_nic_load(bp, LOAD_DIAG);
1904 /* wait until link state is restored */
1905 bnx2x_wait_for_link(bp, link_up, is_serdes);
1906
1907 if (bnx2x_test_registers(bp) != 0) {
1908 buf[0] = 1;
1909 etest->flags |= ETH_TEST_FL_FAILED;
1910 }
1911 if (bnx2x_test_memory(bp) != 0) {
1912 buf[1] = 1;
1913 etest->flags |= ETH_TEST_FL_FAILED;
1914 }
1915
1916 buf[2] = bnx2x_test_loopback(bp, link_up);
1917 if (buf[2] != 0)
1918 etest->flags |= ETH_TEST_FL_FAILED;
1919
1920 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1921
1922 /* restore input for TX port IF */
1923 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1924
1925 bnx2x_nic_load(bp, LOAD_NORMAL);
1926 /* wait until link state is restored */
1927 bnx2x_wait_for_link(bp, link_up, is_serdes);
1928 }
1929 if (bnx2x_test_nvram(bp) != 0) {
1930 buf[3] = 1;
1931 etest->flags |= ETH_TEST_FL_FAILED;
1932 }
1933 if (bnx2x_test_intr(bp) != 0) {
1934 buf[4] = 1;
1935 etest->flags |= ETH_TEST_FL_FAILED;
1936 }
1937 if (bp->port.pmf)
1938 if (bnx2x_link_test(bp, is_serdes) != 0) {
1939 buf[5] = 1;
1940 etest->flags |= ETH_TEST_FL_FAILED;
1941 }
1942
1943 #ifdef BNX2X_EXTRA_DEBUG
1944 bnx2x_panic_dump(bp);
1945 #endif
1946 }
1947
1948 #define IS_PORT_STAT(i) \
1949 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1950 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1951 #define IS_MF_MODE_STAT(bp) \
1952 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1953
1954 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1955 {
1956 struct bnx2x *bp = netdev_priv(dev);
1957 int i, num_stats;
1958
1959 switch (stringset) {
1960 case ETH_SS_STATS:
1961 if (is_multi(bp)) {
1962 num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1963 BNX2X_NUM_Q_STATS;
1964 if (!IS_MF_MODE_STAT(bp))
1965 num_stats += BNX2X_NUM_STATS;
1966 } else {
1967 if (IS_MF_MODE_STAT(bp)) {
1968 num_stats = 0;
1969 for (i = 0; i < BNX2X_NUM_STATS; i++)
1970 if (IS_FUNC_STAT(i))
1971 num_stats++;
1972 } else
1973 num_stats = BNX2X_NUM_STATS;
1974 }
1975 return num_stats;
1976
1977 case ETH_SS_TEST:
1978 return BNX2X_NUM_TESTS;
1979
1980 default:
1981 return -EINVAL;
1982 }
1983 }
1984
1985 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1986 {
1987 struct bnx2x *bp = netdev_priv(dev);
1988 int i, j, k;
1989 char queue_name[MAX_QUEUE_NAME_LEN+1];
1990
1991 switch (stringset) {
1992 case ETH_SS_STATS:
1993 if (is_multi(bp)) {
1994 k = 0;
1995 for_each_napi_queue(bp, i) {
1996 memset(queue_name, 0, sizeof(queue_name));
1997
1998 if (IS_FCOE_IDX(i))
1999 sprintf(queue_name, "fcoe");
2000 else
2001 sprintf(queue_name, "%d", i);
2002
2003 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2004 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2005 ETH_GSTRING_LEN,
2006 bnx2x_q_stats_arr[j].string,
2007 queue_name);
2008 k += BNX2X_NUM_Q_STATS;
2009 }
2010 if (IS_MF_MODE_STAT(bp))
2011 break;
2012 for (j = 0; j < BNX2X_NUM_STATS; j++)
2013 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2014 bnx2x_stats_arr[j].string);
2015 } else {
2016 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2017 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2018 continue;
2019 strcpy(buf + j*ETH_GSTRING_LEN,
2020 bnx2x_stats_arr[i].string);
2021 j++;
2022 }
2023 }
2024 break;
2025
2026 case ETH_SS_TEST:
2027 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2028 break;
2029 }
2030 }
2031
2032 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2033 struct ethtool_stats *stats, u64 *buf)
2034 {
2035 struct bnx2x *bp = netdev_priv(dev);
2036 u32 *hw_stats, *offset;
2037 int i, j, k;
2038
2039 if (is_multi(bp)) {
2040 k = 0;
2041 for_each_napi_queue(bp, i) {
2042 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2043 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2044 if (bnx2x_q_stats_arr[j].size == 0) {
2045 /* skip this counter */
2046 buf[k + j] = 0;
2047 continue;
2048 }
2049 offset = (hw_stats +
2050 bnx2x_q_stats_arr[j].offset);
2051 if (bnx2x_q_stats_arr[j].size == 4) {
2052 /* 4-byte counter */
2053 buf[k + j] = (u64) *offset;
2054 continue;
2055 }
2056 /* 8-byte counter */
2057 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2058 }
2059 k += BNX2X_NUM_Q_STATS;
2060 }
2061 if (IS_MF_MODE_STAT(bp))
2062 return;
2063 hw_stats = (u32 *)&bp->eth_stats;
2064 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2065 if (bnx2x_stats_arr[j].size == 0) {
2066 /* skip this counter */
2067 buf[k + j] = 0;
2068 continue;
2069 }
2070 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2071 if (bnx2x_stats_arr[j].size == 4) {
2072 /* 4-byte counter */
2073 buf[k + j] = (u64) *offset;
2074 continue;
2075 }
2076 /* 8-byte counter */
2077 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2078 }
2079 } else {
2080 hw_stats = (u32 *)&bp->eth_stats;
2081 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2082 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2083 continue;
2084 if (bnx2x_stats_arr[i].size == 0) {
2085 /* skip this counter */
2086 buf[j] = 0;
2087 j++;
2088 continue;
2089 }
2090 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2091 if (bnx2x_stats_arr[i].size == 4) {
2092 /* 4-byte counter */
2093 buf[j] = (u64) *offset;
2094 j++;
2095 continue;
2096 }
2097 /* 8-byte counter */
2098 buf[j] = HILO_U64(*offset, *(offset + 1));
2099 j++;
2100 }
2101 }
2102 }
2103
2104 static int bnx2x_phys_id(struct net_device *dev, u32 data)
2105 {
2106 struct bnx2x *bp = netdev_priv(dev);
2107 int i;
2108
2109 if (!netif_running(dev))
2110 return 0;
2111
2112 if (!bp->port.pmf)
2113 return 0;
2114
2115 if (data == 0)
2116 data = 2;
2117
2118 for (i = 0; i < (data * 2); i++) {
2119 if ((i % 2) == 0)
2120 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2121 LED_MODE_OPER, SPEED_1000);
2122 else
2123 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2124 LED_MODE_OFF, 0);
2125
2126 msleep_interruptible(500);
2127 if (signal_pending(current))
2128 break;
2129 }
2130
2131 if (bp->link_vars.link_up)
2132 bnx2x_set_led(&bp->link_params, &bp->link_vars, LED_MODE_OPER,
2133 bp->link_vars.line_speed);
2134
2135 return 0;
2136 }
2137
2138 static const struct ethtool_ops bnx2x_ethtool_ops = {
2139 .get_settings = bnx2x_get_settings,
2140 .set_settings = bnx2x_set_settings,
2141 .get_drvinfo = bnx2x_get_drvinfo,
2142 .get_regs_len = bnx2x_get_regs_len,
2143 .get_regs = bnx2x_get_regs,
2144 .get_wol = bnx2x_get_wol,
2145 .set_wol = bnx2x_set_wol,
2146 .get_msglevel = bnx2x_get_msglevel,
2147 .set_msglevel = bnx2x_set_msglevel,
2148 .nway_reset = bnx2x_nway_reset,
2149 .get_link = bnx2x_get_link,
2150 .get_eeprom_len = bnx2x_get_eeprom_len,
2151 .get_eeprom = bnx2x_get_eeprom,
2152 .set_eeprom = bnx2x_set_eeprom,
2153 .get_coalesce = bnx2x_get_coalesce,
2154 .set_coalesce = bnx2x_set_coalesce,
2155 .get_ringparam = bnx2x_get_ringparam,
2156 .set_ringparam = bnx2x_set_ringparam,
2157 .get_pauseparam = bnx2x_get_pauseparam,
2158 .set_pauseparam = bnx2x_set_pauseparam,
2159 .get_rx_csum = bnx2x_get_rx_csum,
2160 .set_rx_csum = bnx2x_set_rx_csum,
2161 .get_tx_csum = ethtool_op_get_tx_csum,
2162 .set_tx_csum = ethtool_op_set_tx_hw_csum,
2163 .set_flags = bnx2x_set_flags,
2164 .get_flags = ethtool_op_get_flags,
2165 .get_sg = ethtool_op_get_sg,
2166 .set_sg = ethtool_op_set_sg,
2167 .get_tso = ethtool_op_get_tso,
2168 .set_tso = bnx2x_set_tso,
2169 .self_test = bnx2x_self_test,
2170 .get_sset_count = bnx2x_get_sset_count,
2171 .get_strings = bnx2x_get_strings,
2172 .phys_id = bnx2x_phys_id,
2173 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2174 };
2175
2176 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2177 {
2178 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2179 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree