include/asm-powerpc/pgtable-4k.h

   1 /*
   2  * Entries per page directory level.  The PTE level must use a 64b record
   3  * for each page table entry.  The PMD and PGD level use a 32b record for
   4  * each entry by assuming that each entry is page aligned.
   5  */
   6 #define PTE_INDEX_SIZE  9
   7 #define PMD_INDEX_SIZE  7
   8 #define PUD_INDEX_SIZE  7
   9 #define PGD_INDEX_SIZE  9
  10
  11 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_INDEX_SIZE)
  12 #define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
  13 #define PUD_TABLE_SIZE  (sizeof(pud_t) << PUD_INDEX_SIZE)
  14 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
  15
  16 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
  17 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
  18 #define PTRS_PER_PUD    (1 << PMD_INDEX_SIZE)
  19 #define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
  20
  21 /* PMD_SHIFT determines what a second-level page table entry can map */
  22 #define PMD_SHIFT       (PAGE_SHIFT + PTE_INDEX_SIZE)
  23 #define PMD_SIZE        (1UL << PMD_SHIFT)
  24 #define PMD_MASK        (~(PMD_SIZE-1))
  25
  26 /* With 4k base page size, hugepage PTEs go at the PMD level */
  27 #define MIN_HUGEPTE_SHIFT       PMD_SHIFT
  28
  29 /* PUD_SHIFT determines what a third-level page table entry can map */
  30 #define PUD_SHIFT       (PMD_SHIFT + PMD_INDEX_SIZE)
  31 #define PUD_SIZE        (1UL << PUD_SHIFT)
  32 #define PUD_MASK        (~(PUD_SIZE-1))
  33
  34 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
  35 #define PGDIR_SHIFT     (PUD_SHIFT + PUD_INDEX_SIZE)
  36 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  37 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  38
  39 /* PTE bits */
  40 #define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
  41 #define _PAGE_GROUP_IX  0x7000 /* software: HPTE index within group */
  42 #define _PAGE_F_SECOND  _PAGE_SECONDARY
  43 #define _PAGE_F_GIX     _PAGE_GROUP_IX
  44
  45 /* PTE flags to conserve for HPTE identification */
  46 #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
  47                          _PAGE_SECONDARY | _PAGE_GROUP_IX)
  48
  49 /* PAGE_MASK gives the right answer below, but only by accident */
  50 /* It should be preserving the high 48 bits and then specifically */
  51 /* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
  52 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
  53                          _PAGE_HPTEFLAGS)
  54
  55 /* Bits to mask out from a PMD to get to the PTE page */
  56 #define PMD_MASKED_BITS         0
  57 /* Bits to mask out from a PUD to get to the PMD page */
  58 #define PUD_MASKED_BITS         0
  59 /* Bits to mask out from a PGD to get to the PUD page */
  60 #define PGD_MASKED_BITS         0
  61
  62 /* shift to put page number into pte */
  63 #define PTE_RPN_SHIFT   (17)
  64
  65 #define __real_pte(e,p)         ((real_pte_t)(e))
  66 #define __rpte_to_pte(r)        (r)
  67 #define __rpte_to_hidx(r,index) (pte_val((r)) >> 12)
  68
  69 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)       \
  70         do {                                                             \
  71                 index = 0;                                               \
  72                 shift = mmu_psize_defs[psize].shift;                     \
  73
  74 #define pte_iterate_hashed_end() } while(0)
  75
  76 /*
  77  * 4-level page tables related bits
  78  */
  79
  80 #define pgd_none(pgd)           (!pgd_val(pgd))
  81 #define pgd_bad(pgd)            (pgd_val(pgd) == 0)
  82 #define pgd_present(pgd)        (pgd_val(pgd) != 0)
  83 #define pgd_clear(pgdp)         (pgd_val(*(pgdp)) = 0)
  84 #define pgd_page(pgd)           (pgd_val(pgd) & ~PGD_MASKED_BITS)
  85
  86 #define pud_offset(pgdp, addr)  \
  87   (((pud_t *) pgd_page(*(pgdp))) + \
  88     (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
  89
  90 #define pud_ERROR(e) \
  91         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pud_val(e))