arch/powerpc/sysdev/cpm2_pic.c

   1 /*
   2  * Platform information definitions.
   3  *
   4  * Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
   5  * to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
   6  *
   7  * Author:  Vitaly Bordug <vbordug@ru.mvista.com>
   8  *
   9  * 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
  10  * 2006 (c) MontaVista Software, Inc.
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2. This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /* The CPM2 internal interrupt controller.  It is usually
  18  * the only interrupt controller.
  19  * There are two 32-bit registers (high/low) for up to 64
  20  * possible interrupts.
  21  *
  22  * Now, the fun starts.....Interrupt Numbers DO NOT MAP
  23  * in a simple arithmetic fashion to mask or pending registers.
  24  * That is, interrupt 4 does not map to bit position 4.
  25  * We create two tables, indexed by vector number, to indicate
  26  * which register to use and which bit in the register to use.
  27  */
  28
  29 #include <linux/stddef.h>
  30 #include <linux/init.h>
  31 #include <linux/sched.h>
  32 #include <linux/signal.h>
  33 #include <linux/irq.h>
  34
  35 #include <asm/immap_cpm2.h>
  36 #include <asm/mpc8260.h>
  37 #include <asm/io.h>
  38 #include <asm/prom.h>
  39 #include <asm/fs_pd.h>
  40
  41 #include "cpm2_pic.h"
  42
  43 /* External IRQS */
  44 #define CPM2_IRQ_EXT1           19
  45 #define CPM2_IRQ_EXT7           25
  46
  47 /* Port C IRQS */
  48 #define CPM2_IRQ_PORTC15        48
  49 #define CPM2_IRQ_PORTC0         63
  50
  51 static intctl_cpm2_t *cpm2_intctl;
  52
  53 static struct device_node *cpm2_pic_node;
  54 static struct irq_host *cpm2_pic_host;
  55 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
  56 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  57
  58 static const u_char irq_to_siureg[] = {
  59         1, 1, 1, 1, 1, 1, 1, 1,
  60         1, 1, 1, 1, 1, 1, 1, 1,
  61         0, 0, 0, 0, 0, 0, 0, 0,
  62         0, 0, 0, 0, 0, 0, 0, 0,
  63         1, 1, 1, 1, 1, 1, 1, 1,
  64         1, 1, 1, 1, 1, 1, 1, 1,
  65         0, 0, 0, 0, 0, 0, 0, 0,
  66         0, 0, 0, 0, 0, 0, 0, 0
  67 };
  68
  69 /* bit numbers do not match the docs, these are precomputed so the bit for
  70  * a given irq is (1 << irq_to_siubit[irq]) */
  71 static const u_char irq_to_siubit[] = {
  72          0, 15, 14, 13, 12, 11, 10,  9,
  73          8,  7,  6,  5,  4,  3,  2,  1,
  74          2,  1,  0, 14, 13, 12, 11, 10,
  75          9,  8,  7,  6,  5,  4,  3,  0,
  76         31, 30, 29, 28, 27, 26, 25, 24,
  77         23, 22, 21, 20, 19, 18, 17, 16,
  78         16, 17, 18, 19, 20, 21, 22, 23,
  79         24, 25, 26, 27, 28, 29, 30, 31,
  80 };
  81
  82 static void cpm2_mask_irq(unsigned int virq)
  83 {
  84         int     bit, word;
  85         unsigned int irq_nr = virq_to_hw(virq);
  86
  87         bit = irq_to_siubit[irq_nr];
  88         word = irq_to_siureg[irq_nr];
  89
  90         ppc_cached_irq_mask[word] &= ~(1 << bit);
  91         out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
  92 }
  93
  94 static void cpm2_unmask_irq(unsigned int virq)
  95 {
  96         int     bit, word;
  97         unsigned int irq_nr = virq_to_hw(virq);
  98
  99         bit = irq_to_siubit[irq_nr];
 100         word = irq_to_siureg[irq_nr];
 101
 102         ppc_cached_irq_mask[word] |= 1 << bit;
 103         out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
 104 }
 105
 106 static void cpm2_ack(unsigned int virq)
 107 {
 108         int     bit, word;
 109         unsigned int irq_nr = virq_to_hw(virq);
 110
 111         bit = irq_to_siubit[irq_nr];
 112         word = irq_to_siureg[irq_nr];
 113
 114         out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
 115 }
 116
 117 static void cpm2_end_irq(unsigned int virq)
 118 {
 119         int     bit, word;
 120         unsigned int irq_nr = virq_to_hw(virq);
 121
 122         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 123                         && irq_desc[irq_nr].action) {
 124
 125                 bit = irq_to_siubit[irq_nr];
 126                 word = irq_to_siureg[irq_nr];
 127
 128                 ppc_cached_irq_mask[word] |= 1 << bit;
 129                 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
 130
 131                 /*
 132                  * Work around large numbers of spurious IRQs on PowerPC 82xx
 133                  * systems.
 134                  */
 135                 mb();
 136         }
 137 }
 138
 139 static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
 140 {
 141         unsigned int src = virq_to_hw(virq);
 142         struct irq_desc *desc = get_irq_desc(virq);
 143         unsigned int vold, vnew, edibit;
 144
 145         if (flow_type == IRQ_TYPE_NONE)
 146                 flow_type = IRQ_TYPE_LEVEL_LOW;
 147
 148         if (flow_type & IRQ_TYPE_EDGE_RISING) {
 149                 printk(KERN_ERR "CPM2 PIC: sense type 0x%x not supported\n",
 150                         flow_type);
 151                 return -EINVAL;
 152         }
 153
 154         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 155         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 156         if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
 157                 desc->status |= IRQ_LEVEL;
 158                 desc->handle_irq = handle_level_irq;
 159         } else
 160                 desc->handle_irq = handle_edge_irq;
 161
 162         /* internal IRQ senses are LEVEL_LOW
 163          * EXT IRQ and Port C IRQ senses are programmable
 164          */
 165         if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7)
 166                         edibit = (14 - (src - CPM2_IRQ_EXT1));
 167         else
 168                 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
 169                         edibit = (31 - (src - CPM2_IRQ_PORTC15));
 170                 else
 171                         return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
 172
 173         vold = in_be32(&cpm2_intctl->ic_siexr);
 174
 175         if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING)
 176                 vnew = vold | (1 << edibit);
 177         else
 178                 vnew = vold & ~(1 << edibit);
 179
 180         if (vold != vnew)
 181                 out_be32(&cpm2_intctl->ic_siexr, vnew);
 182         return 0;
 183 }
 184
 185 static struct irq_chip cpm2_pic = {
 186         .typename = " CPM2 SIU ",
 187         .mask = cpm2_mask_irq,
 188         .unmask = cpm2_unmask_irq,
 189         .ack = cpm2_ack,
 190         .eoi = cpm2_end_irq,
 191         .set_type = cpm2_set_irq_type,
 192 };
 193
 194 unsigned int cpm2_get_irq(void)
 195 {
 196         int irq;
 197         unsigned long bits;
 198
 199        /* For CPM2, read the SIVEC register and shift the bits down
 200          * to get the irq number.         */
 201         bits = in_be32(&cpm2_intctl->ic_sivec);
 202         irq = bits >> 26;
 203
 204         if (irq == 0)
 205                 return(-1);
 206         return irq_linear_revmap(cpm2_pic_host, irq);
 207 }
 208
 209 static int cpm2_pic_host_match(struct irq_host *h, struct device_node *node)
 210 {
 211         return cpm2_pic_node == node;
 212 }
 213
 214 static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
 215                           irq_hw_number_t hw)
 216 {
 217         pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
 218
 219         get_irq_desc(virq)->status |= IRQ_LEVEL;
 220         set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
 221         return 0;
 222 }
 223
 224 static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
 225                             u32 *intspec, unsigned int intsize,
 226                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 227 {
 228         *out_hwirq = intspec[0];
 229         if (intsize > 1)
 230                 *out_flags = intspec[1];
 231         else
 232                 *out_flags = IRQ_TYPE_NONE;
 233         return 0;
 234 }
 235
 236 static struct irq_host_ops cpm2_pic_host_ops = {
 237         .match = cpm2_pic_host_match,
 238         .map = cpm2_pic_host_map,
 239         .xlate = cpm2_pic_host_xlate,
 240 };
 241
 242 void cpm2_pic_init(struct device_node *node)
 243 {
 244         int i;
 245
 246         cpm2_intctl = cpm2_map(im_intctl);
 247
 248         /* Clear the CPM IRQ controller, in case it has any bits set
 249          * from the bootloader
 250          */
 251
 252         /* Mask out everything */
 253
 254         out_be32(&cpm2_intctl->ic_simrh, 0x00000000);
 255         out_be32(&cpm2_intctl->ic_simrl, 0x00000000);
 256
 257         wmb();
 258
 259         /* Ack everything */
 260         out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff);
 261         out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff);
 262         wmb();
 263
 264         /* Dummy read of the vector */
 265         i = in_be32(&cpm2_intctl->ic_sivec);
 266         rmb();
 267
 268         /* Initialize the default interrupt mapping priorities,
 269          * in case the boot rom changed something on us.
 270          */
 271         out_be16(&cpm2_intctl->ic_sicr, 0);
 272         out_be32(&cpm2_intctl->ic_scprrh, 0x05309770);
 273         out_be32(&cpm2_intctl->ic_scprrl, 0x05309770);
 274
 275         /* create a legacy host */
 276         cpm2_pic_node = of_node_get(node);
 277         cpm2_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm2_pic_host_ops, 64);
 278         if (cpm2_pic_host == NULL) {
 279                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 280                 return;
 281         }
 282 }