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e1000e: 82577/82578 requires a different method to configure LPLU
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e1000e / ich8lan.c
blob2451dc8aef70df1c6cbd8e4a8ec7e9f07f14ebbd
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 */
56
57 #include <linux/netdevice.h>
58 #include <linux/ethtool.h>
59 #include <linux/delay.h>
60 #include <linux/pci.h>
61
62 #include "e1000.h"
63
64 #define ICH_FLASH_GFPREG 0x0000
65 #define ICH_FLASH_HSFSTS 0x0004
66 #define ICH_FLASH_HSFCTL 0x0006
67 #define ICH_FLASH_FADDR 0x0008
68 #define ICH_FLASH_FDATA0 0x0010
69 #define ICH_FLASH_PR0 0x0074
70
71 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
74 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
75 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
76
77 #define ICH_CYCLE_READ 0
78 #define ICH_CYCLE_WRITE 2
79 #define ICH_CYCLE_ERASE 3
80
81 #define FLASH_GFPREG_BASE_MASK 0x1FFF
82 #define FLASH_SECTOR_ADDR_SHIFT 12
83
84 #define ICH_FLASH_SEG_SIZE_256 256
85 #define ICH_FLASH_SEG_SIZE_4K 4096
86 #define ICH_FLASH_SEG_SIZE_8K 8192
87 #define ICH_FLASH_SEG_SIZE_64K 65536
88
89
90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
91
92 #define E1000_ICH_MNG_IAMT_MODE 0x2
93
94 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
95 (ID_LED_DEF1_OFF2 << 8) | \
96 (ID_LED_DEF1_ON2 << 4) | \
97 (ID_LED_DEF1_DEF2))
98
99 #define E1000_ICH_NVM_SIG_WORD 0x13
100 #define E1000_ICH_NVM_SIG_MASK 0xC000
101 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
102 #define E1000_ICH_NVM_SIG_VALUE 0x80
103
104 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105
106 #define E1000_FEXTNVM_SW_CONFIG 1
107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
108
109 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
110
111 #define E1000_ICH_RAR_ENTRIES 7
112
113 #define PHY_PAGE_SHIFT 5
114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
115 ((reg) & MAX_PHY_REG_ADDRESS))
116 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
117 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
118
119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
121 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
122
123 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
124
125 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
126
127 /* OEM Bits Phy Register */
128 #define HV_OEM_BITS PHY_REG(768, 25)
129 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
130 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
131
132 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
133 /* Offset 04h HSFSTS */
134 union ich8_hws_flash_status {
135 struct ich8_hsfsts {
136 u16 flcdone :1; /* bit 0 Flash Cycle Done */
137 u16 flcerr :1; /* bit 1 Flash Cycle Error */
138 u16 dael :1; /* bit 2 Direct Access error Log */
139 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
140 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
141 u16 reserved1 :2; /* bit 13:6 Reserved */
142 u16 reserved2 :6; /* bit 13:6 Reserved */
143 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
144 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
145 } hsf_status;
146 u16 regval;
147 };
148
149 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
150 /* Offset 06h FLCTL */
151 union ich8_hws_flash_ctrl {
152 struct ich8_hsflctl {
153 u16 flcgo :1; /* 0 Flash Cycle Go */
154 u16 flcycle :2; /* 2:1 Flash Cycle */
155 u16 reserved :5; /* 7:3 Reserved */
156 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
157 u16 flockdn :6; /* 15:10 Reserved */
158 } hsf_ctrl;
159 u16 regval;
160 };
161
162 /* ICH Flash Region Access Permissions */
163 union ich8_hws_flash_regacc {
164 struct ich8_flracc {
165 u32 grra :8; /* 0:7 GbE region Read Access */
166 u32 grwa :8; /* 8:15 GbE region Write Access */
167 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
168 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
169 } hsf_flregacc;
170 u16 regval;
171 };
172
173 /* ICH Flash Protected Region */
174 union ich8_flash_protected_range {
175 struct ich8_pr {
176 u32 base:13; /* 0:12 Protected Range Base */
177 u32 reserved1:2; /* 13:14 Reserved */
178 u32 rpe:1; /* 15 Read Protection Enable */
179 u32 limit:13; /* 16:28 Protected Range Limit */
180 u32 reserved2:2; /* 29:30 Reserved */
181 u32 wpe:1; /* 31 Write Protection Enable */
182 } range;
183 u32 regval;
184 };
185
186 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
187 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
188 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
189 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
190 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
191 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
192 u32 offset, u8 byte);
193 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
194 u8 *data);
195 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
196 u16 *data);
197 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
198 u8 size, u16 *data);
199 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
200 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
201 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
202 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
203 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
204 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
205 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
206 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
207 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
208 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
209 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
210 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
211
212 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
213 {
214 return readw(hw->flash_address + reg);
215 }
216
217 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
218 {
219 return readl(hw->flash_address + reg);
220 }
221
222 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
223 {
224 writew(val, hw->flash_address + reg);
225 }
226
227 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
228 {
229 writel(val, hw->flash_address + reg);
230 }
231
232 #define er16flash(reg) __er16flash(hw, (reg))
233 #define er32flash(reg) __er32flash(hw, (reg))
234 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
235 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
236
237 /**
238 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
239 * @hw: pointer to the HW structure
240 *
241 * Initialize family-specific PHY parameters and function pointers.
242 **/
243 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
244 {
245 struct e1000_phy_info *phy = &hw->phy;
246 s32 ret_val = 0;
247
248 phy->addr = 1;
249 phy->reset_delay_us = 100;
250
251 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
252 phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
253 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
254 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
255 phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
256 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
257
258 phy->id = e1000_phy_unknown;
259 e1000e_get_phy_id(hw);
260 phy->type = e1000e_get_phy_type_from_id(phy->id);
261
262 if (phy->type == e1000_phy_82577) {
263 phy->ops.check_polarity = e1000_check_polarity_82577;
264 phy->ops.force_speed_duplex =
265 e1000_phy_force_speed_duplex_82577;
266 phy->ops.get_cable_length = e1000_get_cable_length_82577;
267 phy->ops.get_phy_info = e1000_get_phy_info_82577;
268 phy->ops.commit_phy = e1000e_phy_sw_reset;
269 }
270
271 return ret_val;
272 }
273
274 /**
275 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
276 * @hw: pointer to the HW structure
277 *
278 * Initialize family-specific PHY parameters and function pointers.
279 **/
280 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
281 {
282 struct e1000_phy_info *phy = &hw->phy;
283 s32 ret_val;
284 u16 i = 0;
285
286 phy->addr = 1;
287 phy->reset_delay_us = 100;
288
289 /*
290 * We may need to do this twice - once for IGP and if that fails,
291 * we'll set BM func pointers and try again
292 */
293 ret_val = e1000e_determine_phy_address(hw);
294 if (ret_val) {
295 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
296 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
297 ret_val = e1000e_determine_phy_address(hw);
298 if (ret_val)
299 return ret_val;
300 }
301
302 phy->id = 0;
303 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
304 (i++ < 100)) {
305 msleep(1);
306 ret_val = e1000e_get_phy_id(hw);
307 if (ret_val)
308 return ret_val;
309 }
310
311 /* Verify phy id */
312 switch (phy->id) {
313 case IGP03E1000_E_PHY_ID:
314 phy->type = e1000_phy_igp_3;
315 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
316 break;
317 case IFE_E_PHY_ID:
318 case IFE_PLUS_E_PHY_ID:
319 case IFE_C_E_PHY_ID:
320 phy->type = e1000_phy_ife;
321 phy->autoneg_mask = E1000_ALL_NOT_GIG;
322 break;
323 case BME1000_E_PHY_ID:
324 phy->type = e1000_phy_bm;
325 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
326 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
327 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
328 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
329 break;
330 default:
331 return -E1000_ERR_PHY;
332 break;
333 }
334
335 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
336
337 return 0;
338 }
339
340 /**
341 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
342 * @hw: pointer to the HW structure
343 *
344 * Initialize family-specific NVM parameters and function
345 * pointers.
346 **/
347 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
348 {
349 struct e1000_nvm_info *nvm = &hw->nvm;
350 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
351 u32 gfpreg, sector_base_addr, sector_end_addr;
352 u16 i;
353
354 /* Can't read flash registers if the register set isn't mapped. */
355 if (!hw->flash_address) {
356 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
357 return -E1000_ERR_CONFIG;
358 }
359
360 nvm->type = e1000_nvm_flash_sw;
361
362 gfpreg = er32flash(ICH_FLASH_GFPREG);
363
364 /*
365 * sector_X_addr is a "sector"-aligned address (4096 bytes)
366 * Add 1 to sector_end_addr since this sector is included in
367 * the overall size.
368 */
369 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
370 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
371
372 /* flash_base_addr is byte-aligned */
373 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
374
375 /*
376 * find total size of the NVM, then cut in half since the total
377 * size represents two separate NVM banks.
378 */
379 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
380 << FLASH_SECTOR_ADDR_SHIFT;
381 nvm->flash_bank_size /= 2;
382 /* Adjust to word count */
383 nvm->flash_bank_size /= sizeof(u16);
384
385 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
386
387 /* Clear shadow ram */
388 for (i = 0; i < nvm->word_size; i++) {
389 dev_spec->shadow_ram[i].modified = 0;
390 dev_spec->shadow_ram[i].value = 0xFFFF;
391 }
392
393 return 0;
394 }
395
396 /**
397 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
398 * @hw: pointer to the HW structure
399 *
400 * Initialize family-specific MAC parameters and function
401 * pointers.
402 **/
403 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
404 {
405 struct e1000_hw *hw = &adapter->hw;
406 struct e1000_mac_info *mac = &hw->mac;
407
408 /* Set media type function pointer */
409 hw->phy.media_type = e1000_media_type_copper;
410
411 /* Set mta register count */
412 mac->mta_reg_count = 32;
413 /* Set rar entry count */
414 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
415 if (mac->type == e1000_ich8lan)
416 mac->rar_entry_count--;
417 /* Set if manageability features are enabled. */
418 mac->arc_subsystem_valid = 1;
419
420 /* LED operations */
421 switch (mac->type) {
422 case e1000_ich8lan:
423 case e1000_ich9lan:
424 case e1000_ich10lan:
425 /* ID LED init */
426 mac->ops.id_led_init = e1000e_id_led_init;
427 /* setup LED */
428 mac->ops.setup_led = e1000e_setup_led_generic;
429 /* cleanup LED */
430 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
431 /* turn on/off LED */
432 mac->ops.led_on = e1000_led_on_ich8lan;
433 mac->ops.led_off = e1000_led_off_ich8lan;
434 break;
435 case e1000_pchlan:
436 /* ID LED init */
437 mac->ops.id_led_init = e1000_id_led_init_pchlan;
438 /* setup LED */
439 mac->ops.setup_led = e1000_setup_led_pchlan;
440 /* cleanup LED */
441 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
442 /* turn on/off LED */
443 mac->ops.led_on = e1000_led_on_pchlan;
444 mac->ops.led_off = e1000_led_off_pchlan;
445 break;
446 default:
447 break;
448 }
449
450 /* Enable PCS Lock-loss workaround for ICH8 */
451 if (mac->type == e1000_ich8lan)
452 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
453
454 return 0;
455 }
456
457 /**
458 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
459 * @hw: pointer to the HW structure
460 *
461 * Checks to see of the link status of the hardware has changed. If a
462 * change in link status has been detected, then we read the PHY registers
463 * to get the current speed/duplex if link exists.
464 **/
465 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
466 {
467 struct e1000_mac_info *mac = &hw->mac;
468 s32 ret_val;
469 bool link;
470
471 /*
472 * We only want to go out to the PHY registers to see if Auto-Neg
473 * has completed and/or if our link status has changed. The
474 * get_link_status flag is set upon receiving a Link Status
475 * Change or Rx Sequence Error interrupt.
476 */
477 if (!mac->get_link_status) {
478 ret_val = 0;
479 goto out;
480 }
481
482 if (hw->mac.type == e1000_pchlan) {
483 ret_val = e1000e_write_kmrn_reg(hw,
484 E1000_KMRNCTRLSTA_K1_CONFIG,
485 E1000_KMRNCTRLSTA_K1_ENABLE);
486 if (ret_val)
487 goto out;
488 }
489
490 /*
491 * First we want to see if the MII Status Register reports
492 * link. If so, then we want to get the current speed/duplex
493 * of the PHY.
494 */
495 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
496 if (ret_val)
497 goto out;
498
499 if (!link)
500 goto out; /* No link detected */
501
502 mac->get_link_status = false;
503
504 if (hw->phy.type == e1000_phy_82578) {
505 ret_val = e1000_link_stall_workaround_hv(hw);
506 if (ret_val)
507 goto out;
508 }
509
510 /*
511 * Check if there was DownShift, must be checked
512 * immediately after link-up
513 */
514 e1000e_check_downshift(hw);
515
516 /*
517 * If we are forcing speed/duplex, then we simply return since
518 * we have already determined whether we have link or not.
519 */
520 if (!mac->autoneg) {
521 ret_val = -E1000_ERR_CONFIG;
522 goto out;
523 }
524
525 /*
526 * Auto-Neg is enabled. Auto Speed Detection takes care
527 * of MAC speed/duplex configuration. So we only need to
528 * configure Collision Distance in the MAC.
529 */
530 e1000e_config_collision_dist(hw);
531
532 /*
533 * Configure Flow Control now that Auto-Neg has completed.
534 * First, we need to restore the desired flow control
535 * settings because we may have had to re-autoneg with a
536 * different link partner.
537 */
538 ret_val = e1000e_config_fc_after_link_up(hw);
539 if (ret_val)
540 hw_dbg(hw, "Error configuring flow control\n");
541
542 out:
543 return ret_val;
544 }
545
546 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
547 {
548 struct e1000_hw *hw = &adapter->hw;
549 s32 rc;
550
551 rc = e1000_init_mac_params_ich8lan(adapter);
552 if (rc)
553 return rc;
554
555 rc = e1000_init_nvm_params_ich8lan(hw);
556 if (rc)
557 return rc;
558
559 if (hw->mac.type == e1000_pchlan)
560 rc = e1000_init_phy_params_pchlan(hw);
561 else
562 rc = e1000_init_phy_params_ich8lan(hw);
563 if (rc)
564 return rc;
565
566 if (adapter->hw.phy.type == e1000_phy_ife) {
567 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
568 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
569 }
570
571 if ((adapter->hw.mac.type == e1000_ich8lan) &&
572 (adapter->hw.phy.type == e1000_phy_igp_3))
573 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
574
575 return 0;
576 }
577
578 static DEFINE_MUTEX(nvm_mutex);
579
580 /**
581 * e1000_acquire_swflag_ich8lan - Acquire software control flag
582 * @hw: pointer to the HW structure
583 *
584 * Acquires the software control flag for performing NVM and PHY
585 * operations. This is a function pointer entry point only called by
586 * read/write routines for the PHY and NVM parts.
587 **/
588 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
589 {
590 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
591 s32 ret_val = 0;
592
593 might_sleep();
594
595 mutex_lock(&nvm_mutex);
596
597 while (timeout) {
598 extcnf_ctrl = er32(EXTCNF_CTRL);
599 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
600 break;
601
602 mdelay(1);
603 timeout--;
604 }
605
606 if (!timeout) {
607 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
608 ret_val = -E1000_ERR_CONFIG;
609 goto out;
610 }
611
612 timeout = SW_FLAG_TIMEOUT;
613
614 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
615 ew32(EXTCNF_CTRL, extcnf_ctrl);
616
617 while (timeout) {
618 extcnf_ctrl = er32(EXTCNF_CTRL);
619 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
620 break;
621
622 mdelay(1);
623 timeout--;
624 }
625
626 if (!timeout) {
627 hw_dbg(hw, "Failed to acquire the semaphore.\n");
628 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
629 ew32(EXTCNF_CTRL, extcnf_ctrl);
630 ret_val = -E1000_ERR_CONFIG;
631 goto out;
632 }
633
634 out:
635 if (ret_val)
636 mutex_unlock(&nvm_mutex);
637
638 return ret_val;
639 }
640
641 /**
642 * e1000_release_swflag_ich8lan - Release software control flag
643 * @hw: pointer to the HW structure
644 *
645 * Releases the software control flag for performing NVM and PHY operations.
646 * This is a function pointer entry point only called by read/write
647 * routines for the PHY and NVM parts.
648 **/
649 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
650 {
651 u32 extcnf_ctrl;
652
653 extcnf_ctrl = er32(EXTCNF_CTRL);
654 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
655 ew32(EXTCNF_CTRL, extcnf_ctrl);
656
657 mutex_unlock(&nvm_mutex);
658 }
659
660 /**
661 * e1000_check_mng_mode_ich8lan - Checks management mode
662 * @hw: pointer to the HW structure
663 *
664 * This checks if the adapter has manageability enabled.
665 * This is a function pointer entry point only called by read/write
666 * routines for the PHY and NVM parts.
667 **/
668 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
669 {
670 u32 fwsm = er32(FWSM);
671
672 return (fwsm & E1000_FWSM_MODE_MASK) ==
673 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
674 }
675
676 /**
677 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
678 * @hw: pointer to the HW structure
679 *
680 * Checks if firmware is blocking the reset of the PHY.
681 * This is a function pointer entry point only called by
682 * reset routines.
683 **/
684 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
685 {
686 u32 fwsm;
687
688 fwsm = er32(FWSM);
689
690 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
691 }
692
693 /**
694 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
695 * @hw: pointer to the HW structure
696 *
697 * Forces the speed and duplex settings of the PHY.
698 * This is a function pointer entry point only called by
699 * PHY setup routines.
700 **/
701 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
702 {
703 struct e1000_phy_info *phy = &hw->phy;
704 s32 ret_val;
705 u16 data;
706 bool link;
707
708 if (phy->type != e1000_phy_ife) {
709 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
710 return ret_val;
711 }
712
713 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
714 if (ret_val)
715 return ret_val;
716
717 e1000e_phy_force_speed_duplex_setup(hw, &data);
718
719 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
720 if (ret_val)
721 return ret_val;
722
723 /* Disable MDI-X support for 10/100 */
724 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
725 if (ret_val)
726 return ret_val;
727
728 data &= ~IFE_PMC_AUTO_MDIX;
729 data &= ~IFE_PMC_FORCE_MDIX;
730
731 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
732 if (ret_val)
733 return ret_val;
734
735 hw_dbg(hw, "IFE PMC: %X\n", data);
736
737 udelay(1);
738
739 if (phy->autoneg_wait_to_complete) {
740 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
741
742 ret_val = e1000e_phy_has_link_generic(hw,
743 PHY_FORCE_LIMIT,
744 100000,
745 &link);
746 if (ret_val)
747 return ret_val;
748
749 if (!link)
750 hw_dbg(hw, "Link taking longer than expected.\n");
751
752 /* Try once more */
753 ret_val = e1000e_phy_has_link_generic(hw,
754 PHY_FORCE_LIMIT,
755 100000,
756 &link);
757 if (ret_val)
758 return ret_val;
759 }
760
761 return 0;
762 }
763
764 /**
765 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
766 * done after every PHY reset.
767 **/
768 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
769 {
770 s32 ret_val = 0;
771
772 if (hw->mac.type != e1000_pchlan)
773 return ret_val;
774
775 if (((hw->phy.type == e1000_phy_82577) &&
776 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
777 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
778 /* Disable generation of early preamble */
779 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
780 if (ret_val)
781 return ret_val;
782
783 /* Preamble tuning for SSC */
784 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
785 if (ret_val)
786 return ret_val;
787 }
788
789 if (hw->phy.type == e1000_phy_82578) {
790 /*
791 * Return registers to default by doing a soft reset then
792 * writing 0x3140 to the control register.
793 */
794 if (hw->phy.revision < 2) {
795 e1000e_phy_sw_reset(hw);
796 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
797 }
798 }
799
800 /* Select page 0 */
801 ret_val = hw->phy.ops.acquire_phy(hw);
802 if (ret_val)
803 return ret_val;
804 hw->phy.addr = 1;
805 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
806 hw->phy.ops.release_phy(hw);
807
808 return ret_val;
809 }
810
811 /**
812 * e1000_lan_init_done_ich8lan - Check for PHY config completion
813 * @hw: pointer to the HW structure
814 *
815 * Check the appropriate indication the MAC has finished configuring the
816 * PHY after a software reset.
817 **/
818 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
819 {
820 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
821
822 /* Wait for basic configuration completes before proceeding */
823 do {
824 data = er32(STATUS);
825 data &= E1000_STATUS_LAN_INIT_DONE;
826 udelay(100);
827 } while ((!data) && --loop);
828
829 /*
830 * If basic configuration is incomplete before the above loop
831 * count reaches 0, loading the configuration from NVM will
832 * leave the PHY in a bad state possibly resulting in no link.
833 */
834 if (loop == 0)
835 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
836
837 /* Clear the Init Done bit for the next init event */
838 data = er32(STATUS);
839 data &= ~E1000_STATUS_LAN_INIT_DONE;
840 ew32(STATUS, data);
841 }
842
843 /**
844 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
845 * @hw: pointer to the HW structure
846 *
847 * Resets the PHY
848 * This is a function pointer entry point called by drivers
849 * or other shared routines.
850 **/
851 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
852 {
853 struct e1000_phy_info *phy = &hw->phy;
854 u32 i;
855 u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
856 s32 ret_val;
857 u16 reg, word_addr, reg_data, reg_addr, phy_page = 0;
858
859 ret_val = e1000e_phy_hw_reset_generic(hw);
860 if (ret_val)
861 return ret_val;
862
863 /* Allow time for h/w to get to a quiescent state after reset */
864 mdelay(10);
865
866 if (hw->mac.type == e1000_pchlan) {
867 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
868 if (ret_val)
869 return ret_val;
870 }
871
872 /* Dummy read to clear the phy wakeup bit after lcd reset */
873 if (hw->mac.type == e1000_pchlan)
874 e1e_rphy(hw, BM_WUC, &reg);
875
876 /*
877 * Initialize the PHY from the NVM on ICH platforms. This
878 * is needed due to an issue where the NVM configuration is
879 * not properly autoloaded after power transitions.
880 * Therefore, after each PHY reset, we will load the
881 * configuration data out of the NVM manually.
882 */
883 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
884 struct e1000_adapter *adapter = hw->adapter;
885
886 /* Check if SW needs configure the PHY */
887 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
888 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
889 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
890 else
891 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
892
893 data = er32(FEXTNVM);
894 if (!(data & sw_cfg_mask))
895 return 0;
896
897 /* Wait for basic configuration completes before proceeding */
898 e1000_lan_init_done_ich8lan(hw);
899
900 /*
901 * Make sure HW does not configure LCD from PHY
902 * extended configuration before SW configuration
903 */
904 data = er32(EXTCNF_CTRL);
905 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
906 return 0;
907
908 cnf_size = er32(EXTCNF_SIZE);
909 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
910 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
911 if (!cnf_size)
912 return 0;
913
914 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
915 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
916
917 /* Configure LCD from extended configuration region. */
918
919 /* cnf_base_addr is in DWORD */
920 word_addr = (u16)(cnf_base_addr << 1);
921
922 for (i = 0; i < cnf_size; i++) {
923 ret_val = e1000_read_nvm(hw,
924 (word_addr + i * 2),
925 1,
926 &reg_data);
927 if (ret_val)
928 return ret_val;
929
930 ret_val = e1000_read_nvm(hw,
931 (word_addr + i * 2 + 1),
932 1,
933 &reg_addr);
934 if (ret_val)
935 return ret_val;
936
937 /* Save off the PHY page for future writes. */
938 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
939 phy_page = reg_data;
940 continue;
941 }
942
943 reg_addr |= phy_page;
944
945 ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
946 if (ret_val)
947 return ret_val;
948 }
949 }
950
951 return 0;
952 }
953
954 /**
955 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
956 * @hw: pointer to the HW structure
957 *
958 * Populates "phy" structure with various feature states.
959 * This function is only called by other family-specific
960 * routines.
961 **/
962 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
963 {
964 struct e1000_phy_info *phy = &hw->phy;
965 s32 ret_val;
966 u16 data;
967 bool link;
968
969 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
970 if (ret_val)
971 return ret_val;
972
973 if (!link) {
974 hw_dbg(hw, "Phy info is only valid if link is up\n");
975 return -E1000_ERR_CONFIG;
976 }
977
978 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
979 if (ret_val)
980 return ret_val;
981 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
982
983 if (phy->polarity_correction) {
984 ret_val = phy->ops.check_polarity(hw);
985 if (ret_val)
986 return ret_val;
987 } else {
988 /* Polarity is forced */
989 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
990 ? e1000_rev_polarity_reversed
991 : e1000_rev_polarity_normal;
992 }
993
994 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
995 if (ret_val)
996 return ret_val;
997
998 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
999
1000 /* The following parameters are undefined for 10/100 operation. */
1001 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1002 phy->local_rx = e1000_1000t_rx_status_undefined;
1003 phy->remote_rx = e1000_1000t_rx_status_undefined;
1004
1005 return 0;
1006 }
1007
1008 /**
1009 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1010 * @hw: pointer to the HW structure
1011 *
1012 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1013 * This is a function pointer entry point called by drivers
1014 * or other shared routines.
1015 **/
1016 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1017 {
1018 switch (hw->phy.type) {
1019 case e1000_phy_ife:
1020 return e1000_get_phy_info_ife_ich8lan(hw);
1021 break;
1022 case e1000_phy_igp_3:
1023 case e1000_phy_bm:
1024 case e1000_phy_82578:
1025 case e1000_phy_82577:
1026 return e1000e_get_phy_info_igp(hw);
1027 break;
1028 default:
1029 break;
1030 }
1031
1032 return -E1000_ERR_PHY_TYPE;
1033 }
1034
1035 /**
1036 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1037 * @hw: pointer to the HW structure
1038 *
1039 * Polarity is determined on the polarity reversal feature being enabled.
1040 * This function is only called by other family-specific
1041 * routines.
1042 **/
1043 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1044 {
1045 struct e1000_phy_info *phy = &hw->phy;
1046 s32 ret_val;
1047 u16 phy_data, offset, mask;
1048
1049 /*
1050 * Polarity is determined based on the reversal feature being enabled.
1051 */
1052 if (phy->polarity_correction) {
1053 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1054 mask = IFE_PESC_POLARITY_REVERSED;
1055 } else {
1056 offset = IFE_PHY_SPECIAL_CONTROL;
1057 mask = IFE_PSC_FORCE_POLARITY;
1058 }
1059
1060 ret_val = e1e_rphy(hw, offset, &phy_data);
1061
1062 if (!ret_val)
1063 phy->cable_polarity = (phy_data & mask)
1064 ? e1000_rev_polarity_reversed
1065 : e1000_rev_polarity_normal;
1066
1067 return ret_val;
1068 }
1069
1070 /**
1071 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1072 * @hw: pointer to the HW structure
1073 * @active: true to enable LPLU, false to disable
1074 *
1075 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1076 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1077 * the phy speed. This function will manually set the LPLU bit and restart
1078 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1079 * since it configures the same bit.
1080 **/
1081 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1082 {
1083 s32 ret_val = 0;
1084 u16 oem_reg;
1085
1086 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1087 if (ret_val)
1088 goto out;
1089
1090 if (active)
1091 oem_reg |= HV_OEM_BITS_LPLU;
1092 else
1093 oem_reg &= ~HV_OEM_BITS_LPLU;
1094
1095 oem_reg |= HV_OEM_BITS_RESTART_AN;
1096 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1097
1098 out:
1099 return ret_val;
1100 }
1101
1102 /**
1103 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1104 * @hw: pointer to the HW structure
1105 * @active: TRUE to enable LPLU, FALSE to disable
1106 *
1107 * Sets the LPLU D0 state according to the active flag. When
1108 * activating LPLU this function also disables smart speed
1109 * and vice versa. LPLU will not be activated unless the
1110 * device autonegotiation advertisement meets standards of
1111 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1112 * This is a function pointer entry point only called by
1113 * PHY setup routines.
1114 **/
1115 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1116 {
1117 struct e1000_phy_info *phy = &hw->phy;
1118 u32 phy_ctrl;
1119 s32 ret_val = 0;
1120 u16 data;
1121
1122 if (phy->type == e1000_phy_ife)
1123 return ret_val;
1124
1125 phy_ctrl = er32(PHY_CTRL);
1126
1127 if (active) {
1128 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1129 ew32(PHY_CTRL, phy_ctrl);
1130
1131 if (phy->type != e1000_phy_igp_3)
1132 return 0;
1133
1134 /*
1135 * Call gig speed drop workaround on LPLU before accessing
1136 * any PHY registers
1137 */
1138 if (hw->mac.type == e1000_ich8lan)
1139 e1000e_gig_downshift_workaround_ich8lan(hw);
1140
1141 /* When LPLU is enabled, we should disable SmartSpeed */
1142 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1143 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1144 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1145 if (ret_val)
1146 return ret_val;
1147 } else {
1148 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1149 ew32(PHY_CTRL, phy_ctrl);
1150
1151 if (phy->type != e1000_phy_igp_3)
1152 return 0;
1153
1154 /*
1155 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1156 * during Dx states where the power conservation is most
1157 * important. During driver activity we should enable
1158 * SmartSpeed, so performance is maintained.
1159 */
1160 if (phy->smart_speed == e1000_smart_speed_on) {
1161 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1162 &data);
1163 if (ret_val)
1164 return ret_val;
1165
1166 data |= IGP01E1000_PSCFR_SMART_SPEED;
1167 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1168 data);
1169 if (ret_val)
1170 return ret_val;
1171 } else if (phy->smart_speed == e1000_smart_speed_off) {
1172 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1173 &data);
1174 if (ret_val)
1175 return ret_val;
1176
1177 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1178 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1179 data);
1180 if (ret_val)
1181 return ret_val;
1182 }
1183 }
1184
1185 return 0;
1186 }
1187
1188 /**
1189 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1190 * @hw: pointer to the HW structure
1191 * @active: TRUE to enable LPLU, FALSE to disable
1192 *
1193 * Sets the LPLU D3 state according to the active flag. When
1194 * activating LPLU this function also disables smart speed
1195 * and vice versa. LPLU will not be activated unless the
1196 * device autonegotiation advertisement meets standards of
1197 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1198 * This is a function pointer entry point only called by
1199 * PHY setup routines.
1200 **/
1201 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1202 {
1203 struct e1000_phy_info *phy = &hw->phy;
1204 u32 phy_ctrl;
1205 s32 ret_val;
1206 u16 data;
1207
1208 phy_ctrl = er32(PHY_CTRL);
1209
1210 if (!active) {
1211 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1212 ew32(PHY_CTRL, phy_ctrl);
1213
1214 if (phy->type != e1000_phy_igp_3)
1215 return 0;
1216
1217 /*
1218 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1219 * during Dx states where the power conservation is most
1220 * important. During driver activity we should enable
1221 * SmartSpeed, so performance is maintained.
1222 */
1223 if (phy->smart_speed == e1000_smart_speed_on) {
1224 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1225 &data);
1226 if (ret_val)
1227 return ret_val;
1228
1229 data |= IGP01E1000_PSCFR_SMART_SPEED;
1230 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1231 data);
1232 if (ret_val)
1233 return ret_val;
1234 } else if (phy->smart_speed == e1000_smart_speed_off) {
1235 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1236 &data);
1237 if (ret_val)
1238 return ret_val;
1239
1240 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1241 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1242 data);
1243 if (ret_val)
1244 return ret_val;
1245 }
1246 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1247 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1248 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1249 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1250 ew32(PHY_CTRL, phy_ctrl);
1251
1252 if (phy->type != e1000_phy_igp_3)
1253 return 0;
1254
1255 /*
1256 * Call gig speed drop workaround on LPLU before accessing
1257 * any PHY registers
1258 */
1259 if (hw->mac.type == e1000_ich8lan)
1260 e1000e_gig_downshift_workaround_ich8lan(hw);
1261
1262 /* When LPLU is enabled, we should disable SmartSpeed */
1263 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1264 if (ret_val)
1265 return ret_val;
1266
1267 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1268 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1269 }
1270
1271 return 0;
1272 }
1273
1274 /**
1275 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1276 * @hw: pointer to the HW structure
1277 * @bank: pointer to the variable that returns the active bank
1278 *
1279 * Reads signature byte from the NVM using the flash access registers.
1280 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1281 **/
1282 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1283 {
1284 u32 eecd;
1285 struct e1000_nvm_info *nvm = &hw->nvm;
1286 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1287 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1288 u8 sig_byte = 0;
1289 s32 ret_val = 0;
1290
1291 switch (hw->mac.type) {
1292 case e1000_ich8lan:
1293 case e1000_ich9lan:
1294 eecd = er32(EECD);
1295 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1296 E1000_EECD_SEC1VAL_VALID_MASK) {
1297 if (eecd & E1000_EECD_SEC1VAL)
1298 *bank = 1;
1299 else
1300 *bank = 0;
1301
1302 return 0;
1303 }
1304 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1305 "reading flash signature\n");
1306 /* fall-thru */
1307 default:
1308 /* set bank to 0 in case flash read fails */
1309 *bank = 0;
1310
1311 /* Check bank 0 */
1312 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1313 &sig_byte);
1314 if (ret_val)
1315 return ret_val;
1316 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1317 E1000_ICH_NVM_SIG_VALUE) {
1318 *bank = 0;
1319 return 0;
1320 }
1321
1322 /* Check bank 1 */
1323 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1324 bank1_offset,
1325 &sig_byte);
1326 if (ret_val)
1327 return ret_val;
1328 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1329 E1000_ICH_NVM_SIG_VALUE) {
1330 *bank = 1;
1331 return 0;
1332 }
1333
1334 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1335 return -E1000_ERR_NVM;
1336 }
1337
1338 return 0;
1339 }
1340
1341 /**
1342 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1343 * @hw: pointer to the HW structure
1344 * @offset: The offset (in bytes) of the word(s) to read.
1345 * @words: Size of data to read in words
1346 * @data: Pointer to the word(s) to read at offset.
1347 *
1348 * Reads a word(s) from the NVM using the flash access registers.
1349 **/
1350 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1351 u16 *data)
1352 {
1353 struct e1000_nvm_info *nvm = &hw->nvm;
1354 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1355 u32 act_offset;
1356 s32 ret_val = 0;
1357 u32 bank = 0;
1358 u16 i, word;
1359
1360 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1361 (words == 0)) {
1362 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1363 return -E1000_ERR_NVM;
1364 }
1365
1366 ret_val = e1000_acquire_swflag_ich8lan(hw);
1367 if (ret_val)
1368 goto out;
1369
1370 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1371 if (ret_val) {
1372 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1373 bank = 0;
1374 }
1375
1376 act_offset = (bank) ? nvm->flash_bank_size : 0;
1377 act_offset += offset;
1378
1379 ret_val = 0;
1380 for (i = 0; i < words; i++) {
1381 if ((dev_spec->shadow_ram) &&
1382 (dev_spec->shadow_ram[offset+i].modified)) {
1383 data[i] = dev_spec->shadow_ram[offset+i].value;
1384 } else {
1385 ret_val = e1000_read_flash_word_ich8lan(hw,
1386 act_offset + i,
1387 &word);
1388 if (ret_val)
1389 break;
1390 data[i] = word;
1391 }
1392 }
1393
1394 e1000_release_swflag_ich8lan(hw);
1395
1396 out:
1397 if (ret_val)
1398 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1399
1400 return ret_val;
1401 }
1402
1403 /**
1404 * e1000_flash_cycle_init_ich8lan - Initialize flash
1405 * @hw: pointer to the HW structure
1406 *
1407 * This function does initial flash setup so that a new read/write/erase cycle
1408 * can be started.
1409 **/
1410 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1411 {
1412 union ich8_hws_flash_status hsfsts;
1413 s32 ret_val = -E1000_ERR_NVM;
1414 s32 i = 0;
1415
1416 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1417
1418 /* Check if the flash descriptor is valid */
1419 if (hsfsts.hsf_status.fldesvalid == 0) {
1420 hw_dbg(hw, "Flash descriptor invalid. "
1421 "SW Sequencing must be used.");
1422 return -E1000_ERR_NVM;
1423 }
1424
1425 /* Clear FCERR and DAEL in hw status by writing 1 */
1426 hsfsts.hsf_status.flcerr = 1;
1427 hsfsts.hsf_status.dael = 1;
1428
1429 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1430
1431 /*
1432 * Either we should have a hardware SPI cycle in progress
1433 * bit to check against, in order to start a new cycle or
1434 * FDONE bit should be changed in the hardware so that it
1435 * is 1 after hardware reset, which can then be used as an
1436 * indication whether a cycle is in progress or has been
1437 * completed.
1438 */
1439
1440 if (hsfsts.hsf_status.flcinprog == 0) {
1441 /*
1442 * There is no cycle running at present,
1443 * so we can start a cycle
1444 * Begin by setting Flash Cycle Done.
1445 */
1446 hsfsts.hsf_status.flcdone = 1;
1447 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1448 ret_val = 0;
1449 } else {
1450 /*
1451 * otherwise poll for sometime so the current
1452 * cycle has a chance to end before giving up.
1453 */
1454 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1455 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1456 if (hsfsts.hsf_status.flcinprog == 0) {
1457 ret_val = 0;
1458 break;
1459 }
1460 udelay(1);
1461 }
1462 if (ret_val == 0) {
1463 /*
1464 * Successful in waiting for previous cycle to timeout,
1465 * now set the Flash Cycle Done.
1466 */
1467 hsfsts.hsf_status.flcdone = 1;
1468 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1469 } else {
1470 hw_dbg(hw, "Flash controller busy, cannot get access");
1471 }
1472 }
1473
1474 return ret_val;
1475 }
1476
1477 /**
1478 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1479 * @hw: pointer to the HW structure
1480 * @timeout: maximum time to wait for completion
1481 *
1482 * This function starts a flash cycle and waits for its completion.
1483 **/
1484 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1485 {
1486 union ich8_hws_flash_ctrl hsflctl;
1487 union ich8_hws_flash_status hsfsts;
1488 s32 ret_val = -E1000_ERR_NVM;
1489 u32 i = 0;
1490
1491 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1492 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1493 hsflctl.hsf_ctrl.flcgo = 1;
1494 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1495
1496 /* wait till FDONE bit is set to 1 */
1497 do {
1498 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1499 if (hsfsts.hsf_status.flcdone == 1)
1500 break;
1501 udelay(1);
1502 } while (i++ < timeout);
1503
1504 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1505 return 0;
1506
1507 return ret_val;
1508 }
1509
1510 /**
1511 * e1000_read_flash_word_ich8lan - Read word from flash
1512 * @hw: pointer to the HW structure
1513 * @offset: offset to data location
1514 * @data: pointer to the location for storing the data
1515 *
1516 * Reads the flash word at offset into data. Offset is converted
1517 * to bytes before read.
1518 **/
1519 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1520 u16 *data)
1521 {
1522 /* Must convert offset into bytes. */
1523 offset <<= 1;
1524
1525 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1526 }
1527
1528 /**
1529 * e1000_read_flash_byte_ich8lan - Read byte from flash
1530 * @hw: pointer to the HW structure
1531 * @offset: The offset of the byte to read.
1532 * @data: Pointer to a byte to store the value read.
1533 *
1534 * Reads a single byte from the NVM using the flash access registers.
1535 **/
1536 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1537 u8 *data)
1538 {
1539 s32 ret_val;
1540 u16 word = 0;
1541
1542 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1543 if (ret_val)
1544 return ret_val;
1545
1546 *data = (u8)word;
1547
1548 return 0;
1549 }
1550
1551 /**
1552 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1553 * @hw: pointer to the HW structure
1554 * @offset: The offset (in bytes) of the byte or word to read.
1555 * @size: Size of data to read, 1=byte 2=word
1556 * @data: Pointer to the word to store the value read.
1557 *
1558 * Reads a byte or word from the NVM using the flash access registers.
1559 **/
1560 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1561 u8 size, u16 *data)
1562 {
1563 union ich8_hws_flash_status hsfsts;
1564 union ich8_hws_flash_ctrl hsflctl;
1565 u32 flash_linear_addr;
1566 u32 flash_data = 0;
1567 s32 ret_val = -E1000_ERR_NVM;
1568 u8 count = 0;
1569
1570 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1571 return -E1000_ERR_NVM;
1572
1573 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1574 hw->nvm.flash_base_addr;
1575
1576 do {
1577 udelay(1);
1578 /* Steps */
1579 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1580 if (ret_val != 0)
1581 break;
1582
1583 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1584 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1585 hsflctl.hsf_ctrl.fldbcount = size - 1;
1586 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1587 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1588
1589 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1590
1591 ret_val = e1000_flash_cycle_ich8lan(hw,
1592 ICH_FLASH_READ_COMMAND_TIMEOUT);
1593
1594 /*
1595 * Check if FCERR is set to 1, if set to 1, clear it
1596 * and try the whole sequence a few more times, else
1597 * read in (shift in) the Flash Data0, the order is
1598 * least significant byte first msb to lsb
1599 */
1600 if (ret_val == 0) {
1601 flash_data = er32flash(ICH_FLASH_FDATA0);
1602 if (size == 1) {
1603 *data = (u8)(flash_data & 0x000000FF);
1604 } else if (size == 2) {
1605 *data = (u16)(flash_data & 0x0000FFFF);
1606 }
1607 break;
1608 } else {
1609 /*
1610 * If we've gotten here, then things are probably
1611 * completely hosed, but if the error condition is
1612 * detected, it won't hurt to give it another try...
1613 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1614 */
1615 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1616 if (hsfsts.hsf_status.flcerr == 1) {
1617 /* Repeat for some time before giving up. */
1618 continue;
1619 } else if (hsfsts.hsf_status.flcdone == 0) {
1620 hw_dbg(hw, "Timeout error - flash cycle "
1621 "did not complete.");
1622 break;
1623 }
1624 }
1625 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1626
1627 return ret_val;
1628 }
1629
1630 /**
1631 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1632 * @hw: pointer to the HW structure
1633 * @offset: The offset (in bytes) of the word(s) to write.
1634 * @words: Size of data to write in words
1635 * @data: Pointer to the word(s) to write at offset.
1636 *
1637 * Writes a byte or word to the NVM using the flash access registers.
1638 **/
1639 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1640 u16 *data)
1641 {
1642 struct e1000_nvm_info *nvm = &hw->nvm;
1643 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1644 u16 i;
1645
1646 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1647 (words == 0)) {
1648 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1649 return -E1000_ERR_NVM;
1650 }
1651
1652 for (i = 0; i < words; i++) {
1653 dev_spec->shadow_ram[offset+i].modified = 1;
1654 dev_spec->shadow_ram[offset+i].value = data[i];
1655 }
1656
1657 return 0;
1658 }
1659
1660 /**
1661 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1662 * @hw: pointer to the HW structure
1663 *
1664 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1665 * which writes the checksum to the shadow ram. The changes in the shadow
1666 * ram are then committed to the EEPROM by processing each bank at a time
1667 * checking for the modified bit and writing only the pending changes.
1668 * After a successful commit, the shadow ram is cleared and is ready for
1669 * future writes.
1670 **/
1671 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1672 {
1673 struct e1000_nvm_info *nvm = &hw->nvm;
1674 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1675 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1676 s32 ret_val;
1677 u16 data;
1678
1679 ret_val = e1000e_update_nvm_checksum_generic(hw);
1680 if (ret_val)
1681 goto out;
1682
1683 if (nvm->type != e1000_nvm_flash_sw)
1684 goto out;
1685
1686 ret_val = e1000_acquire_swflag_ich8lan(hw);
1687 if (ret_val)
1688 goto out;
1689
1690 /*
1691 * We're writing to the opposite bank so if we're on bank 1,
1692 * write to bank 0 etc. We also need to erase the segment that
1693 * is going to be written
1694 */
1695 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1696 if (ret_val) {
1697 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1698 bank = 0;
1699 }
1700
1701 if (bank == 0) {
1702 new_bank_offset = nvm->flash_bank_size;
1703 old_bank_offset = 0;
1704 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1705 if (ret_val) {
1706 e1000_release_swflag_ich8lan(hw);
1707 goto out;
1708 }
1709 } else {
1710 old_bank_offset = nvm->flash_bank_size;
1711 new_bank_offset = 0;
1712 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1713 if (ret_val) {
1714 e1000_release_swflag_ich8lan(hw);
1715 goto out;
1716 }
1717 }
1718
1719 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1720 /*
1721 * Determine whether to write the value stored
1722 * in the other NVM bank or a modified value stored
1723 * in the shadow RAM
1724 */
1725 if (dev_spec->shadow_ram[i].modified) {
1726 data = dev_spec->shadow_ram[i].value;
1727 } else {
1728 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1729 old_bank_offset,
1730 &data);
1731 if (ret_val)
1732 break;
1733 }
1734
1735 /*
1736 * If the word is 0x13, then make sure the signature bits
1737 * (15:14) are 11b until the commit has completed.
1738 * This will allow us to write 10b which indicates the
1739 * signature is valid. We want to do this after the write
1740 * has completed so that we don't mark the segment valid
1741 * while the write is still in progress
1742 */
1743 if (i == E1000_ICH_NVM_SIG_WORD)
1744 data |= E1000_ICH_NVM_SIG_MASK;
1745
1746 /* Convert offset to bytes. */
1747 act_offset = (i + new_bank_offset) << 1;
1748
1749 udelay(100);
1750 /* Write the bytes to the new bank. */
1751 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1752 act_offset,
1753 (u8)data);
1754 if (ret_val)
1755 break;
1756
1757 udelay(100);
1758 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1759 act_offset + 1,
1760 (u8)(data >> 8));
1761 if (ret_val)
1762 break;
1763 }
1764
1765 /*
1766 * Don't bother writing the segment valid bits if sector
1767 * programming failed.
1768 */
1769 if (ret_val) {
1770 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1771 hw_dbg(hw, "Flash commit failed.\n");
1772 e1000_release_swflag_ich8lan(hw);
1773 goto out;
1774 }
1775
1776 /*
1777 * Finally validate the new segment by setting bit 15:14
1778 * to 10b in word 0x13 , this can be done without an
1779 * erase as well since these bits are 11 to start with
1780 * and we need to change bit 14 to 0b
1781 */
1782 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1783 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1784 if (ret_val) {
1785 e1000_release_swflag_ich8lan(hw);
1786 goto out;
1787 }
1788 data &= 0xBFFF;
1789 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1790 act_offset * 2 + 1,
1791 (u8)(data >> 8));
1792 if (ret_val) {
1793 e1000_release_swflag_ich8lan(hw);
1794 goto out;
1795 }
1796
1797 /*
1798 * And invalidate the previously valid segment by setting
1799 * its signature word (0x13) high_byte to 0b. This can be
1800 * done without an erase because flash erase sets all bits
1801 * to 1's. We can write 1's to 0's without an erase
1802 */
1803 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1804 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1805 if (ret_val) {
1806 e1000_release_swflag_ich8lan(hw);
1807 goto out;
1808 }
1809
1810 /* Great! Everything worked, we can now clear the cached entries. */
1811 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1812 dev_spec->shadow_ram[i].modified = 0;
1813 dev_spec->shadow_ram[i].value = 0xFFFF;
1814 }
1815
1816 e1000_release_swflag_ich8lan(hw);
1817
1818 /*
1819 * Reload the EEPROM, or else modifications will not appear
1820 * until after the next adapter reset.
1821 */
1822 e1000e_reload_nvm(hw);
1823 msleep(10);
1824
1825 out:
1826 if (ret_val)
1827 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1828
1829 return ret_val;
1830 }
1831
1832 /**
1833 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1834 * @hw: pointer to the HW structure
1835 *
1836 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1837 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1838 * calculated, in which case we need to calculate the checksum and set bit 6.
1839 **/
1840 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1841 {
1842 s32 ret_val;
1843 u16 data;
1844
1845 /*
1846 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1847 * needs to be fixed. This bit is an indication that the NVM
1848 * was prepared by OEM software and did not calculate the
1849 * checksum...a likely scenario.
1850 */
1851 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1852 if (ret_val)
1853 return ret_val;
1854
1855 if ((data & 0x40) == 0) {
1856 data |= 0x40;
1857 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1858 if (ret_val)
1859 return ret_val;
1860 ret_val = e1000e_update_nvm_checksum(hw);
1861 if (ret_val)
1862 return ret_val;
1863 }
1864
1865 return e1000e_validate_nvm_checksum_generic(hw);
1866 }
1867
1868 /**
1869 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1870 * @hw: pointer to the HW structure
1871 *
1872 * To prevent malicious write/erase of the NVM, set it to be read-only
1873 * so that the hardware ignores all write/erase cycles of the NVM via
1874 * the flash control registers. The shadow-ram copy of the NVM will
1875 * still be updated, however any updates to this copy will not stick
1876 * across driver reloads.
1877 **/
1878 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1879 {
1880 union ich8_flash_protected_range pr0;
1881 union ich8_hws_flash_status hsfsts;
1882 u32 gfpreg;
1883 s32 ret_val;
1884
1885 ret_val = e1000_acquire_swflag_ich8lan(hw);
1886 if (ret_val)
1887 return;
1888
1889 gfpreg = er32flash(ICH_FLASH_GFPREG);
1890
1891 /* Write-protect GbE Sector of NVM */
1892 pr0.regval = er32flash(ICH_FLASH_PR0);
1893 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1894 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1895 pr0.range.wpe = true;
1896 ew32flash(ICH_FLASH_PR0, pr0.regval);
1897
1898 /*
1899 * Lock down a subset of GbE Flash Control Registers, e.g.
1900 * PR0 to prevent the write-protection from being lifted.
1901 * Once FLOCKDN is set, the registers protected by it cannot
1902 * be written until FLOCKDN is cleared by a hardware reset.
1903 */
1904 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1905 hsfsts.hsf_status.flockdn = true;
1906 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1907
1908 e1000_release_swflag_ich8lan(hw);
1909 }
1910
1911 /**
1912 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1913 * @hw: pointer to the HW structure
1914 * @offset: The offset (in bytes) of the byte/word to read.
1915 * @size: Size of data to read, 1=byte 2=word
1916 * @data: The byte(s) to write to the NVM.
1917 *
1918 * Writes one/two bytes to the NVM using the flash access registers.
1919 **/
1920 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1921 u8 size, u16 data)
1922 {
1923 union ich8_hws_flash_status hsfsts;
1924 union ich8_hws_flash_ctrl hsflctl;
1925 u32 flash_linear_addr;
1926 u32 flash_data = 0;
1927 s32 ret_val;
1928 u8 count = 0;
1929
1930 if (size < 1 || size > 2 || data > size * 0xff ||
1931 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1932 return -E1000_ERR_NVM;
1933
1934 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1935 hw->nvm.flash_base_addr;
1936
1937 do {
1938 udelay(1);
1939 /* Steps */
1940 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1941 if (ret_val)
1942 break;
1943
1944 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1945 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1946 hsflctl.hsf_ctrl.fldbcount = size -1;
1947 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1948 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1949
1950 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1951
1952 if (size == 1)
1953 flash_data = (u32)data & 0x00FF;
1954 else
1955 flash_data = (u32)data;
1956
1957 ew32flash(ICH_FLASH_FDATA0, flash_data);
1958
1959 /*
1960 * check if FCERR is set to 1 , if set to 1, clear it
1961 * and try the whole sequence a few more times else done
1962 */
1963 ret_val = e1000_flash_cycle_ich8lan(hw,
1964 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1965 if (!ret_val)
1966 break;
1967
1968 /*
1969 * If we're here, then things are most likely
1970 * completely hosed, but if the error condition
1971 * is detected, it won't hurt to give it another
1972 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1973 */
1974 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1975 if (hsfsts.hsf_status.flcerr == 1)
1976 /* Repeat for some time before giving up. */
1977 continue;
1978 if (hsfsts.hsf_status.flcdone == 0) {
1979 hw_dbg(hw, "Timeout error - flash cycle "
1980 "did not complete.");
1981 break;
1982 }
1983 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1984
1985 return ret_val;
1986 }
1987
1988 /**
1989 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1990 * @hw: pointer to the HW structure
1991 * @offset: The index of the byte to read.
1992 * @data: The byte to write to the NVM.
1993 *
1994 * Writes a single byte to the NVM using the flash access registers.
1995 **/
1996 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1997 u8 data)
1998 {
1999 u16 word = (u16)data;
2000
2001 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2002 }
2003
2004 /**
2005 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2006 * @hw: pointer to the HW structure
2007 * @offset: The offset of the byte to write.
2008 * @byte: The byte to write to the NVM.
2009 *
2010 * Writes a single byte to the NVM using the flash access registers.
2011 * Goes through a retry algorithm before giving up.
2012 **/
2013 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2014 u32 offset, u8 byte)
2015 {
2016 s32 ret_val;
2017 u16 program_retries;
2018
2019 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2020 if (!ret_val)
2021 return ret_val;
2022
2023 for (program_retries = 0; program_retries < 100; program_retries++) {
2024 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
2025 udelay(100);
2026 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2027 if (!ret_val)
2028 break;
2029 }
2030 if (program_retries == 100)
2031 return -E1000_ERR_NVM;
2032
2033 return 0;
2034 }
2035
2036 /**
2037 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2038 * @hw: pointer to the HW structure
2039 * @bank: 0 for first bank, 1 for second bank, etc.
2040 *
2041 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2042 * bank N is 4096 * N + flash_reg_addr.
2043 **/
2044 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2045 {
2046 struct e1000_nvm_info *nvm = &hw->nvm;
2047 union ich8_hws_flash_status hsfsts;
2048 union ich8_hws_flash_ctrl hsflctl;
2049 u32 flash_linear_addr;
2050 /* bank size is in 16bit words - adjust to bytes */
2051 u32 flash_bank_size = nvm->flash_bank_size * 2;
2052 s32 ret_val;
2053 s32 count = 0;
2054 s32 iteration;
2055 s32 sector_size;
2056 s32 j;
2057
2058 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2059
2060 /*
2061 * Determine HW Sector size: Read BERASE bits of hw flash status
2062 * register
2063 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2064 * consecutive sectors. The start index for the nth Hw sector
2065 * can be calculated as = bank * 4096 + n * 256
2066 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2067 * The start index for the nth Hw sector can be calculated
2068 * as = bank * 4096
2069 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2070 * (ich9 only, otherwise error condition)
2071 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2072 */
2073 switch (hsfsts.hsf_status.berasesz) {
2074 case 0:
2075 /* Hw sector size 256 */
2076 sector_size = ICH_FLASH_SEG_SIZE_256;
2077 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2078 break;
2079 case 1:
2080 sector_size = ICH_FLASH_SEG_SIZE_4K;
2081 iteration = 1;
2082 break;
2083 case 2:
2084 sector_size = ICH_FLASH_SEG_SIZE_8K;
2085 iteration = 1;
2086 break;
2087 case 3:
2088 sector_size = ICH_FLASH_SEG_SIZE_64K;
2089 iteration = 1;
2090 break;
2091 default:
2092 return -E1000_ERR_NVM;
2093 }
2094
2095 /* Start with the base address, then add the sector offset. */
2096 flash_linear_addr = hw->nvm.flash_base_addr;
2097 flash_linear_addr += (bank) ? flash_bank_size : 0;
2098
2099 for (j = 0; j < iteration ; j++) {
2100 do {
2101 /* Steps */
2102 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2103 if (ret_val)
2104 return ret_val;
2105
2106 /*
2107 * Write a value 11 (block Erase) in Flash
2108 * Cycle field in hw flash control
2109 */
2110 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2111 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2112 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2113
2114 /*
2115 * Write the last 24 bits of an index within the
2116 * block into Flash Linear address field in Flash
2117 * Address.
2118 */
2119 flash_linear_addr += (j * sector_size);
2120 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2121
2122 ret_val = e1000_flash_cycle_ich8lan(hw,
2123 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2124 if (ret_val == 0)
2125 break;
2126
2127 /*
2128 * Check if FCERR is set to 1. If 1,
2129 * clear it and try the whole sequence
2130 * a few more times else Done
2131 */
2132 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2133 if (hsfsts.hsf_status.flcerr == 1)
2134 /* repeat for some time before giving up */
2135 continue;
2136 else if (hsfsts.hsf_status.flcdone == 0)
2137 return ret_val;
2138 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2139 }
2140
2141 return 0;
2142 }
2143
2144 /**
2145 * e1000_valid_led_default_ich8lan - Set the default LED settings
2146 * @hw: pointer to the HW structure
2147 * @data: Pointer to the LED settings
2148 *
2149 * Reads the LED default settings from the NVM to data. If the NVM LED
2150 * settings is all 0's or F's, set the LED default to a valid LED default
2151 * setting.
2152 **/
2153 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2154 {
2155 s32 ret_val;
2156
2157 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2158 if (ret_val) {
2159 hw_dbg(hw, "NVM Read Error\n");
2160 return ret_val;
2161 }
2162
2163 if (*data == ID_LED_RESERVED_0000 ||
2164 *data == ID_LED_RESERVED_FFFF)
2165 *data = ID_LED_DEFAULT_ICH8LAN;
2166
2167 return 0;
2168 }
2169
2170 /**
2171 * e1000_id_led_init_pchlan - store LED configurations
2172 * @hw: pointer to the HW structure
2173 *
2174 * PCH does not control LEDs via the LEDCTL register, rather it uses
2175 * the PHY LED configuration register.
2176 *
2177 * PCH also does not have an "always on" or "always off" mode which
2178 * complicates the ID feature. Instead of using the "on" mode to indicate
2179 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2180 * use "link_up" mode. The LEDs will still ID on request if there is no
2181 * link based on logic in e1000_led_[on|off]_pchlan().
2182 **/
2183 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2184 {
2185 struct e1000_mac_info *mac = &hw->mac;
2186 s32 ret_val;
2187 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2188 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2189 u16 data, i, temp, shift;
2190
2191 /* Get default ID LED modes */
2192 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2193 if (ret_val)
2194 goto out;
2195
2196 mac->ledctl_default = er32(LEDCTL);
2197 mac->ledctl_mode1 = mac->ledctl_default;
2198 mac->ledctl_mode2 = mac->ledctl_default;
2199
2200 for (i = 0; i < 4; i++) {
2201 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2202 shift = (i * 5);
2203 switch (temp) {
2204 case ID_LED_ON1_DEF2:
2205 case ID_LED_ON1_ON2:
2206 case ID_LED_ON1_OFF2:
2207 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2208 mac->ledctl_mode1 |= (ledctl_on << shift);
2209 break;
2210 case ID_LED_OFF1_DEF2:
2211 case ID_LED_OFF1_ON2:
2212 case ID_LED_OFF1_OFF2:
2213 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2214 mac->ledctl_mode1 |= (ledctl_off << shift);
2215 break;
2216 default:
2217 /* Do nothing */
2218 break;
2219 }
2220 switch (temp) {
2221 case ID_LED_DEF1_ON2:
2222 case ID_LED_ON1_ON2:
2223 case ID_LED_OFF1_ON2:
2224 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2225 mac->ledctl_mode2 |= (ledctl_on << shift);
2226 break;
2227 case ID_LED_DEF1_OFF2:
2228 case ID_LED_ON1_OFF2:
2229 case ID_LED_OFF1_OFF2:
2230 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2231 mac->ledctl_mode2 |= (ledctl_off << shift);
2232 break;
2233 default:
2234 /* Do nothing */
2235 break;
2236 }
2237 }
2238
2239 out:
2240 return ret_val;
2241 }
2242
2243 /**
2244 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2245 * @hw: pointer to the HW structure
2246 *
2247 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2248 * register, so the the bus width is hard coded.
2249 **/
2250 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2251 {
2252 struct e1000_bus_info *bus = &hw->bus;
2253 s32 ret_val;
2254
2255 ret_val = e1000e_get_bus_info_pcie(hw);
2256
2257 /*
2258 * ICH devices are "PCI Express"-ish. They have
2259 * a configuration space, but do not contain
2260 * PCI Express Capability registers, so bus width
2261 * must be hardcoded.
2262 */
2263 if (bus->width == e1000_bus_width_unknown)
2264 bus->width = e1000_bus_width_pcie_x1;
2265
2266 return ret_val;
2267 }
2268
2269 /**
2270 * e1000_reset_hw_ich8lan - Reset the hardware
2271 * @hw: pointer to the HW structure
2272 *
2273 * Does a full reset of the hardware which includes a reset of the PHY and
2274 * MAC.
2275 **/
2276 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2277 {
2278 u16 reg;
2279 u32 ctrl, icr, kab;
2280 s32 ret_val;
2281
2282 /*
2283 * Prevent the PCI-E bus from sticking if there is no TLP connection
2284 * on the last TLP read/write transaction when MAC is reset.
2285 */
2286 ret_val = e1000e_disable_pcie_master(hw);
2287 if (ret_val) {
2288 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2289 }
2290
2291 hw_dbg(hw, "Masking off all interrupts\n");
2292 ew32(IMC, 0xffffffff);
2293
2294 /*
2295 * Disable the Transmit and Receive units. Then delay to allow
2296 * any pending transactions to complete before we hit the MAC
2297 * with the global reset.
2298 */
2299 ew32(RCTL, 0);
2300 ew32(TCTL, E1000_TCTL_PSP);
2301 e1e_flush();
2302
2303 msleep(10);
2304
2305 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2306 if (hw->mac.type == e1000_ich8lan) {
2307 /* Set Tx and Rx buffer allocation to 8k apiece. */
2308 ew32(PBA, E1000_PBA_8K);
2309 /* Set Packet Buffer Size to 16k. */
2310 ew32(PBS, E1000_PBS_16K);
2311 }
2312
2313 ctrl = er32(CTRL);
2314
2315 if (!e1000_check_reset_block(hw)) {
2316 /* Clear PHY Reset Asserted bit */
2317 if (hw->mac.type >= e1000_pchlan) {
2318 u32 status = er32(STATUS);
2319 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2320 }
2321
2322 /*
2323 * PHY HW reset requires MAC CORE reset at the same
2324 * time to make sure the interface between MAC and the
2325 * external PHY is reset.
2326 */
2327 ctrl |= E1000_CTRL_PHY_RST;
2328 }
2329 ret_val = e1000_acquire_swflag_ich8lan(hw);
2330 /* Whether or not the swflag was acquired, we need to reset the part */
2331 hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2332 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2333 msleep(20);
2334
2335 if (!ret_val)
2336 e1000_release_swflag_ich8lan(hw);
2337
2338 if (ctrl & E1000_CTRL_PHY_RST)
2339 ret_val = hw->phy.ops.get_cfg_done(hw);
2340
2341 if (hw->mac.type >= e1000_ich10lan) {
2342 e1000_lan_init_done_ich8lan(hw);
2343 } else {
2344 ret_val = e1000e_get_auto_rd_done(hw);
2345 if (ret_val) {
2346 /*
2347 * When auto config read does not complete, do not
2348 * return with an error. This can happen in situations
2349 * where there is no eeprom and prevents getting link.
2350 */
2351 hw_dbg(hw, "Auto Read Done did not complete\n");
2352 }
2353 }
2354 /* Dummy read to clear the phy wakeup bit after lcd reset */
2355 if (hw->mac.type == e1000_pchlan)
2356 e1e_rphy(hw, BM_WUC, &reg);
2357
2358 /*
2359 * For PCH, this write will make sure that any noise
2360 * will be detected as a CRC error and be dropped rather than show up
2361 * as a bad packet to the DMA engine.
2362 */
2363 if (hw->mac.type == e1000_pchlan)
2364 ew32(CRC_OFFSET, 0x65656565);
2365
2366 ew32(IMC, 0xffffffff);
2367 icr = er32(ICR);
2368
2369 kab = er32(KABGTXD);
2370 kab |= E1000_KABGTXD_BGSQLBIAS;
2371 ew32(KABGTXD, kab);
2372
2373 if (hw->mac.type == e1000_pchlan)
2374 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2375
2376 return ret_val;
2377 }
2378
2379 /**
2380 * e1000_init_hw_ich8lan - Initialize the hardware
2381 * @hw: pointer to the HW structure
2382 *
2383 * Prepares the hardware for transmit and receive by doing the following:
2384 * - initialize hardware bits
2385 * - initialize LED identification
2386 * - setup receive address registers
2387 * - setup flow control
2388 * - setup transmit descriptors
2389 * - clear statistics
2390 **/
2391 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2392 {
2393 struct e1000_mac_info *mac = &hw->mac;
2394 u32 ctrl_ext, txdctl, snoop;
2395 s32 ret_val;
2396 u16 i;
2397
2398 e1000_initialize_hw_bits_ich8lan(hw);
2399
2400 /* Initialize identification LED */
2401 ret_val = mac->ops.id_led_init(hw);
2402 if (ret_val) {
2403 hw_dbg(hw, "Error initializing identification LED\n");
2404 return ret_val;
2405 }
2406
2407 /* Setup the receive address. */
2408 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2409
2410 /* Zero out the Multicast HASH table */
2411 hw_dbg(hw, "Zeroing the MTA\n");
2412 for (i = 0; i < mac->mta_reg_count; i++)
2413 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2414
2415 /*
2416 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2417 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2418 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2419 */
2420 if (hw->phy.type == e1000_phy_82578) {
2421 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2422 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2423 if (ret_val)
2424 return ret_val;
2425 }
2426
2427 /* Setup link and flow control */
2428 ret_val = e1000_setup_link_ich8lan(hw);
2429
2430 /* Set the transmit descriptor write-back policy for both queues */
2431 txdctl = er32(TXDCTL(0));
2432 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2433 E1000_TXDCTL_FULL_TX_DESC_WB;
2434 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2435 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2436 ew32(TXDCTL(0), txdctl);
2437 txdctl = er32(TXDCTL(1));
2438 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2439 E1000_TXDCTL_FULL_TX_DESC_WB;
2440 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2441 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2442 ew32(TXDCTL(1), txdctl);
2443
2444 /*
2445 * ICH8 has opposite polarity of no_snoop bits.
2446 * By default, we should use snoop behavior.
2447 */
2448 if (mac->type == e1000_ich8lan)
2449 snoop = PCIE_ICH8_SNOOP_ALL;
2450 else
2451 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2452 e1000e_set_pcie_no_snoop(hw, snoop);
2453
2454 ctrl_ext = er32(CTRL_EXT);
2455 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2456 ew32(CTRL_EXT, ctrl_ext);
2457
2458 /*
2459 * Clear all of the statistics registers (clear on read). It is
2460 * important that we do this after we have tried to establish link
2461 * because the symbol error count will increment wildly if there
2462 * is no link.
2463 */
2464 e1000_clear_hw_cntrs_ich8lan(hw);
2465
2466 return 0;
2467 }
2468 /**
2469 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2470 * @hw: pointer to the HW structure
2471 *
2472 * Sets/Clears required hardware bits necessary for correctly setting up the
2473 * hardware for transmit and receive.
2474 **/
2475 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2476 {
2477 u32 reg;
2478
2479 /* Extended Device Control */
2480 reg = er32(CTRL_EXT);
2481 reg |= (1 << 22);
2482 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2483 if (hw->mac.type >= e1000_pchlan)
2484 reg |= E1000_CTRL_EXT_PHYPDEN;
2485 ew32(CTRL_EXT, reg);
2486
2487 /* Transmit Descriptor Control 0 */
2488 reg = er32(TXDCTL(0));
2489 reg |= (1 << 22);
2490 ew32(TXDCTL(0), reg);
2491
2492 /* Transmit Descriptor Control 1 */
2493 reg = er32(TXDCTL(1));
2494 reg |= (1 << 22);
2495 ew32(TXDCTL(1), reg);
2496
2497 /* Transmit Arbitration Control 0 */
2498 reg = er32(TARC(0));
2499 if (hw->mac.type == e1000_ich8lan)
2500 reg |= (1 << 28) | (1 << 29);
2501 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2502 ew32(TARC(0), reg);
2503
2504 /* Transmit Arbitration Control 1 */
2505 reg = er32(TARC(1));
2506 if (er32(TCTL) & E1000_TCTL_MULR)
2507 reg &= ~(1 << 28);
2508 else
2509 reg |= (1 << 28);
2510 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2511 ew32(TARC(1), reg);
2512
2513 /* Device Status */
2514 if (hw->mac.type == e1000_ich8lan) {
2515 reg = er32(STATUS);
2516 reg &= ~(1 << 31);
2517 ew32(STATUS, reg);
2518 }
2519 }
2520
2521 /**
2522 * e1000_setup_link_ich8lan - Setup flow control and link settings
2523 * @hw: pointer to the HW structure
2524 *
2525 * Determines which flow control settings to use, then configures flow
2526 * control. Calls the appropriate media-specific link configuration
2527 * function. Assuming the adapter has a valid link partner, a valid link
2528 * should be established. Assumes the hardware has previously been reset
2529 * and the transmitter and receiver are not enabled.
2530 **/
2531 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2532 {
2533 s32 ret_val;
2534
2535 if (e1000_check_reset_block(hw))
2536 return 0;
2537
2538 /*
2539 * ICH parts do not have a word in the NVM to determine
2540 * the default flow control setting, so we explicitly
2541 * set it to full.
2542 */
2543 if (hw->fc.requested_mode == e1000_fc_default) {
2544 /* Workaround h/w hang when Tx flow control enabled */
2545 if (hw->mac.type == e1000_pchlan)
2546 hw->fc.requested_mode = e1000_fc_rx_pause;
2547 else
2548 hw->fc.requested_mode = e1000_fc_full;
2549 }
2550
2551 /*
2552 * Save off the requested flow control mode for use later. Depending
2553 * on the link partner's capabilities, we may or may not use this mode.
2554 */
2555 hw->fc.current_mode = hw->fc.requested_mode;
2556
2557 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2558 hw->fc.current_mode);
2559
2560 /* Continue to configure the copper link. */
2561 ret_val = e1000_setup_copper_link_ich8lan(hw);
2562 if (ret_val)
2563 return ret_val;
2564
2565 ew32(FCTTV, hw->fc.pause_time);
2566 if ((hw->phy.type == e1000_phy_82578) ||
2567 (hw->phy.type == e1000_phy_82577)) {
2568 ret_val = hw->phy.ops.write_phy_reg(hw,
2569 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2570 hw->fc.pause_time);
2571 if (ret_val)
2572 return ret_val;
2573 }
2574
2575 return e1000e_set_fc_watermarks(hw);
2576 }
2577
2578 /**
2579 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2580 * @hw: pointer to the HW structure
2581 *
2582 * Configures the kumeran interface to the PHY to wait the appropriate time
2583 * when polling the PHY, then call the generic setup_copper_link to finish
2584 * configuring the copper link.
2585 **/
2586 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2587 {
2588 u32 ctrl;
2589 s32 ret_val;
2590 u16 reg_data;
2591
2592 ctrl = er32(CTRL);
2593 ctrl |= E1000_CTRL_SLU;
2594 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2595 ew32(CTRL, ctrl);
2596
2597 /*
2598 * Set the mac to wait the maximum time between each iteration
2599 * and increase the max iterations when polling the phy;
2600 * this fixes erroneous timeouts at 10Mbps.
2601 */
2602 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2603 if (ret_val)
2604 return ret_val;
2605 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2606 if (ret_val)
2607 return ret_val;
2608 reg_data |= 0x3F;
2609 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2610 if (ret_val)
2611 return ret_val;
2612
2613 switch (hw->phy.type) {
2614 case e1000_phy_igp_3:
2615 ret_val = e1000e_copper_link_setup_igp(hw);
2616 if (ret_val)
2617 return ret_val;
2618 break;
2619 case e1000_phy_bm:
2620 case e1000_phy_82578:
2621 ret_val = e1000e_copper_link_setup_m88(hw);
2622 if (ret_val)
2623 return ret_val;
2624 break;
2625 case e1000_phy_82577:
2626 ret_val = e1000_copper_link_setup_82577(hw);
2627 if (ret_val)
2628 return ret_val;
2629 break;
2630 case e1000_phy_ife:
2631 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2632 &reg_data);
2633 if (ret_val)
2634 return ret_val;
2635
2636 reg_data &= ~IFE_PMC_AUTO_MDIX;
2637
2638 switch (hw->phy.mdix) {
2639 case 1:
2640 reg_data &= ~IFE_PMC_FORCE_MDIX;
2641 break;
2642 case 2:
2643 reg_data |= IFE_PMC_FORCE_MDIX;
2644 break;
2645 case 0:
2646 default:
2647 reg_data |= IFE_PMC_AUTO_MDIX;
2648 break;
2649 }
2650 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2651 reg_data);
2652 if (ret_val)
2653 return ret_val;
2654 break;
2655 default:
2656 break;
2657 }
2658 return e1000e_setup_copper_link(hw);
2659 }
2660
2661 /**
2662 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2663 * @hw: pointer to the HW structure
2664 * @speed: pointer to store current link speed
2665 * @duplex: pointer to store the current link duplex
2666 *
2667 * Calls the generic get_speed_and_duplex to retrieve the current link
2668 * information and then calls the Kumeran lock loss workaround for links at
2669 * gigabit speeds.
2670 **/
2671 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2672 u16 *duplex)
2673 {
2674 s32 ret_val;
2675
2676 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2677 if (ret_val)
2678 return ret_val;
2679
2680 if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
2681 ret_val = e1000e_write_kmrn_reg(hw,
2682 E1000_KMRNCTRLSTA_K1_CONFIG,
2683 E1000_KMRNCTRLSTA_K1_DISABLE);
2684 if (ret_val)
2685 return ret_val;
2686 }
2687
2688 if ((hw->mac.type == e1000_ich8lan) &&
2689 (hw->phy.type == e1000_phy_igp_3) &&
2690 (*speed == SPEED_1000)) {
2691 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2692 }
2693
2694 return ret_val;
2695 }
2696
2697 /**
2698 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2699 * @hw: pointer to the HW structure
2700 *
2701 * Work-around for 82566 Kumeran PCS lock loss:
2702 * On link status change (i.e. PCI reset, speed change) and link is up and
2703 * speed is gigabit-
2704 * 0) if workaround is optionally disabled do nothing
2705 * 1) wait 1ms for Kumeran link to come up
2706 * 2) check Kumeran Diagnostic register PCS lock loss bit
2707 * 3) if not set the link is locked (all is good), otherwise...
2708 * 4) reset the PHY
2709 * 5) repeat up to 10 times
2710 * Note: this is only called for IGP3 copper when speed is 1gb.
2711 **/
2712 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2713 {
2714 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2715 u32 phy_ctrl;
2716 s32 ret_val;
2717 u16 i, data;
2718 bool link;
2719
2720 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2721 return 0;
2722
2723 /*
2724 * Make sure link is up before proceeding. If not just return.
2725 * Attempting this while link is negotiating fouled up link
2726 * stability
2727 */
2728 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2729 if (!link)
2730 return 0;
2731
2732 for (i = 0; i < 10; i++) {
2733 /* read once to clear */
2734 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2735 if (ret_val)
2736 return ret_val;
2737 /* and again to get new status */
2738 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2739 if (ret_val)
2740 return ret_val;
2741
2742 /* check for PCS lock */
2743 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2744 return 0;
2745
2746 /* Issue PHY reset */
2747 e1000_phy_hw_reset(hw);
2748 mdelay(5);
2749 }
2750 /* Disable GigE link negotiation */
2751 phy_ctrl = er32(PHY_CTRL);
2752 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2753 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2754 ew32(PHY_CTRL, phy_ctrl);
2755
2756 /*
2757 * Call gig speed drop workaround on Gig disable before accessing
2758 * any PHY registers
2759 */
2760 e1000e_gig_downshift_workaround_ich8lan(hw);
2761
2762 /* unable to acquire PCS lock */
2763 return -E1000_ERR_PHY;
2764 }
2765
2766 /**
2767 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2768 * @hw: pointer to the HW structure
2769 * @state: boolean value used to set the current Kumeran workaround state
2770 *
2771 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2772 * /disabled - FALSE).
2773 **/
2774 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2775 bool state)
2776 {
2777 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2778
2779 if (hw->mac.type != e1000_ich8lan) {
2780 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2781 return;
2782 }
2783
2784 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2785 }
2786
2787 /**
2788 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2789 * @hw: pointer to the HW structure
2790 *
2791 * Workaround for 82566 power-down on D3 entry:
2792 * 1) disable gigabit link
2793 * 2) write VR power-down enable
2794 * 3) read it back
2795 * Continue if successful, else issue LCD reset and repeat
2796 **/
2797 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2798 {
2799 u32 reg;
2800 u16 data;
2801 u8 retry = 0;
2802
2803 if (hw->phy.type != e1000_phy_igp_3)
2804 return;
2805
2806 /* Try the workaround twice (if needed) */
2807 do {
2808 /* Disable link */
2809 reg = er32(PHY_CTRL);
2810 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2811 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2812 ew32(PHY_CTRL, reg);
2813
2814 /*
2815 * Call gig speed drop workaround on Gig disable before
2816 * accessing any PHY registers
2817 */
2818 if (hw->mac.type == e1000_ich8lan)
2819 e1000e_gig_downshift_workaround_ich8lan(hw);
2820
2821 /* Write VR power-down enable */
2822 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2823 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2824 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2825
2826 /* Read it back and test */
2827 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2828 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2829 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2830 break;
2831
2832 /* Issue PHY reset and repeat at most one more time */
2833 reg = er32(CTRL);
2834 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2835 retry++;
2836 } while (retry);
2837 }
2838
2839 /**
2840 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2841 * @hw: pointer to the HW structure
2842 *
2843 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2844 * LPLU, Gig disable, MDIC PHY reset):
2845 * 1) Set Kumeran Near-end loopback
2846 * 2) Clear Kumeran Near-end loopback
2847 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2848 **/
2849 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2850 {
2851 s32 ret_val;
2852 u16 reg_data;
2853
2854 if ((hw->mac.type != e1000_ich8lan) ||
2855 (hw->phy.type != e1000_phy_igp_3))
2856 return;
2857
2858 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2859 &reg_data);
2860 if (ret_val)
2861 return;
2862 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2863 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2864 reg_data);
2865 if (ret_val)
2866 return;
2867 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2868 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2869 reg_data);
2870 }
2871
2872 /**
2873 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2874 * @hw: pointer to the HW structure
2875 *
2876 * During S0 to Sx transition, it is possible the link remains at gig
2877 * instead of negotiating to a lower speed. Before going to Sx, set
2878 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2879 * to a lower speed.
2880 *
2881 * Should only be called for applicable parts.
2882 **/
2883 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2884 {
2885 u32 phy_ctrl;
2886
2887 switch (hw->mac.type) {
2888 case e1000_ich9lan:
2889 case e1000_ich10lan:
2890 case e1000_pchlan:
2891 phy_ctrl = er32(PHY_CTRL);
2892 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2893 E1000_PHY_CTRL_GBE_DISABLE;
2894 ew32(PHY_CTRL, phy_ctrl);
2895
2896 if (hw->mac.type == e1000_pchlan)
2897 e1000_phy_hw_reset_ich8lan(hw);
2898 default:
2899 break;
2900 }
2901
2902 return;
2903 }
2904
2905 /**
2906 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2907 * @hw: pointer to the HW structure
2908 *
2909 * Return the LED back to the default configuration.
2910 **/
2911 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2912 {
2913 if (hw->phy.type == e1000_phy_ife)
2914 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2915
2916 ew32(LEDCTL, hw->mac.ledctl_default);
2917 return 0;
2918 }
2919
2920 /**
2921 * e1000_led_on_ich8lan - Turn LEDs on
2922 * @hw: pointer to the HW structure
2923 *
2924 * Turn on the LEDs.
2925 **/
2926 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2927 {
2928 if (hw->phy.type == e1000_phy_ife)
2929 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2930 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2931
2932 ew32(LEDCTL, hw->mac.ledctl_mode2);
2933 return 0;
2934 }
2935
2936 /**
2937 * e1000_led_off_ich8lan - Turn LEDs off
2938 * @hw: pointer to the HW structure
2939 *
2940 * Turn off the LEDs.
2941 **/
2942 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2943 {
2944 if (hw->phy.type == e1000_phy_ife)
2945 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2946 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2947
2948 ew32(LEDCTL, hw->mac.ledctl_mode1);
2949 return 0;
2950 }
2951
2952 /**
2953 * e1000_setup_led_pchlan - Configures SW controllable LED
2954 * @hw: pointer to the HW structure
2955 *
2956 * This prepares the SW controllable LED for use.
2957 **/
2958 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2959 {
2960 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2961 (u16)hw->mac.ledctl_mode1);
2962 }
2963
2964 /**
2965 * e1000_cleanup_led_pchlan - Restore the default LED operation
2966 * @hw: pointer to the HW structure
2967 *
2968 * Return the LED back to the default configuration.
2969 **/
2970 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2971 {
2972 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2973 (u16)hw->mac.ledctl_default);
2974 }
2975
2976 /**
2977 * e1000_led_on_pchlan - Turn LEDs on
2978 * @hw: pointer to the HW structure
2979 *
2980 * Turn on the LEDs.
2981 **/
2982 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2983 {
2984 u16 data = (u16)hw->mac.ledctl_mode2;
2985 u32 i, led;
2986
2987 /*
2988 * If no link, then turn LED on by setting the invert bit
2989 * for each LED that's mode is "link_up" in ledctl_mode2.
2990 */
2991 if (!(er32(STATUS) & E1000_STATUS_LU)) {
2992 for (i = 0; i < 3; i++) {
2993 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2994 if ((led & E1000_PHY_LED0_MODE_MASK) !=
2995 E1000_LEDCTL_MODE_LINK_UP)
2996 continue;
2997 if (led & E1000_PHY_LED0_IVRT)
2998 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2999 else
3000 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3001 }
3002 }
3003
3004 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3005 }
3006
3007 /**
3008 * e1000_led_off_pchlan - Turn LEDs off
3009 * @hw: pointer to the HW structure
3010 *
3011 * Turn off the LEDs.
3012 **/
3013 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3014 {
3015 u16 data = (u16)hw->mac.ledctl_mode1;
3016 u32 i, led;
3017
3018 /*
3019 * If no link, then turn LED off by clearing the invert bit
3020 * for each LED that's mode is "link_up" in ledctl_mode1.
3021 */
3022 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3023 for (i = 0; i < 3; i++) {
3024 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3025 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3026 E1000_LEDCTL_MODE_LINK_UP)
3027 continue;
3028 if (led & E1000_PHY_LED0_IVRT)
3029 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3030 else
3031 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3032 }
3033 }
3034
3035 return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3036 }
3037
3038 /**
3039 * e1000_get_cfg_done_ich8lan - Read config done bit
3040 * @hw: pointer to the HW structure
3041 *
3042 * Read the management control register for the config done bit for
3043 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3044 * to read the config done bit, so an error is *ONLY* logged and returns
3045 * 0. If we were to return with error, EEPROM-less silicon
3046 * would not be able to be reset or change link.
3047 **/
3048 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3049 {
3050 u32 bank = 0;
3051
3052 if (hw->mac.type >= e1000_pchlan) {
3053 u32 status = er32(STATUS);
3054
3055 if (status & E1000_STATUS_PHYRA)
3056 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3057 else
3058 hw_dbg(hw,
3059 "PHY Reset Asserted not set - needs delay\n");
3060 }
3061
3062 e1000e_get_cfg_done(hw);
3063
3064 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3065 if ((hw->mac.type != e1000_ich10lan) &&
3066 (hw->mac.type != e1000_pchlan)) {
3067 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3068 (hw->phy.type == e1000_phy_igp_3)) {
3069 e1000e_phy_init_script_igp3(hw);
3070 }
3071 } else {
3072 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3073 /* Maybe we should do a basic PHY config */
3074 hw_dbg(hw, "EEPROM not present\n");
3075 return -E1000_ERR_CONFIG;
3076 }
3077 }
3078
3079 return 0;
3080 }
3081
3082 /**
3083 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3084 * @hw: pointer to the HW structure
3085 *
3086 * Clears hardware counters specific to the silicon family and calls
3087 * clear_hw_cntrs_generic to clear all general purpose counters.
3088 **/
3089 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3090 {
3091 u32 temp;
3092 u16 phy_data;
3093
3094 e1000e_clear_hw_cntrs_base(hw);
3095
3096 temp = er32(ALGNERRC);
3097 temp = er32(RXERRC);
3098 temp = er32(TNCRS);
3099 temp = er32(CEXTERR);
3100 temp = er32(TSCTC);
3101 temp = er32(TSCTFC);
3102
3103 temp = er32(MGTPRC);
3104 temp = er32(MGTPDC);
3105 temp = er32(MGTPTC);
3106
3107 temp = er32(IAC);
3108 temp = er32(ICRXOC);
3109
3110 /* Clear PHY statistics registers */
3111 if ((hw->phy.type == e1000_phy_82578) ||
3112 (hw->phy.type == e1000_phy_82577)) {
3113 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3114 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3115 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3116 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3117 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3118 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3119 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3120 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3121 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3122 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3123 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3124 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3125 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3126 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3127 }
3128 }
3129
3130 static struct e1000_mac_operations ich8_mac_ops = {
3131 .id_led_init = e1000e_id_led_init,
3132 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3133 .check_for_link = e1000_check_for_copper_link_ich8lan,
3134 /* cleanup_led dependent on mac type */
3135 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3136 .get_bus_info = e1000_get_bus_info_ich8lan,
3137 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3138 /* led_on dependent on mac type */
3139 /* led_off dependent on mac type */
3140 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3141 .reset_hw = e1000_reset_hw_ich8lan,
3142 .init_hw = e1000_init_hw_ich8lan,
3143 .setup_link = e1000_setup_link_ich8lan,
3144 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3145 /* id_led_init dependent on mac type */
3146 };
3147
3148 static struct e1000_phy_operations ich8_phy_ops = {
3149 .acquire_phy = e1000_acquire_swflag_ich8lan,
3150 .check_reset_block = e1000_check_reset_block_ich8lan,
3151 .commit_phy = NULL,
3152 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
3153 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3154 .get_cable_length = e1000e_get_cable_length_igp_2,
3155 .get_phy_info = e1000_get_phy_info_ich8lan,
3156 .read_phy_reg = e1000e_read_phy_reg_igp,
3157 .release_phy = e1000_release_swflag_ich8lan,
3158 .reset_phy = e1000_phy_hw_reset_ich8lan,
3159 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3160 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3161 .write_phy_reg = e1000e_write_phy_reg_igp,
3162 };
3163
3164 static struct e1000_nvm_operations ich8_nvm_ops = {
3165 .acquire_nvm = e1000_acquire_swflag_ich8lan,
3166 .read_nvm = e1000_read_nvm_ich8lan,
3167 .release_nvm = e1000_release_swflag_ich8lan,
3168 .update_nvm = e1000_update_nvm_checksum_ich8lan,
3169 .valid_led_default = e1000_valid_led_default_ich8lan,
3170 .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
3171 .write_nvm = e1000_write_nvm_ich8lan,
3172 };
3173
3174 struct e1000_info e1000_ich8_info = {
3175 .mac = e1000_ich8lan,
3176 .flags = FLAG_HAS_WOL
3177 | FLAG_IS_ICH
3178 | FLAG_RX_CSUM_ENABLED
3179 | FLAG_HAS_CTRLEXT_ON_LOAD
3180 | FLAG_HAS_AMT
3181 | FLAG_HAS_FLASH
3182 | FLAG_APME_IN_WUC,
3183 .pba = 8,
3184 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3185 .get_variants = e1000_get_variants_ich8lan,
3186 .mac_ops = &ich8_mac_ops,
3187 .phy_ops = &ich8_phy_ops,
3188 .nvm_ops = &ich8_nvm_ops,
3189 };
3190
3191 struct e1000_info e1000_ich9_info = {
3192 .mac = e1000_ich9lan,
3193 .flags = FLAG_HAS_JUMBO_FRAMES
3194 | FLAG_IS_ICH
3195 | FLAG_HAS_WOL
3196 | FLAG_RX_CSUM_ENABLED
3197 | FLAG_HAS_CTRLEXT_ON_LOAD
3198 | FLAG_HAS_AMT
3199 | FLAG_HAS_ERT
3200 | FLAG_HAS_FLASH
3201 | FLAG_APME_IN_WUC,
3202 .pba = 10,
3203 .max_hw_frame_size = DEFAULT_JUMBO,
3204 .get_variants = e1000_get_variants_ich8lan,
3205 .mac_ops = &ich8_mac_ops,
3206 .phy_ops = &ich8_phy_ops,
3207 .nvm_ops = &ich8_nvm_ops,
3208 };
3209
3210 struct e1000_info e1000_ich10_info = {
3211 .mac = e1000_ich10lan,
3212 .flags = FLAG_HAS_JUMBO_FRAMES
3213 | FLAG_IS_ICH
3214 | FLAG_HAS_WOL
3215 | FLAG_RX_CSUM_ENABLED
3216 | FLAG_HAS_CTRLEXT_ON_LOAD
3217 | FLAG_HAS_AMT
3218 | FLAG_HAS_ERT
3219 | FLAG_HAS_FLASH
3220 | FLAG_APME_IN_WUC,
3221 .pba = 10,
3222 .max_hw_frame_size = DEFAULT_JUMBO,
3223 .get_variants = e1000_get_variants_ich8lan,
3224 .mac_ops = &ich8_mac_ops,
3225 .phy_ops = &ich8_phy_ops,
3226 .nvm_ops = &ich8_nvm_ops,
3227 };
3228
3229 struct e1000_info e1000_pch_info = {
3230 .mac = e1000_pchlan,
3231 .flags = FLAG_IS_ICH
3232 | FLAG_HAS_WOL
3233 | FLAG_RX_CSUM_ENABLED
3234 | FLAG_HAS_CTRLEXT_ON_LOAD
3235 | FLAG_HAS_AMT
3236 | FLAG_HAS_FLASH
3237 | FLAG_HAS_JUMBO_FRAMES
3238 | FLAG_APME_IN_WUC,
3239 .pba = 26,
3240 .max_hw_frame_size = 4096,
3241 .get_variants = e1000_get_variants_ich8lan,
3242 .mac_ops = &ich8_mac_ops,
3243 .phy_ops = &ich8_phy_ops,
3244 .nvm_ops = &ich8_nvm_ops,
3245 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree