1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include "net_driver.h"
22 #include "workarounds.h"
24 /**************************************************************************
28 **************************************************************************
31 /* This is set to 16 for a good reason. In summary, if larger than
32 * 16, the descriptor cache holds more than a default socket
33 * buffer's worth of packets (for UDP we can only have at most one
34 * socket buffer's worth outstanding). This combined with the fact
35 * that we only get 1 TX event per descriptor cache means the NIC
38 #define TX_DC_ENTRIES 16
39 #define TX_DC_ENTRIES_ORDER 1
41 #define RX_DC_ENTRIES 64
42 #define RX_DC_ENTRIES_ORDER 3
44 /* RX FIFO XOFF watermark
46 * When the amount of the RX FIFO increases used increases past this
47 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
48 * This also has an effect on RX/TX arbitration
50 int efx_nic_rx_xoff_thresh
= -1;
51 module_param_named(rx_xoff_thresh_bytes
, efx_nic_rx_xoff_thresh
, int, 0644);
52 MODULE_PARM_DESC(rx_xoff_thresh_bytes
, "RX fifo XOFF threshold");
54 /* RX FIFO XON watermark
56 * When the amount of the RX FIFO used decreases below this
57 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
58 * This also has an effect on RX/TX arbitration
60 int efx_nic_rx_xon_thresh
= -1;
61 module_param_named(rx_xon_thresh_bytes
, efx_nic_rx_xon_thresh
, int, 0644);
62 MODULE_PARM_DESC(rx_xon_thresh_bytes
, "RX fifo XON threshold");
64 /* If EFX_MAX_INT_ERRORS internal errors occur within
65 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
68 #define EFX_INT_ERROR_EXPIRE 3600
69 #define EFX_MAX_INT_ERRORS 5
71 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
73 #define EFX_FLUSH_INTERVAL 10
74 #define EFX_FLUSH_POLL_COUNT 100
76 /* Size and alignment of special buffers (4KB) */
77 #define EFX_BUF_SIZE 4096
79 /* Depth of RX flush request fifo */
80 #define EFX_RX_FLUSH_COUNT 4
82 /**************************************************************************
84 * Solarstorm hardware access
86 **************************************************************************/
88 static inline void efx_write_buf_tbl(struct efx_nic
*efx
, efx_qword_t
*value
,
91 efx_sram_writeq(efx
, efx
->membase
+ efx
->type
->buf_tbl_base
,
95 /* Read the current event from the event queue */
96 static inline efx_qword_t
*efx_event(struct efx_channel
*channel
,
99 return (((efx_qword_t
*) (channel
->eventq
.addr
)) + index
);
102 /* See if an event is present
104 * We check both the high and low dword of the event for all ones. We
105 * wrote all ones when we cleared the event, and no valid event can
106 * have all ones in either its high or low dwords. This approach is
107 * robust against reordering.
109 * Note that using a single 64-bit comparison is incorrect; even
110 * though the CPU read will be atomic, the DMA write may not be.
112 static inline int efx_event_present(efx_qword_t
*event
)
114 return (!(EFX_DWORD_IS_ALL_ONES(event
->dword
[0]) |
115 EFX_DWORD_IS_ALL_ONES(event
->dword
[1])));
118 static bool efx_masked_compare_oword(const efx_oword_t
*a
, const efx_oword_t
*b
,
119 const efx_oword_t
*mask
)
121 return ((a
->u64
[0] ^ b
->u64
[0]) & mask
->u64
[0]) ||
122 ((a
->u64
[1] ^ b
->u64
[1]) & mask
->u64
[1]);
125 int efx_nic_test_registers(struct efx_nic
*efx
,
126 const struct efx_nic_register_test
*regs
,
129 unsigned address
= 0, i
, j
;
130 efx_oword_t mask
, imask
, original
, reg
, buf
;
132 /* Falcon should be in loopback to isolate the XMAC from the PHY */
133 WARN_ON(!LOOPBACK_INTERNAL(efx
));
135 for (i
= 0; i
< n_regs
; ++i
) {
136 address
= regs
[i
].address
;
137 mask
= imask
= regs
[i
].mask
;
138 EFX_INVERT_OWORD(imask
);
140 efx_reado(efx
, &original
, address
);
142 /* bit sweep on and off */
143 for (j
= 0; j
< 128; j
++) {
144 if (!EFX_EXTRACT_OWORD32(mask
, j
, j
))
147 /* Test this testable bit can be set in isolation */
148 EFX_AND_OWORD(reg
, original
, mask
);
149 EFX_SET_OWORD32(reg
, j
, j
, 1);
151 efx_writeo(efx
, ®
, address
);
152 efx_reado(efx
, &buf
, address
);
154 if (efx_masked_compare_oword(®
, &buf
, &mask
))
157 /* Test this testable bit can be cleared in isolation */
158 EFX_OR_OWORD(reg
, original
, mask
);
159 EFX_SET_OWORD32(reg
, j
, j
, 0);
161 efx_writeo(efx
, ®
, address
);
162 efx_reado(efx
, &buf
, address
);
164 if (efx_masked_compare_oword(®
, &buf
, &mask
))
168 efx_writeo(efx
, &original
, address
);
174 EFX_ERR(efx
, "wrote "EFX_OWORD_FMT
" read "EFX_OWORD_FMT
175 " at address 0x%x mask "EFX_OWORD_FMT
"\n", EFX_OWORD_VAL(reg
),
176 EFX_OWORD_VAL(buf
), address
, EFX_OWORD_VAL(mask
));
180 /**************************************************************************
182 * Special buffer handling
183 * Special buffers are used for event queues and the TX and RX
186 *************************************************************************/
189 * Initialise a special buffer
191 * This will define a buffer (previously allocated via
192 * efx_alloc_special_buffer()) in the buffer table, allowing
193 * it to be used for event queues, descriptor rings etc.
196 efx_init_special_buffer(struct efx_nic
*efx
, struct efx_special_buffer
*buffer
)
198 efx_qword_t buf_desc
;
203 EFX_BUG_ON_PARANOID(!buffer
->addr
);
205 /* Write buffer descriptors to NIC */
206 for (i
= 0; i
< buffer
->entries
; i
++) {
207 index
= buffer
->index
+ i
;
208 dma_addr
= buffer
->dma_addr
+ (i
* 4096);
209 EFX_LOG(efx
, "mapping special buffer %d at %llx\n",
210 index
, (unsigned long long)dma_addr
);
211 EFX_POPULATE_QWORD_3(buf_desc
,
212 FRF_AZ_BUF_ADR_REGION
, 0,
213 FRF_AZ_BUF_ADR_FBUF
, dma_addr
>> 12,
214 FRF_AZ_BUF_OWNER_ID_FBUF
, 0);
215 efx_write_buf_tbl(efx
, &buf_desc
, index
);
219 /* Unmaps a buffer and clears the buffer table entries */
221 efx_fini_special_buffer(struct efx_nic
*efx
, struct efx_special_buffer
*buffer
)
223 efx_oword_t buf_tbl_upd
;
224 unsigned int start
= buffer
->index
;
225 unsigned int end
= (buffer
->index
+ buffer
->entries
- 1);
227 if (!buffer
->entries
)
230 EFX_LOG(efx
, "unmapping special buffers %d-%d\n",
231 buffer
->index
, buffer
->index
+ buffer
->entries
- 1);
233 EFX_POPULATE_OWORD_4(buf_tbl_upd
,
234 FRF_AZ_BUF_UPD_CMD
, 0,
235 FRF_AZ_BUF_CLR_CMD
, 1,
236 FRF_AZ_BUF_CLR_END_ID
, end
,
237 FRF_AZ_BUF_CLR_START_ID
, start
);
238 efx_writeo(efx
, &buf_tbl_upd
, FR_AZ_BUF_TBL_UPD
);
242 * Allocate a new special buffer
244 * This allocates memory for a new buffer, clears it and allocates a
245 * new buffer ID range. It does not write into the buffer table.
247 * This call will allocate 4KB buffers, since 8KB buffers can't be
248 * used for event queues and descriptor rings.
250 static int efx_alloc_special_buffer(struct efx_nic
*efx
,
251 struct efx_special_buffer
*buffer
,
254 len
= ALIGN(len
, EFX_BUF_SIZE
);
256 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
261 buffer
->entries
= len
/ EFX_BUF_SIZE
;
262 BUG_ON(buffer
->dma_addr
& (EFX_BUF_SIZE
- 1));
264 /* All zeros is a potentially valid event so memset to 0xff */
265 memset(buffer
->addr
, 0xff, len
);
267 /* Select new buffer ID */
268 buffer
->index
= efx
->next_buffer_table
;
269 efx
->next_buffer_table
+= buffer
->entries
;
271 EFX_LOG(efx
, "allocating special buffers %d-%d at %llx+%x "
272 "(virt %p phys %llx)\n", buffer
->index
,
273 buffer
->index
+ buffer
->entries
- 1,
274 (u64
)buffer
->dma_addr
, len
,
275 buffer
->addr
, (u64
)virt_to_phys(buffer
->addr
));
281 efx_free_special_buffer(struct efx_nic
*efx
, struct efx_special_buffer
*buffer
)
286 EFX_LOG(efx
, "deallocating special buffers %d-%d at %llx+%x "
287 "(virt %p phys %llx)\n", buffer
->index
,
288 buffer
->index
+ buffer
->entries
- 1,
289 (u64
)buffer
->dma_addr
, buffer
->len
,
290 buffer
->addr
, (u64
)virt_to_phys(buffer
->addr
));
292 pci_free_consistent(efx
->pci_dev
, buffer
->len
, buffer
->addr
,
298 /**************************************************************************
300 * Generic buffer handling
301 * These buffers are used for interrupt status and MAC stats
303 **************************************************************************/
305 int efx_nic_alloc_buffer(struct efx_nic
*efx
, struct efx_buffer
*buffer
,
308 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
313 memset(buffer
->addr
, 0, len
);
317 void efx_nic_free_buffer(struct efx_nic
*efx
, struct efx_buffer
*buffer
)
320 pci_free_consistent(efx
->pci_dev
, buffer
->len
,
321 buffer
->addr
, buffer
->dma_addr
);
326 /**************************************************************************
330 **************************************************************************/
332 /* Returns a pointer to the specified transmit descriptor in the TX
333 * descriptor queue belonging to the specified channel.
335 static inline efx_qword_t
*
336 efx_tx_desc(struct efx_tx_queue
*tx_queue
, unsigned int index
)
338 return (((efx_qword_t
*) (tx_queue
->txd
.addr
)) + index
);
341 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
342 static inline void efx_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
347 write_ptr
= tx_queue
->write_count
& EFX_TXQ_MASK
;
348 EFX_POPULATE_DWORD_1(reg
, FRF_AZ_TX_DESC_WPTR_DWORD
, write_ptr
);
349 efx_writed_page(tx_queue
->efx
, ®
,
350 FR_AZ_TX_DESC_UPD_DWORD_P0
, tx_queue
->queue
);
354 /* For each entry inserted into the software descriptor ring, create a
355 * descriptor in the hardware TX descriptor ring (in host memory), and
358 void efx_nic_push_buffers(struct efx_tx_queue
*tx_queue
)
361 struct efx_tx_buffer
*buffer
;
365 BUG_ON(tx_queue
->write_count
== tx_queue
->insert_count
);
368 write_ptr
= tx_queue
->write_count
& EFX_TXQ_MASK
;
369 buffer
= &tx_queue
->buffer
[write_ptr
];
370 txd
= efx_tx_desc(tx_queue
, write_ptr
);
371 ++tx_queue
->write_count
;
373 /* Create TX descriptor ring entry */
374 EFX_POPULATE_QWORD_4(*txd
,
375 FSF_AZ_TX_KER_CONT
, buffer
->continuation
,
376 FSF_AZ_TX_KER_BYTE_COUNT
, buffer
->len
,
377 FSF_AZ_TX_KER_BUF_REGION
, 0,
378 FSF_AZ_TX_KER_BUF_ADDR
, buffer
->dma_addr
);
379 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
381 wmb(); /* Ensure descriptors are written before they are fetched */
382 efx_notify_tx_desc(tx_queue
);
385 /* Allocate hardware resources for a TX queue */
386 int efx_nic_probe_tx(struct efx_tx_queue
*tx_queue
)
388 struct efx_nic
*efx
= tx_queue
->efx
;
389 BUILD_BUG_ON(EFX_TXQ_SIZE
< 512 || EFX_TXQ_SIZE
> 4096 ||
390 EFX_TXQ_SIZE
& EFX_TXQ_MASK
);
391 return efx_alloc_special_buffer(efx
, &tx_queue
->txd
,
392 EFX_TXQ_SIZE
* sizeof(efx_qword_t
));
395 void efx_nic_init_tx(struct efx_tx_queue
*tx_queue
)
397 efx_oword_t tx_desc_ptr
;
398 struct efx_nic
*efx
= tx_queue
->efx
;
400 tx_queue
->flushed
= FLUSH_NONE
;
402 /* Pin TX descriptor ring */
403 efx_init_special_buffer(efx
, &tx_queue
->txd
);
405 /* Push TX descriptor ring to card */
406 EFX_POPULATE_OWORD_10(tx_desc_ptr
,
407 FRF_AZ_TX_DESCQ_EN
, 1,
408 FRF_AZ_TX_ISCSI_DDIG_EN
, 0,
409 FRF_AZ_TX_ISCSI_HDIG_EN
, 0,
410 FRF_AZ_TX_DESCQ_BUF_BASE_ID
, tx_queue
->txd
.index
,
411 FRF_AZ_TX_DESCQ_EVQ_ID
,
412 tx_queue
->channel
->channel
,
413 FRF_AZ_TX_DESCQ_OWNER_ID
, 0,
414 FRF_AZ_TX_DESCQ_LABEL
, tx_queue
->queue
,
415 FRF_AZ_TX_DESCQ_SIZE
,
416 __ffs(tx_queue
->txd
.entries
),
417 FRF_AZ_TX_DESCQ_TYPE
, 0,
418 FRF_BZ_TX_NON_IP_DROP_DIS
, 1);
420 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) {
421 int csum
= tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
;
422 EFX_SET_OWORD_FIELD(tx_desc_ptr
, FRF_BZ_TX_IP_CHKSM_DIS
, !csum
);
423 EFX_SET_OWORD_FIELD(tx_desc_ptr
, FRF_BZ_TX_TCP_CHKSM_DIS
,
427 efx_writeo_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
430 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
) {
433 /* Only 128 bits in this register */
434 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT
>= 128);
436 efx_reado(efx
, ®
, FR_AA_TX_CHKSM_CFG
);
437 if (tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
)
438 clear_bit_le(tx_queue
->queue
, (void *)®
);
440 set_bit_le(tx_queue
->queue
, (void *)®
);
441 efx_writeo(efx
, ®
, FR_AA_TX_CHKSM_CFG
);
445 static void efx_flush_tx_queue(struct efx_tx_queue
*tx_queue
)
447 struct efx_nic
*efx
= tx_queue
->efx
;
448 efx_oword_t tx_flush_descq
;
450 tx_queue
->flushed
= FLUSH_PENDING
;
452 /* Post a flush command */
453 EFX_POPULATE_OWORD_2(tx_flush_descq
,
454 FRF_AZ_TX_FLUSH_DESCQ_CMD
, 1,
455 FRF_AZ_TX_FLUSH_DESCQ
, tx_queue
->queue
);
456 efx_writeo(efx
, &tx_flush_descq
, FR_AZ_TX_FLUSH_DESCQ
);
459 void efx_nic_fini_tx(struct efx_tx_queue
*tx_queue
)
461 struct efx_nic
*efx
= tx_queue
->efx
;
462 efx_oword_t tx_desc_ptr
;
464 /* The queue should have been flushed */
465 WARN_ON(tx_queue
->flushed
!= FLUSH_DONE
);
467 /* Remove TX descriptor ring from card */
468 EFX_ZERO_OWORD(tx_desc_ptr
);
469 efx_writeo_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
472 /* Unpin TX descriptor ring */
473 efx_fini_special_buffer(efx
, &tx_queue
->txd
);
476 /* Free buffers backing TX queue */
477 void efx_nic_remove_tx(struct efx_tx_queue
*tx_queue
)
479 efx_free_special_buffer(tx_queue
->efx
, &tx_queue
->txd
);
482 /**************************************************************************
486 **************************************************************************/
488 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
489 static inline efx_qword_t
*
490 efx_rx_desc(struct efx_rx_queue
*rx_queue
, unsigned int index
)
492 return (((efx_qword_t
*) (rx_queue
->rxd
.addr
)) + index
);
495 /* This creates an entry in the RX descriptor queue */
497 efx_build_rx_desc(struct efx_rx_queue
*rx_queue
, unsigned index
)
499 struct efx_rx_buffer
*rx_buf
;
502 rxd
= efx_rx_desc(rx_queue
, index
);
503 rx_buf
= efx_rx_buffer(rx_queue
, index
);
504 EFX_POPULATE_QWORD_3(*rxd
,
505 FSF_AZ_RX_KER_BUF_SIZE
,
507 rx_queue
->efx
->type
->rx_buffer_padding
,
508 FSF_AZ_RX_KER_BUF_REGION
, 0,
509 FSF_AZ_RX_KER_BUF_ADDR
, rx_buf
->dma_addr
);
512 /* This writes to the RX_DESC_WPTR register for the specified receive
515 void efx_nic_notify_rx_desc(struct efx_rx_queue
*rx_queue
)
520 while (rx_queue
->notified_count
!= rx_queue
->added_count
) {
521 efx_build_rx_desc(rx_queue
,
522 rx_queue
->notified_count
&
524 ++rx_queue
->notified_count
;
528 write_ptr
= rx_queue
->added_count
& EFX_RXQ_MASK
;
529 EFX_POPULATE_DWORD_1(reg
, FRF_AZ_RX_DESC_WPTR_DWORD
, write_ptr
);
530 efx_writed_page(rx_queue
->efx
, ®
,
531 FR_AZ_RX_DESC_UPD_DWORD_P0
, rx_queue
->queue
);
534 int efx_nic_probe_rx(struct efx_rx_queue
*rx_queue
)
536 struct efx_nic
*efx
= rx_queue
->efx
;
537 BUILD_BUG_ON(EFX_RXQ_SIZE
< 512 || EFX_RXQ_SIZE
> 4096 ||
538 EFX_RXQ_SIZE
& EFX_RXQ_MASK
);
539 return efx_alloc_special_buffer(efx
, &rx_queue
->rxd
,
540 EFX_RXQ_SIZE
* sizeof(efx_qword_t
));
543 void efx_nic_init_rx(struct efx_rx_queue
*rx_queue
)
545 efx_oword_t rx_desc_ptr
;
546 struct efx_nic
*efx
= rx_queue
->efx
;
547 bool is_b0
= efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
;
548 bool iscsi_digest_en
= is_b0
;
550 EFX_LOG(efx
, "RX queue %d ring in special buffers %d-%d\n",
551 rx_queue
->queue
, rx_queue
->rxd
.index
,
552 rx_queue
->rxd
.index
+ rx_queue
->rxd
.entries
- 1);
554 rx_queue
->flushed
= FLUSH_NONE
;
556 /* Pin RX descriptor ring */
557 efx_init_special_buffer(efx
, &rx_queue
->rxd
);
559 /* Push RX descriptor ring to card */
560 EFX_POPULATE_OWORD_10(rx_desc_ptr
,
561 FRF_AZ_RX_ISCSI_DDIG_EN
, iscsi_digest_en
,
562 FRF_AZ_RX_ISCSI_HDIG_EN
, iscsi_digest_en
,
563 FRF_AZ_RX_DESCQ_BUF_BASE_ID
, rx_queue
->rxd
.index
,
564 FRF_AZ_RX_DESCQ_EVQ_ID
,
565 rx_queue
->channel
->channel
,
566 FRF_AZ_RX_DESCQ_OWNER_ID
, 0,
567 FRF_AZ_RX_DESCQ_LABEL
, rx_queue
->queue
,
568 FRF_AZ_RX_DESCQ_SIZE
,
569 __ffs(rx_queue
->rxd
.entries
),
570 FRF_AZ_RX_DESCQ_TYPE
, 0 /* kernel queue */ ,
571 /* For >=B0 this is scatter so disable */
572 FRF_AZ_RX_DESCQ_JUMBO
, !is_b0
,
573 FRF_AZ_RX_DESCQ_EN
, 1);
574 efx_writeo_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
578 static void efx_flush_rx_queue(struct efx_rx_queue
*rx_queue
)
580 struct efx_nic
*efx
= rx_queue
->efx
;
581 efx_oword_t rx_flush_descq
;
583 rx_queue
->flushed
= FLUSH_PENDING
;
585 /* Post a flush command */
586 EFX_POPULATE_OWORD_2(rx_flush_descq
,
587 FRF_AZ_RX_FLUSH_DESCQ_CMD
, 1,
588 FRF_AZ_RX_FLUSH_DESCQ
, rx_queue
->queue
);
589 efx_writeo(efx
, &rx_flush_descq
, FR_AZ_RX_FLUSH_DESCQ
);
592 void efx_nic_fini_rx(struct efx_rx_queue
*rx_queue
)
594 efx_oword_t rx_desc_ptr
;
595 struct efx_nic
*efx
= rx_queue
->efx
;
597 /* The queue should already have been flushed */
598 WARN_ON(rx_queue
->flushed
!= FLUSH_DONE
);
600 /* Remove RX descriptor ring from card */
601 EFX_ZERO_OWORD(rx_desc_ptr
);
602 efx_writeo_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
605 /* Unpin RX descriptor ring */
606 efx_fini_special_buffer(efx
, &rx_queue
->rxd
);
609 /* Free buffers backing RX queue */
610 void efx_nic_remove_rx(struct efx_rx_queue
*rx_queue
)
612 efx_free_special_buffer(rx_queue
->efx
, &rx_queue
->rxd
);
615 /**************************************************************************
617 * Event queue processing
618 * Event queues are processed by per-channel tasklets.
620 **************************************************************************/
622 /* Update a channel's event queue's read pointer (RPTR) register
624 * This writes the EVQ_RPTR_REG register for the specified channel's
627 void efx_nic_eventq_read_ack(struct efx_channel
*channel
)
630 struct efx_nic
*efx
= channel
->efx
;
632 EFX_POPULATE_DWORD_1(reg
, FRF_AZ_EVQ_RPTR
, channel
->eventq_read_ptr
);
633 efx_writed_table(efx
, ®
, efx
->type
->evq_rptr_tbl_base
,
637 /* Use HW to insert a SW defined event */
638 void efx_generate_event(struct efx_channel
*channel
, efx_qword_t
*event
)
640 efx_oword_t drv_ev_reg
;
642 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN
!= 0 ||
643 FRF_AZ_DRV_EV_DATA_WIDTH
!= 64);
644 drv_ev_reg
.u32
[0] = event
->u32
[0];
645 drv_ev_reg
.u32
[1] = event
->u32
[1];
646 drv_ev_reg
.u32
[2] = 0;
647 drv_ev_reg
.u32
[3] = 0;
648 EFX_SET_OWORD_FIELD(drv_ev_reg
, FRF_AZ_DRV_EV_QID
, channel
->channel
);
649 efx_writeo(channel
->efx
, &drv_ev_reg
, FR_AZ_DRV_EV
);
652 /* Handle a transmit completion event
654 * The NIC batches TX completion events; the message we receive is of
655 * the form "complete all TX events up to this index".
658 efx_handle_tx_event(struct efx_channel
*channel
, efx_qword_t
*event
)
660 unsigned int tx_ev_desc_ptr
;
661 unsigned int tx_ev_q_label
;
662 struct efx_tx_queue
*tx_queue
;
663 struct efx_nic
*efx
= channel
->efx
;
666 if (likely(EFX_QWORD_FIELD(*event
, FSF_AZ_TX_EV_COMP
))) {
667 /* Transmit completion */
668 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, FSF_AZ_TX_EV_DESC_PTR
);
669 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, FSF_AZ_TX_EV_Q_LABEL
);
670 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
671 tx_packets
= ((tx_ev_desc_ptr
- tx_queue
->read_count
) &
673 channel
->irq_mod_score
+= tx_packets
;
674 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
);
675 } else if (EFX_QWORD_FIELD(*event
, FSF_AZ_TX_EV_WQ_FF_FULL
)) {
676 /* Rewrite the FIFO write pointer */
677 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, FSF_AZ_TX_EV_Q_LABEL
);
678 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
680 if (efx_dev_registered(efx
))
681 netif_tx_lock(efx
->net_dev
);
682 efx_notify_tx_desc(tx_queue
);
683 if (efx_dev_registered(efx
))
684 netif_tx_unlock(efx
->net_dev
);
685 } else if (EFX_QWORD_FIELD(*event
, FSF_AZ_TX_EV_PKT_ERR
) &&
686 EFX_WORKAROUND_10727(efx
)) {
687 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
689 EFX_ERR(efx
, "channel %d unexpected TX event "
690 EFX_QWORD_FMT
"\n", channel
->channel
,
691 EFX_QWORD_VAL(*event
));
697 /* Detect errors included in the rx_evt_pkt_ok bit. */
698 static void efx_handle_rx_not_ok(struct efx_rx_queue
*rx_queue
,
699 const efx_qword_t
*event
,
703 struct efx_nic
*efx
= rx_queue
->efx
;
704 bool rx_ev_buf_owner_id_err
, rx_ev_ip_hdr_chksum_err
;
705 bool rx_ev_tcp_udp_chksum_err
, rx_ev_eth_crc_err
;
706 bool rx_ev_frm_trunc
, rx_ev_drib_nib
, rx_ev_tobe_disc
;
707 bool rx_ev_other_err
, rx_ev_pause_frm
;
708 bool rx_ev_hdr_type
, rx_ev_mcast_pkt
;
709 unsigned rx_ev_pkt_type
;
711 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_HDR_TYPE
);
712 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_MCAST_PKT
);
713 rx_ev_tobe_disc
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_TOBE_DISC
);
714 rx_ev_pkt_type
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_PKT_TYPE
);
715 rx_ev_buf_owner_id_err
= EFX_QWORD_FIELD(*event
,
716 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR
);
717 rx_ev_ip_hdr_chksum_err
= EFX_QWORD_FIELD(*event
,
718 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR
);
719 rx_ev_tcp_udp_chksum_err
= EFX_QWORD_FIELD(*event
,
720 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR
);
721 rx_ev_eth_crc_err
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_ETH_CRC_ERR
);
722 rx_ev_frm_trunc
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_FRM_TRUNC
);
723 rx_ev_drib_nib
= ((efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) ?
724 0 : EFX_QWORD_FIELD(*event
, FSF_AA_RX_EV_DRIB_NIB
));
725 rx_ev_pause_frm
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_PAUSE_FRM_ERR
);
727 /* Every error apart from tobe_disc and pause_frm */
728 rx_ev_other_err
= (rx_ev_drib_nib
| rx_ev_tcp_udp_chksum_err
|
729 rx_ev_buf_owner_id_err
| rx_ev_eth_crc_err
|
730 rx_ev_frm_trunc
| rx_ev_ip_hdr_chksum_err
);
732 /* Count errors that are not in MAC stats. Ignore expected
733 * checksum errors during self-test. */
735 ++rx_queue
->channel
->n_rx_frm_trunc
;
736 else if (rx_ev_tobe_disc
)
737 ++rx_queue
->channel
->n_rx_tobe_disc
;
738 else if (!efx
->loopback_selftest
) {
739 if (rx_ev_ip_hdr_chksum_err
)
740 ++rx_queue
->channel
->n_rx_ip_hdr_chksum_err
;
741 else if (rx_ev_tcp_udp_chksum_err
)
742 ++rx_queue
->channel
->n_rx_tcp_udp_chksum_err
;
745 /* The frame must be discarded if any of these are true. */
746 *discard
= (rx_ev_eth_crc_err
| rx_ev_frm_trunc
| rx_ev_drib_nib
|
747 rx_ev_tobe_disc
| rx_ev_pause_frm
);
749 /* TOBE_DISC is expected on unicast mismatches; don't print out an
750 * error message. FRM_TRUNC indicates RXDP dropped the packet due
751 * to a FIFO overflow.
753 #ifdef EFX_ENABLE_DEBUG
754 if (rx_ev_other_err
) {
755 EFX_INFO_RL(efx
, " RX queue %d unexpected RX event "
756 EFX_QWORD_FMT
"%s%s%s%s%s%s%s%s\n",
757 rx_queue
->queue
, EFX_QWORD_VAL(*event
),
758 rx_ev_buf_owner_id_err
? " [OWNER_ID_ERR]" : "",
759 rx_ev_ip_hdr_chksum_err
?
760 " [IP_HDR_CHKSUM_ERR]" : "",
761 rx_ev_tcp_udp_chksum_err
?
762 " [TCP_UDP_CHKSUM_ERR]" : "",
763 rx_ev_eth_crc_err
? " [ETH_CRC_ERR]" : "",
764 rx_ev_frm_trunc
? " [FRM_TRUNC]" : "",
765 rx_ev_drib_nib
? " [DRIB_NIB]" : "",
766 rx_ev_tobe_disc
? " [TOBE_DISC]" : "",
767 rx_ev_pause_frm
? " [PAUSE]" : "");
772 /* Handle receive events that are not in-order. */
774 efx_handle_rx_bad_index(struct efx_rx_queue
*rx_queue
, unsigned index
)
776 struct efx_nic
*efx
= rx_queue
->efx
;
777 unsigned expected
, dropped
;
779 expected
= rx_queue
->removed_count
& EFX_RXQ_MASK
;
780 dropped
= (index
- expected
) & EFX_RXQ_MASK
;
781 EFX_INFO(efx
, "dropped %d events (index=%d expected=%d)\n",
782 dropped
, index
, expected
);
784 efx_schedule_reset(efx
, EFX_WORKAROUND_5676(efx
) ?
785 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
788 /* Handle a packet received event
790 * The NIC gives a "discard" flag if it's a unicast packet with the
791 * wrong destination address
792 * Also "is multicast" and "matches multicast filter" flags can be used to
793 * discard non-matching multicast packets.
796 efx_handle_rx_event(struct efx_channel
*channel
, const efx_qword_t
*event
)
798 unsigned int rx_ev_desc_ptr
, rx_ev_byte_cnt
;
799 unsigned int rx_ev_hdr_type
, rx_ev_mcast_pkt
;
800 unsigned expected_ptr
;
801 bool rx_ev_pkt_ok
, discard
= false, checksummed
;
802 struct efx_rx_queue
*rx_queue
;
803 struct efx_nic
*efx
= channel
->efx
;
805 /* Basic packet information */
806 rx_ev_byte_cnt
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_BYTE_CNT
);
807 rx_ev_pkt_ok
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_PKT_OK
);
808 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_HDR_TYPE
);
809 WARN_ON(EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_JUMBO_CONT
));
810 WARN_ON(EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_SOP
) != 1);
811 WARN_ON(EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_Q_LABEL
) !=
814 rx_queue
= &efx
->rx_queue
[channel
->channel
];
816 rx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_DESC_PTR
);
817 expected_ptr
= rx_queue
->removed_count
& EFX_RXQ_MASK
;
818 if (unlikely(rx_ev_desc_ptr
!= expected_ptr
))
819 efx_handle_rx_bad_index(rx_queue
, rx_ev_desc_ptr
);
821 if (likely(rx_ev_pkt_ok
)) {
822 /* If packet is marked as OK and packet type is TCP/IP or
823 * UDP/IP, then we can rely on the hardware checksum.
826 likely(efx
->rx_checksum_enabled
) &&
827 (rx_ev_hdr_type
== FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP
||
828 rx_ev_hdr_type
== FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP
);
830 efx_handle_rx_not_ok(rx_queue
, event
, &rx_ev_pkt_ok
, &discard
);
834 /* Detect multicast packets that didn't match the filter */
835 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_MCAST_PKT
);
836 if (rx_ev_mcast_pkt
) {
837 unsigned int rx_ev_mcast_hash_match
=
838 EFX_QWORD_FIELD(*event
, FSF_AZ_RX_EV_MCAST_HASH_MATCH
);
840 if (unlikely(!rx_ev_mcast_hash_match
)) {
841 ++channel
->n_rx_mcast_mismatch
;
846 channel
->irq_mod_score
+= 2;
848 /* Handle received packet */
849 efx_rx_packet(rx_queue
, rx_ev_desc_ptr
, rx_ev_byte_cnt
,
850 checksummed
, discard
);
853 /* Global events are basically PHY events */
855 efx_handle_global_event(struct efx_channel
*channel
, efx_qword_t
*event
)
857 struct efx_nic
*efx
= channel
->efx
;
858 bool handled
= false;
860 if (EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_G_PHY0_INTR
) ||
861 EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_XG_PHY0_INTR
) ||
862 EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_XFP_PHY0_INTR
)) {
867 if ((efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) &&
868 EFX_QWORD_FIELD(*event
, FSF_BB_GLB_EV_XG_MGT_INTR
)) {
869 efx
->xmac_poll_required
= true;
873 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
?
874 EFX_QWORD_FIELD(*event
, FSF_AA_GLB_EV_RX_RECOVERY
) :
875 EFX_QWORD_FIELD(*event
, FSF_BB_GLB_EV_RX_RECOVERY
)) {
876 EFX_ERR(efx
, "channel %d seen global RX_RESET "
877 "event. Resetting.\n", channel
->channel
);
879 atomic_inc(&efx
->rx_reset
);
880 efx_schedule_reset(efx
, EFX_WORKAROUND_6555(efx
) ?
881 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
886 EFX_ERR(efx
, "channel %d unknown global event "
887 EFX_QWORD_FMT
"\n", channel
->channel
,
888 EFX_QWORD_VAL(*event
));
892 efx_handle_driver_event(struct efx_channel
*channel
, efx_qword_t
*event
)
894 struct efx_nic
*efx
= channel
->efx
;
895 unsigned int ev_sub_code
;
896 unsigned int ev_sub_data
;
898 ev_sub_code
= EFX_QWORD_FIELD(*event
, FSF_AZ_DRIVER_EV_SUBCODE
);
899 ev_sub_data
= EFX_QWORD_FIELD(*event
, FSF_AZ_DRIVER_EV_SUBDATA
);
901 switch (ev_sub_code
) {
902 case FSE_AZ_TX_DESCQ_FLS_DONE_EV
:
903 EFX_TRACE(efx
, "channel %d TXQ %d flushed\n",
904 channel
->channel
, ev_sub_data
);
906 case FSE_AZ_RX_DESCQ_FLS_DONE_EV
:
907 EFX_TRACE(efx
, "channel %d RXQ %d flushed\n",
908 channel
->channel
, ev_sub_data
);
910 case FSE_AZ_EVQ_INIT_DONE_EV
:
911 EFX_LOG(efx
, "channel %d EVQ %d initialised\n",
912 channel
->channel
, ev_sub_data
);
914 case FSE_AZ_SRM_UPD_DONE_EV
:
915 EFX_TRACE(efx
, "channel %d SRAM update done\n",
918 case FSE_AZ_WAKE_UP_EV
:
919 EFX_TRACE(efx
, "channel %d RXQ %d wakeup event\n",
920 channel
->channel
, ev_sub_data
);
922 case FSE_AZ_TIMER_EV
:
923 EFX_TRACE(efx
, "channel %d RX queue %d timer expired\n",
924 channel
->channel
, ev_sub_data
);
926 case FSE_AA_RX_RECOVER_EV
:
927 EFX_ERR(efx
, "channel %d seen DRIVER RX_RESET event. "
928 "Resetting.\n", channel
->channel
);
929 atomic_inc(&efx
->rx_reset
);
930 efx_schedule_reset(efx
,
931 EFX_WORKAROUND_6555(efx
) ?
932 RESET_TYPE_RX_RECOVERY
:
935 case FSE_BZ_RX_DSC_ERROR_EV
:
936 EFX_ERR(efx
, "RX DMA Q %d reports descriptor fetch error."
937 " RX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
938 efx_schedule_reset(efx
, RESET_TYPE_RX_DESC_FETCH
);
940 case FSE_BZ_TX_DSC_ERROR_EV
:
941 EFX_ERR(efx
, "TX DMA Q %d reports descriptor fetch error."
942 " TX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
943 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
946 EFX_TRACE(efx
, "channel %d unknown driver event code %d "
947 "data %04x\n", channel
->channel
, ev_sub_code
,
953 int efx_nic_process_eventq(struct efx_channel
*channel
, int budget
)
955 unsigned int read_ptr
;
956 efx_qword_t event
, *p_event
;
961 read_ptr
= channel
->eventq_read_ptr
;
964 p_event
= efx_event(channel
, read_ptr
);
967 if (!efx_event_present(&event
))
971 EFX_TRACE(channel
->efx
, "channel %d event is "EFX_QWORD_FMT
"\n",
972 channel
->channel
, EFX_QWORD_VAL(event
));
974 /* Clear this event by marking it all ones */
975 EFX_SET_QWORD(*p_event
);
977 /* Increment read pointer */
978 read_ptr
= (read_ptr
+ 1) & EFX_EVQ_MASK
;
980 ev_code
= EFX_QWORD_FIELD(event
, FSF_AZ_EV_CODE
);
983 case FSE_AZ_EV_CODE_RX_EV
:
984 efx_handle_rx_event(channel
, &event
);
985 if (++spent
== budget
)
988 case FSE_AZ_EV_CODE_TX_EV
:
989 tx_packets
+= efx_handle_tx_event(channel
, &event
);
990 if (tx_packets
>= EFX_TXQ_SIZE
) {
995 case FSE_AZ_EV_CODE_DRV_GEN_EV
:
996 channel
->eventq_magic
= EFX_QWORD_FIELD(
997 event
, FSF_AZ_DRV_GEN_EV_MAGIC
);
998 EFX_LOG(channel
->efx
, "channel %d received generated "
999 "event "EFX_QWORD_FMT
"\n", channel
->channel
,
1000 EFX_QWORD_VAL(event
));
1002 case FSE_AZ_EV_CODE_GLOBAL_EV
:
1003 efx_handle_global_event(channel
, &event
);
1005 case FSE_AZ_EV_CODE_DRIVER_EV
:
1006 efx_handle_driver_event(channel
, &event
);
1008 case FSE_CZ_EV_CODE_MCDI_EV
:
1009 efx_mcdi_process_event(channel
, &event
);
1012 EFX_ERR(channel
->efx
, "channel %d unknown event type %d"
1013 " (data " EFX_QWORD_FMT
")\n", channel
->channel
,
1014 ev_code
, EFX_QWORD_VAL(event
));
1019 channel
->eventq_read_ptr
= read_ptr
;
1024 /* Allocate buffer table entries for event queue */
1025 int efx_nic_probe_eventq(struct efx_channel
*channel
)
1027 struct efx_nic
*efx
= channel
->efx
;
1028 BUILD_BUG_ON(EFX_EVQ_SIZE
< 512 || EFX_EVQ_SIZE
> 32768 ||
1029 EFX_EVQ_SIZE
& EFX_EVQ_MASK
);
1030 return efx_alloc_special_buffer(efx
, &channel
->eventq
,
1031 EFX_EVQ_SIZE
* sizeof(efx_qword_t
));
1034 void efx_nic_init_eventq(struct efx_channel
*channel
)
1037 struct efx_nic
*efx
= channel
->efx
;
1039 EFX_LOG(efx
, "channel %d event queue in special buffers %d-%d\n",
1040 channel
->channel
, channel
->eventq
.index
,
1041 channel
->eventq
.index
+ channel
->eventq
.entries
- 1);
1043 if (efx_nic_rev(efx
) >= EFX_REV_SIENA_A0
) {
1044 EFX_POPULATE_OWORD_3(reg
,
1045 FRF_CZ_TIMER_Q_EN
, 1,
1046 FRF_CZ_HOST_NOTIFY_MODE
, 0,
1047 FRF_CZ_TIMER_MODE
, FFE_CZ_TIMER_MODE_DIS
);
1048 efx_writeo_table(efx
, ®
, FR_BZ_TIMER_TBL
, channel
->channel
);
1051 /* Pin event queue buffer */
1052 efx_init_special_buffer(efx
, &channel
->eventq
);
1054 /* Fill event queue with all ones (i.e. empty events) */
1055 memset(channel
->eventq
.addr
, 0xff, channel
->eventq
.len
);
1057 /* Push event queue to card */
1058 EFX_POPULATE_OWORD_3(reg
,
1060 FRF_AZ_EVQ_SIZE
, __ffs(channel
->eventq
.entries
),
1061 FRF_AZ_EVQ_BUF_BASE_ID
, channel
->eventq
.index
);
1062 efx_writeo_table(efx
, ®
, efx
->type
->evq_ptr_tbl_base
,
1065 efx
->type
->push_irq_moderation(channel
);
1068 void efx_nic_fini_eventq(struct efx_channel
*channel
)
1071 struct efx_nic
*efx
= channel
->efx
;
1073 /* Remove event queue from card */
1074 EFX_ZERO_OWORD(reg
);
1075 efx_writeo_table(efx
, ®
, efx
->type
->evq_ptr_tbl_base
,
1077 if (efx_nic_rev(efx
) >= EFX_REV_SIENA_A0
)
1078 efx_writeo_table(efx
, ®
, FR_BZ_TIMER_TBL
, channel
->channel
);
1080 /* Unpin event queue */
1081 efx_fini_special_buffer(efx
, &channel
->eventq
);
1084 /* Free buffers backing event queue */
1085 void efx_nic_remove_eventq(struct efx_channel
*channel
)
1087 efx_free_special_buffer(channel
->efx
, &channel
->eventq
);
1091 /* Generates a test event on the event queue. A subsequent call to
1092 * process_eventq() should pick up the event and place the value of
1093 * "magic" into channel->eventq_magic;
1095 void efx_nic_generate_test_event(struct efx_channel
*channel
, unsigned int magic
)
1097 efx_qword_t test_event
;
1099 EFX_POPULATE_QWORD_2(test_event
, FSF_AZ_EV_CODE
,
1100 FSE_AZ_EV_CODE_DRV_GEN_EV
,
1101 FSF_AZ_DRV_GEN_EV_MAGIC
, magic
);
1102 efx_generate_event(channel
, &test_event
);
1105 /**************************************************************************
1109 **************************************************************************/
1112 static void efx_poll_flush_events(struct efx_nic
*efx
)
1114 struct efx_channel
*channel
= &efx
->channel
[0];
1115 struct efx_tx_queue
*tx_queue
;
1116 struct efx_rx_queue
*rx_queue
;
1117 unsigned int read_ptr
= channel
->eventq_read_ptr
;
1118 unsigned int end_ptr
= (read_ptr
- 1) & EFX_EVQ_MASK
;
1121 efx_qword_t
*event
= efx_event(channel
, read_ptr
);
1122 int ev_code
, ev_sub_code
, ev_queue
;
1125 if (!efx_event_present(event
))
1128 ev_code
= EFX_QWORD_FIELD(*event
, FSF_AZ_EV_CODE
);
1129 ev_sub_code
= EFX_QWORD_FIELD(*event
,
1130 FSF_AZ_DRIVER_EV_SUBCODE
);
1131 if (ev_code
== FSE_AZ_EV_CODE_DRIVER_EV
&&
1132 ev_sub_code
== FSE_AZ_TX_DESCQ_FLS_DONE_EV
) {
1133 ev_queue
= EFX_QWORD_FIELD(*event
,
1134 FSF_AZ_DRIVER_EV_SUBDATA
);
1135 if (ev_queue
< EFX_TX_QUEUE_COUNT
) {
1136 tx_queue
= efx
->tx_queue
+ ev_queue
;
1137 tx_queue
->flushed
= FLUSH_DONE
;
1139 } else if (ev_code
== FSE_AZ_EV_CODE_DRIVER_EV
&&
1140 ev_sub_code
== FSE_AZ_RX_DESCQ_FLS_DONE_EV
) {
1141 ev_queue
= EFX_QWORD_FIELD(
1142 *event
, FSF_AZ_DRIVER_EV_RX_DESCQ_ID
);
1143 ev_failed
= EFX_QWORD_FIELD(
1144 *event
, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL
);
1145 if (ev_queue
< efx
->n_rx_queues
) {
1146 rx_queue
= efx
->rx_queue
+ ev_queue
;
1148 ev_failed
? FLUSH_FAILED
: FLUSH_DONE
;
1152 /* We're about to destroy the queue anyway, so
1153 * it's ok to throw away every non-flush event */
1154 EFX_SET_QWORD(*event
);
1156 read_ptr
= (read_ptr
+ 1) & EFX_EVQ_MASK
;
1157 } while (read_ptr
!= end_ptr
);
1159 channel
->eventq_read_ptr
= read_ptr
;
1162 /* Handle tx and rx flushes at the same time, since they run in
1163 * parallel in the hardware and there's no reason for us to
1165 int efx_nic_flush_queues(struct efx_nic
*efx
)
1167 struct efx_rx_queue
*rx_queue
;
1168 struct efx_tx_queue
*tx_queue
;
1169 int i
, tx_pending
, rx_pending
;
1171 /* If necessary prepare the hardware for flushing */
1172 efx
->type
->prepare_flush(efx
);
1174 /* Flush all tx queues in parallel */
1175 efx_for_each_tx_queue(tx_queue
, efx
)
1176 efx_flush_tx_queue(tx_queue
);
1178 /* The hardware supports four concurrent rx flushes, each of which may
1179 * need to be retried if there is an outstanding descriptor fetch */
1180 for (i
= 0; i
< EFX_FLUSH_POLL_COUNT
; ++i
) {
1181 rx_pending
= tx_pending
= 0;
1182 efx_for_each_rx_queue(rx_queue
, efx
) {
1183 if (rx_queue
->flushed
== FLUSH_PENDING
)
1186 efx_for_each_rx_queue(rx_queue
, efx
) {
1187 if (rx_pending
== EFX_RX_FLUSH_COUNT
)
1189 if (rx_queue
->flushed
== FLUSH_FAILED
||
1190 rx_queue
->flushed
== FLUSH_NONE
) {
1191 efx_flush_rx_queue(rx_queue
);
1195 efx_for_each_tx_queue(tx_queue
, efx
) {
1196 if (tx_queue
->flushed
!= FLUSH_DONE
)
1200 if (rx_pending
== 0 && tx_pending
== 0)
1203 msleep(EFX_FLUSH_INTERVAL
);
1204 efx_poll_flush_events(efx
);
1207 /* Mark the queues as all flushed. We're going to return failure
1208 * leading to a reset, or fake up success anyway */
1209 efx_for_each_tx_queue(tx_queue
, efx
) {
1210 if (tx_queue
->flushed
!= FLUSH_DONE
)
1211 EFX_ERR(efx
, "tx queue %d flush command timed out\n",
1213 tx_queue
->flushed
= FLUSH_DONE
;
1215 efx_for_each_rx_queue(rx_queue
, efx
) {
1216 if (rx_queue
->flushed
!= FLUSH_DONE
)
1217 EFX_ERR(efx
, "rx queue %d flush command timed out\n",
1219 rx_queue
->flushed
= FLUSH_DONE
;
1222 if (EFX_WORKAROUND_7803(efx
))
1228 /**************************************************************************
1230 * Hardware interrupts
1231 * The hardware interrupt handler does very little work; all the event
1232 * queue processing is carried out by per-channel tasklets.
1234 **************************************************************************/
1236 /* Enable/disable/generate interrupts */
1237 static inline void efx_nic_interrupts(struct efx_nic
*efx
,
1238 bool enabled
, bool force
)
1240 efx_oword_t int_en_reg_ker
;
1242 EFX_POPULATE_OWORD_3(int_en_reg_ker
,
1243 FRF_AZ_KER_INT_LEVE_SEL
, efx
->fatal_irq_level
,
1244 FRF_AZ_KER_INT_KER
, force
,
1245 FRF_AZ_DRV_INT_EN_KER
, enabled
);
1246 efx_writeo(efx
, &int_en_reg_ker
, FR_AZ_INT_EN_KER
);
1249 void efx_nic_enable_interrupts(struct efx_nic
*efx
)
1251 struct efx_channel
*channel
;
1253 EFX_ZERO_OWORD(*((efx_oword_t
*) efx
->irq_status
.addr
));
1254 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1256 /* Enable interrupts */
1257 efx_nic_interrupts(efx
, true, false);
1259 /* Force processing of all the channels to get the EVQ RPTRs up to
1261 efx_for_each_channel(channel
, efx
)
1262 efx_schedule_channel(channel
);
1265 void efx_nic_disable_interrupts(struct efx_nic
*efx
)
1267 /* Disable interrupts */
1268 efx_nic_interrupts(efx
, false, false);
1271 /* Generate a test interrupt
1272 * Interrupt must already have been enabled, otherwise nasty things
1275 void efx_nic_generate_interrupt(struct efx_nic
*efx
)
1277 efx_nic_interrupts(efx
, true, true);
1280 /* Process a fatal interrupt
1281 * Disable bus mastering ASAP and schedule a reset
1283 irqreturn_t
efx_nic_fatal_interrupt(struct efx_nic
*efx
)
1285 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1286 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1287 efx_oword_t fatal_intr
;
1288 int error
, mem_perr
;
1290 efx_reado(efx
, &fatal_intr
, FR_AZ_FATAL_INTR_KER
);
1291 error
= EFX_OWORD_FIELD(fatal_intr
, FRF_AZ_FATAL_INTR
);
1293 EFX_ERR(efx
, "SYSTEM ERROR " EFX_OWORD_FMT
" status "
1294 EFX_OWORD_FMT
": %s\n", EFX_OWORD_VAL(*int_ker
),
1295 EFX_OWORD_VAL(fatal_intr
),
1296 error
? "disabling bus mastering" : "no recognised error");
1298 /* If this is a memory parity error dump which blocks are offending */
1299 mem_perr
= (EFX_OWORD_FIELD(fatal_intr
, FRF_AZ_MEM_PERR_INT_KER
) ||
1300 EFX_OWORD_FIELD(fatal_intr
, FRF_AZ_SRM_PERR_INT_KER
));
1303 efx_reado(efx
, ®
, FR_AZ_MEM_STAT
);
1304 EFX_ERR(efx
, "SYSTEM ERROR: memory parity error "
1305 EFX_OWORD_FMT
"\n", EFX_OWORD_VAL(reg
));
1308 /* Disable both devices */
1309 pci_clear_master(efx
->pci_dev
);
1310 if (efx_nic_is_dual_func(efx
))
1311 pci_clear_master(nic_data
->pci_dev2
);
1312 efx_nic_disable_interrupts(efx
);
1314 /* Count errors and reset or disable the NIC accordingly */
1315 if (efx
->int_error_count
== 0 ||
1316 time_after(jiffies
, efx
->int_error_expire
)) {
1317 efx
->int_error_count
= 0;
1318 efx
->int_error_expire
=
1319 jiffies
+ EFX_INT_ERROR_EXPIRE
* HZ
;
1321 if (++efx
->int_error_count
< EFX_MAX_INT_ERRORS
) {
1322 EFX_ERR(efx
, "SYSTEM ERROR - reset scheduled\n");
1323 efx_schedule_reset(efx
, RESET_TYPE_INT_ERROR
);
1325 EFX_ERR(efx
, "SYSTEM ERROR - max number of errors seen."
1326 "NIC will be disabled\n");
1327 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
1333 /* Handle a legacy interrupt
1334 * Acknowledges the interrupt and schedule event queue processing.
1336 static irqreturn_t
efx_legacy_interrupt(int irq
, void *dev_id
)
1338 struct efx_nic
*efx
= dev_id
;
1339 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1340 irqreturn_t result
= IRQ_NONE
;
1341 struct efx_channel
*channel
;
1346 /* Read the ISR which also ACKs the interrupts */
1347 efx_readd(efx
, ®
, FR_BZ_INT_ISR0
);
1348 queues
= EFX_EXTRACT_DWORD(reg
, 0, 31);
1350 /* Check to see if we have a serious error condition */
1351 if (queues
& (1U << efx
->fatal_irq_level
)) {
1352 syserr
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_FATAL_INT
);
1353 if (unlikely(syserr
))
1354 return efx_nic_fatal_interrupt(efx
);
1358 if (EFX_WORKAROUND_15783(efx
))
1359 efx
->irq_zero_count
= 0;
1361 /* Schedule processing of any interrupting queues */
1362 efx_for_each_channel(channel
, efx
) {
1364 efx_schedule_channel(channel
);
1367 result
= IRQ_HANDLED
;
1369 } else if (EFX_WORKAROUND_15783(efx
)) {
1372 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1373 * because this might be a shared interrupt. */
1374 if (efx
->irq_zero_count
++ == 0)
1375 result
= IRQ_HANDLED
;
1377 /* Ensure we schedule or rearm all event queues */
1378 efx_for_each_channel(channel
, efx
) {
1379 event
= efx_event(channel
, channel
->eventq_read_ptr
);
1380 if (efx_event_present(event
))
1381 efx_schedule_channel(channel
);
1383 efx_nic_eventq_read_ack(channel
);
1387 if (result
== IRQ_HANDLED
) {
1388 efx
->last_irq_cpu
= raw_smp_processor_id();
1389 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1390 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1396 /* Handle an MSI interrupt
1398 * Handle an MSI hardware interrupt. This routine schedules event
1399 * queue processing. No interrupt acknowledgement cycle is necessary.
1400 * Also, we never need to check that the interrupt is for us, since
1401 * MSI interrupts cannot be shared.
1403 static irqreturn_t
efx_msi_interrupt(int irq
, void *dev_id
)
1405 struct efx_channel
*channel
= dev_id
;
1406 struct efx_nic
*efx
= channel
->efx
;
1407 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1410 efx
->last_irq_cpu
= raw_smp_processor_id();
1411 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1412 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1414 /* Check to see if we have a serious error condition */
1415 if (channel
->channel
== efx
->fatal_irq_level
) {
1416 syserr
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_FATAL_INT
);
1417 if (unlikely(syserr
))
1418 return efx_nic_fatal_interrupt(efx
);
1421 /* Schedule processing of the channel */
1422 efx_schedule_channel(channel
);
1428 /* Setup RSS indirection table.
1429 * This maps from the hash value of the packet to RXQ
1431 static void efx_setup_rss_indir_table(struct efx_nic
*efx
)
1434 unsigned long offset
;
1437 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
)
1440 for (offset
= FR_BZ_RX_INDIRECTION_TBL
;
1441 offset
< FR_BZ_RX_INDIRECTION_TBL
+ 0x800;
1443 EFX_POPULATE_DWORD_1(dword
, FRF_BZ_IT_QUEUE
,
1444 i
% efx
->n_rx_queues
);
1445 efx_writed(efx
, &dword
, offset
);
1450 /* Hook interrupt handler(s)
1451 * Try MSI and then legacy interrupts.
1453 int efx_nic_init_interrupt(struct efx_nic
*efx
)
1455 struct efx_channel
*channel
;
1458 if (!EFX_INT_MODE_USE_MSI(efx
)) {
1459 irq_handler_t handler
;
1460 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
1461 handler
= efx_legacy_interrupt
;
1463 handler
= falcon_legacy_interrupt_a1
;
1465 rc
= request_irq(efx
->legacy_irq
, handler
, IRQF_SHARED
,
1468 EFX_ERR(efx
, "failed to hook legacy IRQ %d\n",
1475 /* Hook MSI or MSI-X interrupt */
1476 efx_for_each_channel(channel
, efx
) {
1477 rc
= request_irq(channel
->irq
, efx_msi_interrupt
,
1478 IRQF_PROBE_SHARED
, /* Not shared */
1479 channel
->name
, channel
);
1481 EFX_ERR(efx
, "failed to hook IRQ %d\n", channel
->irq
);
1489 efx_for_each_channel(channel
, efx
)
1490 free_irq(channel
->irq
, channel
);
1495 void efx_nic_fini_interrupt(struct efx_nic
*efx
)
1497 struct efx_channel
*channel
;
1500 /* Disable MSI/MSI-X interrupts */
1501 efx_for_each_channel(channel
, efx
) {
1503 free_irq(channel
->irq
, channel
);
1506 /* ACK legacy interrupt */
1507 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
1508 efx_reado(efx
, ®
, FR_BZ_INT_ISR0
);
1510 falcon_irq_ack_a1(efx
);
1512 /* Disable legacy interrupt */
1513 if (efx
->legacy_irq
)
1514 free_irq(efx
->legacy_irq
, efx
);
1517 u32
efx_nic_fpga_ver(struct efx_nic
*efx
)
1519 efx_oword_t altera_build
;
1520 efx_reado(efx
, &altera_build
, FR_AZ_ALTERA_BUILD
);
1521 return EFX_OWORD_FIELD(altera_build
, FRF_AZ_ALTERA_BUILD_VER
);
1524 void efx_nic_init_common(struct efx_nic
*efx
)
1528 /* Set positions of descriptor caches in SRAM. */
1529 EFX_POPULATE_OWORD_1(temp
, FRF_AZ_SRM_TX_DC_BASE_ADR
,
1530 efx
->type
->tx_dc_base
/ 8);
1531 efx_writeo(efx
, &temp
, FR_AZ_SRM_TX_DC_CFG
);
1532 EFX_POPULATE_OWORD_1(temp
, FRF_AZ_SRM_RX_DC_BASE_ADR
,
1533 efx
->type
->rx_dc_base
/ 8);
1534 efx_writeo(efx
, &temp
, FR_AZ_SRM_RX_DC_CFG
);
1536 /* Set TX descriptor cache size. */
1537 BUILD_BUG_ON(TX_DC_ENTRIES
!= (8 << TX_DC_ENTRIES_ORDER
));
1538 EFX_POPULATE_OWORD_1(temp
, FRF_AZ_TX_DC_SIZE
, TX_DC_ENTRIES_ORDER
);
1539 efx_writeo(efx
, &temp
, FR_AZ_TX_DC_CFG
);
1541 /* Set RX descriptor cache size. Set low watermark to size-8, as
1542 * this allows most efficient prefetching.
1544 BUILD_BUG_ON(RX_DC_ENTRIES
!= (8 << RX_DC_ENTRIES_ORDER
));
1545 EFX_POPULATE_OWORD_1(temp
, FRF_AZ_RX_DC_SIZE
, RX_DC_ENTRIES_ORDER
);
1546 efx_writeo(efx
, &temp
, FR_AZ_RX_DC_CFG
);
1547 EFX_POPULATE_OWORD_1(temp
, FRF_AZ_RX_DC_PF_LWM
, RX_DC_ENTRIES
- 8);
1548 efx_writeo(efx
, &temp
, FR_AZ_RX_DC_PF_WM
);
1550 /* Program INT_KER address */
1551 EFX_POPULATE_OWORD_2(temp
,
1552 FRF_AZ_NORM_INT_VEC_DIS_KER
,
1553 EFX_INT_MODE_USE_MSI(efx
),
1554 FRF_AZ_INT_ADR_KER
, efx
->irq_status
.dma_addr
);
1555 efx_writeo(efx
, &temp
, FR_AZ_INT_ADR_KER
);
1557 if (EFX_WORKAROUND_17213(efx
) && !EFX_INT_MODE_USE_MSI(efx
))
1558 /* Use an interrupt level unused by event queues */
1559 efx
->fatal_irq_level
= 0x1f;
1561 /* Use a valid MSI-X vector */
1562 efx
->fatal_irq_level
= 0;
1564 /* Enable all the genuinely fatal interrupts. (They are still
1565 * masked by the overall interrupt mask, controlled by
1566 * falcon_interrupts()).
1568 * Note: All other fatal interrupts are enabled
1570 EFX_POPULATE_OWORD_3(temp
,
1571 FRF_AZ_ILL_ADR_INT_KER_EN
, 1,
1572 FRF_AZ_RBUF_OWN_INT_KER_EN
, 1,
1573 FRF_AZ_TBUF_OWN_INT_KER_EN
, 1);
1574 if (efx_nic_rev(efx
) >= EFX_REV_SIENA_A0
)
1575 EFX_SET_OWORD_FIELD(temp
, FRF_CZ_SRAM_PERR_INT_P_KER_EN
, 1);
1576 EFX_INVERT_OWORD(temp
);
1577 efx_writeo(efx
, &temp
, FR_AZ_FATAL_INTR_KER
);
1579 efx_setup_rss_indir_table(efx
);
1581 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1582 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1584 efx_reado(efx
, &temp
, FR_AZ_TX_RESERVED
);
1585 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_RX_SPACER
, 0xfe);
1586 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_RX_SPACER_EN
, 1);
1587 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_ONE_PKT_PER_Q
, 1);
1588 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_PUSH_EN
, 0);
1589 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_DIS_NON_IP_EV
, 1);
1590 /* Enable SW_EV to inherit in char driver - assume harmless here */
1591 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_SOFT_EVT_EN
, 1);
1592 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1593 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_PREF_THRESHOLD
, 2);
1594 /* Disable hardware watchdog which can misfire */
1595 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_PREF_WD_TMR
, 0x3fffff);
1596 /* Squash TX of packets of 16 bytes or less */
1597 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
1598 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TX_FLUSH_MIN_LEN_EN
, 1);
1599 efx_writeo(efx
, &temp
, FR_AZ_TX_RESERVED
);