2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
72 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
75 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
78 unsigned long segment_offset
;
80 if (!seg
|| !trb
|| trb
< seg
->trbs
)
83 segment_offset
= trb
- seg
->trbs
;
84 if (segment_offset
> TRBS_PER_SEGMENT
)
86 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
89 /* Does this link TRB point to the first segment in a ring,
90 * or was the previous TRB the last TRB on the last segment in the ERST?
92 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
93 struct xhci_segment
*seg
, union xhci_trb
*trb
)
95 if (ring
== xhci
->event_ring
)
96 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
97 (seg
->next
== xhci
->event_ring
->first_seg
);
99 return trb
->link
.control
& LINK_TOGGLE
;
102 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
103 * segment? I.e. would the updated event TRB pointer step off the end of the
106 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
107 struct xhci_segment
*seg
, union xhci_trb
*trb
)
109 if (ring
== xhci
->event_ring
)
110 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
112 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
115 static inline int enqueue_is_link_trb(struct xhci_ring
*ring
)
117 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
118 return ((link
->control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
));
121 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
122 * TRB is in a new segment. This does not skip over link TRBs, and it does not
123 * effect the ring dequeue or enqueue pointers.
125 static void next_trb(struct xhci_hcd
*xhci
,
126 struct xhci_ring
*ring
,
127 struct xhci_segment
**seg
,
128 union xhci_trb
**trb
)
130 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
132 *trb
= ((*seg
)->trbs
);
139 * See Cycle bit rules. SW is the consumer for the event ring only.
140 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
142 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
144 union xhci_trb
*next
= ++(ring
->dequeue
);
145 unsigned long long addr
;
148 /* Update the dequeue pointer further if that was a link TRB or we're at
149 * the end of an event ring segment (which doesn't have link TRBS)
151 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
152 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
153 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
155 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
157 (unsigned int) ring
->cycle_state
);
159 ring
->deq_seg
= ring
->deq_seg
->next
;
160 ring
->dequeue
= ring
->deq_seg
->trbs
;
161 next
= ring
->dequeue
;
163 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
164 if (ring
== xhci
->event_ring
)
165 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
166 else if (ring
== xhci
->cmd_ring
)
167 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
169 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
173 * See Cycle bit rules. SW is the consumer for the event ring only.
174 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
176 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
177 * chain bit is set), then set the chain bit in all the following link TRBs.
178 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
179 * have their chain bit cleared (so that each Link TRB is a separate TD).
181 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
182 * set, but other sections talk about dealing with the chain bit set. This was
183 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
184 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
186 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
189 union xhci_trb
*next
;
190 unsigned long long addr
;
192 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
193 next
= ++(ring
->enqueue
);
196 /* Update the dequeue pointer further if that was a link TRB or we're at
197 * the end of an event ring segment (which doesn't have link TRBS)
199 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
201 if (ring
!= xhci
->event_ring
) {
203 next
->link
.control
|= TRB_CHAIN
;
205 /* Give this link TRB to the hardware */
207 next
->link
.control
^= TRB_CYCLE
;
212 /* Toggle the cycle bit after the last ring segment. */
213 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
214 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
216 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
218 (unsigned int) ring
->cycle_state
);
221 ring
->enq_seg
= ring
->enq_seg
->next
;
222 ring
->enqueue
= ring
->enq_seg
->trbs
;
223 next
= ring
->enqueue
;
225 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
226 if (ring
== xhci
->event_ring
)
227 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
228 else if (ring
== xhci
->cmd_ring
)
229 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
231 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
235 * Check to see if there's room to enqueue num_trbs on the ring. See rules
237 * FIXME: this would be simpler and faster if we just kept track of the number
238 * of free TRBs in a ring.
240 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
241 unsigned int num_trbs
)
244 union xhci_trb
*enq
= ring
->enqueue
;
245 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
246 struct xhci_segment
*cur_seg
;
247 unsigned int left_on_ring
;
249 /* If we are currently pointing to a link TRB, advance the
250 * enqueue pointer before checking for space */
251 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
252 enq_seg
= enq_seg
->next
;
256 /* Check if ring is empty */
257 if (enq
== ring
->dequeue
) {
258 /* Can't use link trbs */
259 left_on_ring
= TRBS_PER_SEGMENT
- 1;
260 for (cur_seg
= enq_seg
->next
; cur_seg
!= enq_seg
;
261 cur_seg
= cur_seg
->next
)
262 left_on_ring
+= TRBS_PER_SEGMENT
- 1;
264 /* Always need one TRB free in the ring. */
266 if (num_trbs
> left_on_ring
) {
267 xhci_warn(xhci
, "Not enough room on ring; "
268 "need %u TRBs, %u TRBs left\n",
269 num_trbs
, left_on_ring
);
274 /* Make sure there's an extra empty TRB available */
275 for (i
= 0; i
<= num_trbs
; ++i
) {
276 if (enq
== ring
->dequeue
)
279 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
280 enq_seg
= enq_seg
->next
;
287 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
292 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
293 xhci
->event_ring
->dequeue
);
294 if (deq
== 0 && !in_interrupt())
295 xhci_warn(xhci
, "WARN something wrong with SW event ring "
297 /* Update HC event ring dequeue pointer */
298 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
299 temp
&= ERST_PTR_MASK
;
300 /* Don't clear the EHB bit (which is RW1C) because
301 * there might be more events to service.
304 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
305 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
306 &xhci
->ir_set
->erst_dequeue
);
309 /* Ring the host controller doorbell after placing a command on the ring */
310 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
314 xhci_dbg(xhci
, "// Ding dong!\n");
315 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
316 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
317 /* Flush PCI posted writes */
318 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
321 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
322 unsigned int slot_id
,
323 unsigned int ep_index
,
324 unsigned int stream_id
)
326 struct xhci_virt_ep
*ep
;
327 unsigned int ep_state
;
329 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
331 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
332 ep_state
= ep
->ep_state
;
333 /* Don't ring the doorbell for this endpoint if there are pending
334 * cancellations because the we don't want to interrupt processing.
335 * We don't want to restart any stream rings if there's a set dequeue
336 * pointer command pending because the device can choose to start any
337 * stream once the endpoint is on the HW schedule.
338 * FIXME - check all the stream rings for pending cancellations.
340 if (!(ep_state
& EP_HALT_PENDING
) && !(ep_state
& SET_DEQ_PENDING
)
341 && !(ep_state
& EP_HALTED
)) {
342 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
343 field
|= EPI_TO_DB(ep_index
) | STREAM_ID_TO_DB(stream_id
);
344 xhci_writel(xhci
, field
, db_addr
);
345 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
346 * isn't time-critical and we shouldn't make the CPU wait for
349 xhci_readl(xhci
, db_addr
);
353 /* Ring the doorbell for any rings with pending URBs */
354 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
355 unsigned int slot_id
,
356 unsigned int ep_index
)
358 unsigned int stream_id
;
359 struct xhci_virt_ep
*ep
;
361 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
363 /* A ring has pending URBs if its TD list is not empty */
364 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
365 if (!(list_empty(&ep
->ring
->td_list
)))
366 ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
370 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
372 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
373 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
374 ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
379 * Find the segment that trb is in. Start searching in start_seg.
380 * If we must move past a segment that has a link TRB with a toggle cycle state
381 * bit set, then we will toggle the value pointed at by cycle_state.
383 static struct xhci_segment
*find_trb_seg(
384 struct xhci_segment
*start_seg
,
385 union xhci_trb
*trb
, int *cycle_state
)
387 struct xhci_segment
*cur_seg
= start_seg
;
388 struct xhci_generic_trb
*generic_trb
;
390 while (cur_seg
->trbs
> trb
||
391 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
392 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
393 if ((generic_trb
->field
[3] & TRB_TYPE_BITMASK
) ==
394 TRB_TYPE(TRB_LINK
) &&
395 (generic_trb
->field
[3] & LINK_TOGGLE
))
396 *cycle_state
= ~(*cycle_state
) & 0x1;
397 cur_seg
= cur_seg
->next
;
398 if (cur_seg
== start_seg
)
399 /* Looped over the entire list. Oops! */
406 * Move the xHC's endpoint ring dequeue pointer past cur_td.
407 * Record the new state of the xHC's endpoint ring dequeue segment,
408 * dequeue pointer, and new consumer cycle state in state.
409 * Update our internal representation of the ring's dequeue pointer.
411 * We do this in three jumps:
412 * - First we update our new ring state to be the same as when the xHC stopped.
413 * - Then we traverse the ring to find the segment that contains
414 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
415 * any link TRBs with the toggle cycle bit set.
416 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
417 * if we've moved it past a link TRB with the toggle cycle bit set.
419 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
420 unsigned int slot_id
, unsigned int ep_index
,
421 unsigned int stream_id
, struct xhci_td
*cur_td
,
422 struct xhci_dequeue_state
*state
)
424 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
425 struct xhci_ring
*ep_ring
;
426 struct xhci_generic_trb
*trb
;
427 struct xhci_ep_ctx
*ep_ctx
;
430 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
431 ep_index
, stream_id
);
433 xhci_warn(xhci
, "WARN can't find new dequeue state "
434 "for invalid stream ID %u.\n",
438 state
->new_cycle_state
= 0;
439 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
440 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
441 dev
->eps
[ep_index
].stopped_trb
,
442 &state
->new_cycle_state
);
443 if (!state
->new_deq_seg
)
445 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
446 xhci_dbg(xhci
, "Finding endpoint context\n");
447 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
448 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
450 state
->new_deq_ptr
= cur_td
->last_trb
;
451 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
452 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
454 &state
->new_cycle_state
);
455 if (!state
->new_deq_seg
)
458 trb
= &state
->new_deq_ptr
->generic
;
459 if ((trb
->field
[3] & TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
) &&
460 (trb
->field
[3] & LINK_TOGGLE
))
461 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
462 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
464 /* Don't update the ring cycle state for the producer (us). */
465 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
467 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
468 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
469 (unsigned long long) addr
);
470 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
471 ep_ring
->dequeue
= state
->new_deq_ptr
;
472 ep_ring
->deq_seg
= state
->new_deq_seg
;
475 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
476 struct xhci_td
*cur_td
)
478 struct xhci_segment
*cur_seg
;
479 union xhci_trb
*cur_trb
;
481 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
483 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
484 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
485 TRB_TYPE(TRB_LINK
)) {
486 /* Unchain any chained Link TRBs, but
487 * leave the pointers intact.
489 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
490 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
491 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
492 "in seg %p (0x%llx dma)\n",
494 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
496 (unsigned long long)cur_seg
->dma
);
498 cur_trb
->generic
.field
[0] = 0;
499 cur_trb
->generic
.field
[1] = 0;
500 cur_trb
->generic
.field
[2] = 0;
501 /* Preserve only the cycle bit of this TRB */
502 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
503 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
504 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
505 "in seg %p (0x%llx dma)\n",
507 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
509 (unsigned long long)cur_seg
->dma
);
511 if (cur_trb
== cur_td
->last_trb
)
516 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
517 unsigned int ep_index
, unsigned int stream_id
,
518 struct xhci_segment
*deq_seg
,
519 union xhci_trb
*deq_ptr
, u32 cycle_state
);
521 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
522 unsigned int slot_id
, unsigned int ep_index
,
523 unsigned int stream_id
,
524 struct xhci_dequeue_state
*deq_state
)
526 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
528 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
529 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
530 deq_state
->new_deq_seg
,
531 (unsigned long long)deq_state
->new_deq_seg
->dma
,
532 deq_state
->new_deq_ptr
,
533 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
534 deq_state
->new_cycle_state
);
535 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
536 deq_state
->new_deq_seg
,
537 deq_state
->new_deq_ptr
,
538 (u32
) deq_state
->new_cycle_state
);
539 /* Stop the TD queueing code from ringing the doorbell until
540 * this command completes. The HC won't set the dequeue pointer
541 * if the ring is running, and ringing the doorbell starts the
544 ep
->ep_state
|= SET_DEQ_PENDING
;
547 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
548 struct xhci_virt_ep
*ep
)
550 ep
->ep_state
&= ~EP_HALT_PENDING
;
551 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
552 * timer is running on another CPU, we don't decrement stop_cmds_pending
553 * (since we didn't successfully stop the watchdog timer).
555 if (del_timer(&ep
->stop_cmd_timer
))
556 ep
->stop_cmds_pending
--;
559 /* Must be called with xhci->lock held in interrupt context */
560 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
561 struct xhci_td
*cur_td
, int status
, char *adjective
)
563 struct usb_hcd
*hcd
= xhci_to_hcd(xhci
);
565 cur_td
->urb
->hcpriv
= NULL
;
566 usb_hcd_unlink_urb_from_ep(hcd
, cur_td
->urb
);
567 xhci_dbg(xhci
, "Giveback %s URB %p\n", adjective
, cur_td
->urb
);
569 spin_unlock(&xhci
->lock
);
570 usb_hcd_giveback_urb(hcd
, cur_td
->urb
, status
);
572 spin_lock(&xhci
->lock
);
573 xhci_dbg(xhci
, "%s URB given back\n", adjective
);
577 * When we get a command completion for a Stop Endpoint Command, we need to
578 * unlink any cancelled TDs from the ring. There are two ways to do that:
580 * 1. If the HW was in the middle of processing the TD that needs to be
581 * cancelled, then we must move the ring's dequeue pointer past the last TRB
582 * in the TD with a Set Dequeue Pointer Command.
583 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
584 * bit cleared) so that the HW will skip over them.
586 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
589 unsigned int slot_id
;
590 unsigned int ep_index
;
591 struct xhci_ring
*ep_ring
;
592 struct xhci_virt_ep
*ep
;
593 struct list_head
*entry
;
594 struct xhci_td
*cur_td
= NULL
;
595 struct xhci_td
*last_unlinked_td
;
597 struct xhci_dequeue_state deq_state
;
599 memset(&deq_state
, 0, sizeof(deq_state
));
600 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
601 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
602 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
604 if (list_empty(&ep
->cancelled_td_list
)) {
605 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
606 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
610 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
611 * We have the xHCI lock, so nothing can modify this list until we drop
612 * it. We're also in the event handler, so we can't get re-interrupted
613 * if another Stop Endpoint command completes
615 list_for_each(entry
, &ep
->cancelled_td_list
) {
616 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
617 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
619 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
620 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
622 /* This shouldn't happen unless a driver is mucking
623 * with the stream ID after submission. This will
624 * leave the TD on the hardware ring, and the hardware
625 * will try to execute it, and may access a buffer
626 * that has already been freed. In the best case, the
627 * hardware will execute it, and the event handler will
628 * ignore the completion event for that TD, since it was
629 * removed from the td_list for that endpoint. In
630 * short, don't muck with the stream ID after
633 xhci_warn(xhci
, "WARN Cancelled URB %p "
634 "has invalid stream ID %u.\n",
636 cur_td
->urb
->stream_id
);
637 goto remove_finished_td
;
640 * If we stopped on the TD we need to cancel, then we have to
641 * move the xHC endpoint ring dequeue pointer past this TD.
643 if (cur_td
== ep
->stopped_td
)
644 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
645 cur_td
->urb
->stream_id
,
648 td_to_noop(xhci
, ep_ring
, cur_td
);
651 * The event handler won't see a completion for this TD anymore,
652 * so remove it from the endpoint ring's TD list. Keep it in
653 * the cancelled TD list for URB completion later.
655 list_del(&cur_td
->td_list
);
657 last_unlinked_td
= cur_td
;
658 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
660 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
661 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
662 xhci_queue_new_dequeue_state(xhci
,
664 ep
->stopped_td
->urb
->stream_id
,
666 xhci_ring_cmd_db(xhci
);
668 /* Otherwise ring the doorbell(s) to restart queued transfers */
669 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
671 ep
->stopped_td
= NULL
;
672 ep
->stopped_trb
= NULL
;
675 * Drop the lock and complete the URBs in the cancelled TD list.
676 * New TDs to be cancelled might be added to the end of the list before
677 * we can complete all the URBs for the TDs we already unlinked.
678 * So stop when we've completed the URB for the last TD we unlinked.
681 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
682 struct xhci_td
, cancelled_td_list
);
683 list_del(&cur_td
->cancelled_td_list
);
685 /* Clean up the cancelled URB */
686 /* Doesn't matter what we pass for status, since the core will
687 * just overwrite it (because the URB has been unlinked).
689 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
691 /* Stop processing the cancelled list if the watchdog timer is
694 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
696 } while (cur_td
!= last_unlinked_td
);
698 /* Return to the event handler with xhci->lock re-acquired */
701 /* Watchdog timer function for when a stop endpoint command fails to complete.
702 * In this case, we assume the host controller is broken or dying or dead. The
703 * host may still be completing some other events, so we have to be careful to
704 * let the event ring handler and the URB dequeueing/enqueueing functions know
705 * through xhci->state.
707 * The timer may also fire if the host takes a very long time to respond to the
708 * command, and the stop endpoint command completion handler cannot delete the
709 * timer before the timer function is called. Another endpoint cancellation may
710 * sneak in before the timer function can grab the lock, and that may queue
711 * another stop endpoint command and add the timer back. So we cannot use a
712 * simple flag to say whether there is a pending stop endpoint command for a
713 * particular endpoint.
715 * Instead we use a combination of that flag and a counter for the number of
716 * pending stop endpoint commands. If the timer is the tail end of the last
717 * stop endpoint command, and the endpoint's command is still pending, we assume
720 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
722 struct xhci_hcd
*xhci
;
723 struct xhci_virt_ep
*ep
;
724 struct xhci_virt_ep
*temp_ep
;
725 struct xhci_ring
*ring
;
726 struct xhci_td
*cur_td
;
729 ep
= (struct xhci_virt_ep
*) arg
;
732 spin_lock(&xhci
->lock
);
734 ep
->stop_cmds_pending
--;
735 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
736 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
737 "xHCI as DYING, exiting.\n");
738 spin_unlock(&xhci
->lock
);
741 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
742 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
744 spin_unlock(&xhci
->lock
);
748 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
749 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
750 /* Oops, HC is dead or dying or at least not responding to the stop
753 xhci
->xhc_state
|= XHCI_STATE_DYING
;
754 /* Disable interrupts from the host controller and start halting it */
756 spin_unlock(&xhci
->lock
);
758 ret
= xhci_halt(xhci
);
760 spin_lock(&xhci
->lock
);
762 /* This is bad; the host is not responding to commands and it's
763 * not allowing itself to be halted. At least interrupts are
764 * disabled, so we can set HC_STATE_HALT and notify the
765 * USB core. But if we call usb_hc_died(), it will attempt to
766 * disconnect all device drivers under this host. Those
767 * disconnect() methods will wait for all URBs to be unlinked,
768 * so we must complete them.
770 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
771 xhci_warn(xhci
, "Completing active URBs anyway.\n");
772 /* We could turn all TDs on the rings to no-ops. This won't
773 * help if the host has cached part of the ring, and is slow if
774 * we want to preserve the cycle bit. Skip it and hope the host
775 * doesn't touch the memory.
778 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
781 for (j
= 0; j
< 31; j
++) {
782 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
783 ring
= temp_ep
->ring
;
786 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
787 "ep index %u\n", i
, j
);
788 while (!list_empty(&ring
->td_list
)) {
789 cur_td
= list_first_entry(&ring
->td_list
,
792 list_del(&cur_td
->td_list
);
793 if (!list_empty(&cur_td
->cancelled_td_list
))
794 list_del(&cur_td
->cancelled_td_list
);
795 xhci_giveback_urb_in_irq(xhci
, cur_td
,
796 -ESHUTDOWN
, "killed");
798 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
799 cur_td
= list_first_entry(
800 &temp_ep
->cancelled_td_list
,
803 list_del(&cur_td
->cancelled_td_list
);
804 xhci_giveback_urb_in_irq(xhci
, cur_td
,
805 -ESHUTDOWN
, "killed");
809 spin_unlock(&xhci
->lock
);
810 xhci_to_hcd(xhci
)->state
= HC_STATE_HALT
;
811 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
812 usb_hc_died(xhci_to_hcd(xhci
));
813 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
817 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
818 * we need to clear the set deq pending flag in the endpoint ring state, so that
819 * the TD queueing code can ring the doorbell again. We also need to ring the
820 * endpoint doorbell to restart the ring, but only if there aren't more
821 * cancellations pending.
823 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
824 struct xhci_event_cmd
*event
,
827 unsigned int slot_id
;
828 unsigned int ep_index
;
829 unsigned int stream_id
;
830 struct xhci_ring
*ep_ring
;
831 struct xhci_virt_device
*dev
;
832 struct xhci_ep_ctx
*ep_ctx
;
833 struct xhci_slot_ctx
*slot_ctx
;
835 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
836 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
837 stream_id
= TRB_TO_STREAM_ID(trb
->generic
.field
[2]);
838 dev
= xhci
->devs
[slot_id
];
840 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
842 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
843 "freed stream ID %u\n",
845 /* XXX: Harmless??? */
846 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
850 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
851 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
853 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
854 unsigned int ep_state
;
855 unsigned int slot_state
;
857 switch (GET_COMP_CODE(event
->status
)) {
859 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
860 "of stream ID configuration\n");
863 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
864 "to incorrect slot or ep state.\n");
865 ep_state
= ep_ctx
->ep_info
;
866 ep_state
&= EP_STATE_MASK
;
867 slot_state
= slot_ctx
->dev_state
;
868 slot_state
= GET_SLOT_STATE(slot_state
);
869 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
870 slot_state
, ep_state
);
873 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
874 "slot %u was not enabled.\n", slot_id
);
877 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
878 "completion code of %u.\n",
879 GET_COMP_CODE(event
->status
));
882 /* OK what do we do now? The endpoint state is hosed, and we
883 * should never get to this point if the synchronization between
884 * queueing, and endpoint state are correct. This might happen
885 * if the device gets disconnected after we've finished
886 * cancelling URBs, which might not be an error...
889 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
893 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
894 /* Restart any rings with pending URBs */
895 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
898 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
899 struct xhci_event_cmd
*event
,
903 unsigned int ep_index
;
905 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
906 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
907 /* This command will only fail if the endpoint wasn't halted,
910 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
911 (unsigned int) GET_COMP_CODE(event
->status
));
913 /* HW with the reset endpoint quirk needs to have a configure endpoint
914 * command complete before the endpoint can be used. Queue that here
915 * because the HW can't handle two commands being queued in a row.
917 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
918 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
919 xhci_queue_configure_endpoint(xhci
,
920 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
922 xhci_ring_cmd_db(xhci
);
924 /* Clear our internal halted state and restart the ring(s) */
925 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
926 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
930 /* Check to see if a command in the device's command queue matches this one.
931 * Signal the completion or free the command, and return 1. Return 0 if the
932 * completed command isn't at the head of the command list.
934 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
935 struct xhci_virt_device
*virt_dev
,
936 struct xhci_event_cmd
*event
)
938 struct xhci_command
*command
;
940 if (list_empty(&virt_dev
->cmd_list
))
943 command
= list_entry(virt_dev
->cmd_list
.next
,
944 struct xhci_command
, cmd_list
);
945 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
949 GET_COMP_CODE(event
->status
);
950 list_del(&command
->cmd_list
);
951 if (command
->completion
)
952 complete(command
->completion
);
954 xhci_free_command(xhci
, command
);
958 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
959 struct xhci_event_cmd
*event
)
961 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
963 dma_addr_t cmd_dequeue_dma
;
964 struct xhci_input_control_ctx
*ctrl_ctx
;
965 struct xhci_virt_device
*virt_dev
;
966 unsigned int ep_index
;
967 struct xhci_ring
*ep_ring
;
968 unsigned int ep_state
;
970 cmd_dma
= event
->cmd_trb
;
971 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
972 xhci
->cmd_ring
->dequeue
);
973 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
974 if (cmd_dequeue_dma
== 0) {
975 xhci
->error_bitmask
|= 1 << 4;
978 /* Does the DMA address match our internal dequeue pointer address? */
979 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
980 xhci
->error_bitmask
|= 1 << 5;
983 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
984 case TRB_TYPE(TRB_ENABLE_SLOT
):
985 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
986 xhci
->slot_id
= slot_id
;
989 complete(&xhci
->addr_dev
);
991 case TRB_TYPE(TRB_DISABLE_SLOT
):
992 if (xhci
->devs
[slot_id
])
993 xhci_free_virt_device(xhci
, slot_id
);
995 case TRB_TYPE(TRB_CONFIG_EP
):
996 virt_dev
= xhci
->devs
[slot_id
];
997 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1000 * Configure endpoint commands can come from the USB core
1001 * configuration or alt setting changes, or because the HW
1002 * needed an extra configure endpoint command after a reset
1003 * endpoint command or streams were being configured.
1004 * If the command was for a halted endpoint, the xHCI driver
1005 * is not waiting on the configure endpoint command.
1007 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1009 /* Input ctx add_flags are the endpoint index plus one */
1010 ep_index
= xhci_last_valid_endpoint(ctrl_ctx
->add_flags
) - 1;
1011 /* A usb_set_interface() call directly after clearing a halted
1012 * condition may race on this quirky hardware. Not worth
1013 * worrying about, since this is prototype hardware. Not sure
1014 * if this will work for streams, but streams support was
1015 * untested on this prototype.
1017 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1018 ep_index
!= (unsigned int) -1 &&
1019 ctrl_ctx
->add_flags
- SLOT_FLAG
==
1020 ctrl_ctx
->drop_flags
) {
1021 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1022 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1023 if (!(ep_state
& EP_HALTED
))
1024 goto bandwidth_change
;
1025 xhci_dbg(xhci
, "Completed config ep cmd - "
1026 "last ep index = %d, state = %d\n",
1027 ep_index
, ep_state
);
1028 /* Clear internal halted state and restart ring(s) */
1029 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1031 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1035 xhci_dbg(xhci
, "Completed config ep cmd\n");
1036 xhci
->devs
[slot_id
]->cmd_status
=
1037 GET_COMP_CODE(event
->status
);
1038 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1040 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1041 virt_dev
= xhci
->devs
[slot_id
];
1042 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1044 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
1045 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1047 case TRB_TYPE(TRB_ADDR_DEV
):
1048 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
1049 complete(&xhci
->addr_dev
);
1051 case TRB_TYPE(TRB_STOP_RING
):
1052 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
1054 case TRB_TYPE(TRB_SET_DEQ
):
1055 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1057 case TRB_TYPE(TRB_CMD_NOOP
):
1058 ++xhci
->noops_handled
;
1060 case TRB_TYPE(TRB_RESET_EP
):
1061 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1063 case TRB_TYPE(TRB_RESET_DEV
):
1064 xhci_dbg(xhci
, "Completed reset device command.\n");
1065 slot_id
= TRB_TO_SLOT_ID(
1066 xhci
->cmd_ring
->dequeue
->generic
.field
[3]);
1067 virt_dev
= xhci
->devs
[slot_id
];
1069 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1071 xhci_warn(xhci
, "Reset device command completion "
1072 "for disabled slot %u\n", slot_id
);
1074 case TRB_TYPE(TRB_NEC_GET_FW
):
1075 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1076 xhci
->error_bitmask
|= 1 << 6;
1079 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1080 NEC_FW_MAJOR(event
->status
),
1081 NEC_FW_MINOR(event
->status
));
1084 /* Skip over unknown commands on the event ring */
1085 xhci
->error_bitmask
|= 1 << 6;
1088 inc_deq(xhci
, xhci
->cmd_ring
, false);
1091 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1092 union xhci_trb
*event
)
1096 trb_type
= TRB_FIELD_TO_TYPE(event
->generic
.field
[3]);
1097 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1098 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1099 handle_cmd_completion(xhci
, &event
->event_cmd
);
1102 static void handle_port_status(struct xhci_hcd
*xhci
,
1103 union xhci_trb
*event
)
1107 /* Port status change events always have a successful completion code */
1108 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
1109 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1110 xhci
->error_bitmask
|= 1 << 8;
1112 /* FIXME: core doesn't care about all port link state changes yet */
1113 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
1114 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1116 /* Update event ring dequeue pointer before dropping the lock */
1117 inc_deq(xhci
, xhci
->event_ring
, true);
1118 xhci_set_hc_event_deq(xhci
);
1120 spin_unlock(&xhci
->lock
);
1121 /* Pass this up to the core */
1122 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
1123 spin_lock(&xhci
->lock
);
1127 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1128 * at end_trb, which may be in another segment. If the suspect DMA address is a
1129 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1132 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1133 union xhci_trb
*start_trb
,
1134 union xhci_trb
*end_trb
,
1135 dma_addr_t suspect_dma
)
1137 dma_addr_t start_dma
;
1138 dma_addr_t end_seg_dma
;
1139 dma_addr_t end_trb_dma
;
1140 struct xhci_segment
*cur_seg
;
1142 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1143 cur_seg
= start_seg
;
1148 /* We may get an event for a Link TRB in the middle of a TD */
1149 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1150 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1151 /* If the end TRB isn't in this segment, this is set to 0 */
1152 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1154 if (end_trb_dma
> 0) {
1155 /* The end TRB is in this segment, so suspect should be here */
1156 if (start_dma
<= end_trb_dma
) {
1157 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1160 /* Case for one segment with
1161 * a TD wrapped around to the top
1163 if ((suspect_dma
>= start_dma
&&
1164 suspect_dma
<= end_seg_dma
) ||
1165 (suspect_dma
>= cur_seg
->dma
&&
1166 suspect_dma
<= end_trb_dma
))
1171 /* Might still be somewhere in this segment */
1172 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1175 cur_seg
= cur_seg
->next
;
1176 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1177 } while (cur_seg
!= start_seg
);
1182 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1183 unsigned int slot_id
, unsigned int ep_index
,
1184 unsigned int stream_id
,
1185 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1187 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1188 ep
->ep_state
|= EP_HALTED
;
1189 ep
->stopped_td
= td
;
1190 ep
->stopped_trb
= event_trb
;
1191 ep
->stopped_stream
= stream_id
;
1193 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1194 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1196 ep
->stopped_td
= NULL
;
1197 ep
->stopped_trb
= NULL
;
1198 ep
->stopped_stream
= 0;
1200 xhci_ring_cmd_db(xhci
);
1203 /* Check if an error has halted the endpoint ring. The class driver will
1204 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1205 * However, a babble and other errors also halt the endpoint ring, and the class
1206 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1207 * Ring Dequeue Pointer command manually.
1209 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1210 struct xhci_ep_ctx
*ep_ctx
,
1211 unsigned int trb_comp_code
)
1213 /* TRB completion codes that may require a manual halt cleanup */
1214 if (trb_comp_code
== COMP_TX_ERR
||
1215 trb_comp_code
== COMP_BABBLE
||
1216 trb_comp_code
== COMP_SPLIT_ERR
)
1217 /* The 0.96 spec says a babbling control endpoint
1218 * is not halted. The 0.96 spec says it is. Some HW
1219 * claims to be 0.95 compliant, but it halts the control
1220 * endpoint anyway. Check if a babble halted the
1223 if ((ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_HALTED
)
1229 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1231 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1232 /* Vendor defined "informational" completion code,
1233 * treat as not-an-error.
1235 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1237 xhci_dbg(xhci
, "Treating code as success.\n");
1244 * If this function returns an error condition, it means it got a Transfer
1245 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1246 * At this point, the host controller is probably hosed and should be reset.
1248 static int handle_tx_event(struct xhci_hcd
*xhci
,
1249 struct xhci_transfer_event
*event
)
1251 struct xhci_virt_device
*xdev
;
1252 struct xhci_virt_ep
*ep
;
1253 struct xhci_ring
*ep_ring
;
1254 unsigned int slot_id
;
1256 struct xhci_td
*td
= NULL
;
1257 dma_addr_t event_dma
;
1258 struct xhci_segment
*event_seg
;
1259 union xhci_trb
*event_trb
;
1260 struct urb
*urb
= NULL
;
1261 int status
= -EINPROGRESS
;
1262 struct xhci_ep_ctx
*ep_ctx
;
1265 xhci_dbg(xhci
, "In %s\n", __func__
);
1266 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
1267 xdev
= xhci
->devs
[slot_id
];
1269 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1273 /* Endpoint ID is 1 based, our index is zero based */
1274 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
1275 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
1276 ep
= &xdev
->eps
[ep_index
];
1277 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1278 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1279 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
1280 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
1281 "or incorrect stream ring\n");
1285 event_dma
= event
->buffer
;
1286 /* This TRB should be in the TD at the head of this ring's TD list */
1287 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
1288 if (list_empty(&ep_ring
->td_list
)) {
1289 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
1290 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
1291 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
1292 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
1293 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
1297 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
1298 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
1300 /* Is this a TRB in the currently executing TD? */
1301 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
1302 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
1303 td
->last_trb
, event_dma
);
1304 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
1306 /* HC is busted, give up! */
1307 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
1310 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
1311 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
1312 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
1313 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
1314 lower_32_bits(event
->buffer
));
1315 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
1316 upper_32_bits(event
->buffer
));
1317 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
1318 (unsigned int) event
->transfer_len
);
1319 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
1320 (unsigned int) event
->flags
);
1322 /* Look for common error cases */
1323 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
1324 switch (trb_comp_code
) {
1325 /* Skip codes that require special handling depending on
1332 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1334 case COMP_STOP_INVAL
:
1335 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1338 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1339 ep
->ep_state
|= EP_HALTED
;
1343 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1346 case COMP_SPLIT_ERR
:
1348 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1352 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1353 status
= -EOVERFLOW
;
1356 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1360 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
1364 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
1368 /* Now update the urb's actual_length and give back to the core */
1369 /* Was this a control transfer? */
1370 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
1371 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1372 switch (trb_comp_code
) {
1374 if (event_trb
== ep_ring
->dequeue
) {
1375 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
1376 status
= -ESHUTDOWN
;
1377 } else if (event_trb
!= td
->last_trb
) {
1378 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
1379 status
= -ESHUTDOWN
;
1381 xhci_dbg(xhci
, "Successful control transfer!\n");
1386 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1387 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1388 status
= -EREMOTEIO
;
1394 if (!xhci_requires_manual_halt_cleanup(xhci
,
1395 ep_ctx
, trb_comp_code
))
1397 xhci_dbg(xhci
, "TRB error code %u, "
1398 "halted endpoint index = %u\n",
1399 trb_comp_code
, ep_index
);
1400 /* else fall through */
1402 /* Did we transfer part of the data (middle) phase? */
1403 if (event_trb
!= ep_ring
->dequeue
&&
1404 event_trb
!= td
->last_trb
)
1405 td
->urb
->actual_length
=
1406 td
->urb
->transfer_buffer_length
1407 - TRB_LEN(event
->transfer_len
);
1409 td
->urb
->actual_length
= 0;
1411 xhci_cleanup_halted_endpoint(xhci
,
1412 slot_id
, ep_index
, 0, td
, event_trb
);
1416 * Did we transfer any data, despite the errors that might have
1417 * happened? I.e. did we get past the setup stage?
1419 if (event_trb
!= ep_ring
->dequeue
) {
1420 /* The event was for the status stage */
1421 if (event_trb
== td
->last_trb
) {
1422 if (td
->urb
->actual_length
!= 0) {
1423 /* Don't overwrite a previously set error code */
1424 if ((status
== -EINPROGRESS
||
1426 (td
->urb
->transfer_flags
1427 & URB_SHORT_NOT_OK
))
1428 /* Did we already see a short data stage? */
1429 status
= -EREMOTEIO
;
1431 td
->urb
->actual_length
=
1432 td
->urb
->transfer_buffer_length
;
1435 /* Maybe the event was for the data stage? */
1436 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1437 /* We didn't stop on a link TRB in the middle */
1438 td
->urb
->actual_length
=
1439 td
->urb
->transfer_buffer_length
-
1440 TRB_LEN(event
->transfer_len
);
1441 xhci_dbg(xhci
, "Waiting for status stage event\n");
1448 switch (trb_comp_code
) {
1450 /* Double check that the HW transferred everything. */
1451 if (event_trb
!= td
->last_trb
) {
1452 xhci_warn(xhci
, "WARN Successful completion "
1454 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1455 status
= -EREMOTEIO
;
1459 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1460 xhci_dbg(xhci
, "Successful bulk "
1463 xhci_dbg(xhci
, "Successful interrupt "
1469 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1470 status
= -EREMOTEIO
;
1475 /* Others already handled above */
1478 dev_dbg(&td
->urb
->dev
->dev
,
1479 "ep %#x - asked for %d bytes, "
1480 "%d bytes untransferred\n",
1481 td
->urb
->ep
->desc
.bEndpointAddress
,
1482 td
->urb
->transfer_buffer_length
,
1483 TRB_LEN(event
->transfer_len
));
1484 /* Fast path - was this the last TRB in the TD for this URB? */
1485 if (event_trb
== td
->last_trb
) {
1486 if (TRB_LEN(event
->transfer_len
) != 0) {
1487 td
->urb
->actual_length
=
1488 td
->urb
->transfer_buffer_length
-
1489 TRB_LEN(event
->transfer_len
);
1490 if (td
->urb
->transfer_buffer_length
<
1491 td
->urb
->actual_length
) {
1492 xhci_warn(xhci
, "HC gave bad length "
1493 "of %d bytes left\n",
1494 TRB_LEN(event
->transfer_len
));
1495 td
->urb
->actual_length
= 0;
1496 if (td
->urb
->transfer_flags
&
1498 status
= -EREMOTEIO
;
1502 /* Don't overwrite a previously set error code */
1503 if (status
== -EINPROGRESS
) {
1504 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1505 status
= -EREMOTEIO
;
1510 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1511 /* Ignore a short packet completion if the
1512 * untransferred length was zero.
1514 if (status
== -EREMOTEIO
)
1518 /* Slow path - walk the list, starting from the dequeue
1519 * pointer, to get the actual length transferred.
1521 union xhci_trb
*cur_trb
;
1522 struct xhci_segment
*cur_seg
;
1524 td
->urb
->actual_length
= 0;
1525 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1526 cur_trb
!= event_trb
;
1527 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1528 if ((cur_trb
->generic
.field
[3] &
1529 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1530 (cur_trb
->generic
.field
[3] &
1531 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1532 td
->urb
->actual_length
+=
1533 TRB_LEN(cur_trb
->generic
.field
[2]);
1535 /* If the ring didn't stop on a Link or No-op TRB, add
1536 * in the actual bytes transferred from the Normal TRB
1538 if (trb_comp_code
!= COMP_STOP_INVAL
)
1539 td
->urb
->actual_length
+=
1540 TRB_LEN(cur_trb
->generic
.field
[2]) -
1541 TRB_LEN(event
->transfer_len
);
1544 if (trb_comp_code
== COMP_STOP_INVAL
||
1545 trb_comp_code
== COMP_STOP
) {
1546 /* The Endpoint Stop Command completion will take care of any
1547 * stopped TDs. A stopped TD may be restarted, so don't update
1548 * the ring dequeue pointer or take this TD off any lists yet.
1550 ep
->stopped_td
= td
;
1551 ep
->stopped_trb
= event_trb
;
1553 if (trb_comp_code
== COMP_STALL
) {
1554 /* The transfer is completed from the driver's
1555 * perspective, but we need to issue a set dequeue
1556 * command for this stalled endpoint to move the dequeue
1557 * pointer past the TD. We can't do that here because
1558 * the halt condition must be cleared first. Let the
1559 * USB class driver clear the stall later.
1561 ep
->stopped_td
= td
;
1562 ep
->stopped_trb
= event_trb
;
1563 ep
->stopped_stream
= ep_ring
->stream_id
;
1564 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1565 ep_ctx
, trb_comp_code
)) {
1566 /* Other types of errors halt the endpoint, but the
1567 * class driver doesn't call usb_reset_endpoint() unless
1568 * the error is -EPIPE. Clear the halted status in the
1569 * xHCI hardware manually.
1571 xhci_cleanup_halted_endpoint(xhci
,
1572 slot_id
, ep_index
, ep_ring
->stream_id
, td
, event_trb
);
1574 /* Update ring dequeue pointer */
1575 while (ep_ring
->dequeue
!= td
->last_trb
)
1576 inc_deq(xhci
, ep_ring
, false);
1577 inc_deq(xhci
, ep_ring
, false);
1581 /* Clean up the endpoint's TD list */
1583 /* Do one last check of the actual transfer length.
1584 * If the host controller said we transferred more data than
1585 * the buffer length, urb->actual_length will be a very big
1586 * number (since it's unsigned). Play it safe and say we didn't
1587 * transfer anything.
1589 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1590 xhci_warn(xhci
, "URB transfer length is wrong, "
1591 "xHC issue? req. len = %u, "
1593 urb
->transfer_buffer_length
,
1594 urb
->actual_length
);
1595 urb
->actual_length
= 0;
1596 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1597 status
= -EREMOTEIO
;
1601 list_del(&td
->td_list
);
1602 /* Was this TD slated to be cancelled but completed anyway? */
1603 if (!list_empty(&td
->cancelled_td_list
))
1604 list_del(&td
->cancelled_td_list
);
1606 /* Leave the TD around for the reset endpoint function to use
1607 * (but only if it's not a control endpoint, since we already
1608 * queued the Set TR dequeue pointer command for stalled
1609 * control endpoints).
1611 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
1612 (trb_comp_code
!= COMP_STALL
&&
1613 trb_comp_code
!= COMP_BABBLE
)) {
1619 inc_deq(xhci
, xhci
->event_ring
, true);
1620 xhci_set_hc_event_deq(xhci
);
1622 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1624 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1625 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1626 urb
, urb
->actual_length
, status
);
1627 spin_unlock(&xhci
->lock
);
1628 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1629 spin_lock(&xhci
->lock
);
1635 * This function handles all OS-owned events on the event ring. It may drop
1636 * xhci->lock between event processing (e.g. to pass up port status changes).
1638 void xhci_handle_event(struct xhci_hcd
*xhci
)
1640 union xhci_trb
*event
;
1641 int update_ptrs
= 1;
1644 xhci_dbg(xhci
, "In %s\n", __func__
);
1645 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1646 xhci
->error_bitmask
|= 1 << 1;
1650 event
= xhci
->event_ring
->dequeue
;
1651 /* Does the HC or OS own the TRB? */
1652 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1653 xhci
->event_ring
->cycle_state
) {
1654 xhci
->error_bitmask
|= 1 << 2;
1657 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1659 /* FIXME: Handle more event types. */
1660 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1661 case TRB_TYPE(TRB_COMPLETION
):
1662 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1663 handle_cmd_completion(xhci
, &event
->event_cmd
);
1664 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1666 case TRB_TYPE(TRB_PORT_STATUS
):
1667 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1668 handle_port_status(xhci
, event
);
1669 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1672 case TRB_TYPE(TRB_TRANSFER
):
1673 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1674 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1675 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1677 xhci
->error_bitmask
|= 1 << 9;
1682 if ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
) >= TRB_TYPE(48))
1683 handle_vendor_event(xhci
, event
);
1685 xhci
->error_bitmask
|= 1 << 3;
1687 /* Any of the above functions may drop and re-acquire the lock, so check
1688 * to make sure a watchdog timer didn't mark the host as non-responsive.
1690 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
1691 xhci_dbg(xhci
, "xHCI host dying, returning from "
1692 "event handler.\n");
1697 /* Update SW and HC event ring dequeue pointer */
1698 inc_deq(xhci
, xhci
->event_ring
, true);
1699 xhci_set_hc_event_deq(xhci
);
1701 /* Are there more items on the event ring? */
1702 xhci_handle_event(xhci
);
1705 /**** Endpoint Ring Operations ****/
1708 * Generic function for queueing a TRB on a ring.
1709 * The caller must have checked to make sure there's room on the ring.
1711 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1713 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1715 struct xhci_generic_trb
*trb
;
1717 trb
= &ring
->enqueue
->generic
;
1718 trb
->field
[0] = field1
;
1719 trb
->field
[1] = field2
;
1720 trb
->field
[2] = field3
;
1721 trb
->field
[3] = field4
;
1722 inc_enq(xhci
, ring
, consumer
);
1726 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1727 * FIXME allocate segments if the ring is full.
1729 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1730 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1732 /* Make sure the endpoint has been added to xHC schedule */
1733 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1735 case EP_STATE_DISABLED
:
1737 * USB core changed config/interfaces without notifying us,
1738 * or hardware is reporting the wrong state.
1740 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1742 case EP_STATE_ERROR
:
1743 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
1744 /* FIXME event handling code for error needs to clear it */
1745 /* XXX not sure if this should be -ENOENT or not */
1747 case EP_STATE_HALTED
:
1748 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
1749 case EP_STATE_STOPPED
:
1750 case EP_STATE_RUNNING
:
1753 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1755 * FIXME issue Configure Endpoint command to try to get the HC
1756 * back into a known state.
1760 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1761 /* FIXME allocate more room */
1762 xhci_err(xhci
, "ERROR no room on ep ring\n");
1766 if (enqueue_is_link_trb(ep_ring
)) {
1767 struct xhci_ring
*ring
= ep_ring
;
1768 union xhci_trb
*next
;
1770 xhci_dbg(xhci
, "prepare_ring: pointing to link trb\n");
1771 next
= ring
->enqueue
;
1773 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
1775 /* If we're not dealing with 0.95 hardware,
1776 * clear the chain bit.
1778 if (!xhci_link_trb_quirk(xhci
))
1779 next
->link
.control
&= ~TRB_CHAIN
;
1781 next
->link
.control
|= TRB_CHAIN
;
1784 next
->link
.control
^= (u32
) TRB_CYCLE
;
1786 /* Toggle the cycle bit after the last ring segment. */
1787 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
1788 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
1789 if (!in_interrupt()) {
1790 xhci_dbg(xhci
, "queue_trb: Toggle cycle "
1791 "state for ring %p = %i\n",
1792 ring
, (unsigned int)ring
->cycle_state
);
1795 ring
->enq_seg
= ring
->enq_seg
->next
;
1796 ring
->enqueue
= ring
->enq_seg
->trbs
;
1797 next
= ring
->enqueue
;
1804 static int prepare_transfer(struct xhci_hcd
*xhci
,
1805 struct xhci_virt_device
*xdev
,
1806 unsigned int ep_index
,
1807 unsigned int stream_id
,
1808 unsigned int num_trbs
,
1810 struct xhci_td
**td
,
1814 struct xhci_ring
*ep_ring
;
1815 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1817 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
1819 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
1824 ret
= prepare_ring(xhci
, ep_ring
,
1825 ep_ctx
->ep_info
& EP_STATE_MASK
,
1826 num_trbs
, mem_flags
);
1829 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1832 INIT_LIST_HEAD(&(*td
)->td_list
);
1833 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1835 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1836 if (unlikely(ret
)) {
1842 urb
->hcpriv
= (void *) (*td
);
1843 /* Add this TD to the tail of the endpoint ring's TD list */
1844 list_add_tail(&(*td
)->td_list
, &ep_ring
->td_list
);
1845 (*td
)->start_seg
= ep_ring
->enq_seg
;
1846 (*td
)->first_trb
= ep_ring
->enqueue
;
1851 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1853 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1854 struct scatterlist
*sg
;
1857 num_sgs
= urb
->num_sgs
;
1858 temp
= urb
->transfer_buffer_length
;
1860 xhci_dbg(xhci
, "count sg list trbs: \n");
1862 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
1863 unsigned int previous_total_trbs
= num_trbs
;
1864 unsigned int len
= sg_dma_len(sg
);
1866 /* Scatter gather list entries may cross 64KB boundaries */
1867 running_total
= TRB_MAX_BUFF_SIZE
-
1868 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1869 if (running_total
!= 0)
1872 /* How many more 64KB chunks to transfer, how many more TRBs? */
1873 while (running_total
< sg_dma_len(sg
)) {
1875 running_total
+= TRB_MAX_BUFF_SIZE
;
1877 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1878 i
, (unsigned long long)sg_dma_address(sg
),
1879 len
, len
, num_trbs
- previous_total_trbs
);
1881 len
= min_t(int, len
, temp
);
1886 xhci_dbg(xhci
, "\n");
1887 if (!in_interrupt())
1888 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1889 urb
->ep
->desc
.bEndpointAddress
,
1890 urb
->transfer_buffer_length
,
1895 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1898 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1899 "TRBs, %d left\n", __func__
,
1900 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1901 if (running_total
!= urb
->transfer_buffer_length
)
1902 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1903 "queued %#x (%d), asked for %#x (%d)\n",
1905 urb
->ep
->desc
.bEndpointAddress
,
1906 running_total
, running_total
,
1907 urb
->transfer_buffer_length
,
1908 urb
->transfer_buffer_length
);
1911 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1912 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
1913 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1916 * Pass all the TRBs to the hardware at once and make sure this write
1920 start_trb
->field
[3] |= start_cycle
;
1921 ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
1925 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1926 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1927 * (comprised of sg list entries) can take several service intervals to
1930 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1931 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1933 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
1934 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1938 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
1939 ep_interval
= urb
->interval
;
1940 /* Convert to microframes */
1941 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1942 urb
->dev
->speed
== USB_SPEED_FULL
)
1944 /* FIXME change this to a warning and a suggestion to use the new API
1945 * to set the polling interval (once the API is added).
1947 if (xhci_interval
!= ep_interval
) {
1948 if (!printk_ratelimit())
1949 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
1950 " (%d microframe%s) than xHCI "
1951 "(%d microframe%s)\n",
1953 ep_interval
== 1 ? "" : "s",
1955 xhci_interval
== 1 ? "" : "s");
1956 urb
->interval
= xhci_interval
;
1957 /* Convert back to frames for LS/FS devices */
1958 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1959 urb
->dev
->speed
== USB_SPEED_FULL
)
1962 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
1966 * The TD size is the number of bytes remaining in the TD (including this TRB),
1967 * right shifted by 10.
1968 * It must fit in bits 21:17, so it can't be bigger than 31.
1970 static u32
xhci_td_remainder(unsigned int remainder
)
1972 u32 max
= (1 << (21 - 17 + 1)) - 1;
1974 if ((remainder
>> 10) >= max
)
1977 return (remainder
>> 10) << 17;
1980 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1981 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1983 struct xhci_ring
*ep_ring
;
1984 unsigned int num_trbs
;
1986 struct scatterlist
*sg
;
1988 int trb_buff_len
, this_sg_len
, running_total
;
1992 struct xhci_generic_trb
*start_trb
;
1995 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
1999 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2000 num_sgs
= urb
->num_sgs
;
2002 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2003 ep_index
, urb
->stream_id
,
2004 num_trbs
, urb
, &td
, mem_flags
);
2005 if (trb_buff_len
< 0)
2006 return trb_buff_len
;
2008 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2009 * until we've finished creating all the other TRBs. The ring's cycle
2010 * state may change as we enqueue the other TRBs, so save it too.
2012 start_trb
= &ep_ring
->enqueue
->generic
;
2013 start_cycle
= ep_ring
->cycle_state
;
2017 * How much data is in the first TRB?
2019 * There are three forces at work for TRB buffer pointers and lengths:
2020 * 1. We don't want to walk off the end of this sg-list entry buffer.
2021 * 2. The transfer length that the driver requested may be smaller than
2022 * the amount of memory allocated for this scatter-gather list.
2023 * 3. TRBs buffers can't cross 64KB boundaries.
2026 addr
= (u64
) sg_dma_address(sg
);
2027 this_sg_len
= sg_dma_len(sg
);
2028 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2029 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2030 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2031 if (trb_buff_len
> urb
->transfer_buffer_length
)
2032 trb_buff_len
= urb
->transfer_buffer_length
;
2033 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
2037 /* Queue the first TRB, even if it's zero-length */
2040 u32 length_field
= 0;
2043 /* Don't change the cycle bit of the first TRB until later */
2047 field
|= ep_ring
->cycle_state
;
2049 /* Chain all the TRBs together; clear the chain bit in the last
2050 * TRB to indicate it's the last TRB in the chain.
2055 /* FIXME - add check for ZERO_PACKET flag before this */
2056 td
->last_trb
= ep_ring
->enqueue
;
2059 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
2060 "64KB boundary at %#x, end dma = %#x\n",
2061 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
2062 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2063 (unsigned int) addr
+ trb_buff_len
);
2064 if (TRB_MAX_BUFF_SIZE
-
2065 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
2066 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2067 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2068 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2069 (unsigned int) addr
+ trb_buff_len
);
2071 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
2073 length_field
= TRB_LEN(trb_buff_len
) |
2076 queue_trb(xhci
, ep_ring
, false,
2077 lower_32_bits(addr
),
2078 upper_32_bits(addr
),
2080 /* We always want to know if the TRB was short,
2081 * or we won't get an event when it completes.
2082 * (Unless we use event data TRBs, which are a
2083 * waste of space and HC resources.)
2085 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
2087 running_total
+= trb_buff_len
;
2089 /* Calculate length for next transfer --
2090 * Are we done queueing all the TRBs for this sg entry?
2092 this_sg_len
-= trb_buff_len
;
2093 if (this_sg_len
== 0) {
2098 addr
= (u64
) sg_dma_address(sg
);
2099 this_sg_len
= sg_dma_len(sg
);
2101 addr
+= trb_buff_len
;
2104 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2105 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2106 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2107 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2109 urb
->transfer_buffer_length
- running_total
;
2110 } while (running_total
< urb
->transfer_buffer_length
);
2112 check_trb_math(urb
, num_trbs
, running_total
);
2113 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2114 start_cycle
, start_trb
, td
);
2118 /* This is very similar to what ehci-q.c qtd_fill() does */
2119 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2120 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2122 struct xhci_ring
*ep_ring
;
2125 struct xhci_generic_trb
*start_trb
;
2128 u32 field
, length_field
;
2130 int running_total
, trb_buff_len
, ret
;
2134 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2136 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2141 /* How much data is (potentially) left before the 64KB boundary? */
2142 running_total
= TRB_MAX_BUFF_SIZE
-
2143 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2145 /* If there's some data on this 64KB chunk, or we have to send a
2146 * zero-length transfer, we need at least one TRB
2148 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
2150 /* How many more 64KB chunks to transfer, how many more TRBs? */
2151 while (running_total
< urb
->transfer_buffer_length
) {
2153 running_total
+= TRB_MAX_BUFF_SIZE
;
2155 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2157 if (!in_interrupt())
2158 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
2159 urb
->ep
->desc
.bEndpointAddress
,
2160 urb
->transfer_buffer_length
,
2161 urb
->transfer_buffer_length
,
2162 (unsigned long long)urb
->transfer_dma
,
2165 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2166 ep_index
, urb
->stream_id
,
2167 num_trbs
, urb
, &td
, mem_flags
);
2172 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2173 * until we've finished creating all the other TRBs. The ring's cycle
2174 * state may change as we enqueue the other TRBs, so save it too.
2176 start_trb
= &ep_ring
->enqueue
->generic
;
2177 start_cycle
= ep_ring
->cycle_state
;
2180 /* How much data is in the first TRB? */
2181 addr
= (u64
) urb
->transfer_dma
;
2182 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2183 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
2184 if (urb
->transfer_buffer_length
< trb_buff_len
)
2185 trb_buff_len
= urb
->transfer_buffer_length
;
2189 /* Queue the first TRB, even if it's zero-length */
2194 /* Don't change the cycle bit of the first TRB until later */
2198 field
|= ep_ring
->cycle_state
;
2200 /* Chain all the TRBs together; clear the chain bit in the last
2201 * TRB to indicate it's the last TRB in the chain.
2206 /* FIXME - add check for ZERO_PACKET flag before this */
2207 td
->last_trb
= ep_ring
->enqueue
;
2210 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
-
2212 length_field
= TRB_LEN(trb_buff_len
) |
2215 queue_trb(xhci
, ep_ring
, false,
2216 lower_32_bits(addr
),
2217 upper_32_bits(addr
),
2219 /* We always want to know if the TRB was short,
2220 * or we won't get an event when it completes.
2221 * (Unless we use event data TRBs, which are a
2222 * waste of space and HC resources.)
2224 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
2226 running_total
+= trb_buff_len
;
2228 /* Calculate length for next transfer */
2229 addr
+= trb_buff_len
;
2230 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
2231 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
2232 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
2233 } while (running_total
< urb
->transfer_buffer_length
);
2235 check_trb_math(urb
, num_trbs
, running_total
);
2236 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2237 start_cycle
, start_trb
, td
);
2241 /* Caller must have locked xhci->lock */
2242 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2243 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2245 struct xhci_ring
*ep_ring
;
2248 struct usb_ctrlrequest
*setup
;
2249 struct xhci_generic_trb
*start_trb
;
2251 u32 field
, length_field
;
2254 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2259 * Need to copy setup packet into setup TRB, so we can't use the setup
2262 if (!urb
->setup_packet
)
2265 if (!in_interrupt())
2266 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
2268 /* 1 TRB for setup, 1 for status */
2271 * Don't need to check if we need additional event data and normal TRBs,
2272 * since data in control transfers will never get bigger than 16MB
2273 * XXX: can we get a buffer that crosses 64KB boundaries?
2275 if (urb
->transfer_buffer_length
> 0)
2277 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2278 ep_index
, urb
->stream_id
,
2279 num_trbs
, urb
, &td
, mem_flags
);
2284 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2285 * until we've finished creating all the other TRBs. The ring's cycle
2286 * state may change as we enqueue the other TRBs, so save it too.
2288 start_trb
= &ep_ring
->enqueue
->generic
;
2289 start_cycle
= ep_ring
->cycle_state
;
2291 /* Queue setup TRB - see section 6.4.1.2.1 */
2292 /* FIXME better way to translate setup_packet into two u32 fields? */
2293 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
2294 queue_trb(xhci
, ep_ring
, false,
2295 /* FIXME endianness is probably going to bite my ass here. */
2296 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
2297 setup
->wIndex
| setup
->wLength
<< 16,
2298 TRB_LEN(8) | TRB_INTR_TARGET(0),
2299 /* Immediate data in pointer */
2300 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
2302 /* If there's data, queue data TRBs */
2304 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
2305 xhci_td_remainder(urb
->transfer_buffer_length
) |
2307 if (urb
->transfer_buffer_length
> 0) {
2308 if (setup
->bRequestType
& USB_DIR_IN
)
2309 field
|= TRB_DIR_IN
;
2310 queue_trb(xhci
, ep_ring
, false,
2311 lower_32_bits(urb
->transfer_dma
),
2312 upper_32_bits(urb
->transfer_dma
),
2314 /* Event on short tx */
2315 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
2318 /* Save the DMA address of the last TRB in the TD */
2319 td
->last_trb
= ep_ring
->enqueue
;
2321 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2322 /* If the device sent data, the status stage is an OUT transfer */
2323 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
2327 queue_trb(xhci
, ep_ring
, false,
2331 /* Event on completion */
2332 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
2334 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
2335 start_cycle
, start_trb
, td
);
2339 /**** Command Ring Operations ****/
2341 /* Generic function for queueing a command TRB on the command ring.
2342 * Check to make sure there's room on the command ring for one command TRB.
2343 * Also check that there's room reserved for commands that must not fail.
2344 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
2345 * then only check for the number of reserved spots.
2346 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
2347 * because the command event handler may want to resubmit a failed command.
2349 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
2350 u32 field3
, u32 field4
, bool command_must_succeed
)
2352 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
2353 if (!command_must_succeed
)
2356 if (!room_on_ring(xhci
, xhci
->cmd_ring
, reserved_trbs
)) {
2357 if (!in_interrupt())
2358 xhci_err(xhci
, "ERR: No room for command on command ring\n");
2359 if (command_must_succeed
)
2360 xhci_err(xhci
, "ERR: Reserved TRB counting for "
2361 "unfailable commands failed.\n");
2364 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
2365 field4
| xhci
->cmd_ring
->cycle_state
);
2369 /* Queue a no-op command on the command ring */
2370 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
2372 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
), false);
2376 * Place a no-op command on the command ring to test the command and
2379 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
2381 if (queue_cmd_noop(xhci
) < 0)
2383 xhci
->noops_submitted
++;
2384 return xhci_ring_cmd_db
;
2387 /* Queue a slot enable or disable request on the command ring */
2388 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
2390 return queue_command(xhci
, 0, 0, 0,
2391 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
2394 /* Queue an address device command TRB */
2395 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2398 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2399 upper_32_bits(in_ctx_ptr
), 0,
2400 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
2404 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
2405 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2407 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
2410 /* Queue a reset device command TRB */
2411 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
2413 return queue_command(xhci
, 0, 0, 0,
2414 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
2418 /* Queue a configure endpoint command TRB */
2419 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2420 u32 slot_id
, bool command_must_succeed
)
2422 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2423 upper_32_bits(in_ctx_ptr
), 0,
2424 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
2425 command_must_succeed
);
2428 /* Queue an evaluate context command TRB */
2429 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
2432 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
2433 upper_32_bits(in_ctx_ptr
), 0,
2434 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
2438 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
2439 unsigned int ep_index
)
2441 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2442 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2443 u32 type
= TRB_TYPE(TRB_STOP_RING
);
2445 return queue_command(xhci
, 0, 0, 0,
2446 trb_slot_id
| trb_ep_index
| type
, false);
2449 /* Set Transfer Ring Dequeue Pointer command.
2450 * This should not be used for endpoints that have streams enabled.
2452 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
2453 unsigned int ep_index
, unsigned int stream_id
,
2454 struct xhci_segment
*deq_seg
,
2455 union xhci_trb
*deq_ptr
, u32 cycle_state
)
2458 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2459 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2460 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
2461 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
2463 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
2465 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
2466 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
2470 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
2471 upper_32_bits(addr
), trb_stream_id
,
2472 trb_slot_id
| trb_ep_index
| type
, false);
2475 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
2476 unsigned int ep_index
)
2478 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2479 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2480 u32 type
= TRB_TYPE(TRB_RESET_EP
);
2482 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,