include/asm-powerpc/irq.h

   1 #ifdef __KERNEL__
   2 #ifndef _ASM_POWERPC_IRQ_H
   3 #define _ASM_POWERPC_IRQ_H
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/threads.h>
  13 #include <linux/list.h>
  14 #include <linux/radix-tree.h>
  15
  16 #include <asm/types.h>
  17 #include <asm/atomic.h>
  18
  19
  20 #define get_irq_desc(irq) (&irq_desc[(irq)])
  21
  22 /* Define a way to iterate across irqs. */
  23 #define for_each_irq(i) \
  24         for ((i) = 0; (i) < NR_IRQS; ++(i))
  25
  26 extern atomic_t ppc_n_lost_interrupts;
  27
  28 #ifdef CONFIG_PPC_MERGE
  29
  30 /* This number is used when no interrupt has been assigned */
  31 #define NO_IRQ                  (0)
  32
  33 /* This is a special irq number to return from get_irq() to tell that
  34  * no interrupt happened _and_ ignore it (don't count it as bad). Some
  35  * platforms like iSeries rely on that.
  36  */
  37 #define NO_IRQ_IGNORE           ((unsigned int)-1)
  38
  39 /* Total number of virq in the platform (make it a CONFIG_* option ? */
  40 #define NR_IRQS         512
  41
  42 /* Number of irqs reserved for the legacy controller */
  43 #define NUM_ISA_INTERRUPTS      16
  44
  45 /* This type is the placeholder for a hardware interrupt number. It has to
  46  * be big enough to enclose whatever representation is used by a given
  47  * platform.
  48  */
  49 typedef unsigned long irq_hw_number_t;
  50
  51 /* Interrupt controller "host" data structure. This could be defined as a
  52  * irq domain controller. That is, it handles the mapping between hardware
  53  * and virtual interrupt numbers for a given interrupt domain. The host
  54  * structure is generally created by the PIC code for a given PIC instance
  55  * (though a host can cover more than one PIC if they have a flat number
  56  * model). It's the host callbacks that are responsible for setting the
  57  * irq_chip on a given irq_desc after it's been mapped.
  58  *
  59  * The host code and data structures are fairly agnostic to the fact that
  60  * we use an open firmware device-tree. We do have references to struct
  61  * device_node in two places: in irq_find_host() to find the host matching
  62  * a given interrupt controller node, and of course as an argument to its
  63  * counterpart host->ops->match() callback. However, those are treated as
  64  * generic pointers by the core and the fact that it's actually a device-node
  65  * pointer is purely a convention between callers and implementation. This
  66  * code could thus be used on other architectures by replacing those two
  67  * by some sort of arch-specific void * "token" used to identify interrupt
  68  * controllers.
  69  */
  70 struct irq_host;
  71 struct radix_tree_root;
  72
  73 /* Functions below are provided by the host and called whenever a new mapping
  74  * is created or an old mapping is disposed. The host can then proceed to
  75  * whatever internal data structures management is required. It also needs
  76  * to setup the irq_desc when returning from map().
  77  */
  78 struct irq_host_ops {
  79         /* Match an interrupt controller device node to a host, returns
  80          * 1 on a match
  81          */
  82         int (*match)(struct irq_host *h, struct device_node *node);
  83
  84         /* Create or update a mapping between a virtual irq number and a hw
  85          * irq number. This is called only once for a given mapping.
  86          */
  87         int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
  88
  89         /* Dispose of such a mapping */
  90         void (*unmap)(struct irq_host *h, unsigned int virq);
  91
  92         /* Update of such a mapping  */
  93         void (*remap)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
  94
  95         /* Translate device-tree interrupt specifier from raw format coming
  96          * from the firmware to a irq_hw_number_t (interrupt line number) and
  97          * type (sense) that can be passed to set_irq_type(). In the absence
  98          * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
  99          * will return the hw number in the first cell and IRQ_TYPE_NONE for
 100          * the type (which amount to keeping whatever default value the
 101          * interrupt controller has for that line)
 102          */
 103         int (*xlate)(struct irq_host *h, struct device_node *ctrler,
 104                      u32 *intspec, unsigned int intsize,
 105                      irq_hw_number_t *out_hwirq, unsigned int *out_type);
 106 };
 107
 108 struct irq_host {
 109         struct list_head        link;
 110
 111         /* type of reverse mapping technique */
 112         unsigned int            revmap_type;
 113 #define IRQ_HOST_MAP_LEGACY     0 /* legacy 8259, gets irqs 1..15 */
 114 #define IRQ_HOST_MAP_NOMAP      1 /* no fast reverse mapping */
 115 #define IRQ_HOST_MAP_LINEAR     2 /* linear map of interrupts */
 116 #define IRQ_HOST_MAP_TREE       3 /* radix tree */
 117         union {
 118                 struct {
 119                         unsigned int size;
 120                         unsigned int *revmap;
 121                 } linear;
 122                 struct radix_tree_root tree;
 123         } revmap_data;
 124         struct irq_host_ops     *ops;
 125         void                    *host_data;
 126         irq_hw_number_t         inval_irq;
 127 };
 128
 129 /* The main irq map itself is an array of NR_IRQ entries containing the
 130  * associate host and irq number. An entry with a host of NULL is free.
 131  * An entry can be allocated if it's free, the allocator always then sets
 132  * hwirq first to the host's invalid irq number and then fills ops.
 133  */
 134 struct irq_map_entry {
 135         irq_hw_number_t hwirq;
 136         struct irq_host *host;
 137 };
 138
 139 extern struct irq_map_entry irq_map[NR_IRQS];
 140
 141 static inline irq_hw_number_t virq_to_hw(unsigned int virq)
 142 {
 143         return irq_map[virq].hwirq;
 144 }
 145
 146 /**
 147  * irq_alloc_host - Allocate a new irq_host data structure
 148  * @node: device-tree node of the interrupt controller
 149  * @revmap_type: type of reverse mapping to use
 150  * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
 151  * @ops: map/unmap host callbacks
 152  * @inval_irq: provide a hw number in that host space that is always invalid
 153  *
 154  * Allocates and initialize and irq_host structure. Note that in the case of
 155  * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
 156  * for all legacy interrupts except 0 (which is always the invalid irq for
 157  * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
 158  * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
 159  * later during boot automatically (the reverse mapping will use the slow path
 160  * until that happens).
 161  */
 162 extern struct irq_host *irq_alloc_host(unsigned int revmap_type,
 163                                        unsigned int revmap_arg,
 164                                        struct irq_host_ops *ops,
 165                                        irq_hw_number_t inval_irq);
 166
 167
 168 /**
 169  * irq_find_host - Locates a host for a given device node
 170  * @node: device-tree node of the interrupt controller
 171  */
 172 extern struct irq_host *irq_find_host(struct device_node *node);
 173
 174
 175 /**
 176  * irq_set_default_host - Set a "default" host
 177  * @host: default host pointer
 178  *
 179  * For convenience, it's possible to set a "default" host that will be used
 180  * whenever NULL is passed to irq_create_mapping(). It makes life easier for
 181  * platforms that want to manipulate a few hard coded interrupt numbers that
 182  * aren't properly represented in the device-tree.
 183  */
 184 extern void irq_set_default_host(struct irq_host *host);
 185
 186
 187 /**
 188  * irq_set_virq_count - Set the maximum number of virt irqs
 189  * @count: number of linux virtual irqs, capped with NR_IRQS
 190  *
 191  * This is mainly for use by platforms like iSeries who want to program
 192  * the virtual irq number in the controller to avoid the reverse mapping
 193  */
 194 extern void irq_set_virq_count(unsigned int count);
 195
 196
 197 /**
 198  * irq_create_mapping - Map a hardware interrupt into linux virq space
 199  * @host: host owning this hardware interrupt or NULL for default host
 200  * @hwirq: hardware irq number in that host space
 201  *
 202  * Only one mapping per hardware interrupt is permitted. Returns a linux
 203  * virq number.
 204  * If the sense/trigger is to be specified, set_irq_type() should be called
 205  * on the number returned from that call.
 206  */
 207 extern unsigned int irq_create_mapping(struct irq_host *host,
 208                                        irq_hw_number_t hwirq);
 209
 210
 211 /**
 212  * irq_dispose_mapping - Unmap an interrupt
 213  * @virq: linux virq number of the interrupt to unmap
 214  */
 215 extern void irq_dispose_mapping(unsigned int virq);
 216
 217 /**
 218  * irq_find_mapping - Find a linux virq from an hw irq number.
 219  * @host: host owning this hardware interrupt
 220  * @hwirq: hardware irq number in that host space
 221  *
 222  * This is a slow path, for use by generic code. It's expected that an
 223  * irq controller implementation directly calls the appropriate low level
 224  * mapping function.
 225  */
 226 extern unsigned int irq_find_mapping(struct irq_host *host,
 227                                      irq_hw_number_t hwirq);
 228
 229
 230 /**
 231  * irq_radix_revmap - Find a linux virq from a hw irq number.
 232  * @host: host owning this hardware interrupt
 233  * @hwirq: hardware irq number in that host space
 234  *
 235  * This is a fast path, for use by irq controller code that uses radix tree
 236  * revmaps
 237  */
 238 extern unsigned int irq_radix_revmap(struct irq_host *host,
 239                                      irq_hw_number_t hwirq);
 240
 241 /**
 242  * irq_linear_revmap - Find a linux virq from a hw irq number.
 243  * @host: host owning this hardware interrupt
 244  * @hwirq: hardware irq number in that host space
 245  *
 246  * This is a fast path, for use by irq controller code that uses linear
 247  * revmaps. It does fallback to the slow path if the revmap doesn't exist
 248  * yet and will create the revmap entry with appropriate locking
 249  */
 250
 251 extern unsigned int irq_linear_revmap(struct irq_host *host,
 252                                       irq_hw_number_t hwirq);
 253
 254
 255
 256 /**
 257  * irq_alloc_virt - Allocate virtual irq numbers
 258  * @host: host owning these new virtual irqs
 259  * @count: number of consecutive numbers to allocate
 260  * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
 261  *
 262  * This is a low level function that is used internally by irq_create_mapping()
 263  * and that can be used by some irq controllers implementations for things
 264  * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
 265  */
 266 extern unsigned int irq_alloc_virt(struct irq_host *host,
 267                                    unsigned int count,
 268                                    unsigned int hint);
 269
 270 /**
 271  * irq_free_virt - Free virtual irq numbers
 272  * @virq: virtual irq number of the first interrupt to free
 273  * @count: number of interrupts to free
 274  *
 275  * This function is the opposite of irq_alloc_virt. It will not clear reverse
 276  * maps, this should be done previously by unmap'ing the interrupt. In fact,
 277  * all interrupts covered by the range being freed should have been unmapped
 278  * prior to calling this.
 279  */
 280 extern void irq_free_virt(unsigned int virq, unsigned int count);
 281
 282
 283 /* -- OF helpers -- */
 284
 285 /* irq_create_of_mapping - Map a hardware interrupt into linux virq space
 286  * @controller: Device node of the interrupt controller
 287  * @inspec: Interrupt specifier from the device-tree
 288  * @intsize: Size of the interrupt specifier from the device-tree
 289  *
 290  * This function is identical to irq_create_mapping except that it takes
 291  * as input informations straight from the device-tree (typically the results
 292  * of the of_irq_map_*() functions.
 293  */
 294 extern unsigned int irq_create_of_mapping(struct device_node *controller,
 295                                           u32 *intspec, unsigned int intsize);
 296
 297
 298 /* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
 299  * @device: Device node of the device whose interrupt is to be mapped
 300  * @index: Index of the interrupt to map
 301  *
 302  * This function is a wrapper that chains of_irq_map_one() and
 303  * irq_create_of_mapping() to make things easier to callers
 304  */
 305 extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
 306
 307 /* -- End OF helpers -- */
 308
 309 /**
 310  * irq_early_init - Init irq remapping subsystem
 311  */
 312 extern void irq_early_init(void);
 313
 314 static __inline__ int irq_canonicalize(int irq)
 315 {
 316         return irq;
 317 }
 318
 319
 320 #else /* CONFIG_PPC_MERGE */
 321
 322 /* This number is used when no interrupt has been assigned */
 323 #define NO_IRQ                  (-1)
 324 #define NO_IRQ_IGNORE           (-2)
 325
 326
 327 /*
 328  * These constants are used for passing information about interrupt
 329  * signal polarity and level/edge sensing to the low-level PIC chip
 330  * drivers.
 331  */
 332 #define IRQ_SENSE_MASK          0x1
 333 #define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
 334 #define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
 335
 336 #define IRQ_POLARITY_MASK       0x2
 337 #define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
 338 #define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
 339
 340
 341 #if defined(CONFIG_40x)
 342 #include <asm/ibm4xx.h>
 343
 344 #ifndef NR_BOARD_IRQS
 345 #define NR_BOARD_IRQS 0
 346 #endif
 347
 348 #ifndef UIC_WIDTH /* Number of interrupts per device */
 349 #define UIC_WIDTH 32
 350 #endif
 351
 352 #ifndef NR_UICS /* number  of UIC devices */
 353 #define NR_UICS 1
 354 #endif
 355
 356 #if defined (CONFIG_403)
 357 /*
 358  * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
 359  * 32 possible interrupts, a majority of which are not implemented on
 360  * all cores. There are six configurable, external interrupt pins and
 361  * there are eight internal interrupts for the on-chip serial port
 362  * (SPU), DMA controller, and JTAG controller.
 363  *
 364  */
 365
 366 #define NR_AIC_IRQS 32
 367 #define NR_IRQS  (NR_AIC_IRQS + NR_BOARD_IRQS)
 368
 369 #elif !defined (CONFIG_403)
 370
 371 /*
 372  *  The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
 373  * possible interrupts as well. There are seven, configurable external
 374  * interrupt pins and there are 17 internal interrupts for the on-chip
 375  * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
 376  *
 377  */
 378
 379
 380 #define NR_UIC_IRQS UIC_WIDTH
 381 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
 382 #endif
 383
 384 #elif defined(CONFIG_44x)
 385 #include <asm/ibm44x.h>
 386
 387 #define NR_UIC_IRQS     32
 388 #define NR_IRQS         ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
 389
 390 #elif defined(CONFIG_8xx)
 391
 392 /* Now include the board configuration specific associations.
 393 */
 394 #include <asm/mpc8xx.h>
 395
 396 /* The MPC8xx cores have 16 possible interrupts.  There are eight
 397  * possible level sensitive interrupts assigned and generated internally
 398  * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
 399  * There are eight external interrupts (IRQs) that can be configured
 400  * as either level or edge sensitive.
 401  *
 402  * On some implementations, there is also the possibility of an 8259
 403  * through the PCI and PCI-ISA bridges.
 404  *
 405  * We are "flattening" the interrupt vectors of the cascaded CPM
 406  * and 8259 interrupt controllers so that we can uniquely identify
 407  * any interrupt source with a single integer.
 408  */
 409 #define NR_SIU_INTS     16
 410 #define NR_CPM_INTS     32
 411 #ifndef NR_8259_INTS
 412 #define NR_8259_INTS 0
 413 #endif
 414
 415 #define SIU_IRQ_OFFSET          0
 416 #define CPM_IRQ_OFFSET          (SIU_IRQ_OFFSET + NR_SIU_INTS)
 417 #define I8259_IRQ_OFFSET        (CPM_IRQ_OFFSET + NR_CPM_INTS)
 418
 419 #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
 420
 421 /* These values must be zero-based and map 1:1 with the SIU configuration.
 422  * They are used throughout the 8xx I/O subsystem to generate
 423  * interrupt masks, flags, and other control patterns.  This is why the
 424  * current kernel assumption of the 8259 as the base controller is such
 425  * a pain in the butt.
 426  */
 427 #define SIU_IRQ0        (0)     /* Highest priority */
 428 #define SIU_LEVEL0      (1)
 429 #define SIU_IRQ1        (2)
 430 #define SIU_LEVEL1      (3)
 431 #define SIU_IRQ2        (4)
 432 #define SIU_LEVEL2      (5)
 433 #define SIU_IRQ3        (6)
 434 #define SIU_LEVEL3      (7)
 435 #define SIU_IRQ4        (8)
 436 #define SIU_LEVEL4      (9)
 437 #define SIU_IRQ5        (10)
 438 #define SIU_LEVEL5      (11)
 439 #define SIU_IRQ6        (12)
 440 #define SIU_LEVEL6      (13)
 441 #define SIU_IRQ7        (14)
 442 #define SIU_LEVEL7      (15)
 443
 444 #define MPC8xx_INT_FEC1         SIU_LEVEL1
 445 #define MPC8xx_INT_FEC2         SIU_LEVEL3
 446
 447 #define MPC8xx_INT_SCC1         (CPM_IRQ_OFFSET + CPMVEC_SCC1)
 448 #define MPC8xx_INT_SCC2         (CPM_IRQ_OFFSET + CPMVEC_SCC2)
 449 #define MPC8xx_INT_SCC3         (CPM_IRQ_OFFSET + CPMVEC_SCC3)
 450 #define MPC8xx_INT_SCC4         (CPM_IRQ_OFFSET + CPMVEC_SCC4)
 451 #define MPC8xx_INT_SMC1         (CPM_IRQ_OFFSET + CPMVEC_SMC1)
 452 #define MPC8xx_INT_SMC2         (CPM_IRQ_OFFSET + CPMVEC_SMC2)
 453
 454 /* The internal interrupts we can configure as we see fit.
 455  * My personal preference is CPM at level 2, which puts it above the
 456  * MBX PCI/ISA/IDE interrupts.
 457  */
 458 #ifndef PIT_INTERRUPT
 459 #define PIT_INTERRUPT           SIU_LEVEL0
 460 #endif
 461 #ifndef CPM_INTERRUPT
 462 #define CPM_INTERRUPT           SIU_LEVEL2
 463 #endif
 464 #ifndef PCMCIA_INTERRUPT
 465 #define PCMCIA_INTERRUPT        SIU_LEVEL6
 466 #endif
 467 #ifndef DEC_INTERRUPT
 468 #define DEC_INTERRUPT           SIU_LEVEL7
 469 #endif
 470
 471 /* Some internal interrupt registers use an 8-bit mask for the interrupt
 472  * level instead of a number.
 473  */
 474 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
 475
 476 #elif defined(CONFIG_83xx)
 477 #include <asm/mpc83xx.h>
 478
 479 #define NR_IRQS (NR_IPIC_INTS)
 480
 481 #elif defined(CONFIG_85xx)
 482 /* Now include the board configuration specific associations.
 483 */
 484 #include <asm/mpc85xx.h>
 485
 486 /* The MPC8548 openpic has 48 internal interrupts and 12 external
 487  * interrupts.
 488  *
 489  * We are "flattening" the interrupt vectors of the cascaded CPM
 490  * so that we can uniquely identify any interrupt source with a
 491  * single integer.
 492  */
 493 #define NR_CPM_INTS     64
 494 #define NR_EPIC_INTS    60
 495 #ifndef NR_8259_INTS
 496 #define NR_8259_INTS    0
 497 #endif
 498 #define NUM_8259_INTERRUPTS NR_8259_INTS
 499
 500 #ifndef CPM_IRQ_OFFSET
 501 #define CPM_IRQ_OFFSET  0
 502 #endif
 503
 504 #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
 505
 506 /* Internal IRQs on MPC85xx OpenPIC */
 507
 508 #ifndef MPC85xx_OPENPIC_IRQ_OFFSET
 509 #ifdef CONFIG_CPM2
 510 #define MPC85xx_OPENPIC_IRQ_OFFSET      (CPM_IRQ_OFFSET + NR_CPM_INTS)
 511 #else
 512 #define MPC85xx_OPENPIC_IRQ_OFFSET      0
 513 #endif
 514 #endif
 515
 516 /* Not all of these exist on all MPC85xx implementations */
 517 #define MPC85xx_IRQ_L2CACHE     ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
 518 #define MPC85xx_IRQ_ECM         ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
 519 #define MPC85xx_IRQ_DDR         ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
 520 #define MPC85xx_IRQ_LBIU        ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
 521 #define MPC85xx_IRQ_DMA0        ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
 522 #define MPC85xx_IRQ_DMA1        ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
 523 #define MPC85xx_IRQ_DMA2        ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
 524 #define MPC85xx_IRQ_DMA3        ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
 525 #define MPC85xx_IRQ_PCI1        ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
 526 #define MPC85xx_IRQ_PCI2        ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
 527 #define MPC85xx_IRQ_RIO_ERROR   ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
 528 #define MPC85xx_IRQ_RIO_BELL    (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
 529 #define MPC85xx_IRQ_RIO_TX      (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
 530 #define MPC85xx_IRQ_RIO_RX      (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
 531 #define MPC85xx_IRQ_TSEC1_TX    (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
 532 #define MPC85xx_IRQ_TSEC1_RX    (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
 533 #define MPC85xx_IRQ_TSEC3_TX    (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
 534 #define MPC85xx_IRQ_TSEC3_RX    (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
 535 #define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
 536 #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
 537 #define MPC85xx_IRQ_TSEC2_TX    (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
 538 #define MPC85xx_IRQ_TSEC2_RX    (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
 539 #define MPC85xx_IRQ_TSEC4_TX    (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
 540 #define MPC85xx_IRQ_TSEC4_RX    (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
 541 #define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
 542 #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
 543 #define MPC85xx_IRQ_FEC         (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
 544 #define MPC85xx_IRQ_DUART       (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
 545 #define MPC85xx_IRQ_IIC1        (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
 546 #define MPC85xx_IRQ_PERFMON     (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
 547 #define MPC85xx_IRQ_SEC2        (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
 548 #define MPC85xx_IRQ_CPM         (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
 549
 550 /* The 12 external interrupt lines */
 551 #define MPC85xx_IRQ_EXT0        (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
 552 #define MPC85xx_IRQ_EXT1        (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
 553 #define MPC85xx_IRQ_EXT2        (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
 554 #define MPC85xx_IRQ_EXT3        (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
 555 #define MPC85xx_IRQ_EXT4        (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
 556 #define MPC85xx_IRQ_EXT5        (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
 557 #define MPC85xx_IRQ_EXT6        (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
 558 #define MPC85xx_IRQ_EXT7        (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
 559 #define MPC85xx_IRQ_EXT8        (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
 560 #define MPC85xx_IRQ_EXT9        (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
 561 #define MPC85xx_IRQ_EXT10       (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
 562 #define MPC85xx_IRQ_EXT11       (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
 563
 564 /* CPM related interrupts */
 565 #define SIU_INT_ERROR           ((uint)0x00+CPM_IRQ_OFFSET)
 566 #define SIU_INT_I2C             ((uint)0x01+CPM_IRQ_OFFSET)
 567 #define SIU_INT_SPI             ((uint)0x02+CPM_IRQ_OFFSET)
 568 #define SIU_INT_RISC            ((uint)0x03+CPM_IRQ_OFFSET)
 569 #define SIU_INT_SMC1            ((uint)0x04+CPM_IRQ_OFFSET)
 570 #define SIU_INT_SMC2            ((uint)0x05+CPM_IRQ_OFFSET)
 571 #define SIU_INT_USB             ((uint)0x0b+CPM_IRQ_OFFSET)
 572 #define SIU_INT_TIMER1          ((uint)0x0c+CPM_IRQ_OFFSET)
 573 #define SIU_INT_TIMER2          ((uint)0x0d+CPM_IRQ_OFFSET)
 574 #define SIU_INT_TIMER3          ((uint)0x0e+CPM_IRQ_OFFSET)
 575 #define SIU_INT_TIMER4          ((uint)0x0f+CPM_IRQ_OFFSET)
 576 #define SIU_INT_FCC1            ((uint)0x20+CPM_IRQ_OFFSET)
 577 #define SIU_INT_FCC2            ((uint)0x21+CPM_IRQ_OFFSET)
 578 #define SIU_INT_FCC3            ((uint)0x22+CPM_IRQ_OFFSET)
 579 #define SIU_INT_MCC1            ((uint)0x24+CPM_IRQ_OFFSET)
 580 #define SIU_INT_MCC2            ((uint)0x25+CPM_IRQ_OFFSET)
 581 #define SIU_INT_SCC1            ((uint)0x28+CPM_IRQ_OFFSET)
 582 #define SIU_INT_SCC2            ((uint)0x29+CPM_IRQ_OFFSET)
 583 #define SIU_INT_SCC3            ((uint)0x2a+CPM_IRQ_OFFSET)
 584 #define SIU_INT_SCC4            ((uint)0x2b+CPM_IRQ_OFFSET)
 585 #define SIU_INT_PC15            ((uint)0x30+CPM_IRQ_OFFSET)
 586 #define SIU_INT_PC14            ((uint)0x31+CPM_IRQ_OFFSET)
 587 #define SIU_INT_PC13            ((uint)0x32+CPM_IRQ_OFFSET)
 588 #define SIU_INT_PC12            ((uint)0x33+CPM_IRQ_OFFSET)
 589 #define SIU_INT_PC11            ((uint)0x34+CPM_IRQ_OFFSET)
 590 #define SIU_INT_PC10            ((uint)0x35+CPM_IRQ_OFFSET)
 591 #define SIU_INT_PC9             ((uint)0x36+CPM_IRQ_OFFSET)
 592 #define SIU_INT_PC8             ((uint)0x37+CPM_IRQ_OFFSET)
 593 #define SIU_INT_PC7             ((uint)0x38+CPM_IRQ_OFFSET)
 594 #define SIU_INT_PC6             ((uint)0x39+CPM_IRQ_OFFSET)
 595 #define SIU_INT_PC5             ((uint)0x3a+CPM_IRQ_OFFSET)
 596 #define SIU_INT_PC4             ((uint)0x3b+CPM_IRQ_OFFSET)
 597 #define SIU_INT_PC3             ((uint)0x3c+CPM_IRQ_OFFSET)
 598 #define SIU_INT_PC2             ((uint)0x3d+CPM_IRQ_OFFSET)
 599 #define SIU_INT_PC1             ((uint)0x3e+CPM_IRQ_OFFSET)
 600 #define SIU_INT_PC0             ((uint)0x3f+CPM_IRQ_OFFSET)
 601
 602 #elif defined(CONFIG_PPC_86xx)
 603 #include <asm/mpc86xx.h>
 604
 605 #define NR_EPIC_INTS 48
 606 #ifndef NR_8259_INTS
 607 #define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
 608 #endif
 609 #define NUM_8259_INTERRUPTS NR_8259_INTS
 610
 611 #ifndef I8259_OFFSET
 612 #define I8259_OFFSET 0
 613 #endif
 614
 615 #define NR_IRQS 256
 616
 617 /* Internal IRQs on MPC86xx OpenPIC */
 618
 619 #ifndef MPC86xx_OPENPIC_IRQ_OFFSET
 620 #define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
 621 #endif
 622
 623 /* The 48 internal sources */
 624 #define MPC86xx_IRQ_NULL        ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
 625 #define MPC86xx_IRQ_MCM         ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
 626 #define MPC86xx_IRQ_DDR         ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
 627 #define MPC86xx_IRQ_LBC         ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
 628 #define MPC86xx_IRQ_DMA0        ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
 629 #define MPC86xx_IRQ_DMA1        ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
 630 #define MPC86xx_IRQ_DMA2        ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
 631 #define MPC86xx_IRQ_DMA3        ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
 632
 633 /* no 10,11 */
 634 #define MPC86xx_IRQ_UART2       (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
 635 #define MPC86xx_IRQ_TSEC1_TX    (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
 636 #define MPC86xx_IRQ_TSEC1_RX    (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
 637 #define MPC86xx_IRQ_TSEC3_TX    (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
 638 #define MPC86xx_IRQ_TSEC3_RX    (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
 639 #define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
 640 #define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
 641 #define MPC86xx_IRQ_TSEC2_TX    (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
 642 #define MPC86xx_IRQ_TSEC2_RX    (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
 643 #define MPC86xx_IRQ_TSEC4_TX    (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
 644 #define MPC86xx_IRQ_TSEC4_RX    (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
 645 #define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
 646 #define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
 647 /* no 25 */
 648 #define MPC86xx_IRQ_UART1       (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
 649 #define MPC86xx_IRQ_IIC         (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
 650 #define MPC86xx_IRQ_PERFMON       (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
 651 /* no 29,30,31 */
 652 #define MPC86xx_IRQ_SRIO_ERROR    (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
 653 #define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
 654 #define MPC86xx_IRQ_SRIO_IN_BELL  (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
 655 /* no 35,36 */
 656 #define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
 657 #define MPC86xx_IRQ_SRIO_IN_MSG1  (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
 658 #define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
 659 #define MPC86xx_IRQ_SRIO_IN_MSG2  (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
 660
 661 /* The 12 external interrupt lines */
 662 #define MPC86xx_IRQ_EXT_BASE    48
 663 #define MPC86xx_IRQ_EXT0        (0 + MPC86xx_IRQ_EXT_BASE \
 664                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 665 #define MPC86xx_IRQ_EXT1        (1 + MPC86xx_IRQ_EXT_BASE \
 666                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 667 #define MPC86xx_IRQ_EXT2        (2 + MPC86xx_IRQ_EXT_BASE \
 668                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 669 #define MPC86xx_IRQ_EXT3        (3 + MPC86xx_IRQ_EXT_BASE \
 670                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 671 #define MPC86xx_IRQ_EXT4        (4 + MPC86xx_IRQ_EXT_BASE \
 672                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 673 #define MPC86xx_IRQ_EXT5        (5 + MPC86xx_IRQ_EXT_BASE \
 674                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 675 #define MPC86xx_IRQ_EXT6        (6 + MPC86xx_IRQ_EXT_BASE \
 676                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 677 #define MPC86xx_IRQ_EXT7        (7 + MPC86xx_IRQ_EXT_BASE \
 678                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 679 #define MPC86xx_IRQ_EXT8        (8 + MPC86xx_IRQ_EXT_BASE \
 680                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 681 #define MPC86xx_IRQ_EXT9        (9 + MPC86xx_IRQ_EXT_BASE \
 682                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 683 #define MPC86xx_IRQ_EXT10       (10 + MPC86xx_IRQ_EXT_BASE \
 684                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 685 #define MPC86xx_IRQ_EXT11       (11 + MPC86xx_IRQ_EXT_BASE \
 686                 + MPC86xx_OPENPIC_IRQ_OFFSET)
 687
 688 #else /* CONFIG_40x + CONFIG_8xx */
 689 /*
 690  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
 691  * so it is the max of them all
 692  */
 693 #define NR_IRQS                 256
 694 #define __DO_IRQ_CANON  1
 695
 696 #ifndef CONFIG_8260
 697
 698 #define NUM_8259_INTERRUPTS     16
 699
 700 #else /* CONFIG_8260 */
 701
 702 /* The 8260 has an internal interrupt controller with a maximum of
 703  * 64 IRQs.  We will use NR_IRQs from above since it is large enough.
 704  * Don't be confused by the 8260 documentation where they list an
 705  * "interrupt number" and "interrupt vector".  We are only interested
 706  * in the interrupt vector.  There are "reserved" holes where the
 707  * vector number increases, but the interrupt number in the table does not.
 708  * (Document errata updates have fixed this...make sure you have up to
 709  * date processor documentation -- Dan).
 710  */
 711
 712 #ifndef CPM_IRQ_OFFSET
 713 #define CPM_IRQ_OFFSET  0
 714 #endif
 715
 716 #define NR_CPM_INTS     64
 717
 718 #define SIU_INT_ERROR           ((uint)0x00 + CPM_IRQ_OFFSET)
 719 #define SIU_INT_I2C             ((uint)0x01 + CPM_IRQ_OFFSET)
 720 #define SIU_INT_SPI             ((uint)0x02 + CPM_IRQ_OFFSET)
 721 #define SIU_INT_RISC            ((uint)0x03 + CPM_IRQ_OFFSET)
 722 #define SIU_INT_SMC1            ((uint)0x04 + CPM_IRQ_OFFSET)
 723 #define SIU_INT_SMC2            ((uint)0x05 + CPM_IRQ_OFFSET)
 724 #define SIU_INT_IDMA1           ((uint)0x06 + CPM_IRQ_OFFSET)
 725 #define SIU_INT_IDMA2           ((uint)0x07 + CPM_IRQ_OFFSET)
 726 #define SIU_INT_IDMA3           ((uint)0x08 + CPM_IRQ_OFFSET)
 727 #define SIU_INT_IDMA4           ((uint)0x09 + CPM_IRQ_OFFSET)
 728 #define SIU_INT_SDMA            ((uint)0x0a + CPM_IRQ_OFFSET)
 729 #define SIU_INT_USB             ((uint)0x0b + CPM_IRQ_OFFSET)
 730 #define SIU_INT_TIMER1          ((uint)0x0c + CPM_IRQ_OFFSET)
 731 #define SIU_INT_TIMER2          ((uint)0x0d + CPM_IRQ_OFFSET)
 732 #define SIU_INT_TIMER3          ((uint)0x0e + CPM_IRQ_OFFSET)
 733 #define SIU_INT_TIMER4          ((uint)0x0f + CPM_IRQ_OFFSET)
 734 #define SIU_INT_TMCNT           ((uint)0x10 + CPM_IRQ_OFFSET)
 735 #define SIU_INT_PIT             ((uint)0x11 + CPM_IRQ_OFFSET)
 736 #define SIU_INT_PCI             ((uint)0x12 + CPM_IRQ_OFFSET)
 737 #define SIU_INT_IRQ1            ((uint)0x13 + CPM_IRQ_OFFSET)
 738 #define SIU_INT_IRQ2            ((uint)0x14 + CPM_IRQ_OFFSET)
 739 #define SIU_INT_IRQ3            ((uint)0x15 + CPM_IRQ_OFFSET)
 740 #define SIU_INT_IRQ4            ((uint)0x16 + CPM_IRQ_OFFSET)
 741 #define SIU_INT_IRQ5            ((uint)0x17 + CPM_IRQ_OFFSET)
 742 #define SIU_INT_IRQ6            ((uint)0x18 + CPM_IRQ_OFFSET)
 743 #define SIU_INT_IRQ7            ((uint)0x19 + CPM_IRQ_OFFSET)
 744 #define SIU_INT_FCC1            ((uint)0x20 + CPM_IRQ_OFFSET)
 745 #define SIU_INT_FCC2            ((uint)0x21 + CPM_IRQ_OFFSET)
 746 #define SIU_INT_FCC3            ((uint)0x22 + CPM_IRQ_OFFSET)
 747 #define SIU_INT_MCC1            ((uint)0x24 + CPM_IRQ_OFFSET)
 748 #define SIU_INT_MCC2            ((uint)0x25 + CPM_IRQ_OFFSET)
 749 #define SIU_INT_SCC1            ((uint)0x28 + CPM_IRQ_OFFSET)
 750 #define SIU_INT_SCC2            ((uint)0x29 + CPM_IRQ_OFFSET)
 751 #define SIU_INT_SCC3            ((uint)0x2a + CPM_IRQ_OFFSET)
 752 #define SIU_INT_SCC4            ((uint)0x2b + CPM_IRQ_OFFSET)
 753 #define SIU_INT_PC15            ((uint)0x30 + CPM_IRQ_OFFSET)
 754 #define SIU_INT_PC14            ((uint)0x31 + CPM_IRQ_OFFSET)
 755 #define SIU_INT_PC13            ((uint)0x32 + CPM_IRQ_OFFSET)
 756 #define SIU_INT_PC12            ((uint)0x33 + CPM_IRQ_OFFSET)
 757 #define SIU_INT_PC11            ((uint)0x34 + CPM_IRQ_OFFSET)
 758 #define SIU_INT_PC10            ((uint)0x35 + CPM_IRQ_OFFSET)
 759 #define SIU_INT_PC9             ((uint)0x36 + CPM_IRQ_OFFSET)
 760 #define SIU_INT_PC8             ((uint)0x37 + CPM_IRQ_OFFSET)
 761 #define SIU_INT_PC7             ((uint)0x38 + CPM_IRQ_OFFSET)
 762 #define SIU_INT_PC6             ((uint)0x39 + CPM_IRQ_OFFSET)
 763 #define SIU_INT_PC5             ((uint)0x3a + CPM_IRQ_OFFSET)
 764 #define SIU_INT_PC4             ((uint)0x3b + CPM_IRQ_OFFSET)
 765 #define SIU_INT_PC3             ((uint)0x3c + CPM_IRQ_OFFSET)
 766 #define SIU_INT_PC2             ((uint)0x3d + CPM_IRQ_OFFSET)
 767 #define SIU_INT_PC1             ((uint)0x3e + CPM_IRQ_OFFSET)
 768 #define SIU_INT_PC0             ((uint)0x3f + CPM_IRQ_OFFSET)
 769
 770 #endif /* CONFIG_8260 */
 771
 772 #endif /* Whatever way too big #ifdef */
 773
 774 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
 775 /* pedantic: these are long because they are used with set_bit --RR */
 776 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
 777
 778 /*
 779  * Because many systems have two overlapping names spaces for
 780  * interrupts (ISA and XICS for example), and the ISA interrupts
 781  * have historically not been easy to renumber, we allow ISA
 782  * interrupts to take values 0 - 15, and shift up the remaining
 783  * interrupts by 0x10.
 784  */
 785 #define NUM_ISA_INTERRUPTS      0x10
 786 extern int __irq_offset_value;
 787
 788 static inline int irq_offset_up(int irq)
 789 {
 790         return(irq + __irq_offset_value);
 791 }
 792
 793 static inline int irq_offset_down(int irq)
 794 {
 795         return(irq - __irq_offset_value);
 796 }
 797
 798 static inline int irq_offset_value(void)
 799 {
 800         return __irq_offset_value;
 801 }
 802
 803 #ifdef __DO_IRQ_CANON
 804 extern int ppc_do_canonicalize_irqs;
 805 #else
 806 #define ppc_do_canonicalize_irqs        0
 807 #endif
 808
 809 static __inline__ int irq_canonicalize(int irq)
 810 {
 811         if (ppc_do_canonicalize_irqs && irq == 2)
 812                 irq = 9;
 813         return irq;
 814 }
 815 #endif /* CONFIG_PPC_MERGE */
 816
 817 extern int distribute_irqs;
 818
 819 struct irqaction;
 820 struct pt_regs;
 821
 822 #define __ARCH_HAS_DO_SOFTIRQ
 823
 824 extern void __do_softirq(void);
 825
 826 #ifdef CONFIG_IRQSTACKS
 827 /*
 828  * Per-cpu stacks for handling hard and soft interrupts.
 829  */
 830 extern struct thread_info *hardirq_ctx[NR_CPUS];
 831 extern struct thread_info *softirq_ctx[NR_CPUS];
 832
 833 extern void irq_ctx_init(void);
 834 extern void call_do_softirq(struct thread_info *tp);
 835 extern int call_handle_irq(int irq, void *p1,
 836                            struct thread_info *tp, void *func);
 837 #else
 838 #define irq_ctx_init()
 839
 840 #endif /* CONFIG_IRQSTACKS */
 841
 842 extern void do_IRQ(struct pt_regs *regs);
 843
 844 #endif /* _ASM_IRQ_H */
 845 #endif /* __KERNEL__ */