1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
33 #include <plat/regs-usb-hsotg-phy.h>
34 #include <plat/regs-usb-hsotg.h>
35 #include <mach/regs-sys.h>
36 #include <plat/udc-hs.h>
39 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 * Unfortunately there seems to be a limit of the amount of data that can
44 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
45 * packets (which practically means 1 packet and 63 bytes of data) when the
48 * This means if we are wanting to move >127 bytes of data, we need to
49 * split the transactions up, but just doing one packet at a time does
50 * not work (this may be an implicit DATA0 PID on first packet of the
51 * transaction) and doing 2 packets is outside the controller's limits.
53 * If we try to lower the MPS size for EP0, then no transfers work properly
54 * for EP0, and the system will fail basic enumeration. As no cause for this
55 * has currently been found, we cannot support any large IN transfers for
58 #define EP0_MPS_LIMIT 64
64 * struct s3c_hsotg_ep - driver endpoint definition.
65 * @ep: The gadget layer representation of the endpoint.
66 * @name: The driver generated name for the endpoint.
67 * @queue: Queue of requests for this endpoint.
68 * @parent: Reference back to the parent device structure.
69 * @req: The current request that the endpoint is processing. This is
70 * used to indicate an request has been loaded onto the endpoint
71 * and has yet to be completed (maybe due to data move, or simply
72 * awaiting an ack from the core all the data has been completed).
73 * @debugfs: File entry for debugfs file for this endpoint.
74 * @lock: State lock to protect contents of endpoint.
75 * @dir_in: Set to true if this endpoint is of the IN direction, which
76 * means that it is sending data to the Host.
77 * @index: The index for the endpoint registers.
78 * @name: The name array passed to the USB core.
79 * @halted: Set if the endpoint has been halted.
80 * @periodic: Set if this is a periodic ep, such as Interrupt
81 * @sent_zlp: Set if we've sent a zero-length packet.
82 * @total_data: The total number of data bytes done.
83 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
84 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
85 * @last_load: The offset of data for the last start of request.
86 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
88 * This is the driver's state for each registered enpoint, allowing it
89 * to keep track of transactions that need doing. Each endpoint has a
90 * lock to protect the state, to try and avoid using an overall lock
91 * for the host controller as much as possible.
93 * For periodic IN endpoints, we have fifo_size and fifo_load to try
94 * and keep track of the amount of data in the periodic FIFO for each
95 * of these as we don't have a status register that tells us how much
96 * is in each of them. (note, this may actually be useless information
97 * as in shared-fifo mode periodic in acts like a single-frame packet
100 struct s3c_hsotg_ep
{
102 struct list_head queue
;
103 struct s3c_hsotg
*parent
;
104 struct s3c_hsotg_req
*req
;
105 struct dentry
*debugfs
;
109 unsigned long total_data
;
110 unsigned int size_loaded
;
111 unsigned int last_load
;
112 unsigned int fifo_load
;
113 unsigned short fifo_size
;
115 unsigned char dir_in
;
118 unsigned int halted
:1;
119 unsigned int periodic
:1;
120 unsigned int sent_zlp
:1;
125 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
128 * struct s3c_hsotg - driver state.
129 * @dev: The parent device supplied to the probe function
130 * @driver: USB gadget driver
131 * @plat: The platform specific configuration data.
132 * @regs: The memory area mapped for accessing registers.
133 * @regs_res: The resource that was allocated when claiming register space.
134 * @irq: The IRQ number we are using
135 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
136 * @debug_root: root directrory for debugfs.
137 * @debug_file: main status file for debugfs.
138 * @debug_fifo: FIFO status file for debugfs.
139 * @ep0_reply: Request used for ep0 reply.
140 * @ep0_buff: Buffer for EP0 reply data, if needed.
141 * @ctrl_buff: Buffer for EP0 control requests.
142 * @ctrl_req: Request for EP0 control packets.
143 * @eps: The endpoints being supplied to the gadget framework
147 struct usb_gadget_driver
*driver
;
148 struct s3c_hsotg_plat
*plat
;
151 struct resource
*regs_res
;
155 unsigned int dedicated_fifos
:1;
157 struct dentry
*debug_root
;
158 struct dentry
*debug_file
;
159 struct dentry
*debug_fifo
;
161 struct usb_request
*ep0_reply
;
162 struct usb_request
*ctrl_req
;
166 struct usb_gadget gadget
;
167 struct s3c_hsotg_ep eps
[];
171 * struct s3c_hsotg_req - data transfer request
172 * @req: The USB gadget request
173 * @queue: The list of requests for the endpoint this is queued for.
174 * @in_progress: Has already had size/packets written to core
175 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
177 struct s3c_hsotg_req
{
178 struct usb_request req
;
179 struct list_head queue
;
180 unsigned char in_progress
;
181 unsigned char mapped
;
184 /* conversion functions */
185 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
187 return container_of(req
, struct s3c_hsotg_req
, req
);
190 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
192 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
195 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
197 return container_of(gadget
, struct s3c_hsotg
, gadget
);
200 static inline void __orr32(void __iomem
*ptr
, u32 val
)
202 writel(readl(ptr
) | val
, ptr
);
205 static inline void __bic32(void __iomem
*ptr
, u32 val
)
207 writel(readl(ptr
) & ~val
, ptr
);
210 /* forward decleration of functions */
211 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
214 * using_dma - return the DMA status of the driver.
215 * @hsotg: The driver state.
217 * Return true if we're using DMA.
219 * Currently, we have the DMA support code worked into everywhere
220 * that needs it, but the AMBA DMA implementation in the hardware can
221 * only DMA from 32bit aligned addresses. This means that gadgets such
222 * as the CDC Ethernet cannot work as they often pass packets which are
225 * Unfortunately the choice to use DMA or not is global to the controller
226 * and seems to be only settable when the controller is being put through
227 * a core reset. This means we either need to fix the gadgets to take
228 * account of DMA alignment, or add bounce buffers (yuerk).
230 * Until this issue is sorted out, we always return 'false'.
232 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
234 return false; /* support is not complete */
238 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
239 * @hsotg: The device state
240 * @ints: A bitmask of the interrupts to enable
242 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
244 u32 gsintmsk
= readl(hsotg
->regs
+ S3C_GINTMSK
);
247 new_gsintmsk
= gsintmsk
| ints
;
249 if (new_gsintmsk
!= gsintmsk
) {
250 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
251 writel(new_gsintmsk
, hsotg
->regs
+ S3C_GINTMSK
);
256 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
257 * @hsotg: The device state
258 * @ints: A bitmask of the interrupts to enable
260 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
262 u32 gsintmsk
= readl(hsotg
->regs
+ S3C_GINTMSK
);
265 new_gsintmsk
= gsintmsk
& ~ints
;
267 if (new_gsintmsk
!= gsintmsk
)
268 writel(new_gsintmsk
, hsotg
->regs
+ S3C_GINTMSK
);
272 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
273 * @hsotg: The device state
274 * @ep: The endpoint index
275 * @dir_in: True if direction is in.
276 * @en: The enable value, true to enable
278 * Set or clear the mask for an individual endpoint's interrupt
281 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
282 unsigned int ep
, unsigned int dir_in
,
292 local_irq_save(flags
);
293 daint
= readl(hsotg
->regs
+ S3C_DAINTMSK
);
298 writel(daint
, hsotg
->regs
+ S3C_DAINTMSK
);
299 local_irq_restore(flags
);
303 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
304 * @hsotg: The device instance.
306 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
314 /* the ryu 2.6.24 release ahs
315 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
316 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
317 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
318 hsotg->regs + S3C_GNPTXFSIZ);
321 /* set FIFO sizes to 2048/1024 */
323 writel(2048, hsotg
->regs
+ S3C_GRXFSIZ
);
324 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
325 S3C_GNPTXFSIZ_NPTxFDep(1024),
326 hsotg
->regs
+ S3C_GNPTXFSIZ
);
328 /* arange all the rest of the TX FIFOs, as some versions of this
329 * block have overlapping default addresses. This also ensures
330 * that if the settings have been changed, then they are set to
333 /* start at the end of the GNPTXFSIZ, rounded up */
337 /* currently we allocate TX FIFOs for all possible endpoints,
338 * and assume that they are all the same size. */
340 for (ep
= 0; ep
<= 15; ep
++) {
342 val
|= size
<< S3C_DPTXFSIZn_DPTxFSize_SHIFT
;
345 writel(val
, hsotg
->regs
+ S3C_DPTXFSIZn(ep
));
348 /* according to p428 of the design guide, we need to ensure that
349 * all fifos are flushed before continuing */
351 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh
|
352 S3C_GRSTCTL_RxFFlsh
, hsotg
->regs
+ S3C_GRSTCTL
);
354 /* wait until the fifos are both flushed */
357 val
= readl(hsotg
->regs
+ S3C_GRSTCTL
);
359 if ((val
& (S3C_GRSTCTL_TxFFlsh
| S3C_GRSTCTL_RxFFlsh
)) == 0)
362 if (--timeout
== 0) {
364 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
371 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
375 * @ep: USB endpoint to allocate request for.
376 * @flags: Allocation flags
378 * Allocate a new USB request structure appropriate for the specified endpoint
380 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
383 struct s3c_hsotg_req
*req
;
385 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
389 INIT_LIST_HEAD(&req
->queue
);
391 req
->req
.dma
= DMA_ADDR_INVALID
;
396 * is_ep_periodic - return true if the endpoint is in periodic mode.
397 * @hs_ep: The endpoint to query.
399 * Returns true if the endpoint is in periodic mode, meaning it is being
400 * used for an Interrupt or ISO transfer.
402 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
404 return hs_ep
->periodic
;
408 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
409 * @hsotg: The device state.
410 * @hs_ep: The endpoint for the request
411 * @hs_req: The request being processed.
413 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
414 * of a request to ensure the buffer is ready for access by the caller.
416 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
417 struct s3c_hsotg_ep
*hs_ep
,
418 struct s3c_hsotg_req
*hs_req
)
420 struct usb_request
*req
= &hs_req
->req
;
421 enum dma_data_direction dir
;
423 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
425 /* ignore this if we're not moving any data */
426 if (hs_req
->req
.length
== 0)
429 if (hs_req
->mapped
) {
430 /* we mapped this, so unmap and remove the dma */
432 dma_unmap_single(hsotg
->dev
, req
->dma
, req
->length
, dir
);
434 req
->dma
= DMA_ADDR_INVALID
;
437 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
442 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
443 * @hsotg: The controller state.
444 * @hs_ep: The endpoint we're going to write for.
445 * @hs_req: The request to write data for.
447 * This is called when the TxFIFO has some space in it to hold a new
448 * transmission and we have something to give it. The actual setup of
449 * the data size is done elsewhere, so all we have to do is to actually
452 * The return value is zero if there is more space (or nothing was done)
453 * otherwise -ENOSPC is returned if the FIFO space was used up.
455 * This routine is only needed for PIO
457 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
458 struct s3c_hsotg_ep
*hs_ep
,
459 struct s3c_hsotg_req
*hs_req
)
461 bool periodic
= is_ep_periodic(hs_ep
);
462 u32 gnptxsts
= readl(hsotg
->regs
+ S3C_GNPTXSTS
);
463 int buf_pos
= hs_req
->req
.actual
;
464 int to_write
= hs_ep
->size_loaded
;
469 to_write
-= (buf_pos
- hs_ep
->last_load
);
471 /* if there's nothing to write, get out early */
475 if (periodic
&& !hsotg
->dedicated_fifos
) {
476 u32 epsize
= readl(hsotg
->regs
+ S3C_DIEPTSIZ(hs_ep
->index
));
480 /* work out how much data was loaded so we can calculate
481 * how much data is left in the fifo. */
483 size_left
= S3C_DxEPTSIZ_XferSize_GET(epsize
);
485 /* if shared fifo, we cannot write anything until the
486 * previous data has been completely sent.
488 if (hs_ep
->fifo_load
!= 0) {
489 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_PTxFEmp
);
493 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
495 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
497 /* how much of the data has moved */
498 size_done
= hs_ep
->size_loaded
- size_left
;
500 /* how much data is left in the fifo */
501 can_write
= hs_ep
->fifo_load
- size_done
;
502 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
503 __func__
, can_write
);
505 can_write
= hs_ep
->fifo_size
- can_write
;
506 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
507 __func__
, can_write
);
509 if (can_write
<= 0) {
510 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_PTxFEmp
);
513 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
514 can_write
= readl(hsotg
->regs
+ S3C_DTXFSTS(hs_ep
->index
));
519 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
521 "%s: no queue slots available (0x%08x)\n",
524 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_NPTxFEmp
);
528 can_write
= S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
529 can_write
*= 4; /* fifo size is in 32bit quantities. */
532 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
533 __func__
, gnptxsts
, can_write
, to_write
, hs_ep
->ep
.maxpacket
);
535 /* limit to 512 bytes of data, it seems at least on the non-periodic
536 * FIFO, requests of >512 cause the endpoint to get stuck with a
537 * fragment of the end of the transfer in it.
542 /* limit the write to one max-packet size worth of data, but allow
543 * the transfer to return that it did not run out of fifo space
545 if (to_write
> hs_ep
->ep
.maxpacket
) {
546 to_write
= hs_ep
->ep
.maxpacket
;
548 s3c_hsotg_en_gsint(hsotg
,
549 periodic
? S3C_GINTSTS_PTxFEmp
:
550 S3C_GINTSTS_NPTxFEmp
);
553 /* see if we can write data */
555 if (to_write
> can_write
) {
556 to_write
= can_write
;
557 pkt_round
= to_write
% hs_ep
->ep
.maxpacket
;
559 /* Not sure, but we probably shouldn't be writing partial
560 * packets into the FIFO, so round the write down to an
561 * exact number of packets.
563 * Note, we do not currently check to see if we can ever
564 * write a full packet or not to the FIFO.
568 to_write
-= pkt_round
;
570 /* enable correct FIFO interrupt to alert us when there
571 * is more room left. */
573 s3c_hsotg_en_gsint(hsotg
,
574 periodic
? S3C_GINTSTS_PTxFEmp
:
575 S3C_GINTSTS_NPTxFEmp
);
578 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
579 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
584 hs_req
->req
.actual
= buf_pos
+ to_write
;
585 hs_ep
->total_data
+= to_write
;
588 hs_ep
->fifo_load
+= to_write
;
590 to_write
= DIV_ROUND_UP(to_write
, 4);
591 data
= hs_req
->req
.buf
+ buf_pos
;
593 writesl(hsotg
->regs
+ S3C_EPFIFO(hs_ep
->index
), data
, to_write
);
595 return (to_write
>= can_write
) ? -ENOSPC
: 0;
599 * get_ep_limit - get the maximum data legnth for this endpoint
600 * @hs_ep: The endpoint
602 * Return the maximum data that can be queued in one go on a given endpoint
603 * so that transfers that are too long can be split.
605 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
607 int index
= hs_ep
->index
;
612 maxsize
= S3C_DxEPTSIZ_XferSize_LIMIT
+ 1;
613 maxpkt
= S3C_DxEPTSIZ_PktCnt_LIMIT
+ 1;
617 maxpkt
= S3C_DIEPTSIZ0_PktCnt_LIMIT
+ 1;
623 /* we made the constant loading easier above by using +1 */
627 /* constrain by packet count if maxpkts*pktsize is greater
628 * than the length register size. */
630 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
631 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
637 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
638 * @hsotg: The controller state.
639 * @hs_ep: The endpoint to process a request for
640 * @hs_req: The request to start.
641 * @continuing: True if we are doing more for the current request.
643 * Start the given request running by setting the endpoint registers
644 * appropriately, and writing any data to the FIFOs.
646 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
647 struct s3c_hsotg_ep
*hs_ep
,
648 struct s3c_hsotg_req
*hs_req
,
651 struct usb_request
*ureq
= &hs_req
->req
;
652 int index
= hs_ep
->index
;
653 int dir_in
= hs_ep
->dir_in
;
663 if (hs_ep
->req
&& !continuing
) {
664 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
667 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
669 "%s: continue different req\n", __func__
);
675 epctrl_reg
= dir_in
? S3C_DIEPCTL(index
) : S3C_DOEPCTL(index
);
676 epsize_reg
= dir_in
? S3C_DIEPTSIZ(index
) : S3C_DOEPTSIZ(index
);
678 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
679 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
680 hs_ep
->dir_in
? "in" : "out");
682 /* If endpoint is stalled, we will restart request later */
683 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
685 if (ctrl
& S3C_DxEPCTL_Stall
) {
686 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
690 length
= ureq
->length
- ureq
->actual
;
694 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
695 ureq
->buf
, length
, ureq
->dma
,
696 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
698 maxreq
= get_ep_limit(hs_ep
);
699 if (length
> maxreq
) {
700 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
702 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
703 __func__
, length
, maxreq
, round
);
705 /* round down to multiple of packets */
713 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
715 packets
= 1; /* send one packet if length is zero. */
717 if (dir_in
&& index
!= 0)
718 epsize
= S3C_DxEPTSIZ_MC(1);
722 if (index
!= 0 && ureq
->zero
) {
723 /* test for the packets being exactly right for the
726 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
730 epsize
|= S3C_DxEPTSIZ_PktCnt(packets
);
731 epsize
|= S3C_DxEPTSIZ_XferSize(length
);
733 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
734 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
736 /* store the request as the current one we're doing */
739 /* write size / packets */
740 writel(epsize
, hsotg
->regs
+ epsize_reg
);
742 if (using_dma(hsotg
)) {
743 unsigned int dma_reg
;
745 /* write DMA address to control register, buffer already
746 * synced by s3c_hsotg_ep_queue(). */
748 dma_reg
= dir_in
? S3C_DIEPDMA(index
) : S3C_DOEPDMA(index
);
749 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
751 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
752 __func__
, ureq
->dma
, dma_reg
);
755 ctrl
|= S3C_DxEPCTL_EPEna
; /* ensure ep enabled */
756 ctrl
|= S3C_DxEPCTL_USBActEp
;
757 ctrl
|= S3C_DxEPCTL_CNAK
; /* clear NAK set by core */
759 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
760 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
762 /* set these, it seems that DMA support increments past the end
763 * of the packet buffer so we need to calculate the length from
764 * this information. */
765 hs_ep
->size_loaded
= length
;
766 hs_ep
->last_load
= ureq
->actual
;
768 if (dir_in
&& !using_dma(hsotg
)) {
769 /* set these anyway, we may need them for non-periodic in */
770 hs_ep
->fifo_load
= 0;
772 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
775 /* clear the INTknTXFEmpMsk when we start request, more as a aide
776 * to debugging to see what is going on. */
778 writel(S3C_DIEPMSK_INTknTXFEmpMsk
,
779 hsotg
->regs
+ S3C_DIEPINT(index
));
781 /* Note, trying to clear the NAK here causes problems with transmit
782 * on the S3C6400 ending up with the TXFIFO becoming full. */
784 /* check ep is enabled */
785 if (!(readl(hsotg
->regs
+ epctrl_reg
) & S3C_DxEPCTL_EPEna
))
787 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
788 index
, readl(hsotg
->regs
+ epctrl_reg
));
790 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
791 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
795 * s3c_hsotg_map_dma - map the DMA memory being used for the request
796 * @hsotg: The device state.
797 * @hs_ep: The endpoint the request is on.
798 * @req: The request being processed.
800 * We've been asked to queue a request, so ensure that the memory buffer
801 * is correctly setup for DMA. If we've been passed an extant DMA address
802 * then ensure the buffer has been synced to memory. If our buffer has no
803 * DMA memory, then we map the memory and mark our request to allow us to
804 * cleanup on completion.
806 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
807 struct s3c_hsotg_ep
*hs_ep
,
808 struct usb_request
*req
)
810 enum dma_data_direction dir
;
811 struct s3c_hsotg_req
*hs_req
= our_req(req
);
813 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
815 /* if the length is zero, ignore the DMA data */
816 if (hs_req
->req
.length
== 0)
819 if (req
->dma
== DMA_ADDR_INVALID
) {
822 dma
= dma_map_single(hsotg
->dev
, req
->buf
, req
->length
, dir
);
824 if (unlikely(dma_mapping_error(hsotg
->dev
, dma
)))
828 dev_err(hsotg
->dev
, "%s: unaligned dma buffer\n",
831 dma_unmap_single(hsotg
->dev
, dma
, req
->length
, dir
);
838 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
845 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
846 __func__
, req
->buf
, req
->length
);
851 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
854 struct s3c_hsotg_req
*hs_req
= our_req(req
);
855 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
856 struct s3c_hsotg
*hs
= hs_ep
->parent
;
857 unsigned long irqflags
;
860 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
861 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
862 req
->zero
, req
->short_not_ok
);
864 /* initialise status of the request */
865 INIT_LIST_HEAD(&hs_req
->queue
);
867 req
->status
= -EINPROGRESS
;
869 /* if we're using DMA, sync the buffers as necessary */
871 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
876 spin_lock_irqsave(&hs_ep
->lock
, irqflags
);
878 first
= list_empty(&hs_ep
->queue
);
879 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
882 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
884 spin_unlock_irqrestore(&hs_ep
->lock
, irqflags
);
889 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
890 struct usb_request
*req
)
892 struct s3c_hsotg_req
*hs_req
= our_req(req
);
898 * s3c_hsotg_complete_oursetup - setup completion callback
899 * @ep: The endpoint the request was on.
900 * @req: The request completed.
902 * Called on completion of any requests the driver itself
903 * submitted that need cleaning up.
905 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
906 struct usb_request
*req
)
908 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
909 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
911 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
913 s3c_hsotg_ep_free_request(ep
, req
);
917 * ep_from_windex - convert control wIndex value to endpoint
918 * @hsotg: The driver state.
919 * @windex: The control request wIndex field (in host order).
921 * Convert the given wIndex into a pointer to an driver endpoint
922 * structure, or return NULL if it is not a valid endpoint.
924 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
927 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
928 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
929 int idx
= windex
& 0x7F;
934 if (idx
> S3C_HSOTG_EPS
)
937 if (idx
&& ep
->dir_in
!= dir
)
944 * s3c_hsotg_send_reply - send reply to control request
945 * @hsotg: The device state
947 * @buff: Buffer for request
948 * @length: Length of reply.
950 * Create a request and queue it on the given endpoint. This is useful as
951 * an internal method of sending replies to certain control requests, etc.
953 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
954 struct s3c_hsotg_ep
*ep
,
958 struct usb_request
*req
;
961 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
963 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
964 hsotg
->ep0_reply
= req
;
966 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
970 req
->buf
= hsotg
->ep0_buff
;
971 req
->length
= length
;
972 req
->zero
= 1; /* always do zero-length final transfer */
973 req
->complete
= s3c_hsotg_complete_oursetup
;
976 memcpy(req
->buf
, buff
, length
);
980 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
982 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
990 * s3c_hsotg_process_req_status - process request GET_STATUS
991 * @hsotg: The device state
992 * @ctrl: USB control request
994 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
995 struct usb_ctrlrequest
*ctrl
)
997 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
998 struct s3c_hsotg_ep
*ep
;
1002 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1005 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1009 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1010 case USB_RECIP_DEVICE
:
1011 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1012 * bit 1 => remote wakeup */
1015 case USB_RECIP_INTERFACE
:
1016 /* currently, the data result should be zero */
1017 reply
= cpu_to_le16(0);
1020 case USB_RECIP_ENDPOINT
:
1021 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1025 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1032 if (le16_to_cpu(ctrl
->wLength
) != 2)
1035 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1037 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1044 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1047 * get_ep_head - return the first request on the endpoint
1048 * @hs_ep: The controller endpoint to get
1050 * Get the first request on the endpoint.
1052 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1054 if (list_empty(&hs_ep
->queue
))
1057 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1061 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1062 * @hsotg: The device state
1063 * @ctrl: USB control request
1065 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1066 struct usb_ctrlrequest
*ctrl
)
1068 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1069 struct s3c_hsotg_req
*hs_req
;
1071 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1072 struct s3c_hsotg_ep
*ep
;
1075 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1076 __func__
, set
? "SET" : "CLEAR");
1078 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1079 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1081 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1082 __func__
, le16_to_cpu(ctrl
->wIndex
));
1086 switch (le16_to_cpu(ctrl
->wValue
)) {
1087 case USB_ENDPOINT_HALT
:
1088 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1090 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1093 "%s: failed to send reply\n", __func__
);
1099 * If we have request in progress,
1105 list_del_init(&hs_req
->queue
);
1106 hs_req
->req
.complete(&ep
->ep
,
1110 /* If we have pending request, then start it */
1111 restart
= !list_empty(&ep
->queue
);
1113 hs_req
= get_ep_head(ep
);
1114 s3c_hsotg_start_req(hsotg
, ep
,
1125 return -ENOENT
; /* currently only deal with endpoint */
1131 * s3c_hsotg_process_control - process a control request
1132 * @hsotg: The device state
1133 * @ctrl: The control request received
1135 * The controller has received the SETUP phase of a control request, and
1136 * needs to work out what to do next (and whether to pass it on to the
1139 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1140 struct usb_ctrlrequest
*ctrl
)
1142 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1148 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1149 ctrl
->bRequest
, ctrl
->bRequestType
,
1150 ctrl
->wValue
, ctrl
->wLength
);
1152 /* record the direction of the request, for later use when enquing
1153 * packets onto EP0. */
1155 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1156 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1158 /* if we've no data with this request, then the last part of the
1159 * transaction is going to implicitly be IN. */
1160 if (ctrl
->wLength
== 0)
1163 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1164 switch (ctrl
->bRequest
) {
1165 case USB_REQ_SET_ADDRESS
:
1166 dcfg
= readl(hsotg
->regs
+ S3C_DCFG
);
1167 dcfg
&= ~S3C_DCFG_DevAddr_MASK
;
1168 dcfg
|= ctrl
->wValue
<< S3C_DCFG_DevAddr_SHIFT
;
1169 writel(dcfg
, hsotg
->regs
+ S3C_DCFG
);
1171 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1173 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1176 case USB_REQ_GET_STATUS
:
1177 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1180 case USB_REQ_CLEAR_FEATURE
:
1181 case USB_REQ_SET_FEATURE
:
1182 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1187 /* as a fallback, try delivering it to the driver to deal with */
1189 if (ret
== 0 && hsotg
->driver
) {
1190 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1192 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1195 /* the request is either unhandlable, or is not formatted correctly
1196 * so respond with a STALL for the status stage to indicate failure.
1203 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1204 reg
= (ep0
->dir_in
) ? S3C_DIEPCTL0
: S3C_DOEPCTL0
;
1206 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1207 * taken effect, so no need to clear later. */
1209 ctrl
= readl(hsotg
->regs
+ reg
);
1210 ctrl
|= S3C_DxEPCTL_Stall
;
1211 ctrl
|= S3C_DxEPCTL_CNAK
;
1212 writel(ctrl
, hsotg
->regs
+ reg
);
1215 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1216 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1218 /* don't believe we need to anything more to get the EP
1219 * to reply with a STALL packet */
1223 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1226 * s3c_hsotg_complete_setup - completion of a setup transfer
1227 * @ep: The endpoint the request was on.
1228 * @req: The request completed.
1230 * Called on completion of any requests the driver itself submitted for
1233 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1234 struct usb_request
*req
)
1236 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1237 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1239 if (req
->status
< 0) {
1240 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1244 if (req
->actual
== 0)
1245 s3c_hsotg_enqueue_setup(hsotg
);
1247 s3c_hsotg_process_control(hsotg
, req
->buf
);
1251 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1252 * @hsotg: The device state.
1254 * Enqueue a request on EP0 if necessary to received any SETUP packets
1255 * received from the host.
1257 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1259 struct usb_request
*req
= hsotg
->ctrl_req
;
1260 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1263 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1267 req
->buf
= hsotg
->ctrl_buff
;
1268 req
->complete
= s3c_hsotg_complete_setup
;
1270 if (!list_empty(&hs_req
->queue
)) {
1271 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1275 hsotg
->eps
[0].dir_in
= 0;
1277 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1279 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1280 /* Don't think there's much we can do other than watch the
1286 * s3c_hsotg_complete_request - complete a request given to us
1287 * @hsotg: The device state.
1288 * @hs_ep: The endpoint the request was on.
1289 * @hs_req: The request to complete.
1290 * @result: The result code (0 => Ok, otherwise errno)
1292 * The given request has finished, so call the necessary completion
1293 * if it has one and then look to see if we can start a new request
1296 * Note, expects the ep to already be locked as appropriate.
1298 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1299 struct s3c_hsotg_ep
*hs_ep
,
1300 struct s3c_hsotg_req
*hs_req
,
1306 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1310 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1311 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1313 /* only replace the status if we've not already set an error
1314 * from a previous transaction */
1316 if (hs_req
->req
.status
== -EINPROGRESS
)
1317 hs_req
->req
.status
= result
;
1320 list_del_init(&hs_req
->queue
);
1322 if (using_dma(hsotg
))
1323 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1325 /* call the complete request with the locks off, just in case the
1326 * request tries to queue more work for this endpoint. */
1328 if (hs_req
->req
.complete
) {
1329 spin_unlock(&hs_ep
->lock
);
1330 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1331 spin_lock(&hs_ep
->lock
);
1334 /* Look to see if there is anything else to do. Note, the completion
1335 * of the previous request may have caused a new request to be started
1336 * so be careful when doing this. */
1338 if (!hs_ep
->req
&& result
>= 0) {
1339 restart
= !list_empty(&hs_ep
->queue
);
1341 hs_req
= get_ep_head(hs_ep
);
1342 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1348 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1349 * @hsotg: The device state.
1350 * @hs_ep: The endpoint the request was on.
1351 * @hs_req: The request to complete.
1352 * @result: The result code (0 => Ok, otherwise errno)
1354 * See s3c_hsotg_complete_request(), but called with the endpoint's
1357 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg
*hsotg
,
1358 struct s3c_hsotg_ep
*hs_ep
,
1359 struct s3c_hsotg_req
*hs_req
,
1362 unsigned long flags
;
1364 spin_lock_irqsave(&hs_ep
->lock
, flags
);
1365 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1366 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
1370 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1371 * @hsotg: The device state.
1372 * @ep_idx: The endpoint index for the data
1373 * @size: The size of data in the fifo, in bytes
1375 * The FIFO status shows there is data to read from the FIFO for a given
1376 * endpoint, so sort out whether we need to read the data into a request
1377 * that has been made for that endpoint.
1379 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1381 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1382 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1383 void __iomem
*fifo
= hsotg
->regs
+ S3C_EPFIFO(ep_idx
);
1389 u32 epctl
= readl(hsotg
->regs
+ S3C_DOEPCTL(ep_idx
));
1392 dev_warn(hsotg
->dev
,
1393 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1394 __func__
, size
, ep_idx
, epctl
);
1396 /* dump the data from the FIFO, we've nothing we can do */
1397 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1403 spin_lock(&hs_ep
->lock
);
1406 read_ptr
= hs_req
->req
.actual
;
1407 max_req
= hs_req
->req
.length
- read_ptr
;
1409 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1410 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1412 if (to_read
> max_req
) {
1413 /* more data appeared than we where willing
1414 * to deal with in this request.
1417 /* currently we don't deal this */
1421 hs_ep
->total_data
+= to_read
;
1422 hs_req
->req
.actual
+= to_read
;
1423 to_read
= DIV_ROUND_UP(to_read
, 4);
1425 /* note, we might over-write the buffer end by 3 bytes depending on
1426 * alignment of the data. */
1427 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1429 spin_unlock(&hs_ep
->lock
);
1433 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1434 * @hsotg: The device instance
1435 * @req: The request currently on this endpoint
1437 * Generate a zero-length IN packet request for terminating a SETUP
1440 * Note, since we don't write any data to the TxFIFO, then it is
1441 * currently believed that we do not need to wait for any space in
1444 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1445 struct s3c_hsotg_req
*req
)
1450 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1454 if (req
->req
.length
== 0) {
1455 hsotg
->eps
[0].sent_zlp
= 1;
1456 s3c_hsotg_enqueue_setup(hsotg
);
1460 hsotg
->eps
[0].dir_in
= 1;
1461 hsotg
->eps
[0].sent_zlp
= 1;
1463 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1465 /* issue a zero-sized packet to terminate this */
1466 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1467 S3C_DxEPTSIZ_XferSize(0), hsotg
->regs
+ S3C_DIEPTSIZ(0));
1469 ctrl
= readl(hsotg
->regs
+ S3C_DIEPCTL0
);
1470 ctrl
|= S3C_DxEPCTL_CNAK
; /* clear NAK set by core */
1471 ctrl
|= S3C_DxEPCTL_EPEna
; /* ensure ep enabled */
1472 ctrl
|= S3C_DxEPCTL_USBActEp
;
1473 writel(ctrl
, hsotg
->regs
+ S3C_DIEPCTL0
);
1477 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1478 * @hsotg: The device instance
1479 * @epnum: The endpoint received from
1480 * @was_setup: Set if processing a SetupDone event.
1482 * The RXFIFO has delivered an OutDone event, which means that the data
1483 * transfer for an OUT endpoint has been completed, either by a short
1484 * packet or by the finish of a transfer.
1486 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1487 int epnum
, bool was_setup
)
1489 u32 epsize
= readl(hsotg
->regs
+ S3C_DOEPTSIZ(epnum
));
1490 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1491 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1492 struct usb_request
*req
= &hs_req
->req
;
1493 unsigned size_left
= S3C_DxEPTSIZ_XferSize_GET(epsize
);
1497 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1501 if (using_dma(hsotg
)) {
1504 /* Calculate the size of the transfer by checking how much
1505 * is left in the endpoint size register and then working it
1506 * out from the amount we loaded for the transfer.
1508 * We need to do this as DMA pointers are always 32bit aligned
1509 * so may overshoot/undershoot the transfer.
1512 size_done
= hs_ep
->size_loaded
- size_left
;
1513 size_done
+= hs_ep
->last_load
;
1515 req
->actual
= size_done
;
1518 /* if there is more request to do, schedule new transfer */
1519 if (req
->actual
< req
->length
&& size_left
== 0) {
1520 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1524 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1525 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1526 __func__
, req
->actual
, req
->length
);
1528 /* todo - what should we return here? there's no one else
1529 * even bothering to check the status. */
1533 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1534 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1537 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, result
);
1541 * s3c_hsotg_read_frameno - read current frame number
1542 * @hsotg: The device instance
1544 * Return the current frame number
1546 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1550 dsts
= readl(hsotg
->regs
+ S3C_DSTS
);
1551 dsts
&= S3C_DSTS_SOFFN_MASK
;
1552 dsts
>>= S3C_DSTS_SOFFN_SHIFT
;
1558 * s3c_hsotg_handle_rx - RX FIFO has data
1559 * @hsotg: The device instance
1561 * The IRQ handler has detected that the RX FIFO has some data in it
1562 * that requires processing, so find out what is in there and do the
1565 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1566 * chunks, so if you have x packets received on an endpoint you'll get x
1567 * FIFO events delivered, each with a packet's worth of data in it.
1569 * When using DMA, we should not be processing events from the RXFIFO
1570 * as the actual data should be sent to the memory directly and we turn
1571 * on the completion interrupts to get notifications of transfer completion.
1573 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1575 u32 grxstsr
= readl(hsotg
->regs
+ S3C_GRXSTSP
);
1576 u32 epnum
, status
, size
;
1578 WARN_ON(using_dma(hsotg
));
1580 epnum
= grxstsr
& S3C_GRXSTS_EPNum_MASK
;
1581 status
= grxstsr
& S3C_GRXSTS_PktSts_MASK
;
1583 size
= grxstsr
& S3C_GRXSTS_ByteCnt_MASK
;
1584 size
>>= S3C_GRXSTS_ByteCnt_SHIFT
;
1587 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1588 __func__
, grxstsr
, size
, epnum
);
1590 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1592 switch (status
>> S3C_GRXSTS_PktSts_SHIFT
) {
1593 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK
):
1594 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1597 case __status(S3C_GRXSTS_PktSts_OutDone
):
1598 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1599 s3c_hsotg_read_frameno(hsotg
));
1601 if (!using_dma(hsotg
))
1602 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1605 case __status(S3C_GRXSTS_PktSts_SetupDone
):
1607 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1608 s3c_hsotg_read_frameno(hsotg
),
1609 readl(hsotg
->regs
+ S3C_DOEPCTL(0)));
1611 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1614 case __status(S3C_GRXSTS_PktSts_OutRX
):
1615 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1618 case __status(S3C_GRXSTS_PktSts_SetupRX
):
1620 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1621 s3c_hsotg_read_frameno(hsotg
),
1622 readl(hsotg
->regs
+ S3C_DOEPCTL(0)));
1624 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1628 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1631 s3c_hsotg_dump(hsotg
);
1637 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1638 * @mps: The maximum packet size in bytes.
1640 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1644 return S3C_D0EPCTL_MPS_64
;
1646 return S3C_D0EPCTL_MPS_32
;
1648 return S3C_D0EPCTL_MPS_16
;
1650 return S3C_D0EPCTL_MPS_8
;
1653 /* bad max packet size, warn and return invalid result */
1659 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1660 * @hsotg: The driver state.
1661 * @ep: The index number of the endpoint
1662 * @mps: The maximum packet size in bytes
1664 * Configure the maximum packet size for the given endpoint, updating
1665 * the hardware control registers to reflect this.
1667 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1668 unsigned int ep
, unsigned int mps
)
1670 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1671 void __iomem
*regs
= hsotg
->regs
;
1676 /* EP0 is a special case */
1677 mpsval
= s3c_hsotg_ep0_mps(mps
);
1681 if (mps
>= S3C_DxEPCTL_MPS_LIMIT
+1)
1687 hs_ep
->ep
.maxpacket
= mps
;
1689 /* update both the in and out endpoint controldir_ registers, even
1690 * if one of the directions may not be in use. */
1692 reg
= readl(regs
+ S3C_DIEPCTL(ep
));
1693 reg
&= ~S3C_DxEPCTL_MPS_MASK
;
1695 writel(reg
, regs
+ S3C_DIEPCTL(ep
));
1697 reg
= readl(regs
+ S3C_DOEPCTL(ep
));
1698 reg
&= ~S3C_DxEPCTL_MPS_MASK
;
1700 writel(reg
, regs
+ S3C_DOEPCTL(ep
));
1705 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1709 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1710 * @hsotg: The driver state
1711 * @idx: The index for the endpoint (0..15)
1713 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1718 writel(S3C_GRSTCTL_TxFNum(idx
) | S3C_GRSTCTL_TxFFlsh
,
1719 hsotg
->regs
+ S3C_GRSTCTL
);
1721 /* wait until the fifo is flushed */
1725 val
= readl(hsotg
->regs
+ S3C_GRSTCTL
);
1727 if ((val
& (S3C_GRSTCTL_TxFFlsh
)) == 0)
1730 if (--timeout
== 0) {
1732 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1741 * s3c_hsotg_trytx - check to see if anything needs transmitting
1742 * @hsotg: The driver state
1743 * @hs_ep: The driver endpoint to check.
1745 * Check to see if there is a request that has data to send, and if so
1746 * make an attempt to write data into the FIFO.
1748 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1749 struct s3c_hsotg_ep
*hs_ep
)
1751 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1753 if (!hs_ep
->dir_in
|| !hs_req
)
1756 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1757 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1759 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1766 * s3c_hsotg_complete_in - complete IN transfer
1767 * @hsotg: The device state.
1768 * @hs_ep: The endpoint that has just completed.
1770 * An IN transfer has been completed, update the transfer's state and then
1771 * call the relevant completion routines.
1773 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1774 struct s3c_hsotg_ep
*hs_ep
)
1776 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1777 u32 epsize
= readl(hsotg
->regs
+ S3C_DIEPTSIZ(hs_ep
->index
));
1778 int size_left
, size_done
;
1781 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1785 /* Calculate the size of the transfer by checking how much is left
1786 * in the endpoint size register and then working it out from
1787 * the amount we loaded for the transfer.
1789 * We do this even for DMA, as the transfer may have incremented
1790 * past the end of the buffer (DMA transfers are always 32bit
1794 size_left
= S3C_DxEPTSIZ_XferSize_GET(epsize
);
1796 size_done
= hs_ep
->size_loaded
- size_left
;
1797 size_done
+= hs_ep
->last_load
;
1799 if (hs_req
->req
.actual
!= size_done
)
1800 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1801 __func__
, hs_req
->req
.actual
, size_done
);
1803 hs_req
->req
.actual
= size_done
;
1805 /* if we did all of the transfer, and there is more data left
1806 * around, then try restarting the rest of the request */
1808 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1809 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1810 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1812 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, 0);
1816 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1817 * @hsotg: The driver state
1818 * @idx: The index for the endpoint (0..15)
1819 * @dir_in: Set if this is an IN endpoint
1821 * Process and clear any interrupt pending for an individual endpoint
1823 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1826 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1827 u32 epint_reg
= dir_in
? S3C_DIEPINT(idx
) : S3C_DOEPINT(idx
);
1828 u32 epctl_reg
= dir_in
? S3C_DIEPCTL(idx
) : S3C_DOEPCTL(idx
);
1829 u32 epsiz_reg
= dir_in
? S3C_DIEPTSIZ(idx
) : S3C_DOEPTSIZ(idx
);
1832 ints
= readl(hsotg
->regs
+ epint_reg
);
1834 /* Clear endpoint interrupts */
1835 writel(ints
, hsotg
->regs
+ epint_reg
);
1837 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1838 __func__
, idx
, dir_in
? "in" : "out", ints
);
1840 if (ints
& S3C_DxEPINT_XferCompl
) {
1842 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1843 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1844 readl(hsotg
->regs
+ epsiz_reg
));
1846 /* we get OutDone from the FIFO, so we only need to look
1847 * at completing IN requests here */
1849 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1851 if (idx
== 0 && !hs_ep
->req
)
1852 s3c_hsotg_enqueue_setup(hsotg
);
1853 } else if (using_dma(hsotg
)) {
1854 /* We're using DMA, we need to fire an OutDone here
1855 * as we ignore the RXFIFO. */
1857 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1861 if (ints
& S3C_DxEPINT_EPDisbld
) {
1862 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1865 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1867 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1869 if ((epctl
& S3C_DxEPCTL_Stall
) &&
1870 (epctl
& S3C_DxEPCTL_EPType_Bulk
)) {
1871 int dctl
= readl(hsotg
->regs
+ S3C_DCTL
);
1873 dctl
|= S3C_DCTL_CGNPInNAK
;
1874 writel(dctl
, hsotg
->regs
+ S3C_DCTL
);
1879 if (ints
& S3C_DxEPINT_AHBErr
)
1880 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1882 if (ints
& S3C_DxEPINT_Setup
) { /* Setup or Timeout */
1883 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1885 if (using_dma(hsotg
) && idx
== 0) {
1886 /* this is the notification we've received a
1887 * setup packet. In non-DMA mode we'd get this
1888 * from the RXFIFO, instead we need to process
1889 * the setup here. */
1894 s3c_hsotg_handle_outdone(hsotg
, 0, true);
1898 if (ints
& S3C_DxEPINT_Back2BackSetup
)
1899 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
1902 /* not sure if this is important, but we'll clear it anyway
1904 if (ints
& S3C_DIEPMSK_INTknTXFEmpMsk
) {
1905 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
1909 /* this probably means something bad is happening */
1910 if (ints
& S3C_DIEPMSK_INTknEPMisMsk
) {
1911 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
1915 /* FIFO has space or is empty (see GAHBCFG) */
1916 if (hsotg
->dedicated_fifos
&&
1917 ints
& S3C_DIEPMSK_TxFIFOEmpty
) {
1918 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
1920 s3c_hsotg_trytx(hsotg
, hs_ep
);
1926 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1927 * @hsotg: The device state.
1929 * Handle updating the device settings after the enumeration phase has
1932 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
1934 u32 dsts
= readl(hsotg
->regs
+ S3C_DSTS
);
1935 int ep0_mps
= 0, ep_mps
;
1937 /* This should signal the finish of the enumeration phase
1938 * of the USB handshaking, so we should now know what rate
1939 * we connected at. */
1941 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
1943 /* note, since we're limited by the size of transfer on EP0, and
1944 * it seems IN transfers must be a even number of packets we do
1945 * not advertise a 64byte MPS on EP0. */
1947 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1948 switch (dsts
& S3C_DSTS_EnumSpd_MASK
) {
1949 case S3C_DSTS_EnumSpd_FS
:
1950 case S3C_DSTS_EnumSpd_FS48
:
1951 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
1952 dev_info(hsotg
->dev
, "new device is full-speed\n");
1954 ep0_mps
= EP0_MPS_LIMIT
;
1958 case S3C_DSTS_EnumSpd_HS
:
1959 dev_info(hsotg
->dev
, "new device is high-speed\n");
1960 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
1962 ep0_mps
= EP0_MPS_LIMIT
;
1966 case S3C_DSTS_EnumSpd_LS
:
1967 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
1968 dev_info(hsotg
->dev
, "new device is low-speed\n");
1970 /* note, we don't actually support LS in this driver at the
1971 * moment, and the documentation seems to imply that it isn't
1972 * supported by the PHYs on some of the devices.
1977 /* we should now know the maximum packet size for an
1978 * endpoint, so set the endpoints to a default value. */
1982 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
1983 for (i
= 1; i
< S3C_HSOTG_EPS
; i
++)
1984 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
1987 /* ensure after enumeration our EP0 is active */
1989 s3c_hsotg_enqueue_setup(hsotg
);
1991 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1992 readl(hsotg
->regs
+ S3C_DIEPCTL0
),
1993 readl(hsotg
->regs
+ S3C_DOEPCTL0
));
1997 * kill_all_requests - remove all requests from the endpoint's queue
1998 * @hsotg: The device state.
1999 * @ep: The endpoint the requests may be on.
2000 * @result: The result code to use.
2001 * @force: Force removal of any current requests
2003 * Go through the requests on the given endpoint and mark them
2004 * completed with the given result code.
2006 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2007 struct s3c_hsotg_ep
*ep
,
2008 int result
, bool force
)
2010 struct s3c_hsotg_req
*req
, *treq
;
2011 unsigned long flags
;
2013 spin_lock_irqsave(&ep
->lock
, flags
);
2015 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2016 /* currently, we can't do much about an already
2017 * running request on an in endpoint */
2019 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2022 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2026 spin_unlock_irqrestore(&ep
->lock
, flags
);
2029 #define call_gadget(_hs, _entry) \
2030 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2031 (_hs)->driver && (_hs)->driver->_entry) \
2032 (_hs)->driver->_entry(&(_hs)->gadget);
2035 * s3c_hsotg_disconnect_irq - disconnect irq service
2036 * @hsotg: The device state.
2038 * A disconnect IRQ has been received, meaning that the host has
2039 * lost contact with the bus. Remove all current transactions
2040 * and signal the gadget driver that this has happened.
2042 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg
*hsotg
)
2046 for (ep
= 0; ep
< S3C_HSOTG_EPS
; ep
++)
2047 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2049 call_gadget(hsotg
, disconnect
);
2053 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2054 * @hsotg: The device state:
2055 * @periodic: True if this is a periodic FIFO interrupt
2057 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2059 struct s3c_hsotg_ep
*ep
;
2062 /* look through for any more data to transmit */
2064 for (epno
= 0; epno
< S3C_HSOTG_EPS
; epno
++) {
2065 ep
= &hsotg
->eps
[epno
];
2070 if ((periodic
&& !ep
->periodic
) ||
2071 (!periodic
&& ep
->periodic
))
2074 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2080 static struct s3c_hsotg
*our_hsotg
;
2082 /* IRQ flags which will trigger a retry around the IRQ loop */
2083 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2084 S3C_GINTSTS_PTxFEmp | \
2088 * s3c_hsotg_irq - handle device interrupt
2089 * @irq: The IRQ number triggered
2090 * @pw: The pw value when registered the handler.
2092 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2094 struct s3c_hsotg
*hsotg
= pw
;
2095 int retry_count
= 8;
2100 gintsts
= readl(hsotg
->regs
+ S3C_GINTSTS
);
2101 gintmsk
= readl(hsotg
->regs
+ S3C_GINTMSK
);
2103 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2104 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2108 if (gintsts
& S3C_GINTSTS_OTGInt
) {
2109 u32 otgint
= readl(hsotg
->regs
+ S3C_GOTGINT
);
2111 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2113 writel(otgint
, hsotg
->regs
+ S3C_GOTGINT
);
2116 if (gintsts
& S3C_GINTSTS_DisconnInt
) {
2117 dev_dbg(hsotg
->dev
, "%s: DisconnInt\n", __func__
);
2118 writel(S3C_GINTSTS_DisconnInt
, hsotg
->regs
+ S3C_GINTSTS
);
2120 s3c_hsotg_disconnect_irq(hsotg
);
2123 if (gintsts
& S3C_GINTSTS_SessReqInt
) {
2124 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2125 writel(S3C_GINTSTS_SessReqInt
, hsotg
->regs
+ S3C_GINTSTS
);
2128 if (gintsts
& S3C_GINTSTS_EnumDone
) {
2129 writel(S3C_GINTSTS_EnumDone
, hsotg
->regs
+ S3C_GINTSTS
);
2131 s3c_hsotg_irq_enumdone(hsotg
);
2134 if (gintsts
& S3C_GINTSTS_ConIDStsChng
) {
2135 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2136 readl(hsotg
->regs
+ S3C_DSTS
),
2137 readl(hsotg
->regs
+ S3C_GOTGCTL
));
2139 writel(S3C_GINTSTS_ConIDStsChng
, hsotg
->regs
+ S3C_GINTSTS
);
2142 if (gintsts
& (S3C_GINTSTS_OEPInt
| S3C_GINTSTS_IEPInt
)) {
2143 u32 daint
= readl(hsotg
->regs
+ S3C_DAINT
);
2144 u32 daint_out
= daint
>> S3C_DAINT_OutEP_SHIFT
;
2145 u32 daint_in
= daint
& ~(daint_out
<< S3C_DAINT_OutEP_SHIFT
);
2148 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2150 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2152 s3c_hsotg_epint(hsotg
, ep
, 0);
2155 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2157 s3c_hsotg_epint(hsotg
, ep
, 1);
2161 if (gintsts
& S3C_GINTSTS_USBRst
) {
2162 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2163 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2164 readl(hsotg
->regs
+ S3C_GNPTXSTS
));
2166 writel(S3C_GINTSTS_USBRst
, hsotg
->regs
+ S3C_GINTSTS
);
2168 kill_all_requests(hsotg
, &hsotg
->eps
[0], -ECONNRESET
, true);
2170 /* it seems after a reset we can end up with a situation
2171 * where the TXFIFO still has data in it... the docs
2172 * suggest resetting all the fifos, so use the init_fifo
2173 * code to relayout and flush the fifos.
2176 s3c_hsotg_init_fifo(hsotg
);
2178 s3c_hsotg_enqueue_setup(hsotg
);
2181 /* check both FIFOs */
2183 if (gintsts
& S3C_GINTSTS_NPTxFEmp
) {
2184 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2186 /* Disable the interrupt to stop it happening again
2187 * unless one of these endpoint routines decides that
2188 * it needs re-enabling */
2190 s3c_hsotg_disable_gsint(hsotg
, S3C_GINTSTS_NPTxFEmp
);
2191 s3c_hsotg_irq_fifoempty(hsotg
, false);
2194 if (gintsts
& S3C_GINTSTS_PTxFEmp
) {
2195 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2197 /* See note in S3C_GINTSTS_NPTxFEmp */
2199 s3c_hsotg_disable_gsint(hsotg
, S3C_GINTSTS_PTxFEmp
);
2200 s3c_hsotg_irq_fifoempty(hsotg
, true);
2203 if (gintsts
& S3C_GINTSTS_RxFLvl
) {
2204 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2205 * we need to retry s3c_hsotg_handle_rx if this is still
2208 s3c_hsotg_handle_rx(hsotg
);
2211 if (gintsts
& S3C_GINTSTS_ModeMis
) {
2212 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2213 writel(S3C_GINTSTS_ModeMis
, hsotg
->regs
+ S3C_GINTSTS
);
2216 if (gintsts
& S3C_GINTSTS_USBSusp
) {
2217 dev_info(hsotg
->dev
, "S3C_GINTSTS_USBSusp\n");
2218 writel(S3C_GINTSTS_USBSusp
, hsotg
->regs
+ S3C_GINTSTS
);
2220 call_gadget(hsotg
, suspend
);
2223 if (gintsts
& S3C_GINTSTS_WkUpInt
) {
2224 dev_info(hsotg
->dev
, "S3C_GINTSTS_WkUpIn\n");
2225 writel(S3C_GINTSTS_WkUpInt
, hsotg
->regs
+ S3C_GINTSTS
);
2227 call_gadget(hsotg
, resume
);
2230 if (gintsts
& S3C_GINTSTS_ErlySusp
) {
2231 dev_dbg(hsotg
->dev
, "S3C_GINTSTS_ErlySusp\n");
2232 writel(S3C_GINTSTS_ErlySusp
, hsotg
->regs
+ S3C_GINTSTS
);
2235 /* these next two seem to crop-up occasionally causing the core
2236 * to shutdown the USB transfer, so try clearing them and logging
2237 * the occurrence. */
2239 if (gintsts
& S3C_GINTSTS_GOUTNakEff
) {
2240 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2242 writel(S3C_DCTL_CGOUTNak
, hsotg
->regs
+ S3C_DCTL
);
2244 s3c_hsotg_dump(hsotg
);
2247 if (gintsts
& S3C_GINTSTS_GINNakEff
) {
2248 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2250 writel(S3C_DCTL_CGNPInNAK
, hsotg
->regs
+ S3C_DCTL
);
2252 s3c_hsotg_dump(hsotg
);
2255 /* if we've had fifo events, we should try and go around the
2256 * loop again to see if there's any point in returning yet. */
2258 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2265 * s3c_hsotg_ep_enable - enable the given endpoint
2266 * @ep: The USB endpint to configure
2267 * @desc: The USB endpoint descriptor to configure with.
2269 * This is called from the USB gadget code's usb_ep_enable().
2271 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2272 const struct usb_endpoint_descriptor
*desc
)
2274 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2275 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2276 unsigned long flags
;
2277 int index
= hs_ep
->index
;
2285 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2286 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2287 desc
->wMaxPacketSize
, desc
->bInterval
);
2289 /* not to be called for EP0 */
2290 WARN_ON(index
== 0);
2292 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2293 if (dir_in
!= hs_ep
->dir_in
) {
2294 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2298 mps
= le16_to_cpu(desc
->wMaxPacketSize
);
2300 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2302 epctrl_reg
= dir_in
? S3C_DIEPCTL(index
) : S3C_DOEPCTL(index
);
2303 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2305 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2306 __func__
, epctrl
, epctrl_reg
);
2308 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2310 epctrl
&= ~(S3C_DxEPCTL_EPType_MASK
| S3C_DxEPCTL_MPS_MASK
);
2311 epctrl
|= S3C_DxEPCTL_MPS(mps
);
2313 /* mark the endpoint as active, otherwise the core may ignore
2314 * transactions entirely for this endpoint */
2315 epctrl
|= S3C_DxEPCTL_USBActEp
;
2317 /* set the NAK status on the endpoint, otherwise we might try and
2318 * do something with data that we've yet got a request to process
2319 * since the RXFIFO will take data for an endpoint even if the
2320 * size register hasn't been set.
2323 epctrl
|= S3C_DxEPCTL_SNAK
;
2325 /* update the endpoint state */
2326 hs_ep
->ep
.maxpacket
= mps
;
2328 /* default, set to non-periodic */
2329 hs_ep
->periodic
= 0;
2331 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2332 case USB_ENDPOINT_XFER_ISOC
:
2333 dev_err(hsotg
->dev
, "no current ISOC support\n");
2337 case USB_ENDPOINT_XFER_BULK
:
2338 epctrl
|= S3C_DxEPCTL_EPType_Bulk
;
2341 case USB_ENDPOINT_XFER_INT
:
2343 /* Allocate our TxFNum by simply using the index
2344 * of the endpoint for the moment. We could do
2345 * something better if the host indicates how
2346 * many FIFOs we are expecting to use. */
2348 hs_ep
->periodic
= 1;
2349 epctrl
|= S3C_DxEPCTL_TxFNum(index
);
2352 epctrl
|= S3C_DxEPCTL_EPType_Intterupt
;
2355 case USB_ENDPOINT_XFER_CONTROL
:
2356 epctrl
|= S3C_DxEPCTL_EPType_Control
;
2360 /* if the hardware has dedicated fifos, we must give each IN EP
2361 * a unique tx-fifo even if it is non-periodic.
2363 if (dir_in
&& hsotg
->dedicated_fifos
)
2364 epctrl
|= S3C_DxEPCTL_TxFNum(index
);
2366 /* for non control endpoints, set PID to D0 */
2368 epctrl
|= S3C_DxEPCTL_SetD0PID
;
2370 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2373 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2374 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2375 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2377 /* enable the endpoint interrupt */
2378 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2381 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2385 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2387 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2388 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2389 int dir_in
= hs_ep
->dir_in
;
2390 int index
= hs_ep
->index
;
2391 unsigned long flags
;
2395 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2397 if (ep
== &hsotg
->eps
[0].ep
) {
2398 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2402 epctrl_reg
= dir_in
? S3C_DIEPCTL(index
) : S3C_DOEPCTL(index
);
2404 /* terminate all requests with shutdown */
2405 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2407 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2409 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2410 ctrl
&= ~S3C_DxEPCTL_EPEna
;
2411 ctrl
&= ~S3C_DxEPCTL_USBActEp
;
2412 ctrl
|= S3C_DxEPCTL_SNAK
;
2414 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2415 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2417 /* disable endpoint interrupts */
2418 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2420 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2425 * on_list - check request is on the given endpoint
2426 * @ep: The endpoint to check.
2427 * @test: The request to test if it is on the endpoint.
2429 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2431 struct s3c_hsotg_req
*req
, *treq
;
2433 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2441 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2443 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2444 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2445 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2446 unsigned long flags
;
2448 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2450 spin_lock_irqsave(&hs_ep
->lock
, flags
);
2452 if (!on_list(hs_ep
, hs_req
)) {
2453 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2457 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2458 spin_unlock_irqrestore(&hs_ep
->lock
, flags
);
2463 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2465 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2466 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2467 int index
= hs_ep
->index
;
2468 unsigned long irqflags
;
2473 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2475 spin_lock_irqsave(&hs_ep
->lock
, irqflags
);
2477 /* write both IN and OUT control registers */
2479 epreg
= S3C_DIEPCTL(index
);
2480 epctl
= readl(hs
->regs
+ epreg
);
2483 epctl
|= S3C_DxEPCTL_Stall
+ S3C_DxEPCTL_SNAK
;
2484 if (epctl
& S3C_DxEPCTL_EPEna
)
2485 epctl
|= S3C_DxEPCTL_EPDis
;
2487 epctl
&= ~S3C_DxEPCTL_Stall
;
2488 xfertype
= epctl
& S3C_DxEPCTL_EPType_MASK
;
2489 if (xfertype
== S3C_DxEPCTL_EPType_Bulk
||
2490 xfertype
== S3C_DxEPCTL_EPType_Intterupt
)
2491 epctl
|= S3C_DxEPCTL_SetD0PID
;
2494 writel(epctl
, hs
->regs
+ epreg
);
2496 epreg
= S3C_DOEPCTL(index
);
2497 epctl
= readl(hs
->regs
+ epreg
);
2500 epctl
|= S3C_DxEPCTL_Stall
;
2502 epctl
&= ~S3C_DxEPCTL_Stall
;
2503 xfertype
= epctl
& S3C_DxEPCTL_EPType_MASK
;
2504 if (xfertype
== S3C_DxEPCTL_EPType_Bulk
||
2505 xfertype
== S3C_DxEPCTL_EPType_Intterupt
)
2506 epctl
|= S3C_DxEPCTL_SetD0PID
;
2509 writel(epctl
, hs
->regs
+ epreg
);
2511 spin_unlock_irqrestore(&hs_ep
->lock
, irqflags
);
2516 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2517 .enable
= s3c_hsotg_ep_enable
,
2518 .disable
= s3c_hsotg_ep_disable
,
2519 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2520 .free_request
= s3c_hsotg_ep_free_request
,
2521 .queue
= s3c_hsotg_ep_queue
,
2522 .dequeue
= s3c_hsotg_ep_dequeue
,
2523 .set_halt
= s3c_hsotg_ep_sethalt
,
2524 /* note, don't believe we have any call for the fifo routines */
2528 * s3c_hsotg_corereset - issue softreset to the core
2529 * @hsotg: The device state
2531 * Issue a soft reset to the core, and await the core finishing it.
2533 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2538 dev_dbg(hsotg
->dev
, "resetting core\n");
2540 /* issue soft reset */
2541 writel(S3C_GRSTCTL_CSftRst
, hsotg
->regs
+ S3C_GRSTCTL
);
2545 grstctl
= readl(hsotg
->regs
+ S3C_GRSTCTL
);
2546 } while ((grstctl
& S3C_GRSTCTL_CSftRst
) && timeout
-- > 0);
2548 if (grstctl
& S3C_GRSTCTL_CSftRst
) {
2549 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2556 u32 grstctl
= readl(hsotg
->regs
+ S3C_GRSTCTL
);
2558 if (timeout
-- < 0) {
2559 dev_info(hsotg
->dev
,
2560 "%s: reset failed, GRSTCTL=%08x\n",
2565 if (!(grstctl
& S3C_GRSTCTL_AHBIdle
))
2568 break; /* reset done */
2571 dev_dbg(hsotg
->dev
, "reset successful\n");
2575 int usb_gadget_probe_driver(struct usb_gadget_driver
*driver
,
2576 int (*bind
)(struct usb_gadget
*))
2578 struct s3c_hsotg
*hsotg
= our_hsotg
;
2582 printk(KERN_ERR
"%s: called with no device\n", __func__
);
2587 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2591 if (driver
->speed
!= USB_SPEED_HIGH
&&
2592 driver
->speed
!= USB_SPEED_FULL
) {
2593 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2596 if (!bind
|| !driver
->setup
) {
2597 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2601 WARN_ON(hsotg
->driver
);
2603 driver
->driver
.bus
= NULL
;
2604 hsotg
->driver
= driver
;
2605 hsotg
->gadget
.dev
.driver
= &driver
->driver
;
2606 hsotg
->gadget
.dev
.dma_mask
= hsotg
->dev
->dma_mask
;
2607 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2609 ret
= device_add(&hsotg
->gadget
.dev
);
2611 dev_err(hsotg
->dev
, "failed to register gadget device\n");
2615 ret
= bind(&hsotg
->gadget
);
2617 dev_err(hsotg
->dev
, "failed bind %s\n", driver
->driver
.name
);
2619 hsotg
->gadget
.dev
.driver
= NULL
;
2620 hsotg
->driver
= NULL
;
2624 /* we must now enable ep0 ready for host detection and then
2625 * set configuration. */
2627 s3c_hsotg_corereset(hsotg
);
2629 /* set the PLL on, remove the HNP/SRP and set the PHY */
2630 writel(S3C_GUSBCFG_PHYIf16
| S3C_GUSBCFG_TOutCal(7) |
2631 (0x5 << 10), hsotg
->regs
+ S3C_GUSBCFG
);
2633 /* looks like soft-reset changes state of FIFOs */
2634 s3c_hsotg_init_fifo(hsotg
);
2636 __orr32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_SftDiscon
);
2638 writel(1 << 18 | S3C_DCFG_DevSpd_HS
, hsotg
->regs
+ S3C_DCFG
);
2640 /* Clear any pending OTG interrupts */
2641 writel(0xffffffff, hsotg
->regs
+ S3C_GOTGINT
);
2643 /* Clear any pending interrupts */
2644 writel(0xffffffff, hsotg
->regs
+ S3C_GINTSTS
);
2646 writel(S3C_GINTSTS_DisconnInt
| S3C_GINTSTS_SessReqInt
|
2647 S3C_GINTSTS_ConIDStsChng
| S3C_GINTSTS_USBRst
|
2648 S3C_GINTSTS_EnumDone
| S3C_GINTSTS_OTGInt
|
2649 S3C_GINTSTS_USBSusp
| S3C_GINTSTS_WkUpInt
|
2650 S3C_GINTSTS_GOUTNakEff
| S3C_GINTSTS_GINNakEff
|
2651 S3C_GINTSTS_ErlySusp
,
2652 hsotg
->regs
+ S3C_GINTMSK
);
2654 if (using_dma(hsotg
))
2655 writel(S3C_GAHBCFG_GlblIntrEn
| S3C_GAHBCFG_DMAEn
|
2656 S3C_GAHBCFG_HBstLen_Incr4
,
2657 hsotg
->regs
+ S3C_GAHBCFG
);
2659 writel(S3C_GAHBCFG_GlblIntrEn
, hsotg
->regs
+ S3C_GAHBCFG
);
2661 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2662 * up being flooded with interrupts if the host is polling the
2663 * endpoint to try and read data. */
2665 writel(S3C_DIEPMSK_TimeOUTMsk
| S3C_DIEPMSK_AHBErrMsk
|
2666 S3C_DIEPMSK_INTknEPMisMsk
|
2667 S3C_DIEPMSK_EPDisbldMsk
| S3C_DIEPMSK_XferComplMsk
|
2668 ((hsotg
->dedicated_fifos
) ? S3C_DIEPMSK_TxFIFOEmpty
: 0),
2669 hsotg
->regs
+ S3C_DIEPMSK
);
2671 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2672 * DMA mode we may need this. */
2673 writel(S3C_DOEPMSK_SetupMsk
| S3C_DOEPMSK_AHBErrMsk
|
2674 S3C_DOEPMSK_EPDisbldMsk
|
2675 (using_dma(hsotg
) ? (S3C_DIEPMSK_XferComplMsk
|
2676 S3C_DIEPMSK_TimeOUTMsk
) : 0),
2677 hsotg
->regs
+ S3C_DOEPMSK
);
2679 writel(0, hsotg
->regs
+ S3C_DAINTMSK
);
2681 dev_info(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2682 readl(hsotg
->regs
+ S3C_DIEPCTL0
),
2683 readl(hsotg
->regs
+ S3C_DOEPCTL0
));
2685 /* enable in and out endpoint interrupts */
2686 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_OEPInt
| S3C_GINTSTS_IEPInt
);
2688 /* Enable the RXFIFO when in slave mode, as this is how we collect
2689 * the data. In DMA mode, we get events from the FIFO but also
2690 * things we cannot process, so do not use it. */
2691 if (!using_dma(hsotg
))
2692 s3c_hsotg_en_gsint(hsotg
, S3C_GINTSTS_RxFLvl
);
2694 /* Enable interrupts for EP0 in and out */
2695 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2696 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2698 __orr32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_PWROnPrgDone
);
2699 udelay(10); /* see openiboot */
2700 __bic32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_PWROnPrgDone
);
2702 dev_info(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ S3C_DCTL
));
2704 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2705 writing to the EPCTL register.. */
2707 /* set to read 1 8byte packet */
2708 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2709 S3C_DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2711 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2712 S3C_DxEPCTL_CNAK
| S3C_DxEPCTL_EPEna
|
2713 S3C_DxEPCTL_USBActEp
,
2714 hsotg
->regs
+ S3C_DOEPCTL0
);
2716 /* enable, but don't activate EP0in */
2717 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2718 S3C_DxEPCTL_USBActEp
, hsotg
->regs
+ S3C_DIEPCTL0
);
2720 s3c_hsotg_enqueue_setup(hsotg
);
2722 dev_info(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2723 readl(hsotg
->regs
+ S3C_DIEPCTL0
),
2724 readl(hsotg
->regs
+ S3C_DOEPCTL0
));
2726 /* clear global NAKs */
2727 writel(S3C_DCTL_CGOUTNak
| S3C_DCTL_CGNPInNAK
,
2728 hsotg
->regs
+ S3C_DCTL
);
2730 /* must be at-least 3ms to allow bus to see disconnect */
2733 /* remove the soft-disconnect and let's go */
2734 __bic32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_SftDiscon
);
2736 /* report to the user, and return */
2738 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2742 hsotg
->driver
= NULL
;
2743 hsotg
->gadget
.dev
.driver
= NULL
;
2746 EXPORT_SYMBOL(usb_gadget_probe_driver
);
2748 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
2750 struct s3c_hsotg
*hsotg
= our_hsotg
;
2756 if (!driver
|| driver
!= hsotg
->driver
|| !driver
->unbind
)
2759 /* all endpoints should be shutdown */
2760 for (ep
= 0; ep
< S3C_HSOTG_EPS
; ep
++)
2761 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
2763 call_gadget(hsotg
, disconnect
);
2765 driver
->unbind(&hsotg
->gadget
);
2766 hsotg
->driver
= NULL
;
2767 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2769 device_del(&hsotg
->gadget
.dev
);
2771 dev_info(hsotg
->dev
, "unregistered gadget driver '%s'\n",
2772 driver
->driver
.name
);
2776 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
2778 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
2780 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
2783 static struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
2784 .get_frame
= s3c_hsotg_gadget_getframe
,
2788 * s3c_hsotg_initep - initialise a single endpoint
2789 * @hsotg: The device state.
2790 * @hs_ep: The endpoint to be initialised.
2791 * @epnum: The endpoint number
2793 * Initialise the given endpoint (as part of the probe and device state
2794 * creation) to give to the gadget driver. Setup the endpoint name, any
2795 * direction information and other state that may be required.
2797 static void __devinit
s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
2798 struct s3c_hsotg_ep
*hs_ep
,
2806 else if ((epnum
% 2) == 0) {
2813 hs_ep
->index
= epnum
;
2815 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
2817 INIT_LIST_HEAD(&hs_ep
->queue
);
2818 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
2820 spin_lock_init(&hs_ep
->lock
);
2822 /* add to the list of endpoints known by the gadget driver */
2824 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
2826 hs_ep
->parent
= hsotg
;
2827 hs_ep
->ep
.name
= hs_ep
->name
;
2828 hs_ep
->ep
.maxpacket
= epnum
? 512 : EP0_MPS_LIMIT
;
2829 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
2831 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2832 * an OUT endpoint, we may as well do this if in future the
2833 * code is changed to make each endpoint's direction changeable.
2836 ptxfifo
= readl(hsotg
->regs
+ S3C_DPTXFSIZn(epnum
));
2837 hs_ep
->fifo_size
= S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
2839 /* if we're using dma, we need to set the next-endpoint pointer
2840 * to be something valid.
2843 if (using_dma(hsotg
)) {
2844 u32 next
= S3C_DxEPCTL_NextEp((epnum
+ 1) % 15);
2845 writel(next
, hsotg
->regs
+ S3C_DIEPCTL(epnum
));
2846 writel(next
, hsotg
->regs
+ S3C_DOEPCTL(epnum
));
2851 * s3c_hsotg_otgreset - reset the OtG phy block
2852 * @hsotg: The host state.
2854 * Power up the phy, set the basic configuration and start the PHY.
2856 static void s3c_hsotg_otgreset(struct s3c_hsotg
*hsotg
)
2858 struct clk
*xusbxti
;
2861 pwr
= readl(S3C_PHYPWR
);
2863 writel(pwr
, S3C_PHYPWR
);
2866 osc
= hsotg
->plat
->is_osc
? S3C_PHYCLK_EXT_OSC
: 0;
2868 xusbxti
= clk_get(hsotg
->dev
, "xusbxti");
2869 if (xusbxti
&& !IS_ERR(xusbxti
)) {
2870 switch (clk_get_rate(xusbxti
)) {
2872 osc
|= S3C_PHYCLK_CLKSEL_12M
;
2875 osc
|= S3C_PHYCLK_CLKSEL_24M
;
2879 /* default reference clock */
2885 writel(osc
| 0x10, S3C_PHYCLK
);
2887 /* issue a full set of resets to the otg and core */
2889 writel(S3C_RSTCON_PHY
, S3C_RSTCON
);
2890 udelay(20); /* at-least 10uS */
2891 writel(0, S3C_RSTCON
);
2895 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2899 /* unmask subset of endpoint interrupts */
2901 writel(S3C_DIEPMSK_TimeOUTMsk
| S3C_DIEPMSK_AHBErrMsk
|
2902 S3C_DIEPMSK_EPDisbldMsk
| S3C_DIEPMSK_XferComplMsk
,
2903 hsotg
->regs
+ S3C_DIEPMSK
);
2905 writel(S3C_DOEPMSK_SetupMsk
| S3C_DOEPMSK_AHBErrMsk
|
2906 S3C_DOEPMSK_EPDisbldMsk
| S3C_DOEPMSK_XferComplMsk
,
2907 hsotg
->regs
+ S3C_DOEPMSK
);
2909 writel(0, hsotg
->regs
+ S3C_DAINTMSK
);
2911 /* Be in disconnected state until gadget is registered */
2912 __orr32(hsotg
->regs
+ S3C_DCTL
, S3C_DCTL_SftDiscon
);
2915 /* post global nak until we're ready */
2916 writel(S3C_DCTL_SGNPInNAK
| S3C_DCTL_SGOUTNak
,
2917 hsotg
->regs
+ S3C_DCTL
);
2922 dev_info(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2923 readl(hsotg
->regs
+ S3C_GRXFSIZ
),
2924 readl(hsotg
->regs
+ S3C_GNPTXFSIZ
));
2926 s3c_hsotg_init_fifo(hsotg
);
2928 /* set the PLL on, remove the HNP/SRP and set the PHY */
2929 writel(S3C_GUSBCFG_PHYIf16
| S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2930 hsotg
->regs
+ S3C_GUSBCFG
);
2932 writel(using_dma(hsotg
) ? S3C_GAHBCFG_DMAEn
: 0x0,
2933 hsotg
->regs
+ S3C_GAHBCFG
);
2935 /* check hardware configuration */
2937 cfg4
= readl(hsotg
->regs
+ 0x50);
2938 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
2940 dev_info(hsotg
->dev
, "%s fifos\n",
2941 hsotg
->dedicated_fifos
? "dedicated" : "shared");
2944 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
2946 struct device
*dev
= hsotg
->dev
;
2947 void __iomem
*regs
= hsotg
->regs
;
2951 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2952 readl(regs
+ S3C_DCFG
), readl(regs
+ S3C_DCTL
),
2953 readl(regs
+ S3C_DIEPMSK
));
2955 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2956 readl(regs
+ S3C_GAHBCFG
), readl(regs
+ 0x44));
2958 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2959 readl(regs
+ S3C_GRXFSIZ
), readl(regs
+ S3C_GNPTXFSIZ
));
2961 /* show periodic fifo settings */
2963 for (idx
= 1; idx
<= 15; idx
++) {
2964 val
= readl(regs
+ S3C_DPTXFSIZn(idx
));
2965 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
2966 val
>> S3C_DPTXFSIZn_DPTxFSize_SHIFT
,
2967 val
& S3C_DPTXFSIZn_DPTxFStAddr_MASK
);
2970 for (idx
= 0; idx
< 15; idx
++) {
2972 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
2973 readl(regs
+ S3C_DIEPCTL(idx
)),
2974 readl(regs
+ S3C_DIEPTSIZ(idx
)),
2975 readl(regs
+ S3C_DIEPDMA(idx
)));
2977 val
= readl(regs
+ S3C_DOEPCTL(idx
));
2979 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2980 idx
, readl(regs
+ S3C_DOEPCTL(idx
)),
2981 readl(regs
+ S3C_DOEPTSIZ(idx
)),
2982 readl(regs
+ S3C_DOEPDMA(idx
)));
2986 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2987 readl(regs
+ S3C_DVBUSDIS
), readl(regs
+ S3C_DVBUSPULSE
));
2992 * state_show - debugfs: show overall driver and device state.
2993 * @seq: The seq file to write to.
2994 * @v: Unused parameter.
2996 * This debugfs entry shows the overall state of the hardware and
2997 * some general information about each of the endpoints available
3000 static int state_show(struct seq_file
*seq
, void *v
)
3002 struct s3c_hsotg
*hsotg
= seq
->private;
3003 void __iomem
*regs
= hsotg
->regs
;
3006 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3007 readl(regs
+ S3C_DCFG
),
3008 readl(regs
+ S3C_DCTL
),
3009 readl(regs
+ S3C_DSTS
));
3011 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3012 readl(regs
+ S3C_DIEPMSK
), readl(regs
+ S3C_DOEPMSK
));
3014 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3015 readl(regs
+ S3C_GINTMSK
),
3016 readl(regs
+ S3C_GINTSTS
));
3018 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3019 readl(regs
+ S3C_DAINTMSK
),
3020 readl(regs
+ S3C_DAINT
));
3022 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3023 readl(regs
+ S3C_GNPTXSTS
),
3024 readl(regs
+ S3C_GRXSTSR
));
3026 seq_printf(seq
, "\nEndpoint status:\n");
3028 for (idx
= 0; idx
< 15; idx
++) {
3031 in
= readl(regs
+ S3C_DIEPCTL(idx
));
3032 out
= readl(regs
+ S3C_DOEPCTL(idx
));
3034 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3037 in
= readl(regs
+ S3C_DIEPTSIZ(idx
));
3038 out
= readl(regs
+ S3C_DOEPTSIZ(idx
));
3040 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3043 seq_printf(seq
, "\n");
3049 static int state_open(struct inode
*inode
, struct file
*file
)
3051 return single_open(file
, state_show
, inode
->i_private
);
3054 static const struct file_operations state_fops
= {
3055 .owner
= THIS_MODULE
,
3058 .llseek
= seq_lseek
,
3059 .release
= single_release
,
3063 * fifo_show - debugfs: show the fifo information
3064 * @seq: The seq_file to write data to.
3065 * @v: Unused parameter.
3067 * Show the FIFO information for the overall fifo and all the
3068 * periodic transmission FIFOs.
3070 static int fifo_show(struct seq_file
*seq
, void *v
)
3072 struct s3c_hsotg
*hsotg
= seq
->private;
3073 void __iomem
*regs
= hsotg
->regs
;
3077 seq_printf(seq
, "Non-periodic FIFOs:\n");
3078 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ S3C_GRXFSIZ
));
3080 val
= readl(regs
+ S3C_GNPTXFSIZ
);
3081 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3082 val
>> S3C_GNPTXFSIZ_NPTxFDep_SHIFT
,
3083 val
& S3C_GNPTXFSIZ_NPTxFStAddr_MASK
);
3085 seq_printf(seq
, "\nPeriodic TXFIFOs:\n");
3087 for (idx
= 1; idx
<= 15; idx
++) {
3088 val
= readl(regs
+ S3C_DPTXFSIZn(idx
));
3090 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3091 val
>> S3C_DPTXFSIZn_DPTxFSize_SHIFT
,
3092 val
& S3C_DPTXFSIZn_DPTxFStAddr_MASK
);
3098 static int fifo_open(struct inode
*inode
, struct file
*file
)
3100 return single_open(file
, fifo_show
, inode
->i_private
);
3103 static const struct file_operations fifo_fops
= {
3104 .owner
= THIS_MODULE
,
3107 .llseek
= seq_lseek
,
3108 .release
= single_release
,
3112 static const char *decode_direction(int is_in
)
3114 return is_in
? "in" : "out";
3118 * ep_show - debugfs: show the state of an endpoint.
3119 * @seq: The seq_file to write data to.
3120 * @v: Unused parameter.
3122 * This debugfs entry shows the state of the given endpoint (one is
3123 * registered for each available).
3125 static int ep_show(struct seq_file
*seq
, void *v
)
3127 struct s3c_hsotg_ep
*ep
= seq
->private;
3128 struct s3c_hsotg
*hsotg
= ep
->parent
;
3129 struct s3c_hsotg_req
*req
;
3130 void __iomem
*regs
= hsotg
->regs
;
3131 int index
= ep
->index
;
3132 int show_limit
= 15;
3133 unsigned long flags
;
3135 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3136 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3138 /* first show the register state */
3140 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3141 readl(regs
+ S3C_DIEPCTL(index
)),
3142 readl(regs
+ S3C_DOEPCTL(index
)));
3144 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3145 readl(regs
+ S3C_DIEPDMA(index
)),
3146 readl(regs
+ S3C_DOEPDMA(index
)));
3148 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3149 readl(regs
+ S3C_DIEPINT(index
)),
3150 readl(regs
+ S3C_DOEPINT(index
)));
3152 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3153 readl(regs
+ S3C_DIEPTSIZ(index
)),
3154 readl(regs
+ S3C_DOEPTSIZ(index
)));
3156 seq_printf(seq
, "\n");
3157 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3158 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3160 seq_printf(seq
, "request list (%p,%p):\n",
3161 ep
->queue
.next
, ep
->queue
.prev
);
3163 spin_lock_irqsave(&ep
->lock
, flags
);
3165 list_for_each_entry(req
, &ep
->queue
, queue
) {
3166 if (--show_limit
< 0) {
3167 seq_printf(seq
, "not showing more requests...\n");
3171 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3172 req
== ep
->req
? '*' : ' ',
3173 req
, req
->req
.length
, req
->req
.buf
);
3174 seq_printf(seq
, "%d done, res %d\n",
3175 req
->req
.actual
, req
->req
.status
);
3178 spin_unlock_irqrestore(&ep
->lock
, flags
);
3183 static int ep_open(struct inode
*inode
, struct file
*file
)
3185 return single_open(file
, ep_show
, inode
->i_private
);
3188 static const struct file_operations ep_fops
= {
3189 .owner
= THIS_MODULE
,
3192 .llseek
= seq_lseek
,
3193 .release
= single_release
,
3197 * s3c_hsotg_create_debug - create debugfs directory and files
3198 * @hsotg: The driver state
3200 * Create the debugfs files to allow the user to get information
3201 * about the state of the system. The directory name is created
3202 * with the same name as the device itself, in case we end up
3203 * with multiple blocks in future systems.
3205 static void __devinit
s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3207 struct dentry
*root
;
3210 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3211 hsotg
->debug_root
= root
;
3213 dev_err(hsotg
->dev
, "cannot create debug root\n");
3217 /* create general state file */
3219 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3220 hsotg
, &state_fops
);
3222 if (IS_ERR(hsotg
->debug_file
))
3223 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3225 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3228 if (IS_ERR(hsotg
->debug_fifo
))
3229 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3231 /* create one file for each endpoint */
3233 for (epidx
= 0; epidx
< S3C_HSOTG_EPS
; epidx
++) {
3234 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3236 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3237 root
, ep
, &ep_fops
);
3239 if (IS_ERR(ep
->debugfs
))
3240 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3246 * s3c_hsotg_delete_debug - cleanup debugfs entries
3247 * @hsotg: The driver state
3249 * Cleanup (remove) the debugfs files for use on module exit.
3251 static void __devexit
s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3255 for (epidx
= 0; epidx
< S3C_HSOTG_EPS
; epidx
++) {
3256 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3257 debugfs_remove(ep
->debugfs
);
3260 debugfs_remove(hsotg
->debug_file
);
3261 debugfs_remove(hsotg
->debug_fifo
);
3262 debugfs_remove(hsotg
->debug_root
);
3266 * s3c_hsotg_gate - set the hardware gate for the block
3267 * @pdev: The device we bound to
3270 * Set the hardware gate setting into the block. If we end up on
3271 * something other than an S3C64XX, then we might need to change this
3272 * to using a platform data callback, or some other mechanism.
3274 static void s3c_hsotg_gate(struct platform_device
*pdev
, bool on
)
3276 unsigned long flags
;
3279 local_irq_save(flags
);
3281 others
= __raw_readl(S3C64XX_OTHERS
);
3283 others
|= S3C64XX_OTHERS_USBMASK
;
3285 others
&= ~S3C64XX_OTHERS_USBMASK
;
3286 __raw_writel(others
, S3C64XX_OTHERS
);
3288 local_irq_restore(flags
);
3291 static struct s3c_hsotg_plat s3c_hsotg_default_pdata
;
3293 static int __devinit
s3c_hsotg_probe(struct platform_device
*pdev
)
3295 struct s3c_hsotg_plat
*plat
= pdev
->dev
.platform_data
;
3296 struct device
*dev
= &pdev
->dev
;
3297 struct s3c_hsotg
*hsotg
;
3298 struct resource
*res
;
3303 plat
= &s3c_hsotg_default_pdata
;
3305 hsotg
= kzalloc(sizeof(struct s3c_hsotg
) +
3306 sizeof(struct s3c_hsotg_ep
) * S3C_HSOTG_EPS
,
3309 dev_err(dev
, "cannot get memory\n");
3316 hsotg
->clk
= clk_get(&pdev
->dev
, "otg");
3317 if (IS_ERR(hsotg
->clk
)) {
3318 dev_err(dev
, "cannot get otg clock\n");
3323 platform_set_drvdata(pdev
, hsotg
);
3325 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3327 dev_err(dev
, "cannot find register resource 0\n");
3332 hsotg
->regs_res
= request_mem_region(res
->start
, resource_size(res
),
3334 if (!hsotg
->regs_res
) {
3335 dev_err(dev
, "cannot reserve registers\n");
3340 hsotg
->regs
= ioremap(res
->start
, resource_size(res
));
3342 dev_err(dev
, "cannot map registers\n");
3347 ret
= platform_get_irq(pdev
, 0);
3349 dev_err(dev
, "cannot find IRQ\n");
3355 ret
= request_irq(ret
, s3c_hsotg_irq
, 0, dev_name(dev
), hsotg
);
3357 dev_err(dev
, "cannot claim IRQ\n");
3361 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3363 device_initialize(&hsotg
->gadget
.dev
);
3365 dev_set_name(&hsotg
->gadget
.dev
, "gadget");
3367 hsotg
->gadget
.is_dualspeed
= 1;
3368 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3369 hsotg
->gadget
.name
= dev_name(dev
);
3371 hsotg
->gadget
.dev
.parent
= dev
;
3372 hsotg
->gadget
.dev
.dma_mask
= dev
->dma_mask
;
3374 /* setup endpoint information */
3376 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3377 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3379 /* allocate EP0 request */
3381 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3383 if (!hsotg
->ctrl_req
) {
3384 dev_err(dev
, "failed to allocate ctrl req\n");
3388 /* reset the system */
3390 clk_enable(hsotg
->clk
);
3392 s3c_hsotg_gate(pdev
, true);
3394 s3c_hsotg_otgreset(hsotg
);
3395 s3c_hsotg_corereset(hsotg
);
3396 s3c_hsotg_init(hsotg
);
3398 /* initialise the endpoints now the core has been initialised */
3399 for (epnum
= 0; epnum
< S3C_HSOTG_EPS
; epnum
++)
3400 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3402 s3c_hsotg_create_debug(hsotg
);
3404 s3c_hsotg_dump(hsotg
);
3410 iounmap(hsotg
->regs
);
3413 release_resource(hsotg
->regs_res
);
3414 kfree(hsotg
->regs_res
);
3416 clk_put(hsotg
->clk
);
3422 static int __devexit
s3c_hsotg_remove(struct platform_device
*pdev
)
3424 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3426 s3c_hsotg_delete_debug(hsotg
);
3428 usb_gadget_unregister_driver(hsotg
->driver
);
3430 free_irq(hsotg
->irq
, hsotg
);
3431 iounmap(hsotg
->regs
);
3433 release_resource(hsotg
->regs_res
);
3434 kfree(hsotg
->regs_res
);
3436 s3c_hsotg_gate(pdev
, false);
3438 clk_disable(hsotg
->clk
);
3439 clk_put(hsotg
->clk
);
3446 #define s3c_hsotg_suspend NULL
3447 #define s3c_hsotg_resume NULL
3450 static struct platform_driver s3c_hsotg_driver
= {
3452 .name
= "s3c-hsotg",
3453 .owner
= THIS_MODULE
,
3455 .probe
= s3c_hsotg_probe
,
3456 .remove
= __devexit_p(s3c_hsotg_remove
),
3457 .suspend
= s3c_hsotg_suspend
,
3458 .resume
= s3c_hsotg_resume
,
3461 static int __init
s3c_hsotg_modinit(void)
3463 return platform_driver_register(&s3c_hsotg_driver
);
3466 static void __exit
s3c_hsotg_modexit(void)
3468 platform_driver_unregister(&s3c_hsotg_driver
);
3471 module_init(s3c_hsotg_modinit
);
3472 module_exit(s3c_hsotg_modexit
);
3474 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3475 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3476 MODULE_LICENSE("GPL");
3477 MODULE_ALIAS("platform:s3c-hsotg");