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infiniband: ehca: remove driver_data direct access of struct device
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / gianfar.c
blob4ae1d259fced7d6525a6818a1c641db5d1cf3850
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
83 #include <linux/in.h>
84
85 #include <asm/io.h>
86 #include <asm/irq.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
94 #include <linux/of.h>
95
96 #include "gianfar.h"
97 #include "fsl_pq_mdio.h"
98
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
132 #endif
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
136 int amount_pull);
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 static const struct net_device_ops gfar_netdev_ops = {
151 .ndo_open = gfar_enet_open,
152 .ndo_start_xmit = gfar_start_xmit,
153 .ndo_stop = gfar_close,
154 .ndo_change_mtu = gfar_change_mtu,
155 .ndo_set_multicast_list = gfar_set_multi,
156 .ndo_tx_timeout = gfar_timeout,
157 .ndo_do_ioctl = gfar_ioctl,
158 .ndo_vlan_rx_register = gfar_vlan_rx_register,
159 #ifdef CONFIG_NET_POLL_CONTROLLER
160 .ndo_poll_controller = gfar_netpoll,
161 #endif
162 };
163
164 /* Returns 1 if incoming frames use an FCB */
165 static inline int gfar_uses_fcb(struct gfar_private *priv)
166 {
167 return priv->vlgrp || priv->rx_csum_enable;
168 }
169
170 static int gfar_of_init(struct net_device *dev)
171 {
172 const char *model;
173 const char *ctype;
174 const void *mac_addr;
175 u64 addr, size;
176 int err = 0;
177 struct gfar_private *priv = netdev_priv(dev);
178 struct device_node *np = priv->node;
179 const u32 *stash;
180 const u32 *stash_len;
181 const u32 *stash_idx;
182
183 if (!np || !of_device_is_available(np))
184 return -ENODEV;
185
186 /* get a pointer to the register memory */
187 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
188 priv->regs = ioremap(addr, size);
189
190 if (priv->regs == NULL)
191 return -ENOMEM;
192
193 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
194
195 model = of_get_property(np, "model", NULL);
196
197 /* If we aren't the FEC we have multiple interrupts */
198 if (model && strcasecmp(model, "FEC")) {
199 priv->interruptReceive = irq_of_parse_and_map(np, 1);
200
201 priv->interruptError = irq_of_parse_and_map(np, 2);
202
203 if (priv->interruptTransmit < 0 ||
204 priv->interruptReceive < 0 ||
205 priv->interruptError < 0) {
206 err = -EINVAL;
207 goto err_out;
208 }
209 }
210
211 stash = of_get_property(np, "bd-stash", NULL);
212
213 if(stash) {
214 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
215 priv->bd_stash_en = 1;
216 }
217
218 stash_len = of_get_property(np, "rx-stash-len", NULL);
219
220 if (stash_len)
221 priv->rx_stash_size = *stash_len;
222
223 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
224
225 if (stash_idx)
226 priv->rx_stash_index = *stash_idx;
227
228 if (stash_len || stash_idx)
229 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
230
231 mac_addr = of_get_mac_address(np);
232 if (mac_addr)
233 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
234
235 if (model && !strcasecmp(model, "TSEC"))
236 priv->device_flags =
237 FSL_GIANFAR_DEV_HAS_GIGABIT |
238 FSL_GIANFAR_DEV_HAS_COALESCE |
239 FSL_GIANFAR_DEV_HAS_RMON |
240 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
241 if (model && !strcasecmp(model, "eTSEC"))
242 priv->device_flags =
243 FSL_GIANFAR_DEV_HAS_GIGABIT |
244 FSL_GIANFAR_DEV_HAS_COALESCE |
245 FSL_GIANFAR_DEV_HAS_RMON |
246 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
247 FSL_GIANFAR_DEV_HAS_PADDING |
248 FSL_GIANFAR_DEV_HAS_CSUM |
249 FSL_GIANFAR_DEV_HAS_VLAN |
250 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
251 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
252
253 ctype = of_get_property(np, "phy-connection-type", NULL);
254
255 /* We only care about rgmii-id. The rest are autodetected */
256 if (ctype && !strcmp(ctype, "rgmii-id"))
257 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
258 else
259 priv->interface = PHY_INTERFACE_MODE_MII;
260
261 if (of_get_property(np, "fsl,magic-packet", NULL))
262 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
263
264 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
265 if (!priv->phy_node) {
266 u32 *fixed_link;
267
268 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
269 if (!fixed_link) {
270 err = -ENODEV;
271 goto err_out;
272 }
273 }
274
275 /* Find the TBI PHY. If it's not there, we don't support SGMII */
276 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
277
278 return 0;
279
280 err_out:
281 iounmap(priv->regs);
282 return err;
283 }
284
285 /* Ioctl MII Interface */
286 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
287 {
288 struct gfar_private *priv = netdev_priv(dev);
289
290 if (!netif_running(dev))
291 return -EINVAL;
292
293 if (!priv->phydev)
294 return -ENODEV;
295
296 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
297 }
298
299 /* Set up the ethernet device structure, private data,
300 * and anything else we need before we start */
301 static int gfar_probe(struct of_device *ofdev,
302 const struct of_device_id *match)
303 {
304 u32 tempval;
305 struct net_device *dev = NULL;
306 struct gfar_private *priv = NULL;
307 DECLARE_MAC_BUF(mac);
308 int err = 0;
309 int len_devname;
310
311 /* Create an ethernet device instance */
312 dev = alloc_etherdev(sizeof (*priv));
313
314 if (NULL == dev)
315 return -ENOMEM;
316
317 priv = netdev_priv(dev);
318 priv->ndev = dev;
319 priv->ofdev = ofdev;
320 priv->node = ofdev->node;
321 SET_NETDEV_DEV(dev, &ofdev->dev);
322
323 err = gfar_of_init(dev);
324
325 if (err)
326 goto regs_fail;
327
328 spin_lock_init(&priv->txlock);
329 spin_lock_init(&priv->rxlock);
330 spin_lock_init(&priv->bflock);
331 INIT_WORK(&priv->reset_task, gfar_reset_task);
332
333 dev_set_drvdata(&ofdev->dev, priv);
334
335 /* Stop the DMA engine now, in case it was running before */
336 /* (The firmware could have used it, and left it running). */
337 gfar_halt(dev);
338
339 /* Reset MAC layer */
340 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
341
342 /* We need to delay at least 3 TX clocks */
343 udelay(2);
344
345 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
346 gfar_write(&priv->regs->maccfg1, tempval);
347
348 /* Initialize MACCFG2. */
349 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
350
351 /* Initialize ECNTRL */
352 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
353
354 /* Set the dev->base_addr to the gfar reg region */
355 dev->base_addr = (unsigned long) (priv->regs);
356
357 SET_NETDEV_DEV(dev, &ofdev->dev);
358
359 /* Fill in the dev structure */
360 dev->watchdog_timeo = TX_TIMEOUT;
361 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
362 dev->mtu = 1500;
363
364 dev->netdev_ops = &gfar_netdev_ops;
365 dev->ethtool_ops = &gfar_ethtool_ops;
366
367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
368 priv->rx_csum_enable = 1;
369 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
370 } else
371 priv->rx_csum_enable = 0;
372
373 priv->vlgrp = NULL;
374
375 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
376 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
377
378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
379 priv->extended_hash = 1;
380 priv->hash_width = 9;
381
382 priv->hash_regs[0] = &priv->regs->igaddr0;
383 priv->hash_regs[1] = &priv->regs->igaddr1;
384 priv->hash_regs[2] = &priv->regs->igaddr2;
385 priv->hash_regs[3] = &priv->regs->igaddr3;
386 priv->hash_regs[4] = &priv->regs->igaddr4;
387 priv->hash_regs[5] = &priv->regs->igaddr5;
388 priv->hash_regs[6] = &priv->regs->igaddr6;
389 priv->hash_regs[7] = &priv->regs->igaddr7;
390 priv->hash_regs[8] = &priv->regs->gaddr0;
391 priv->hash_regs[9] = &priv->regs->gaddr1;
392 priv->hash_regs[10] = &priv->regs->gaddr2;
393 priv->hash_regs[11] = &priv->regs->gaddr3;
394 priv->hash_regs[12] = &priv->regs->gaddr4;
395 priv->hash_regs[13] = &priv->regs->gaddr5;
396 priv->hash_regs[14] = &priv->regs->gaddr6;
397 priv->hash_regs[15] = &priv->regs->gaddr7;
398
399 } else {
400 priv->extended_hash = 0;
401 priv->hash_width = 8;
402
403 priv->hash_regs[0] = &priv->regs->gaddr0;
404 priv->hash_regs[1] = &priv->regs->gaddr1;
405 priv->hash_regs[2] = &priv->regs->gaddr2;
406 priv->hash_regs[3] = &priv->regs->gaddr3;
407 priv->hash_regs[4] = &priv->regs->gaddr4;
408 priv->hash_regs[5] = &priv->regs->gaddr5;
409 priv->hash_regs[6] = &priv->regs->gaddr6;
410 priv->hash_regs[7] = &priv->regs->gaddr7;
411 }
412
413 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
414 priv->padding = DEFAULT_PADDING;
415 else
416 priv->padding = 0;
417
418 if (dev->features & NETIF_F_IP_CSUM)
419 dev->hard_header_len += GMAC_FCB_LEN;
420
421 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
422 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
423 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
424 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
425
426 priv->txcoalescing = DEFAULT_TX_COALESCE;
427 priv->txic = DEFAULT_TXIC;
428 priv->rxcoalescing = DEFAULT_RX_COALESCE;
429 priv->rxic = DEFAULT_RXIC;
430
431 /* Enable most messages by default */
432 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
433
434 /* Carrier starts down, phylib will bring it up */
435 netif_carrier_off(dev);
436
437 err = register_netdev(dev);
438
439 if (err) {
440 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
441 dev->name);
442 goto register_fail;
443 }
444
445 device_init_wakeup(&dev->dev,
446 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
447
448 /* fill out IRQ number and name fields */
449 len_devname = strlen(dev->name);
450 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
451 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
452 strncpy(&priv->int_name_tx[len_devname],
453 "_tx", sizeof("_tx") + 1);
454
455 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
456 strncpy(&priv->int_name_rx[len_devname],
457 "_rx", sizeof("_rx") + 1);
458
459 strncpy(&priv->int_name_er[0], dev->name, len_devname);
460 strncpy(&priv->int_name_er[len_devname],
461 "_er", sizeof("_er") + 1);
462 } else
463 priv->int_name_tx[len_devname] = '\0';
464
465 /* Create all the sysfs files */
466 gfar_init_sysfs(dev);
467
468 /* Print out the device info */
469 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
470
471 /* Even more device info helps when determining which kernel */
472 /* provided which set of benchmarks. */
473 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
474 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
475 dev->name, priv->rx_ring_size, priv->tx_ring_size);
476
477 return 0;
478
479 register_fail:
480 iounmap(priv->regs);
481 regs_fail:
482 if (priv->phy_node)
483 of_node_put(priv->phy_node);
484 if (priv->tbi_node)
485 of_node_put(priv->tbi_node);
486 free_netdev(dev);
487 return err;
488 }
489
490 static int gfar_remove(struct of_device *ofdev)
491 {
492 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
493
494 if (priv->phy_node)
495 of_node_put(priv->phy_node);
496 if (priv->tbi_node)
497 of_node_put(priv->tbi_node);
498
499 dev_set_drvdata(&ofdev->dev, NULL);
500
501 iounmap(priv->regs);
502 free_netdev(priv->ndev);
503
504 return 0;
505 }
506
507 #ifdef CONFIG_PM
508 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
509 {
510 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
511 struct net_device *dev = priv->ndev;
512 unsigned long flags;
513 u32 tempval;
514
515 int magic_packet = priv->wol_en &&
516 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
517
518 netif_device_detach(dev);
519
520 if (netif_running(dev)) {
521 spin_lock_irqsave(&priv->txlock, flags);
522 spin_lock(&priv->rxlock);
523
524 gfar_halt_nodisable(dev);
525
526 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
527 tempval = gfar_read(&priv->regs->maccfg1);
528
529 tempval &= ~MACCFG1_TX_EN;
530
531 if (!magic_packet)
532 tempval &= ~MACCFG1_RX_EN;
533
534 gfar_write(&priv->regs->maccfg1, tempval);
535
536 spin_unlock(&priv->rxlock);
537 spin_unlock_irqrestore(&priv->txlock, flags);
538
539 napi_disable(&priv->napi);
540
541 if (magic_packet) {
542 /* Enable interrupt on Magic Packet */
543 gfar_write(&priv->regs->imask, IMASK_MAG);
544
545 /* Enable Magic Packet mode */
546 tempval = gfar_read(&priv->regs->maccfg2);
547 tempval |= MACCFG2_MPEN;
548 gfar_write(&priv->regs->maccfg2, tempval);
549 } else {
550 phy_stop(priv->phydev);
551 }
552 }
553
554 return 0;
555 }
556
557 static int gfar_resume(struct of_device *ofdev)
558 {
559 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
560 struct net_device *dev = priv->ndev;
561 unsigned long flags;
562 u32 tempval;
563 int magic_packet = priv->wol_en &&
564 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
565
566 if (!netif_running(dev)) {
567 netif_device_attach(dev);
568 return 0;
569 }
570
571 if (!magic_packet && priv->phydev)
572 phy_start(priv->phydev);
573
574 /* Disable Magic Packet mode, in case something
575 * else woke us up.
576 */
577
578 spin_lock_irqsave(&priv->txlock, flags);
579 spin_lock(&priv->rxlock);
580
581 tempval = gfar_read(&priv->regs->maccfg2);
582 tempval &= ~MACCFG2_MPEN;
583 gfar_write(&priv->regs->maccfg2, tempval);
584
585 gfar_start(dev);
586
587 spin_unlock(&priv->rxlock);
588 spin_unlock_irqrestore(&priv->txlock, flags);
589
590 netif_device_attach(dev);
591
592 napi_enable(&priv->napi);
593
594 return 0;
595 }
596 #else
597 #define gfar_suspend NULL
598 #define gfar_resume NULL
599 #endif
600
601 /* Reads the controller's registers to determine what interface
602 * connects it to the PHY.
603 */
604 static phy_interface_t gfar_get_interface(struct net_device *dev)
605 {
606 struct gfar_private *priv = netdev_priv(dev);
607 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
608
609 if (ecntrl & ECNTRL_SGMII_MODE)
610 return PHY_INTERFACE_MODE_SGMII;
611
612 if (ecntrl & ECNTRL_TBI_MODE) {
613 if (ecntrl & ECNTRL_REDUCED_MODE)
614 return PHY_INTERFACE_MODE_RTBI;
615 else
616 return PHY_INTERFACE_MODE_TBI;
617 }
618
619 if (ecntrl & ECNTRL_REDUCED_MODE) {
620 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
621 return PHY_INTERFACE_MODE_RMII;
622 else {
623 phy_interface_t interface = priv->interface;
624
625 /*
626 * This isn't autodetected right now, so it must
627 * be set by the device tree or platform code.
628 */
629 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
630 return PHY_INTERFACE_MODE_RGMII_ID;
631
632 return PHY_INTERFACE_MODE_RGMII;
633 }
634 }
635
636 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
637 return PHY_INTERFACE_MODE_GMII;
638
639 return PHY_INTERFACE_MODE_MII;
640 }
641
642
643 /* Initializes driver's PHY state, and attaches to the PHY.
644 * Returns 0 on success.
645 */
646 static int init_phy(struct net_device *dev)
647 {
648 struct gfar_private *priv = netdev_priv(dev);
649 uint gigabit_support =
650 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
651 SUPPORTED_1000baseT_Full : 0;
652 phy_interface_t interface;
653
654 priv->oldlink = 0;
655 priv->oldspeed = 0;
656 priv->oldduplex = -1;
657
658 interface = gfar_get_interface(dev);
659
660 if (priv->phy_node) {
661 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link,
662 0, interface);
663 if (!priv->phydev) {
664 dev_err(&dev->dev, "error: Could not attach to PHY\n");
665 return -ENODEV;
666 }
667 }
668
669 if (interface == PHY_INTERFACE_MODE_SGMII)
670 gfar_configure_serdes(dev);
671
672 /* Remove any features not supported by the controller */
673 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
674 priv->phydev->advertising = priv->phydev->supported;
675
676 return 0;
677 }
678
679 /*
680 * Initialize TBI PHY interface for communicating with the
681 * SERDES lynx PHY on the chip. We communicate with this PHY
682 * through the MDIO bus on each controller, treating it as a
683 * "normal" PHY at the address found in the TBIPA register. We assume
684 * that the TBIPA register is valid. Either the MDIO bus code will set
685 * it to a value that doesn't conflict with other PHYs on the bus, or the
686 * value doesn't matter, as there are no other PHYs on the bus.
687 */
688 static void gfar_configure_serdes(struct net_device *dev)
689 {
690 struct gfar_private *priv = netdev_priv(dev);
691 struct phy_device *tbiphy;
692
693 if (!priv->tbi_node) {
694 dev_warn(&dev->dev, "error: SGMII mode requires that the "
695 "device tree specify a tbi-handle\n");
696 return;
697 }
698
699 tbiphy = of_phy_find_device(priv->tbi_node);
700 if (!tbiphy) {
701 dev_err(&dev->dev, "error: Could not get TBI device\n");
702 return;
703 }
704
705 /*
706 * If the link is already up, we must already be ok, and don't need to
707 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
708 * everything for us? Resetting it takes the link down and requires
709 * several seconds for it to come back.
710 */
711 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
712 return;
713
714 /* Single clk mode, mii mode off(for serdes communication) */
715 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
716
717 phy_write(tbiphy, MII_ADVERTISE,
718 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
719 ADVERTISE_1000XPSE_ASYM);
720
721 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
722 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
723 }
724
725 static void init_registers(struct net_device *dev)
726 {
727 struct gfar_private *priv = netdev_priv(dev);
728
729 /* Clear IEVENT */
730 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
731
732 /* Initialize IMASK */
733 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
734
735 /* Init hash registers to zero */
736 gfar_write(&priv->regs->igaddr0, 0);
737 gfar_write(&priv->regs->igaddr1, 0);
738 gfar_write(&priv->regs->igaddr2, 0);
739 gfar_write(&priv->regs->igaddr3, 0);
740 gfar_write(&priv->regs->igaddr4, 0);
741 gfar_write(&priv->regs->igaddr5, 0);
742 gfar_write(&priv->regs->igaddr6, 0);
743 gfar_write(&priv->regs->igaddr7, 0);
744
745 gfar_write(&priv->regs->gaddr0, 0);
746 gfar_write(&priv->regs->gaddr1, 0);
747 gfar_write(&priv->regs->gaddr2, 0);
748 gfar_write(&priv->regs->gaddr3, 0);
749 gfar_write(&priv->regs->gaddr4, 0);
750 gfar_write(&priv->regs->gaddr5, 0);
751 gfar_write(&priv->regs->gaddr6, 0);
752 gfar_write(&priv->regs->gaddr7, 0);
753
754 /* Zero out the rmon mib registers if it has them */
755 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
756 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
757
758 /* Mask off the CAM interrupts */
759 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
760 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
761 }
762
763 /* Initialize the max receive buffer length */
764 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
765
766 /* Initialize the Minimum Frame Length Register */
767 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
768 }
769
770
771 /* Halt the receive and transmit queues */
772 static void gfar_halt_nodisable(struct net_device *dev)
773 {
774 struct gfar_private *priv = netdev_priv(dev);
775 struct gfar __iomem *regs = priv->regs;
776 u32 tempval;
777
778 /* Mask all interrupts */
779 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
780
781 /* Clear all interrupts */
782 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
783
784 /* Stop the DMA, and wait for it to stop */
785 tempval = gfar_read(&priv->regs->dmactrl);
786 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
787 != (DMACTRL_GRS | DMACTRL_GTS)) {
788 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
789 gfar_write(&priv->regs->dmactrl, tempval);
790
791 while (!(gfar_read(&priv->regs->ievent) &
792 (IEVENT_GRSC | IEVENT_GTSC)))
793 cpu_relax();
794 }
795 }
796
797 /* Halt the receive and transmit queues */
798 void gfar_halt(struct net_device *dev)
799 {
800 struct gfar_private *priv = netdev_priv(dev);
801 struct gfar __iomem *regs = priv->regs;
802 u32 tempval;
803
804 gfar_halt_nodisable(dev);
805
806 /* Disable Rx and Tx */
807 tempval = gfar_read(&regs->maccfg1);
808 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
809 gfar_write(&regs->maccfg1, tempval);
810 }
811
812 void stop_gfar(struct net_device *dev)
813 {
814 struct gfar_private *priv = netdev_priv(dev);
815 struct gfar __iomem *regs = priv->regs;
816 unsigned long flags;
817
818 phy_stop(priv->phydev);
819
820 /* Lock it down */
821 spin_lock_irqsave(&priv->txlock, flags);
822 spin_lock(&priv->rxlock);
823
824 gfar_halt(dev);
825
826 spin_unlock(&priv->rxlock);
827 spin_unlock_irqrestore(&priv->txlock, flags);
828
829 /* Free the IRQs */
830 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
831 free_irq(priv->interruptError, dev);
832 free_irq(priv->interruptTransmit, dev);
833 free_irq(priv->interruptReceive, dev);
834 } else {
835 free_irq(priv->interruptTransmit, dev);
836 }
837
838 free_skb_resources(priv);
839
840 dma_free_coherent(&priv->ofdev->dev,
841 sizeof(struct txbd8)*priv->tx_ring_size
842 + sizeof(struct rxbd8)*priv->rx_ring_size,
843 priv->tx_bd_base,
844 gfar_read(&regs->tbase0));
845 }
846
847 /* If there are any tx skbs or rx skbs still around, free them.
848 * Then free tx_skbuff and rx_skbuff */
849 static void free_skb_resources(struct gfar_private *priv)
850 {
851 struct rxbd8 *rxbdp;
852 struct txbd8 *txbdp;
853 int i, j;
854
855 /* Go through all the buffer descriptors and free their data buffers */
856 txbdp = priv->tx_bd_base;
857
858 for (i = 0; i < priv->tx_ring_size; i++) {
859 if (!priv->tx_skbuff[i])
860 continue;
861
862 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
863 txbdp->length, DMA_TO_DEVICE);
864 txbdp->lstatus = 0;
865 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
866 txbdp++;
867 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
868 txbdp->length, DMA_TO_DEVICE);
869 }
870 txbdp++;
871 dev_kfree_skb_any(priv->tx_skbuff[i]);
872 priv->tx_skbuff[i] = NULL;
873 }
874
875 kfree(priv->tx_skbuff);
876
877 rxbdp = priv->rx_bd_base;
878
879 /* rx_skbuff is not guaranteed to be allocated, so only
880 * free it and its contents if it is allocated */
881 if(priv->rx_skbuff != NULL) {
882 for (i = 0; i < priv->rx_ring_size; i++) {
883 if (priv->rx_skbuff[i]) {
884 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
885 priv->rx_buffer_size,
886 DMA_FROM_DEVICE);
887
888 dev_kfree_skb_any(priv->rx_skbuff[i]);
889 priv->rx_skbuff[i] = NULL;
890 }
891
892 rxbdp->lstatus = 0;
893 rxbdp->bufPtr = 0;
894
895 rxbdp++;
896 }
897
898 kfree(priv->rx_skbuff);
899 }
900 }
901
902 void gfar_start(struct net_device *dev)
903 {
904 struct gfar_private *priv = netdev_priv(dev);
905 struct gfar __iomem *regs = priv->regs;
906 u32 tempval;
907
908 /* Enable Rx and Tx in MACCFG1 */
909 tempval = gfar_read(&regs->maccfg1);
910 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
911 gfar_write(&regs->maccfg1, tempval);
912
913 /* Initialize DMACTRL to have WWR and WOP */
914 tempval = gfar_read(&priv->regs->dmactrl);
915 tempval |= DMACTRL_INIT_SETTINGS;
916 gfar_write(&priv->regs->dmactrl, tempval);
917
918 /* Make sure we aren't stopped */
919 tempval = gfar_read(&priv->regs->dmactrl);
920 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
921 gfar_write(&priv->regs->dmactrl, tempval);
922
923 /* Clear THLT/RHLT, so that the DMA starts polling now */
924 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
925 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
926
927 /* Unmask the interrupts we look for */
928 gfar_write(&regs->imask, IMASK_DEFAULT);
929
930 dev->trans_start = jiffies;
931 }
932
933 /* Bring the controller up and running */
934 int startup_gfar(struct net_device *dev)
935 {
936 struct txbd8 *txbdp;
937 struct rxbd8 *rxbdp;
938 dma_addr_t addr = 0;
939 unsigned long vaddr;
940 int i;
941 struct gfar_private *priv = netdev_priv(dev);
942 struct gfar __iomem *regs = priv->regs;
943 int err = 0;
944 u32 rctrl = 0;
945 u32 attrs = 0;
946
947 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
948
949 /* Allocate memory for the buffer descriptors */
950 vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
951 sizeof (struct txbd8) * priv->tx_ring_size +
952 sizeof (struct rxbd8) * priv->rx_ring_size,
953 &addr, GFP_KERNEL);
954
955 if (vaddr == 0) {
956 if (netif_msg_ifup(priv))
957 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
958 dev->name);
959 return -ENOMEM;
960 }
961
962 priv->tx_bd_base = (struct txbd8 *) vaddr;
963
964 /* enet DMA only understands physical addresses */
965 gfar_write(&regs->tbase0, addr);
966
967 /* Start the rx descriptor ring where the tx ring leaves off */
968 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
969 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
970 priv->rx_bd_base = (struct rxbd8 *) vaddr;
971 gfar_write(&regs->rbase0, addr);
972
973 /* Setup the skbuff rings */
974 priv->tx_skbuff =
975 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
976 priv->tx_ring_size, GFP_KERNEL);
977
978 if (NULL == priv->tx_skbuff) {
979 if (netif_msg_ifup(priv))
980 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
981 dev->name);
982 err = -ENOMEM;
983 goto tx_skb_fail;
984 }
985
986 for (i = 0; i < priv->tx_ring_size; i++)
987 priv->tx_skbuff[i] = NULL;
988
989 priv->rx_skbuff =
990 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
991 priv->rx_ring_size, GFP_KERNEL);
992
993 if (NULL == priv->rx_skbuff) {
994 if (netif_msg_ifup(priv))
995 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
996 dev->name);
997 err = -ENOMEM;
998 goto rx_skb_fail;
999 }
1000
1001 for (i = 0; i < priv->rx_ring_size; i++)
1002 priv->rx_skbuff[i] = NULL;
1003
1004 /* Initialize some variables in our dev structure */
1005 priv->num_txbdfree = priv->tx_ring_size;
1006 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1007 priv->cur_rx = priv->rx_bd_base;
1008 priv->skb_curtx = priv->skb_dirtytx = 0;
1009 priv->skb_currx = 0;
1010
1011 /* Initialize Transmit Descriptor Ring */
1012 txbdp = priv->tx_bd_base;
1013 for (i = 0; i < priv->tx_ring_size; i++) {
1014 txbdp->lstatus = 0;
1015 txbdp->bufPtr = 0;
1016 txbdp++;
1017 }
1018
1019 /* Set the last descriptor in the ring to indicate wrap */
1020 txbdp--;
1021 txbdp->status |= TXBD_WRAP;
1022
1023 rxbdp = priv->rx_bd_base;
1024 for (i = 0; i < priv->rx_ring_size; i++) {
1025 struct sk_buff *skb;
1026
1027 skb = gfar_new_skb(dev);
1028
1029 if (!skb) {
1030 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1031 dev->name);
1032
1033 goto err_rxalloc_fail;
1034 }
1035
1036 priv->rx_skbuff[i] = skb;
1037
1038 gfar_new_rxbdp(dev, rxbdp, skb);
1039
1040 rxbdp++;
1041 }
1042
1043 /* Set the last descriptor in the ring to wrap */
1044 rxbdp--;
1045 rxbdp->status |= RXBD_WRAP;
1046
1047 /* If the device has multiple interrupts, register for
1048 * them. Otherwise, only register for the one */
1049 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1050 /* Install our interrupt handlers for Error,
1051 * Transmit, and Receive */
1052 if (request_irq(priv->interruptError, gfar_error,
1053 0, priv->int_name_er, dev) < 0) {
1054 if (netif_msg_intr(priv))
1055 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1056 dev->name, priv->interruptError);
1057
1058 err = -1;
1059 goto err_irq_fail;
1060 }
1061
1062 if (request_irq(priv->interruptTransmit, gfar_transmit,
1063 0, priv->int_name_tx, dev) < 0) {
1064 if (netif_msg_intr(priv))
1065 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1066 dev->name, priv->interruptTransmit);
1067
1068 err = -1;
1069
1070 goto tx_irq_fail;
1071 }
1072
1073 if (request_irq(priv->interruptReceive, gfar_receive,
1074 0, priv->int_name_rx, dev) < 0) {
1075 if (netif_msg_intr(priv))
1076 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1077 dev->name, priv->interruptReceive);
1078
1079 err = -1;
1080 goto rx_irq_fail;
1081 }
1082 } else {
1083 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1084 0, priv->int_name_tx, dev) < 0) {
1085 if (netif_msg_intr(priv))
1086 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1087 dev->name, priv->interruptTransmit);
1088
1089 err = -1;
1090 goto err_irq_fail;
1091 }
1092 }
1093
1094 phy_start(priv->phydev);
1095
1096 /* Configure the coalescing support */
1097 gfar_write(&regs->txic, 0);
1098 if (priv->txcoalescing)
1099 gfar_write(&regs->txic, priv->txic);
1100
1101 gfar_write(&regs->rxic, 0);
1102 if (priv->rxcoalescing)
1103 gfar_write(&regs->rxic, priv->rxic);
1104
1105 if (priv->rx_csum_enable)
1106 rctrl |= RCTRL_CHECKSUMMING;
1107
1108 if (priv->extended_hash) {
1109 rctrl |= RCTRL_EXTHASH;
1110
1111 gfar_clear_exact_match(dev);
1112 rctrl |= RCTRL_EMEN;
1113 }
1114
1115 if (priv->padding) {
1116 rctrl &= ~RCTRL_PAL_MASK;
1117 rctrl |= RCTRL_PADDING(priv->padding);
1118 }
1119
1120 /* Init rctrl based on our settings */
1121 gfar_write(&priv->regs->rctrl, rctrl);
1122
1123 if (dev->features & NETIF_F_IP_CSUM)
1124 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1125
1126 /* Set the extraction length and index */
1127 attrs = ATTRELI_EL(priv->rx_stash_size) |
1128 ATTRELI_EI(priv->rx_stash_index);
1129
1130 gfar_write(&priv->regs->attreli, attrs);
1131
1132 /* Start with defaults, and add stashing or locking
1133 * depending on the approprate variables */
1134 attrs = ATTR_INIT_SETTINGS;
1135
1136 if (priv->bd_stash_en)
1137 attrs |= ATTR_BDSTASH;
1138
1139 if (priv->rx_stash_size != 0)
1140 attrs |= ATTR_BUFSTASH;
1141
1142 gfar_write(&priv->regs->attr, attrs);
1143
1144 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1145 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1146 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1147
1148 /* Start the controller */
1149 gfar_start(dev);
1150
1151 return 0;
1152
1153 rx_irq_fail:
1154 free_irq(priv->interruptTransmit, dev);
1155 tx_irq_fail:
1156 free_irq(priv->interruptError, dev);
1157 err_irq_fail:
1158 err_rxalloc_fail:
1159 rx_skb_fail:
1160 free_skb_resources(priv);
1161 tx_skb_fail:
1162 dma_free_coherent(&priv->ofdev->dev,
1163 sizeof(struct txbd8)*priv->tx_ring_size
1164 + sizeof(struct rxbd8)*priv->rx_ring_size,
1165 priv->tx_bd_base,
1166 gfar_read(&regs->tbase0));
1167
1168 return err;
1169 }
1170
1171 /* Called when something needs to use the ethernet device */
1172 /* Returns 0 for success. */
1173 static int gfar_enet_open(struct net_device *dev)
1174 {
1175 struct gfar_private *priv = netdev_priv(dev);
1176 int err;
1177
1178 napi_enable(&priv->napi);
1179
1180 skb_queue_head_init(&priv->rx_recycle);
1181
1182 /* Initialize a bunch of registers */
1183 init_registers(dev);
1184
1185 gfar_set_mac_address(dev);
1186
1187 err = init_phy(dev);
1188
1189 if(err) {
1190 napi_disable(&priv->napi);
1191 return err;
1192 }
1193
1194 err = startup_gfar(dev);
1195 if (err) {
1196 napi_disable(&priv->napi);
1197 return err;
1198 }
1199
1200 netif_start_queue(dev);
1201
1202 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1203
1204 return err;
1205 }
1206
1207 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1208 {
1209 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1210
1211 memset(fcb, 0, GMAC_FCB_LEN);
1212
1213 return fcb;
1214 }
1215
1216 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1217 {
1218 u8 flags = 0;
1219
1220 /* If we're here, it's a IP packet with a TCP or UDP
1221 * payload. We set it to checksum, using a pseudo-header
1222 * we provide
1223 */
1224 flags = TXFCB_DEFAULT;
1225
1226 /* Tell the controller what the protocol is */
1227 /* And provide the already calculated phcs */
1228 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1229 flags |= TXFCB_UDP;
1230 fcb->phcs = udp_hdr(skb)->check;
1231 } else
1232 fcb->phcs = tcp_hdr(skb)->check;
1233
1234 /* l3os is the distance between the start of the
1235 * frame (skb->data) and the start of the IP hdr.
1236 * l4os is the distance between the start of the
1237 * l3 hdr and the l4 hdr */
1238 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1239 fcb->l4os = skb_network_header_len(skb);
1240
1241 fcb->flags = flags;
1242 }
1243
1244 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1245 {
1246 fcb->flags |= TXFCB_VLN;
1247 fcb->vlctl = vlan_tx_tag_get(skb);
1248 }
1249
1250 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1251 struct txbd8 *base, int ring_size)
1252 {
1253 struct txbd8 *new_bd = bdp + stride;
1254
1255 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1256 }
1257
1258 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1259 int ring_size)
1260 {
1261 return skip_txbd(bdp, 1, base, ring_size);
1262 }
1263
1264 /* This is called by the kernel when a frame is ready for transmission. */
1265 /* It is pointed to by the dev->hard_start_xmit function pointer */
1266 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1267 {
1268 struct gfar_private *priv = netdev_priv(dev);
1269 struct txfcb *fcb = NULL;
1270 struct txbd8 *txbdp, *txbdp_start, *base;
1271 u32 lstatus;
1272 int i;
1273 u32 bufaddr;
1274 unsigned long flags;
1275 unsigned int nr_frags, length;
1276
1277 base = priv->tx_bd_base;
1278
1279 /* make space for additional header when fcb is needed */
1280 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1281 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1282 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1283 struct sk_buff *skb_new;
1284
1285 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1286 if (!skb_new) {
1287 dev->stats.tx_errors++;
1288 kfree_skb(skb);
1289 return NETDEV_TX_OK;
1290 }
1291 kfree_skb(skb);
1292 skb = skb_new;
1293 }
1294
1295 /* total number of fragments in the SKB */
1296 nr_frags = skb_shinfo(skb)->nr_frags;
1297
1298 spin_lock_irqsave(&priv->txlock, flags);
1299
1300 /* check if there is space to queue this packet */
1301 if ((nr_frags+1) > priv->num_txbdfree) {
1302 /* no space, stop the queue */
1303 netif_stop_queue(dev);
1304 dev->stats.tx_fifo_errors++;
1305 spin_unlock_irqrestore(&priv->txlock, flags);
1306 return NETDEV_TX_BUSY;
1307 }
1308
1309 /* Update transmit stats */
1310 dev->stats.tx_bytes += skb->len;
1311
1312 txbdp = txbdp_start = priv->cur_tx;
1313
1314 if (nr_frags == 0) {
1315 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1316 } else {
1317 /* Place the fragment addresses and lengths into the TxBDs */
1318 for (i = 0; i < nr_frags; i++) {
1319 /* Point at the next BD, wrapping as needed */
1320 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1321
1322 length = skb_shinfo(skb)->frags[i].size;
1323
1324 lstatus = txbdp->lstatus | length |
1325 BD_LFLAG(TXBD_READY);
1326
1327 /* Handle the last BD specially */
1328 if (i == nr_frags - 1)
1329 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1330
1331 bufaddr = dma_map_page(&priv->ofdev->dev,
1332 skb_shinfo(skb)->frags[i].page,
1333 skb_shinfo(skb)->frags[i].page_offset,
1334 length,
1335 DMA_TO_DEVICE);
1336
1337 /* set the TxBD length and buffer pointer */
1338 txbdp->bufPtr = bufaddr;
1339 txbdp->lstatus = lstatus;
1340 }
1341
1342 lstatus = txbdp_start->lstatus;
1343 }
1344
1345 /* Set up checksumming */
1346 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1347 fcb = gfar_add_fcb(skb);
1348 lstatus |= BD_LFLAG(TXBD_TOE);
1349 gfar_tx_checksum(skb, fcb);
1350 }
1351
1352 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1353 if (unlikely(NULL == fcb)) {
1354 fcb = gfar_add_fcb(skb);
1355 lstatus |= BD_LFLAG(TXBD_TOE);
1356 }
1357
1358 gfar_tx_vlan(skb, fcb);
1359 }
1360
1361 /* setup the TxBD length and buffer pointer for the first BD */
1362 priv->tx_skbuff[priv->skb_curtx] = skb;
1363 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1364 skb_headlen(skb), DMA_TO_DEVICE);
1365
1366 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1367
1368 /*
1369 * The powerpc-specific eieio() is used, as wmb() has too strong
1370 * semantics (it requires synchronization between cacheable and
1371 * uncacheable mappings, which eieio doesn't provide and which we
1372 * don't need), thus requiring a more expensive sync instruction. At
1373 * some point, the set of architecture-independent barrier functions
1374 * should be expanded to include weaker barriers.
1375 */
1376 eieio();
1377
1378 txbdp_start->lstatus = lstatus;
1379
1380 /* Update the current skb pointer to the next entry we will use
1381 * (wrapping if necessary) */
1382 priv->skb_curtx = (priv->skb_curtx + 1) &
1383 TX_RING_MOD_MASK(priv->tx_ring_size);
1384
1385 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1386
1387 /* reduce TxBD free count */
1388 priv->num_txbdfree -= (nr_frags + 1);
1389
1390 dev->trans_start = jiffies;
1391
1392 /* If the next BD still needs to be cleaned up, then the bds
1393 are full. We need to tell the kernel to stop sending us stuff. */
1394 if (!priv->num_txbdfree) {
1395 netif_stop_queue(dev);
1396
1397 dev->stats.tx_fifo_errors++;
1398 }
1399
1400 /* Tell the DMA to go go go */
1401 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1402
1403 /* Unlock priv */
1404 spin_unlock_irqrestore(&priv->txlock, flags);
1405
1406 return NETDEV_TX_OK;
1407 }
1408
1409 /* Stops the kernel queue, and halts the controller */
1410 static int gfar_close(struct net_device *dev)
1411 {
1412 struct gfar_private *priv = netdev_priv(dev);
1413
1414 napi_disable(&priv->napi);
1415
1416 skb_queue_purge(&priv->rx_recycle);
1417 cancel_work_sync(&priv->reset_task);
1418 stop_gfar(dev);
1419
1420 /* Disconnect from the PHY */
1421 phy_disconnect(priv->phydev);
1422 priv->phydev = NULL;
1423
1424 netif_stop_queue(dev);
1425
1426 return 0;
1427 }
1428
1429 /* Changes the mac address if the controller is not running. */
1430 static int gfar_set_mac_address(struct net_device *dev)
1431 {
1432 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1433
1434 return 0;
1435 }
1436
1437
1438 /* Enables and disables VLAN insertion/extraction */
1439 static void gfar_vlan_rx_register(struct net_device *dev,
1440 struct vlan_group *grp)
1441 {
1442 struct gfar_private *priv = netdev_priv(dev);
1443 unsigned long flags;
1444 u32 tempval;
1445
1446 spin_lock_irqsave(&priv->rxlock, flags);
1447
1448 priv->vlgrp = grp;
1449
1450 if (grp) {
1451 /* Enable VLAN tag insertion */
1452 tempval = gfar_read(&priv->regs->tctrl);
1453 tempval |= TCTRL_VLINS;
1454
1455 gfar_write(&priv->regs->tctrl, tempval);
1456
1457 /* Enable VLAN tag extraction */
1458 tempval = gfar_read(&priv->regs->rctrl);
1459 tempval |= RCTRL_VLEX;
1460 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1461 gfar_write(&priv->regs->rctrl, tempval);
1462 } else {
1463 /* Disable VLAN tag insertion */
1464 tempval = gfar_read(&priv->regs->tctrl);
1465 tempval &= ~TCTRL_VLINS;
1466 gfar_write(&priv->regs->tctrl, tempval);
1467
1468 /* Disable VLAN tag extraction */
1469 tempval = gfar_read(&priv->regs->rctrl);
1470 tempval &= ~RCTRL_VLEX;
1471 /* If parse is no longer required, then disable parser */
1472 if (tempval & RCTRL_REQ_PARSER)
1473 tempval |= RCTRL_PRSDEP_INIT;
1474 else
1475 tempval &= ~RCTRL_PRSDEP_INIT;
1476 gfar_write(&priv->regs->rctrl, tempval);
1477 }
1478
1479 gfar_change_mtu(dev, dev->mtu);
1480
1481 spin_unlock_irqrestore(&priv->rxlock, flags);
1482 }
1483
1484 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1485 {
1486 int tempsize, tempval;
1487 struct gfar_private *priv = netdev_priv(dev);
1488 int oldsize = priv->rx_buffer_size;
1489 int frame_size = new_mtu + ETH_HLEN;
1490
1491 if (priv->vlgrp)
1492 frame_size += VLAN_HLEN;
1493
1494 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1495 if (netif_msg_drv(priv))
1496 printk(KERN_ERR "%s: Invalid MTU setting\n",
1497 dev->name);
1498 return -EINVAL;
1499 }
1500
1501 if (gfar_uses_fcb(priv))
1502 frame_size += GMAC_FCB_LEN;
1503
1504 frame_size += priv->padding;
1505
1506 tempsize =
1507 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1508 INCREMENTAL_BUFFER_SIZE;
1509
1510 /* Only stop and start the controller if it isn't already
1511 * stopped, and we changed something */
1512 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1513 stop_gfar(dev);
1514
1515 priv->rx_buffer_size = tempsize;
1516
1517 dev->mtu = new_mtu;
1518
1519 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1520 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1521
1522 /* If the mtu is larger than the max size for standard
1523 * ethernet frames (ie, a jumbo frame), then set maccfg2
1524 * to allow huge frames, and to check the length */
1525 tempval = gfar_read(&priv->regs->maccfg2);
1526
1527 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1528 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1529 else
1530 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1531
1532 gfar_write(&priv->regs->maccfg2, tempval);
1533
1534 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1535 startup_gfar(dev);
1536
1537 return 0;
1538 }
1539
1540 /* gfar_reset_task gets scheduled when a packet has not been
1541 * transmitted after a set amount of time.
1542 * For now, assume that clearing out all the structures, and
1543 * starting over will fix the problem.
1544 */
1545 static void gfar_reset_task(struct work_struct *work)
1546 {
1547 struct gfar_private *priv = container_of(work, struct gfar_private,
1548 reset_task);
1549 struct net_device *dev = priv->ndev;
1550
1551 if (dev->flags & IFF_UP) {
1552 netif_stop_queue(dev);
1553 stop_gfar(dev);
1554 startup_gfar(dev);
1555 netif_start_queue(dev);
1556 }
1557
1558 netif_tx_schedule_all(dev);
1559 }
1560
1561 static void gfar_timeout(struct net_device *dev)
1562 {
1563 struct gfar_private *priv = netdev_priv(dev);
1564
1565 dev->stats.tx_errors++;
1566 schedule_work(&priv->reset_task);
1567 }
1568
1569 /* Interrupt Handler for Transmit complete */
1570 static int gfar_clean_tx_ring(struct net_device *dev)
1571 {
1572 struct gfar_private *priv = netdev_priv(dev);
1573 struct txbd8 *bdp;
1574 struct txbd8 *lbdp = NULL;
1575 struct txbd8 *base = priv->tx_bd_base;
1576 struct sk_buff *skb;
1577 int skb_dirtytx;
1578 int tx_ring_size = priv->tx_ring_size;
1579 int frags = 0;
1580 int i;
1581 int howmany = 0;
1582 u32 lstatus;
1583
1584 bdp = priv->dirty_tx;
1585 skb_dirtytx = priv->skb_dirtytx;
1586
1587 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1588 frags = skb_shinfo(skb)->nr_frags;
1589 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1590
1591 lstatus = lbdp->lstatus;
1592
1593 /* Only clean completed frames */
1594 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1595 (lstatus & BD_LENGTH_MASK))
1596 break;
1597
1598 dma_unmap_single(&priv->ofdev->dev,
1599 bdp->bufPtr,
1600 bdp->length,
1601 DMA_TO_DEVICE);
1602
1603 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1604 bdp = next_txbd(bdp, base, tx_ring_size);
1605
1606 for (i = 0; i < frags; i++) {
1607 dma_unmap_page(&priv->ofdev->dev,
1608 bdp->bufPtr,
1609 bdp->length,
1610 DMA_TO_DEVICE);
1611 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1612 bdp = next_txbd(bdp, base, tx_ring_size);
1613 }
1614
1615 /*
1616 * If there's room in the queue (limit it to rx_buffer_size)
1617 * we add this skb back into the pool, if it's the right size
1618 */
1619 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1620 skb_recycle_check(skb, priv->rx_buffer_size +
1621 RXBUF_ALIGNMENT))
1622 __skb_queue_head(&priv->rx_recycle, skb);
1623 else
1624 dev_kfree_skb_any(skb);
1625
1626 priv->tx_skbuff[skb_dirtytx] = NULL;
1627
1628 skb_dirtytx = (skb_dirtytx + 1) &
1629 TX_RING_MOD_MASK(tx_ring_size);
1630
1631 howmany++;
1632 priv->num_txbdfree += frags + 1;
1633 }
1634
1635 /* If we freed a buffer, we can restart transmission, if necessary */
1636 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1637 netif_wake_queue(dev);
1638
1639 /* Update dirty indicators */
1640 priv->skb_dirtytx = skb_dirtytx;
1641 priv->dirty_tx = bdp;
1642
1643 dev->stats.tx_packets += howmany;
1644
1645 return howmany;
1646 }
1647
1648 static void gfar_schedule_cleanup(struct net_device *dev)
1649 {
1650 struct gfar_private *priv = netdev_priv(dev);
1651 unsigned long flags;
1652
1653 spin_lock_irqsave(&priv->txlock, flags);
1654 spin_lock(&priv->rxlock);
1655
1656 if (napi_schedule_prep(&priv->napi)) {
1657 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1658 __napi_schedule(&priv->napi);
1659 } else {
1660 /*
1661 * Clear IEVENT, so interrupts aren't called again
1662 * because of the packets that have already arrived.
1663 */
1664 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1665 }
1666
1667 spin_unlock(&priv->rxlock);
1668 spin_unlock_irqrestore(&priv->txlock, flags);
1669 }
1670
1671 /* Interrupt Handler for Transmit complete */
1672 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1673 {
1674 gfar_schedule_cleanup((struct net_device *)dev_id);
1675 return IRQ_HANDLED;
1676 }
1677
1678 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1679 struct sk_buff *skb)
1680 {
1681 struct gfar_private *priv = netdev_priv(dev);
1682 u32 lstatus;
1683
1684 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1685 priv->rx_buffer_size, DMA_FROM_DEVICE);
1686
1687 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1688
1689 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1690 lstatus |= BD_LFLAG(RXBD_WRAP);
1691
1692 eieio();
1693
1694 bdp->lstatus = lstatus;
1695 }
1696
1697
1698 struct sk_buff * gfar_new_skb(struct net_device *dev)
1699 {
1700 unsigned int alignamount;
1701 struct gfar_private *priv = netdev_priv(dev);
1702 struct sk_buff *skb = NULL;
1703
1704 skb = __skb_dequeue(&priv->rx_recycle);
1705 if (!skb)
1706 skb = netdev_alloc_skb(dev,
1707 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1708
1709 if (!skb)
1710 return NULL;
1711
1712 alignamount = RXBUF_ALIGNMENT -
1713 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1714
1715 /* We need the data buffer to be aligned properly. We will reserve
1716 * as many bytes as needed to align the data properly
1717 */
1718 skb_reserve(skb, alignamount);
1719
1720 return skb;
1721 }
1722
1723 static inline void count_errors(unsigned short status, struct net_device *dev)
1724 {
1725 struct gfar_private *priv = netdev_priv(dev);
1726 struct net_device_stats *stats = &dev->stats;
1727 struct gfar_extra_stats *estats = &priv->extra_stats;
1728
1729 /* If the packet was truncated, none of the other errors
1730 * matter */
1731 if (status & RXBD_TRUNCATED) {
1732 stats->rx_length_errors++;
1733
1734 estats->rx_trunc++;
1735
1736 return;
1737 }
1738 /* Count the errors, if there were any */
1739 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1740 stats->rx_length_errors++;
1741
1742 if (status & RXBD_LARGE)
1743 estats->rx_large++;
1744 else
1745 estats->rx_short++;
1746 }
1747 if (status & RXBD_NONOCTET) {
1748 stats->rx_frame_errors++;
1749 estats->rx_nonoctet++;
1750 }
1751 if (status & RXBD_CRCERR) {
1752 estats->rx_crcerr++;
1753 stats->rx_crc_errors++;
1754 }
1755 if (status & RXBD_OVERRUN) {
1756 estats->rx_overrun++;
1757 stats->rx_crc_errors++;
1758 }
1759 }
1760
1761 irqreturn_t gfar_receive(int irq, void *dev_id)
1762 {
1763 gfar_schedule_cleanup((struct net_device *)dev_id);
1764 return IRQ_HANDLED;
1765 }
1766
1767 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1768 {
1769 /* If valid headers were found, and valid sums
1770 * were verified, then we tell the kernel that no
1771 * checksumming is necessary. Otherwise, it is */
1772 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1773 skb->ip_summed = CHECKSUM_UNNECESSARY;
1774 else
1775 skb->ip_summed = CHECKSUM_NONE;
1776 }
1777
1778
1779 /* gfar_process_frame() -- handle one incoming packet if skb
1780 * isn't NULL. */
1781 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1782 int amount_pull)
1783 {
1784 struct gfar_private *priv = netdev_priv(dev);
1785 struct rxfcb *fcb = NULL;
1786
1787 int ret;
1788
1789 /* fcb is at the beginning if exists */
1790 fcb = (struct rxfcb *)skb->data;
1791
1792 /* Remove the FCB from the skb */
1793 /* Remove the padded bytes, if there are any */
1794 if (amount_pull)
1795 skb_pull(skb, amount_pull);
1796
1797 if (priv->rx_csum_enable)
1798 gfar_rx_checksum(skb, fcb);
1799
1800 /* Tell the skb what kind of packet this is */
1801 skb->protocol = eth_type_trans(skb, dev);
1802
1803 /* Send the packet up the stack */
1804 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1805 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1806 else
1807 ret = netif_receive_skb(skb);
1808
1809 if (NET_RX_DROP == ret)
1810 priv->extra_stats.kernel_dropped++;
1811
1812 return 0;
1813 }
1814
1815 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1816 * until the budget/quota has been reached. Returns the number
1817 * of frames handled
1818 */
1819 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1820 {
1821 struct rxbd8 *bdp, *base;
1822 struct sk_buff *skb;
1823 int pkt_len;
1824 int amount_pull;
1825 int howmany = 0;
1826 struct gfar_private *priv = netdev_priv(dev);
1827
1828 /* Get the first full descriptor */
1829 bdp = priv->cur_rx;
1830 base = priv->rx_bd_base;
1831
1832 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1833 priv->padding;
1834
1835 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1836 struct sk_buff *newskb;
1837 rmb();
1838
1839 /* Add another skb for the future */
1840 newskb = gfar_new_skb(dev);
1841
1842 skb = priv->rx_skbuff[priv->skb_currx];
1843
1844 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1845 priv->rx_buffer_size, DMA_FROM_DEVICE);
1846
1847 /* We drop the frame if we failed to allocate a new buffer */
1848 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1849 bdp->status & RXBD_ERR)) {
1850 count_errors(bdp->status, dev);
1851
1852 if (unlikely(!newskb))
1853 newskb = skb;
1854 else if (skb) {
1855 /*
1856 * We need to reset ->data to what it
1857 * was before gfar_new_skb() re-aligned
1858 * it to an RXBUF_ALIGNMENT boundary
1859 * before we put the skb back on the
1860 * recycle list.
1861 */
1862 skb->data = skb->head + NET_SKB_PAD;
1863 __skb_queue_head(&priv->rx_recycle, skb);
1864 }
1865 } else {
1866 /* Increment the number of packets */
1867 dev->stats.rx_packets++;
1868 howmany++;
1869
1870 if (likely(skb)) {
1871 pkt_len = bdp->length - ETH_FCS_LEN;
1872 /* Remove the FCS from the packet length */
1873 skb_put(skb, pkt_len);
1874 dev->stats.rx_bytes += pkt_len;
1875
1876 if (in_irq() || irqs_disabled())
1877 printk("Interrupt problem!\n");
1878 gfar_process_frame(dev, skb, amount_pull);
1879
1880 } else {
1881 if (netif_msg_rx_err(priv))
1882 printk(KERN_WARNING
1883 "%s: Missing skb!\n", dev->name);
1884 dev->stats.rx_dropped++;
1885 priv->extra_stats.rx_skbmissing++;
1886 }
1887
1888 }
1889
1890 priv->rx_skbuff[priv->skb_currx] = newskb;
1891
1892 /* Setup the new bdp */
1893 gfar_new_rxbdp(dev, bdp, newskb);
1894
1895 /* Update to the next pointer */
1896 bdp = next_bd(bdp, base, priv->rx_ring_size);
1897
1898 /* update to point at the next skb */
1899 priv->skb_currx =
1900 (priv->skb_currx + 1) &
1901 RX_RING_MOD_MASK(priv->rx_ring_size);
1902 }
1903
1904 /* Update the current rxbd pointer to be the next one */
1905 priv->cur_rx = bdp;
1906
1907 return howmany;
1908 }
1909
1910 static int gfar_poll(struct napi_struct *napi, int budget)
1911 {
1912 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1913 struct net_device *dev = priv->ndev;
1914 int tx_cleaned = 0;
1915 int rx_cleaned = 0;
1916 unsigned long flags;
1917
1918 /* Clear IEVENT, so interrupts aren't called again
1919 * because of the packets that have already arrived */
1920 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1921
1922 /* If we fail to get the lock, don't bother with the TX BDs */
1923 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1924 tx_cleaned = gfar_clean_tx_ring(dev);
1925 spin_unlock_irqrestore(&priv->txlock, flags);
1926 }
1927
1928 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1929
1930 if (tx_cleaned)
1931 return budget;
1932
1933 if (rx_cleaned < budget) {
1934 napi_complete(napi);
1935
1936 /* Clear the halt bit in RSTAT */
1937 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1938
1939 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1940
1941 /* If we are coalescing interrupts, update the timer */
1942 /* Otherwise, clear it */
1943 if (likely(priv->rxcoalescing)) {
1944 gfar_write(&priv->regs->rxic, 0);
1945 gfar_write(&priv->regs->rxic, priv->rxic);
1946 }
1947 if (likely(priv->txcoalescing)) {
1948 gfar_write(&priv->regs->txic, 0);
1949 gfar_write(&priv->regs->txic, priv->txic);
1950 }
1951 }
1952
1953 return rx_cleaned;
1954 }
1955
1956 #ifdef CONFIG_NET_POLL_CONTROLLER
1957 /*
1958 * Polling 'interrupt' - used by things like netconsole to send skbs
1959 * without having to re-enable interrupts. It's not called while
1960 * the interrupt routine is executing.
1961 */
1962 static void gfar_netpoll(struct net_device *dev)
1963 {
1964 struct gfar_private *priv = netdev_priv(dev);
1965
1966 /* If the device has multiple interrupts, run tx/rx */
1967 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1968 disable_irq(priv->interruptTransmit);
1969 disable_irq(priv->interruptReceive);
1970 disable_irq(priv->interruptError);
1971 gfar_interrupt(priv->interruptTransmit, dev);
1972 enable_irq(priv->interruptError);
1973 enable_irq(priv->interruptReceive);
1974 enable_irq(priv->interruptTransmit);
1975 } else {
1976 disable_irq(priv->interruptTransmit);
1977 gfar_interrupt(priv->interruptTransmit, dev);
1978 enable_irq(priv->interruptTransmit);
1979 }
1980 }
1981 #endif
1982
1983 /* The interrupt handler for devices with one interrupt */
1984 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1985 {
1986 struct net_device *dev = dev_id;
1987 struct gfar_private *priv = netdev_priv(dev);
1988
1989 /* Save ievent for future reference */
1990 u32 events = gfar_read(&priv->regs->ievent);
1991
1992 /* Check for reception */
1993 if (events & IEVENT_RX_MASK)
1994 gfar_receive(irq, dev_id);
1995
1996 /* Check for transmit completion */
1997 if (events & IEVENT_TX_MASK)
1998 gfar_transmit(irq, dev_id);
1999
2000 /* Check for errors */
2001 if (events & IEVENT_ERR_MASK)
2002 gfar_error(irq, dev_id);
2003
2004 return IRQ_HANDLED;
2005 }
2006
2007 /* Called every time the controller might need to be made
2008 * aware of new link state. The PHY code conveys this
2009 * information through variables in the phydev structure, and this
2010 * function converts those variables into the appropriate
2011 * register values, and can bring down the device if needed.
2012 */
2013 static void adjust_link(struct net_device *dev)
2014 {
2015 struct gfar_private *priv = netdev_priv(dev);
2016 struct gfar __iomem *regs = priv->regs;
2017 unsigned long flags;
2018 struct phy_device *phydev = priv->phydev;
2019 int new_state = 0;
2020
2021 spin_lock_irqsave(&priv->txlock, flags);
2022 if (phydev->link) {
2023 u32 tempval = gfar_read(&regs->maccfg2);
2024 u32 ecntrl = gfar_read(&regs->ecntrl);
2025
2026 /* Now we make sure that we can be in full duplex mode.
2027 * If not, we operate in half-duplex mode. */
2028 if (phydev->duplex != priv->oldduplex) {
2029 new_state = 1;
2030 if (!(phydev->duplex))
2031 tempval &= ~(MACCFG2_FULL_DUPLEX);
2032 else
2033 tempval |= MACCFG2_FULL_DUPLEX;
2034
2035 priv->oldduplex = phydev->duplex;
2036 }
2037
2038 if (phydev->speed != priv->oldspeed) {
2039 new_state = 1;
2040 switch (phydev->speed) {
2041 case 1000:
2042 tempval =
2043 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2044
2045 ecntrl &= ~(ECNTRL_R100);
2046 break;
2047 case 100:
2048 case 10:
2049 tempval =
2050 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2051
2052 /* Reduced mode distinguishes
2053 * between 10 and 100 */
2054 if (phydev->speed == SPEED_100)
2055 ecntrl |= ECNTRL_R100;
2056 else
2057 ecntrl &= ~(ECNTRL_R100);
2058 break;
2059 default:
2060 if (netif_msg_link(priv))
2061 printk(KERN_WARNING
2062 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2063 dev->name, phydev->speed);
2064 break;
2065 }
2066
2067 priv->oldspeed = phydev->speed;
2068 }
2069
2070 gfar_write(&regs->maccfg2, tempval);
2071 gfar_write(&regs->ecntrl, ecntrl);
2072
2073 if (!priv->oldlink) {
2074 new_state = 1;
2075 priv->oldlink = 1;
2076 }
2077 } else if (priv->oldlink) {
2078 new_state = 1;
2079 priv->oldlink = 0;
2080 priv->oldspeed = 0;
2081 priv->oldduplex = -1;
2082 }
2083
2084 if (new_state && netif_msg_link(priv))
2085 phy_print_status(phydev);
2086
2087 spin_unlock_irqrestore(&priv->txlock, flags);
2088 }
2089
2090 /* Update the hash table based on the current list of multicast
2091 * addresses we subscribe to. Also, change the promiscuity of
2092 * the device based on the flags (this function is called
2093 * whenever dev->flags is changed */
2094 static void gfar_set_multi(struct net_device *dev)
2095 {
2096 struct dev_mc_list *mc_ptr;
2097 struct gfar_private *priv = netdev_priv(dev);
2098 struct gfar __iomem *regs = priv->regs;
2099 u32 tempval;
2100
2101 if(dev->flags & IFF_PROMISC) {
2102 /* Set RCTRL to PROM */
2103 tempval = gfar_read(&regs->rctrl);
2104 tempval |= RCTRL_PROM;
2105 gfar_write(&regs->rctrl, tempval);
2106 } else {
2107 /* Set RCTRL to not PROM */
2108 tempval = gfar_read(&regs->rctrl);
2109 tempval &= ~(RCTRL_PROM);
2110 gfar_write(&regs->rctrl, tempval);
2111 }
2112
2113 if(dev->flags & IFF_ALLMULTI) {
2114 /* Set the hash to rx all multicast frames */
2115 gfar_write(&regs->igaddr0, 0xffffffff);
2116 gfar_write(&regs->igaddr1, 0xffffffff);
2117 gfar_write(&regs->igaddr2, 0xffffffff);
2118 gfar_write(&regs->igaddr3, 0xffffffff);
2119 gfar_write(&regs->igaddr4, 0xffffffff);
2120 gfar_write(&regs->igaddr5, 0xffffffff);
2121 gfar_write(&regs->igaddr6, 0xffffffff);
2122 gfar_write(&regs->igaddr7, 0xffffffff);
2123 gfar_write(&regs->gaddr0, 0xffffffff);
2124 gfar_write(&regs->gaddr1, 0xffffffff);
2125 gfar_write(&regs->gaddr2, 0xffffffff);
2126 gfar_write(&regs->gaddr3, 0xffffffff);
2127 gfar_write(&regs->gaddr4, 0xffffffff);
2128 gfar_write(&regs->gaddr5, 0xffffffff);
2129 gfar_write(&regs->gaddr6, 0xffffffff);
2130 gfar_write(&regs->gaddr7, 0xffffffff);
2131 } else {
2132 int em_num;
2133 int idx;
2134
2135 /* zero out the hash */
2136 gfar_write(&regs->igaddr0, 0x0);
2137 gfar_write(&regs->igaddr1, 0x0);
2138 gfar_write(&regs->igaddr2, 0x0);
2139 gfar_write(&regs->igaddr3, 0x0);
2140 gfar_write(&regs->igaddr4, 0x0);
2141 gfar_write(&regs->igaddr5, 0x0);
2142 gfar_write(&regs->igaddr6, 0x0);
2143 gfar_write(&regs->igaddr7, 0x0);
2144 gfar_write(&regs->gaddr0, 0x0);
2145 gfar_write(&regs->gaddr1, 0x0);
2146 gfar_write(&regs->gaddr2, 0x0);
2147 gfar_write(&regs->gaddr3, 0x0);
2148 gfar_write(&regs->gaddr4, 0x0);
2149 gfar_write(&regs->gaddr5, 0x0);
2150 gfar_write(&regs->gaddr6, 0x0);
2151 gfar_write(&regs->gaddr7, 0x0);
2152
2153 /* If we have extended hash tables, we need to
2154 * clear the exact match registers to prepare for
2155 * setting them */
2156 if (priv->extended_hash) {
2157 em_num = GFAR_EM_NUM + 1;
2158 gfar_clear_exact_match(dev);
2159 idx = 1;
2160 } else {
2161 idx = 0;
2162 em_num = 0;
2163 }
2164
2165 if(dev->mc_count == 0)
2166 return;
2167
2168 /* Parse the list, and set the appropriate bits */
2169 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2170 if (idx < em_num) {
2171 gfar_set_mac_for_addr(dev, idx,
2172 mc_ptr->dmi_addr);
2173 idx++;
2174 } else
2175 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2176 }
2177 }
2178
2179 return;
2180 }
2181
2182
2183 /* Clears each of the exact match registers to zero, so they
2184 * don't interfere with normal reception */
2185 static void gfar_clear_exact_match(struct net_device *dev)
2186 {
2187 int idx;
2188 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2189
2190 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2191 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2192 }
2193
2194 /* Set the appropriate hash bit for the given addr */
2195 /* The algorithm works like so:
2196 * 1) Take the Destination Address (ie the multicast address), and
2197 * do a CRC on it (little endian), and reverse the bits of the
2198 * result.
2199 * 2) Use the 8 most significant bits as a hash into a 256-entry
2200 * table. The table is controlled through 8 32-bit registers:
2201 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2202 * gaddr7. This means that the 3 most significant bits in the
2203 * hash index which gaddr register to use, and the 5 other bits
2204 * indicate which bit (assuming an IBM numbering scheme, which
2205 * for PowerPC (tm) is usually the case) in the register holds
2206 * the entry. */
2207 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2208 {
2209 u32 tempval;
2210 struct gfar_private *priv = netdev_priv(dev);
2211 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2212 int width = priv->hash_width;
2213 u8 whichbit = (result >> (32 - width)) & 0x1f;
2214 u8 whichreg = result >> (32 - width + 5);
2215 u32 value = (1 << (31-whichbit));
2216
2217 tempval = gfar_read(priv->hash_regs[whichreg]);
2218 tempval |= value;
2219 gfar_write(priv->hash_regs[whichreg], tempval);
2220
2221 return;
2222 }
2223
2224
2225 /* There are multiple MAC Address register pairs on some controllers
2226 * This function sets the numth pair to a given address
2227 */
2228 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2229 {
2230 struct gfar_private *priv = netdev_priv(dev);
2231 int idx;
2232 char tmpbuf[MAC_ADDR_LEN];
2233 u32 tempval;
2234 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2235
2236 macptr += num*2;
2237
2238 /* Now copy it into the mac registers backwards, cuz */
2239 /* little endian is silly */
2240 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2241 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2242
2243 gfar_write(macptr, *((u32 *) (tmpbuf)));
2244
2245 tempval = *((u32 *) (tmpbuf + 4));
2246
2247 gfar_write(macptr+1, tempval);
2248 }
2249
2250 /* GFAR error interrupt handler */
2251 static irqreturn_t gfar_error(int irq, void *dev_id)
2252 {
2253 struct net_device *dev = dev_id;
2254 struct gfar_private *priv = netdev_priv(dev);
2255
2256 /* Save ievent for future reference */
2257 u32 events = gfar_read(&priv->regs->ievent);
2258
2259 /* Clear IEVENT */
2260 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2261
2262 /* Magic Packet is not an error. */
2263 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2264 (events & IEVENT_MAG))
2265 events &= ~IEVENT_MAG;
2266
2267 /* Hmm... */
2268 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2269 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2270 dev->name, events, gfar_read(&priv->regs->imask));
2271
2272 /* Update the error counters */
2273 if (events & IEVENT_TXE) {
2274 dev->stats.tx_errors++;
2275
2276 if (events & IEVENT_LC)
2277 dev->stats.tx_window_errors++;
2278 if (events & IEVENT_CRL)
2279 dev->stats.tx_aborted_errors++;
2280 if (events & IEVENT_XFUN) {
2281 if (netif_msg_tx_err(priv))
2282 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2283 "packet dropped.\n", dev->name);
2284 dev->stats.tx_dropped++;
2285 priv->extra_stats.tx_underrun++;
2286
2287 /* Reactivate the Tx Queues */
2288 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2289 }
2290 if (netif_msg_tx_err(priv))
2291 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2292 }
2293 if (events & IEVENT_BSY) {
2294 dev->stats.rx_errors++;
2295 priv->extra_stats.rx_bsy++;
2296
2297 gfar_receive(irq, dev_id);
2298
2299 if (netif_msg_rx_err(priv))
2300 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2301 dev->name, gfar_read(&priv->regs->rstat));
2302 }
2303 if (events & IEVENT_BABR) {
2304 dev->stats.rx_errors++;
2305 priv->extra_stats.rx_babr++;
2306
2307 if (netif_msg_rx_err(priv))
2308 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2309 }
2310 if (events & IEVENT_EBERR) {
2311 priv->extra_stats.eberr++;
2312 if (netif_msg_rx_err(priv))
2313 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2314 }
2315 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2316 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2317
2318 if (events & IEVENT_BABT) {
2319 priv->extra_stats.tx_babt++;
2320 if (netif_msg_tx_err(priv))
2321 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2322 }
2323 return IRQ_HANDLED;
2324 }
2325
2326 /* work with hotplug and coldplug */
2327 MODULE_ALIAS("platform:fsl-gianfar");
2328
2329 static struct of_device_id gfar_match[] =
2330 {
2331 {
2332 .type = "network",
2333 .compatible = "gianfar",
2334 },
2335 {},
2336 };
2337
2338 /* Structure for a device driver */
2339 static struct of_platform_driver gfar_driver = {
2340 .name = "fsl-gianfar",
2341 .match_table = gfar_match,
2342
2343 .probe = gfar_probe,
2344 .remove = gfar_remove,
2345 .suspend = gfar_suspend,
2346 .resume = gfar_resume,
2347 };
2348
2349 static int __init gfar_init(void)
2350 {
2351 return of_register_platform_driver(&gfar_driver);
2352 }
2353
2354 static void __exit gfar_exit(void)
2355 {
2356 of_unregister_platform_driver(&gfar_driver);
2357 }
2358
2359 module_init(gfar_init);
2360 module_exit(gfar_exit);
2361
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