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Staging: iio: dereferencing uninitialized variable
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / iio / adc / max1363_core.c
blob72b0917412eea9e115c5c694002f6d0a41f4e679
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33
34 #include "../iio.h"
35 #include "../sysfs.h"
36
37 #include "../ring_generic.h"
38 #include "adc.h"
39 #include "max1363.h"
40
41 #define MAX1363_MODE_SINGLE(_num, _mask) { \
42 .conf = MAX1363_CHANNEL_SEL(_num) \
43 | MAX1363_CONFIG_SCAN_SINGLE_1 \
44 | MAX1363_CONFIG_SE, \
45 .modemask = _mask, \
46 }
47
48 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
49 .conf = MAX1363_CHANNEL_SEL(_num) \
50 | MAX1363_CONFIG_SCAN_TO_CS \
51 | MAX1363_CONFIG_SE, \
52 .modemask = _mask, \
53 }
54
55 /* note not available for max1363 hence naming */
56 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
57 .conf = MAX1363_CHANNEL_SEL(_num) \
58 | MAX1236_SCAN_MID_TO_CHANNEL \
59 | MAX1363_CONFIG_SE, \
60 .modemask = _mask \
61 }
62
63 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
64 .conf = MAX1363_CHANNEL_SEL(_nump) \
65 | MAX1363_CONFIG_SCAN_SINGLE_1 \
66 | MAX1363_CONFIG_DE, \
67 .modemask = _mask \
68 }
69
70 /* Can't think how to automate naming so specify for now */
71 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
72 .conf = MAX1363_CHANNEL_SEL(_num) \
73 | MAX1363_CONFIG_SCAN_TO_CS \
74 | MAX1363_CONFIG_DE, \
75 .modemask = _mask \
76 }
77
78 /* note only available for max1363 hence naming */
79 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
80 .conf = MAX1363_CHANNEL_SEL(_num) \
81 | MAX1236_SCAN_MID_TO_CHANNEL \
82 | MAX1363_CONFIG_SE, \
83 .modemask = _mask \
84 }
85
86 static const struct max1363_mode max1363_mode_table[] = {
87 /* All of the single channel options first */
88 MAX1363_MODE_SINGLE(0, 1 << 0),
89 MAX1363_MODE_SINGLE(1, 1 << 1),
90 MAX1363_MODE_SINGLE(2, 1 << 2),
91 MAX1363_MODE_SINGLE(3, 1 << 3),
92 MAX1363_MODE_SINGLE(4, 1 << 4),
93 MAX1363_MODE_SINGLE(5, 1 << 5),
94 MAX1363_MODE_SINGLE(6, 1 << 6),
95 MAX1363_MODE_SINGLE(7, 1 << 7),
96 MAX1363_MODE_SINGLE(8, 1 << 8),
97 MAX1363_MODE_SINGLE(9, 1 << 9),
98 MAX1363_MODE_SINGLE(10, 1 << 10),
99 MAX1363_MODE_SINGLE(11, 1 << 11),
100
101 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
102 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
103 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
104 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
105 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
106 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
107 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
108 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
109 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
110 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
111 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
112 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
113
114 /* The multichannel scans next */
115 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
116 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
117 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
118 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
119 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
120 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
121 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
122 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
123 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
124 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
125 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
126 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
127 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
128 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
129 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
130 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
131 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
132
133 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
134 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
135 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
136 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
137 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
138 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
139 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
140 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
141 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
142 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
143 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
144 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
145 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
146 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
147 };
148
149 const struct max1363_mode
150 *max1363_match_mode(u32 mask, const struct max1363_chip_info *ci)
151 {
152 int i;
153 if (mask)
154 for (i = 0; i < ci->num_modes; i++)
155 if (!((~max1363_mode_table[ci->mode_list[i]].modemask) &
156 mask))
157 return &max1363_mode_table[ci->mode_list[i]];
158 return NULL;
159 }
160
161 static int max1363_write_basic_config(struct i2c_client *client,
162 unsigned char d1,
163 unsigned char d2)
164 {
165 u8 tx_buf[2] = {d1, d2};
166
167 return i2c_master_send(client, tx_buf, 2);
168 }
169
170 int max1363_set_scan_mode(struct max1363_state *st)
171 {
172 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
173 | MAX1363_SCAN_MASK
174 | MAX1363_SE_DE_MASK);
175 st->configbyte |= st->current_mode->conf;
176
177 return max1363_write_basic_config(st->client,
178 st->setupbyte,
179 st->configbyte);
180 }
181
182 static int max1363_read_single_chan(struct iio_dev *indio_dev,
183 struct iio_chan_spec const *chan,
184 int *val,
185 long m)
186 {
187 int ret = 0;
188 s32 data;
189 char rxbuf[2];
190 long mask;
191 struct max1363_state *st = iio_priv(indio_dev);
192 struct i2c_client *client = st->client;
193
194 mutex_lock(&indio_dev->mlock);
195 /*
196 * If monitor mode is enabled, the method for reading a single
197 * channel will have to be rather different and has not yet
198 * been implemented.
199 */
200 if (st->monitor_on) {
201 ret = -EBUSY;
202 goto error_ret;
203 }
204
205 /* If ring buffer capture is occurring, query the buffer */
206 if (iio_ring_enabled(indio_dev)) {
207 mask = max1363_mode_table[chan->address].modemask;
208 data = max1363_single_channel_from_ring(mask, st);
209 if (data < 0) {
210 ret = data;
211 goto error_ret;
212 }
213 } else {
214 /* Check to see if current scan mode is correct */
215 if (st->current_mode != &max1363_mode_table[chan->address]) {
216 /* Update scan mode if needed */
217 st->current_mode = &max1363_mode_table[chan->address];
218 ret = max1363_set_scan_mode(st);
219 if (ret < 0)
220 goto error_ret;
221 }
222 if (st->chip_info->bits != 8) {
223 /* Get reading */
224 data = i2c_master_recv(client, rxbuf, 2);
225 if (data < 0) {
226 ret = data;
227 goto error_ret;
228 }
229 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
230 } else {
231 /* Get reading */
232 data = i2c_master_recv(client, rxbuf, 1);
233 if (data < 0) {
234 ret = data;
235 goto error_ret;
236 }
237 data = rxbuf[0];
238 }
239 }
240 *val = data;
241 error_ret:
242 mutex_unlock(&indio_dev->mlock);
243 return ret;
244
245 }
246
247 static int max1363_read_raw(struct iio_dev *indio_dev,
248 struct iio_chan_spec const *chan,
249 int *val,
250 int *val2,
251 long m)
252 {
253 struct max1363_state *st = iio_priv(indio_dev);
254 int ret;
255 switch (m) {
256 case 0:
257 ret = max1363_read_single_chan(indio_dev, chan, val, m);
258 if (ret)
259 return ret;
260 return IIO_VAL_INT;
261 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
262 if ((1 << (st->chip_info->bits + 1)) >
263 st->chip_info->int_vref_mv) {
264 *val = 0;
265 *val2 = 500000;
266 return IIO_VAL_INT_PLUS_MICRO;
267 } else {
268 *val = (st->chip_info->int_vref_mv)
269 >> st->chip_info->bits;
270 return IIO_VAL_INT;
271 }
272 default:
273 return -EINVAL;
274 }
275 return 0;
276 }
277
278 /* Applies to max1363 */
279 static const enum max1363_modes max1363_mode_list[] = {
280 _s0, _s1, _s2, _s3,
281 s0to1, s0to2, s0to3,
282 d0m1, d2m3, d1m0, d3m2,
283 d0m1to2m3, d1m0to3m2,
284 };
285
286 #define MAX1363_EV_M \
287 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
288 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
289 #define MAX1363_INFO_MASK (1 << IIO_CHAN_INFO_SCALE_SHARED)
290
291 static struct iio_chan_spec max1363_channels[] = {
292 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
293 _s0, 0, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
294 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
295 _s1, 1, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
296 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
297 _s2, 2, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
298 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
299 _s3, 3, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
300 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
301 d0m1, 4, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
302 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
303 d2m3, 5, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
304 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
305 d1m0, 6, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
306 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
307 d3m2, 7, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
308 IIO_CHAN_SOFT_TIMESTAMP(8)
309 };
310
311 static struct iio_chan_spec max1361_channels[] = {
312 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
313 _s0, 0, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
314 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
315 _s1, 1, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
316 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
317 _s2, 2, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
318 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
319 _s3, 3, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
320 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
321 d0m1, 4, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
322 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
323 d2m3, 5, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
324 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
325 d1m0, 6, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
326 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
327 d3m2, 7, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
328 IIO_CHAN_SOFT_TIMESTAMP(8)
329 };
330
331 #define MAX1363_CHAN_U(num, address, scan_index, bits) \
332 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, num, 0, MAX1363_INFO_MASK, \
333 address, scan_index, IIO_ST('u', bits, \
334 (bits == 8) ? 8 : 16, 0), 0)
335 /* bipolar channel */
336 #define MAX1363_CHAN_B(num, num2, address, scan_index, bits) \
337 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, num, num2, MAX1363_INFO_MASK,\
338 address, scan_index, IIO_ST('s', bits, \
339 (bits == 8) ? 8 : 16, 0), 0)
340
341 #define MAX1363_4X_CHANS(bits) { \
342 MAX1363_CHAN_U(0, _s0, 0, bits), \
343 MAX1363_CHAN_U(1, _s1, 1, bits), \
344 MAX1363_CHAN_U(2, _s2, 2, bits), \
345 MAX1363_CHAN_U(3, _s3, 3, bits), \
346 MAX1363_CHAN_B(0, 1, d0m1, 4, bits), \
347 MAX1363_CHAN_B(2, 3, d2m3, 5, bits), \
348 MAX1363_CHAN_B(1, 0, d1m0, 6, bits), \
349 MAX1363_CHAN_B(3, 2, d3m2, 7, bits), \
350 IIO_CHAN_SOFT_TIMESTAMP(8) \
351 }
352
353 static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8);
354 static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10);
355 static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12);
356
357 /* Appies to max1236, max1237 */
358 static const enum max1363_modes max1236_mode_list[] = {
359 _s0, _s1, _s2, _s3,
360 s0to1, s0to2, s0to3,
361 d0m1, d2m3, d1m0, d3m2,
362 d0m1to2m3, d1m0to3m2,
363 s2to3,
364 };
365
366 /* Applies to max1238, max1239 */
367 static const enum max1363_modes max1238_mode_list[] = {
368 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
369 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
370 s0to7, s0to8, s0to9, s0to10, s0to11,
371 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
372 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
373 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
374 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
375 s6to7, s6to8, s6to9, s6to10, s6to11,
376 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
377 };
378
379 #define MAX1363_12X_CHANS(bits) { \
380 MAX1363_CHAN_U(0, _s0, 0, bits), \
381 MAX1363_CHAN_U(1, _s1, 1, bits), \
382 MAX1363_CHAN_U(2, _s2, 2, bits), \
383 MAX1363_CHAN_U(3, _s3, 3, bits), \
384 MAX1363_CHAN_U(4, _s4, 4, bits), \
385 MAX1363_CHAN_U(5, _s5, 5, bits), \
386 MAX1363_CHAN_U(6, _s6, 6, bits), \
387 MAX1363_CHAN_U(7, _s7, 7, bits), \
388 MAX1363_CHAN_U(8, _s8, 8, bits), \
389 MAX1363_CHAN_U(9, _s9, 9, bits), \
390 MAX1363_CHAN_U(10, _s10, 10, bits), \
391 MAX1363_CHAN_U(11, _s11, 11, bits), \
392 MAX1363_CHAN_B(0, 1, d0m1, 12, bits), \
393 MAX1363_CHAN_B(2, 3, d2m3, 13, bits), \
394 MAX1363_CHAN_B(4, 5, d4m5, 14, bits), \
395 MAX1363_CHAN_B(6, 7, d6m7, 15, bits), \
396 MAX1363_CHAN_B(8, 9, d8m9, 16, bits), \
397 MAX1363_CHAN_B(10, 11, d10m11, 17, bits), \
398 MAX1363_CHAN_B(1, 0, d1m0, 18, bits), \
399 MAX1363_CHAN_B(3, 2, d3m2, 19, bits), \
400 MAX1363_CHAN_B(5, 4, d5m4, 20, bits), \
401 MAX1363_CHAN_B(7, 6, d7m6, 21, bits), \
402 MAX1363_CHAN_B(9, 8, d9m8, 22, bits), \
403 MAX1363_CHAN_B(11, 10, d11m10, 23, bits), \
404 IIO_CHAN_SOFT_TIMESTAMP(24) \
405 }
406 static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
407 static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
408 static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
409
410 static const enum max1363_modes max11607_mode_list[] = {
411 _s0, _s1, _s2, _s3,
412 s0to1, s0to2, s0to3,
413 s2to3,
414 d0m1, d2m3, d1m0, d3m2,
415 d0m1to2m3, d1m0to3m2,
416 };
417
418 static const enum max1363_modes max11608_mode_list[] = {
419 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
420 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
421 s6to7,
422 d0m1, d2m3, d4m5, d6m7,
423 d1m0, d3m2, d5m4, d7m6,
424 d0m1to2m3, d0m1to4m5, d0m1to6m7,
425 d1m0to3m2, d1m0to5m4, d1m0to7m6,
426 };
427
428 #define MAX1363_8X_CHANS(bits) { \
429 MAX1363_CHAN_U(0, _s0, 0, bits), \
430 MAX1363_CHAN_U(1, _s1, 1, bits), \
431 MAX1363_CHAN_U(2, _s2, 2, bits), \
432 MAX1363_CHAN_U(3, _s3, 3, bits), \
433 MAX1363_CHAN_U(4, _s4, 4, bits), \
434 MAX1363_CHAN_U(5, _s5, 5, bits), \
435 MAX1363_CHAN_U(6, _s6, 6, bits), \
436 MAX1363_CHAN_U(7, _s7, 7, bits), \
437 MAX1363_CHAN_B(0, 1, d0m1, 8, bits), \
438 MAX1363_CHAN_B(2, 3, d2m3, 9, bits), \
439 MAX1363_CHAN_B(4, 5, d4m5, 10, bits), \
440 MAX1363_CHAN_B(6, 7, d6m7, 11, bits), \
441 MAX1363_CHAN_B(1, 0, d1m0, 12, bits), \
442 MAX1363_CHAN_B(3, 2, d3m2, 13, bits), \
443 MAX1363_CHAN_B(5, 4, d5m4, 14, bits), \
444 MAX1363_CHAN_B(7, 6, d7m6, 15, bits), \
445 IIO_CHAN_SOFT_TIMESTAMP(16) \
446 }
447 static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
448 static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
449 static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
450
451 static const enum max1363_modes max11644_mode_list[] = {
452 _s0, _s1, s0to1, d0m1, d1m0,
453 };
454
455 #define MAX1363_2X_CHANS(bits) { \
456 MAX1363_CHAN_U(0, _s0, 0, bits), \
457 MAX1363_CHAN_U(1, _s1, 1, bits), \
458 MAX1363_CHAN_B(0, 1, d0m1, 2, bits), \
459 MAX1363_CHAN_B(1, 0, d1m0, 3, bits), \
460 IIO_CHAN_SOFT_TIMESTAMP(4) \
461 }
462
463 static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
464 static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
465
466 enum { max1361,
467 max1362,
468 max1363,
469 max1364,
470 max1036,
471 max1037,
472 max1038,
473 max1039,
474 max1136,
475 max1137,
476 max1138,
477 max1139,
478 max1236,
479 max1237,
480 max1238,
481 max1239,
482 max11600,
483 max11601,
484 max11602,
485 max11603,
486 max11604,
487 max11605,
488 max11606,
489 max11607,
490 max11608,
491 max11609,
492 max11610,
493 max11611,
494 max11612,
495 max11613,
496 max11614,
497 max11615,
498 max11616,
499 max11617,
500 max11644,
501 max11645,
502 max11646,
503 max11647
504 };
505
506 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
507 8300, 4200, 2000, 1000 };
508
509 static ssize_t max1363_monitor_show_freq(struct device *dev,
510 struct device_attribute *attr,
511 char *buf)
512 {
513 struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
514 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
515 }
516
517 static ssize_t max1363_monitor_store_freq(struct device *dev,
518 struct device_attribute *attr,
519 const char *buf,
520 size_t len)
521 {
522 struct iio_dev *indio_dev = dev_get_drvdata(dev);
523 struct max1363_state *st = iio_priv(indio_dev);
524 int i, ret;
525 unsigned long val;
526 bool found = false;
527
528 ret = strict_strtoul(buf, 10, &val);
529 if (ret)
530 return -EINVAL;
531 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
532 if (val == max1363_monitor_speeds[i]) {
533 found = true;
534 break;
535 }
536 if (!found)
537 return -EINVAL;
538
539 mutex_lock(&indio_dev->mlock);
540 st->monitor_speed = i;
541 mutex_unlock(&indio_dev->mlock);
542
543 return 0;
544 }
545
546 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
547 max1363_monitor_show_freq,
548 max1363_monitor_store_freq);
549
550 static IIO_CONST_ATTR(sampling_frequency_available,
551 "133000 665000 33300 16600 8300 4200 2000 1000");
552
553 static int max1363_read_thresh(struct iio_dev *indio_dev,
554 int event_code,
555 int *val)
556 {
557 struct max1363_state *st = iio_priv(indio_dev);
558 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
559 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
560 else
561 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
562 return 0;
563 }
564
565 static int max1363_write_thresh(struct iio_dev *indio_dev,
566 int event_code,
567 int val)
568 {
569 struct max1363_state *st = iio_priv(indio_dev);
570 /* make it handle signed correctly as well */
571 switch (st->chip_info->bits) {
572 case 10:
573 if (val > 0x3FF)
574 return -EINVAL;
575 break;
576 case 12:
577 if (val > 0xFFF)
578 return -EINVAL;
579 break;
580 }
581
582 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
583 case IIO_EV_DIR_FALLING:
584 st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
585 break;
586 case IIO_EV_DIR_RISING:
587 st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
588 break;
589 }
590
591 return 0;
592 }
593
594 static const int max1363_event_codes[] = {
595 IIO_EVENT_CODE_IN_LOW_THRESH(3), IIO_EVENT_CODE_IN_HIGH_THRESH(3),
596 IIO_EVENT_CODE_IN_LOW_THRESH(2), IIO_EVENT_CODE_IN_HIGH_THRESH(2),
597 IIO_EVENT_CODE_IN_LOW_THRESH(1), IIO_EVENT_CODE_IN_HIGH_THRESH(1),
598 IIO_EVENT_CODE_IN_LOW_THRESH(0), IIO_EVENT_CODE_IN_HIGH_THRESH(0)
599 };
600
601 static irqreturn_t max1363_event_handler(int irq, void *private)
602 {
603 struct iio_dev *indio_dev = private;
604 struct max1363_state *st = iio_priv(indio_dev);
605 s64 timestamp = iio_get_time_ns();
606 unsigned long mask, loc;
607 u8 rx;
608 u8 tx[2] = { st->setupbyte,
609 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
610
611 i2c_master_recv(st->client, &rx, 1);
612 mask = rx;
613 for_each_set_bit(loc, &mask, 8)
614 iio_push_event(indio_dev, 0, max1363_event_codes[loc],
615 timestamp);
616 i2c_master_send(st->client, tx, 2);
617
618 return IRQ_HANDLED;
619 }
620
621 static int max1363_read_event_config(struct iio_dev *indio_dev,
622 int event_code)
623 {
624 struct max1363_state *st = iio_priv(indio_dev);
625
626 int val;
627 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
628 mutex_lock(&indio_dev->mlock);
629 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
630 val = (1 << number) & st->mask_low;
631 else
632 val = (1 << number) & st->mask_high;
633 mutex_unlock(&indio_dev->mlock);
634
635 return val;
636 }
637
638 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
639 {
640 u8 *tx_buf;
641 int ret, i = 3, j;
642 unsigned long numelements;
643 int len;
644 long modemask;
645
646 if (!enabled) {
647 /* transition to ring capture is not currently supported */
648 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
649 st->configbyte &= ~MAX1363_SCAN_MASK;
650 st->monitor_on = false;
651 return max1363_write_basic_config(st->client,
652 st->setupbyte,
653 st->configbyte);
654 }
655
656 /* Ensure we are in the relevant mode */
657 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
658 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
659 | MAX1363_SCAN_MASK
660 | MAX1363_SE_DE_MASK);
661 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
662 if ((st->mask_low | st->mask_high) & 0x0F) {
663 st->configbyte |= max1363_mode_table[s0to3].conf;
664 modemask = max1363_mode_table[s0to3].modemask;
665 } else if ((st->mask_low | st->mask_high) & 0x30) {
666 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
667 modemask = max1363_mode_table[d0m1to2m3].modemask;
668 } else {
669 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
670 modemask = max1363_mode_table[d1m0to3m2].modemask;
671 }
672 numelements = hweight_long(modemask);
673 len = 3 * numelements + 3;
674 tx_buf = kmalloc(len, GFP_KERNEL);
675 if (!tx_buf) {
676 ret = -ENOMEM;
677 goto error_ret;
678 }
679 tx_buf[0] = st->configbyte;
680 tx_buf[1] = st->setupbyte;
681 tx_buf[2] = (st->monitor_speed << 1);
682
683 /*
684 * So we need to do yet another bit of nefarious scan mode
685 * setup to match what we need.
686 */
687 for (j = 0; j < 8; j++)
688 if (modemask & (1 << j)) {
689 /* Establish the mode is in the scan */
690 if (st->mask_low & (1 << j)) {
691 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
692 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
693 } else if (j < 4) {
694 tx_buf[i] = 0;
695 tx_buf[i + 1] = 0;
696 } else {
697 tx_buf[i] = 0x80;
698 tx_buf[i + 1] = 0;
699 }
700 if (st->mask_high & (1 << j)) {
701 tx_buf[i + 1] |=
702 (st->thresh_high[j] >> 8) & 0x0F;
703 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
704 } else if (j < 4) {
705 tx_buf[i + 1] |= 0x0F;
706 tx_buf[i + 2] = 0xFF;
707 } else {
708 tx_buf[i + 1] |= 0x07;
709 tx_buf[i + 2] = 0xFF;
710 }
711 i += 3;
712 }
713
714
715 ret = i2c_master_send(st->client, tx_buf, len);
716 if (ret < 0)
717 goto error_ret;
718 if (ret != len) {
719 ret = -EIO;
720 goto error_ret;
721 }
722
723 /*
724 * Now that we hopefully have sensible thresholds in place it is
725 * time to turn the interrupts on.
726 * It is unclear from the data sheet if this should be necessary
727 * (i.e. whether monitor mode setup is atomic) but it appears to
728 * be in practice.
729 */
730 tx_buf[0] = st->setupbyte;
731 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
732 ret = i2c_master_send(st->client, tx_buf, 2);
733 if (ret < 0)
734 goto error_ret;
735 if (ret != 2) {
736 ret = -EIO;
737 goto error_ret;
738 }
739 ret = 0;
740 st->monitor_on = true;
741 error_ret:
742
743 kfree(tx_buf);
744
745 return ret;
746 }
747
748 /*
749 * To keep this manageable we always use one of 3 scan modes.
750 * Scan 0...3, 0-1,2-3 and 1-0,3-2
751 */
752
753 static inline int __max1363_check_event_mask(int thismask, int checkmask)
754 {
755 int ret = 0;
756 /* Is it unipolar */
757 if (thismask < 4) {
758 if (checkmask & ~0x0F) {
759 ret = -EBUSY;
760 goto error_ret;
761 }
762 } else if (thismask < 6) {
763 if (checkmask & ~0x30) {
764 ret = -EBUSY;
765 goto error_ret;
766 }
767 } else if (checkmask & ~0xC0)
768 ret = -EBUSY;
769 error_ret:
770 return ret;
771 }
772
773 static int max1363_write_event_config(struct iio_dev *indio_dev,
774 int event_code,
775 int state)
776 {
777 int ret = 0;
778 struct max1363_state *st = iio_priv(indio_dev);
779 u16 unifiedmask;
780 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
781
782 mutex_lock(&indio_dev->mlock);
783 unifiedmask = st->mask_low | st->mask_high;
784 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
785
786 if (state == 0)
787 st->mask_low &= ~(1 << number);
788 else {
789 ret = __max1363_check_event_mask((1 << number),
790 unifiedmask);
791 if (ret)
792 goto error_ret;
793 st->mask_low |= (1 << number);
794 }
795 } else {
796 if (state == 0)
797 st->mask_high &= ~(1 << number);
798 else {
799 ret = __max1363_check_event_mask((1 << number),
800 unifiedmask);
801 if (ret)
802 goto error_ret;
803 st->mask_high |= (1 << number);
804 }
805 }
806
807 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
808 error_ret:
809 mutex_unlock(&indio_dev->mlock);
810
811 return ret;
812 }
813
814 /*
815 * As with scan_elements, only certain sets of these can
816 * be combined.
817 */
818 static struct attribute *max1363_event_attributes[] = {
819 &iio_dev_attr_sampling_frequency.dev_attr.attr,
820 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
821 NULL,
822 };
823
824 static struct attribute_group max1363_event_attribute_group = {
825 .attrs = max1363_event_attributes,
826 };
827
828 #define MAX1363_EVENT_FUNCS \
829
830
831 static const struct iio_info max1238_info = {
832 .read_raw = &max1363_read_raw,
833 .driver_module = THIS_MODULE,
834 };
835
836 static const struct iio_info max1363_info = {
837 .read_event_value = &max1363_read_thresh,
838 .write_event_value = &max1363_write_thresh,
839 .read_event_config = &max1363_read_event_config,
840 .write_event_config = &max1363_write_event_config,
841 .read_raw = &max1363_read_raw,
842 .driver_module = THIS_MODULE,
843 .num_interrupt_lines = 1,
844 .event_attrs = &max1363_event_attribute_group,
845 };
846
847 /* max1363 and max1368 tested - rest from data sheet */
848 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
849 [max1361] = {
850 .bits = 10,
851 .int_vref_mv = 2048,
852 .mode_list = max1363_mode_list,
853 .num_modes = ARRAY_SIZE(max1363_mode_list),
854 .default_mode = s0to3,
855 .channels = max1361_channels,
856 .num_channels = ARRAY_SIZE(max1361_channels),
857 .info = &max1363_info,
858 },
859 [max1362] = {
860 .bits = 10,
861 .int_vref_mv = 4096,
862 .mode_list = max1363_mode_list,
863 .num_modes = ARRAY_SIZE(max1363_mode_list),
864 .default_mode = s0to3,
865 .channels = max1361_channels,
866 .num_channels = ARRAY_SIZE(max1361_channels),
867 .info = &max1363_info,
868 },
869 [max1363] = {
870 .bits = 12,
871 .int_vref_mv = 2048,
872 .mode_list = max1363_mode_list,
873 .num_modes = ARRAY_SIZE(max1363_mode_list),
874 .default_mode = s0to3,
875 .channels = max1363_channels,
876 .num_channels = ARRAY_SIZE(max1363_channels),
877 .info = &max1363_info,
878 },
879 [max1364] = {
880 .bits = 12,
881 .int_vref_mv = 4096,
882 .mode_list = max1363_mode_list,
883 .num_modes = ARRAY_SIZE(max1363_mode_list),
884 .default_mode = s0to3,
885 .channels = max1363_channels,
886 .num_channels = ARRAY_SIZE(max1363_channels),
887 .info = &max1363_info,
888 },
889 [max1036] = {
890 .bits = 8,
891 .int_vref_mv = 4096,
892 .mode_list = max1236_mode_list,
893 .num_modes = ARRAY_SIZE(max1236_mode_list),
894 .default_mode = s0to3,
895 .info = &max1238_info,
896 .channels = max1036_channels,
897 .num_channels = ARRAY_SIZE(max1036_channels),
898 },
899 [max1037] = {
900 .bits = 8,
901 .int_vref_mv = 2048,
902 .mode_list = max1236_mode_list,
903 .num_modes = ARRAY_SIZE(max1236_mode_list),
904 .default_mode = s0to3,
905 .info = &max1238_info,
906 .channels = max1036_channels,
907 .num_channels = ARRAY_SIZE(max1036_channels),
908 },
909 [max1038] = {
910 .bits = 8,
911 .int_vref_mv = 4096,
912 .mode_list = max1238_mode_list,
913 .num_modes = ARRAY_SIZE(max1238_mode_list),
914 .default_mode = s0to11,
915 .info = &max1238_info,
916 .channels = max1038_channels,
917 .num_channels = ARRAY_SIZE(max1038_channels),
918 },
919 [max1039] = {
920 .bits = 8,
921 .int_vref_mv = 2048,
922 .mode_list = max1238_mode_list,
923 .num_modes = ARRAY_SIZE(max1238_mode_list),
924 .default_mode = s0to11,
925 .info = &max1238_info,
926 .channels = max1038_channels,
927 .num_channels = ARRAY_SIZE(max1038_channels),
928 },
929 [max1136] = {
930 .bits = 10,
931 .int_vref_mv = 4096,
932 .mode_list = max1236_mode_list,
933 .num_modes = ARRAY_SIZE(max1236_mode_list),
934 .default_mode = s0to3,
935 .info = &max1238_info,
936 .channels = max1136_channels,
937 .num_channels = ARRAY_SIZE(max1136_channels),
938 },
939 [max1137] = {
940 .bits = 10,
941 .int_vref_mv = 2048,
942 .mode_list = max1236_mode_list,
943 .num_modes = ARRAY_SIZE(max1236_mode_list),
944 .default_mode = s0to3,
945 .info = &max1238_info,
946 .channels = max1136_channels,
947 .num_channels = ARRAY_SIZE(max1136_channels),
948 },
949 [max1138] = {
950 .bits = 10,
951 .int_vref_mv = 4096,
952 .mode_list = max1238_mode_list,
953 .num_modes = ARRAY_SIZE(max1238_mode_list),
954 .default_mode = s0to11,
955 .info = &max1238_info,
956 .channels = max1138_channels,
957 .num_channels = ARRAY_SIZE(max1138_channels),
958 },
959 [max1139] = {
960 .bits = 10,
961 .int_vref_mv = 2048,
962 .mode_list = max1238_mode_list,
963 .num_modes = ARRAY_SIZE(max1238_mode_list),
964 .default_mode = s0to11,
965 .info = &max1238_info,
966 .channels = max1138_channels,
967 .num_channels = ARRAY_SIZE(max1138_channels),
968 },
969 [max1236] = {
970 .bits = 12,
971 .int_vref_mv = 4096,
972 .mode_list = max1236_mode_list,
973 .num_modes = ARRAY_SIZE(max1236_mode_list),
974 .default_mode = s0to3,
975 .info = &max1238_info,
976 .channels = max1236_channels,
977 .num_channels = ARRAY_SIZE(max1236_channels),
978 },
979 [max1237] = {
980 .bits = 12,
981 .int_vref_mv = 2048,
982 .mode_list = max1236_mode_list,
983 .num_modes = ARRAY_SIZE(max1236_mode_list),
984 .default_mode = s0to3,
985 .info = &max1238_info,
986 .channels = max1236_channels,
987 .num_channels = ARRAY_SIZE(max1236_channels),
988 },
989 [max1238] = {
990 .bits = 12,
991 .int_vref_mv = 4096,
992 .mode_list = max1238_mode_list,
993 .num_modes = ARRAY_SIZE(max1238_mode_list),
994 .default_mode = s0to11,
995 .info = &max1238_info,
996 .channels = max1238_channels,
997 .num_channels = ARRAY_SIZE(max1238_channels),
998 },
999 [max1239] = {
1000 .bits = 12,
1001 .int_vref_mv = 2048,
1002 .mode_list = max1238_mode_list,
1003 .num_modes = ARRAY_SIZE(max1238_mode_list),
1004 .default_mode = s0to11,
1005 .info = &max1238_info,
1006 .channels = max1238_channels,
1007 .num_channels = ARRAY_SIZE(max1238_channels),
1008 },
1009 [max11600] = {
1010 .bits = 8,
1011 .int_vref_mv = 4096,
1012 .mode_list = max11607_mode_list,
1013 .num_modes = ARRAY_SIZE(max11607_mode_list),
1014 .default_mode = s0to3,
1015 .info = &max1238_info,
1016 .channels = max1036_channels,
1017 .num_channels = ARRAY_SIZE(max1036_channels),
1018 },
1019 [max11601] = {
1020 .bits = 8,
1021 .int_vref_mv = 2048,
1022 .mode_list = max11607_mode_list,
1023 .num_modes = ARRAY_SIZE(max11607_mode_list),
1024 .default_mode = s0to3,
1025 .info = &max1238_info,
1026 .channels = max1036_channels,
1027 .num_channels = ARRAY_SIZE(max1036_channels),
1028 },
1029 [max11602] = {
1030 .bits = 8,
1031 .int_vref_mv = 4096,
1032 .mode_list = max11608_mode_list,
1033 .num_modes = ARRAY_SIZE(max11608_mode_list),
1034 .default_mode = s0to7,
1035 .info = &max1238_info,
1036 .channels = max11602_channels,
1037 .num_channels = ARRAY_SIZE(max11602_channels),
1038 },
1039 [max11603] = {
1040 .bits = 8,
1041 .int_vref_mv = 2048,
1042 .mode_list = max11608_mode_list,
1043 .num_modes = ARRAY_SIZE(max11608_mode_list),
1044 .default_mode = s0to7,
1045 .info = &max1238_info,
1046 .channels = max11602_channels,
1047 .num_channels = ARRAY_SIZE(max11602_channels),
1048 },
1049 [max11604] = {
1050 .bits = 8,
1051 .int_vref_mv = 4098,
1052 .mode_list = max1238_mode_list,
1053 .num_modes = ARRAY_SIZE(max1238_mode_list),
1054 .default_mode = s0to11,
1055 .info = &max1238_info,
1056 .channels = max1238_channels,
1057 .num_channels = ARRAY_SIZE(max1238_channels),
1058 },
1059 [max11605] = {
1060 .bits = 8,
1061 .int_vref_mv = 2048,
1062 .mode_list = max1238_mode_list,
1063 .num_modes = ARRAY_SIZE(max1238_mode_list),
1064 .default_mode = s0to11,
1065 .info = &max1238_info,
1066 .channels = max1238_channels,
1067 .num_channels = ARRAY_SIZE(max1238_channels),
1068 },
1069 [max11606] = {
1070 .bits = 10,
1071 .int_vref_mv = 4096,
1072 .mode_list = max11607_mode_list,
1073 .num_modes = ARRAY_SIZE(max11607_mode_list),
1074 .default_mode = s0to3,
1075 .info = &max1238_info,
1076 .channels = max1136_channels,
1077 .num_channels = ARRAY_SIZE(max1136_channels),
1078 },
1079 [max11607] = {
1080 .bits = 10,
1081 .int_vref_mv = 2048,
1082 .mode_list = max11607_mode_list,
1083 .num_modes = ARRAY_SIZE(max11607_mode_list),
1084 .default_mode = s0to3,
1085 .info = &max1238_info,
1086 .channels = max1136_channels,
1087 .num_channels = ARRAY_SIZE(max1136_channels),
1088 },
1089 [max11608] = {
1090 .bits = 10,
1091 .int_vref_mv = 4096,
1092 .mode_list = max11608_mode_list,
1093 .num_modes = ARRAY_SIZE(max11608_mode_list),
1094 .default_mode = s0to7,
1095 .info = &max1238_info,
1096 .channels = max11608_channels,
1097 .num_channels = ARRAY_SIZE(max11608_channels),
1098 },
1099 [max11609] = {
1100 .bits = 10,
1101 .int_vref_mv = 2048,
1102 .mode_list = max11608_mode_list,
1103 .num_modes = ARRAY_SIZE(max11608_mode_list),
1104 .default_mode = s0to7,
1105 .info = &max1238_info,
1106 .channels = max11608_channels,
1107 .num_channels = ARRAY_SIZE(max11608_channels),
1108 },
1109 [max11610] = {
1110 .bits = 10,
1111 .int_vref_mv = 4098,
1112 .mode_list = max1238_mode_list,
1113 .num_modes = ARRAY_SIZE(max1238_mode_list),
1114 .default_mode = s0to11,
1115 .info = &max1238_info,
1116 .channels = max1238_channels,
1117 .num_channels = ARRAY_SIZE(max1238_channels),
1118 },
1119 [max11611] = {
1120 .bits = 10,
1121 .int_vref_mv = 2048,
1122 .mode_list = max1238_mode_list,
1123 .num_modes = ARRAY_SIZE(max1238_mode_list),
1124 .default_mode = s0to11,
1125 .info = &max1238_info,
1126 .channels = max1238_channels,
1127 .num_channels = ARRAY_SIZE(max1238_channels),
1128 },
1129 [max11612] = {
1130 .bits = 12,
1131 .int_vref_mv = 4096,
1132 .mode_list = max11607_mode_list,
1133 .num_modes = ARRAY_SIZE(max11607_mode_list),
1134 .default_mode = s0to3,
1135 .info = &max1238_info,
1136 .channels = max1363_channels,
1137 .num_channels = ARRAY_SIZE(max1363_channels),
1138 },
1139 [max11613] = {
1140 .bits = 12,
1141 .int_vref_mv = 2048,
1142 .mode_list = max11607_mode_list,
1143 .num_modes = ARRAY_SIZE(max11607_mode_list),
1144 .default_mode = s0to3,
1145 .info = &max1238_info,
1146 .channels = max1363_channels,
1147 .num_channels = ARRAY_SIZE(max1363_channels),
1148 },
1149 [max11614] = {
1150 .bits = 12,
1151 .int_vref_mv = 4096,
1152 .mode_list = max11608_mode_list,
1153 .num_modes = ARRAY_SIZE(max11608_mode_list),
1154 .default_mode = s0to7,
1155 .info = &max1238_info,
1156 .channels = max11614_channels,
1157 .num_channels = ARRAY_SIZE(max11614_channels),
1158 },
1159 [max11615] = {
1160 .bits = 12,
1161 .int_vref_mv = 2048,
1162 .mode_list = max11608_mode_list,
1163 .num_modes = ARRAY_SIZE(max11608_mode_list),
1164 .default_mode = s0to7,
1165 .info = &max1238_info,
1166 .channels = max11614_channels,
1167 .num_channels = ARRAY_SIZE(max11614_channels),
1168 },
1169 [max11616] = {
1170 .bits = 12,
1171 .int_vref_mv = 4098,
1172 .mode_list = max1238_mode_list,
1173 .num_modes = ARRAY_SIZE(max1238_mode_list),
1174 .default_mode = s0to11,
1175 .info = &max1238_info,
1176 .channels = max1238_channels,
1177 .num_channels = ARRAY_SIZE(max1238_channels),
1178 },
1179 [max11617] = {
1180 .bits = 12,
1181 .int_vref_mv = 2048,
1182 .mode_list = max1238_mode_list,
1183 .num_modes = ARRAY_SIZE(max1238_mode_list),
1184 .default_mode = s0to11,
1185 .info = &max1238_info,
1186 .channels = max1238_channels,
1187 .num_channels = ARRAY_SIZE(max1238_channels),
1188 },
1189 [max11644] = {
1190 .bits = 12,
1191 .int_vref_mv = 2048,
1192 .mode_list = max11644_mode_list,
1193 .num_modes = ARRAY_SIZE(max11644_mode_list),
1194 .default_mode = s0to1,
1195 .info = &max1238_info,
1196 .channels = max11644_channels,
1197 .num_channels = ARRAY_SIZE(max11644_channels),
1198 },
1199 [max11645] = {
1200 .bits = 12,
1201 .int_vref_mv = 4096,
1202 .mode_list = max11644_mode_list,
1203 .num_modes = ARRAY_SIZE(max11644_mode_list),
1204 .default_mode = s0to1,
1205 .info = &max1238_info,
1206 .channels = max11644_channels,
1207 .num_channels = ARRAY_SIZE(max11644_channels),
1208 },
1209 [max11646] = {
1210 .bits = 10,
1211 .int_vref_mv = 2048,
1212 .mode_list = max11644_mode_list,
1213 .num_modes = ARRAY_SIZE(max11644_mode_list),
1214 .default_mode = s0to1,
1215 .info = &max1238_info,
1216 .channels = max11646_channels,
1217 .num_channels = ARRAY_SIZE(max11646_channels),
1218 },
1219 [max11647] = {
1220 .bits = 10,
1221 .int_vref_mv = 4096,
1222 .mode_list = max11644_mode_list,
1223 .num_modes = ARRAY_SIZE(max11644_mode_list),
1224 .default_mode = s0to1,
1225 .info = &max1238_info,
1226 .channels = max11646_channels,
1227 .num_channels = ARRAY_SIZE(max11646_channels),
1228 },
1229 };
1230
1231
1232
1233 static int max1363_initial_setup(struct max1363_state *st)
1234 {
1235 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1236 | MAX1363_SETUP_POWER_UP_INT_REF
1237 | MAX1363_SETUP_INT_CLOCK
1238 | MAX1363_SETUP_UNIPOLAR
1239 | MAX1363_SETUP_NORESET;
1240
1241 /* Set scan mode writes the config anyway so wait until then*/
1242 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1243 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1244 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1245
1246 return max1363_set_scan_mode(st);
1247 }
1248
1249 static int __devinit max1363_probe(struct i2c_client *client,
1250 const struct i2c_device_id *id)
1251 {
1252 int ret, i, regdone = 0;
1253 struct max1363_state *st;
1254 struct iio_dev *indio_dev;
1255 struct regulator *reg;
1256
1257 reg = regulator_get(&client->dev, "vcc");
1258 if (IS_ERR(reg)) {
1259 ret = PTR_ERR(reg);
1260 goto error_out;
1261 }
1262
1263 ret = regulator_enable(reg);
1264 if (ret)
1265 goto error_put_reg;
1266
1267 indio_dev = iio_allocate_device(sizeof(struct max1363_state));
1268 if (indio_dev == NULL) {
1269 ret = -ENOMEM;
1270 goto error_disable_reg;
1271 }
1272 st = iio_priv(indio_dev);
1273 st->reg = reg;
1274 /* this is only used for device removal purposes */
1275 i2c_set_clientdata(client, indio_dev);
1276
1277 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1278 st->client = client;
1279
1280 indio_dev->available_scan_masks
1281 = kzalloc(sizeof(*indio_dev->available_scan_masks)*
1282 (st->chip_info->num_modes + 1), GFP_KERNEL);
1283 if (!indio_dev->available_scan_masks) {
1284 ret = -ENOMEM;
1285 goto error_free_device;
1286 }
1287
1288 for (i = 0; i < st->chip_info->num_modes; i++)
1289 indio_dev->available_scan_masks[i] =
1290 max1363_mode_table[st->chip_info->mode_list[i]]
1291 .modemask;
1292 /* Estabilish that the iio_dev is a child of the i2c device */
1293 indio_dev->dev.parent = &client->dev;
1294 indio_dev->name = id->name;
1295
1296 indio_dev->info = st->chip_info->info;
1297 indio_dev->modes = INDIO_DIRECT_MODE;
1298 ret = max1363_initial_setup(st);
1299 if (ret < 0)
1300 goto error_free_available_scan_masks;
1301
1302 ret = max1363_register_ring_funcs_and_init(indio_dev);
1303 if (ret)
1304 goto error_free_available_scan_masks;
1305
1306 ret = iio_device_register(indio_dev);
1307 if (ret)
1308 goto error_cleanup_ring;
1309 regdone = 1;
1310 ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
1311 st->chip_info->channels,
1312 st->chip_info->num_channels);
1313 if (ret)
1314 goto error_cleanup_ring;
1315
1316 if (client->irq) {
1317 ret = request_threaded_irq(st->client->irq,
1318 NULL,
1319 &max1363_event_handler,
1320 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1321 "max1363_event",
1322 indio_dev);
1323
1324 if (ret)
1325 goto error_uninit_ring;
1326 }
1327
1328 return 0;
1329
1330 error_uninit_ring:
1331 iio_ring_buffer_unregister(indio_dev->ring);
1332 error_cleanup_ring:
1333 max1363_ring_cleanup(indio_dev);
1334 error_free_available_scan_masks:
1335 kfree(indio_dev->available_scan_masks);
1336 error_free_device:
1337 if (!regdone)
1338 iio_free_device(indio_dev);
1339 else
1340 iio_device_unregister(indio_dev);
1341 error_disable_reg:
1342 regulator_disable(reg);
1343 error_put_reg:
1344 regulator_put(reg);
1345 error_out:
1346 return ret;
1347 }
1348
1349 static int max1363_remove(struct i2c_client *client)
1350 {
1351 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1352 struct max1363_state *st = iio_priv(indio_dev);
1353 struct regulator *reg = st->reg;
1354
1355 if (client->irq)
1356 free_irq(st->client->irq, indio_dev);
1357 iio_ring_buffer_unregister(indio_dev->ring);
1358 max1363_ring_cleanup(indio_dev);
1359 kfree(indio_dev->available_scan_masks);
1360 if (!IS_ERR(reg)) {
1361 regulator_disable(reg);
1362 regulator_put(reg);
1363 }
1364 iio_device_unregister(indio_dev);
1365
1366 return 0;
1367 }
1368
1369 static const struct i2c_device_id max1363_id[] = {
1370 { "max1361", max1361 },
1371 { "max1362", max1362 },
1372 { "max1363", max1363 },
1373 { "max1364", max1364 },
1374 { "max1036", max1036 },
1375 { "max1037", max1037 },
1376 { "max1038", max1038 },
1377 { "max1039", max1039 },
1378 { "max1136", max1136 },
1379 { "max1137", max1137 },
1380 { "max1138", max1138 },
1381 { "max1139", max1139 },
1382 { "max1236", max1236 },
1383 { "max1237", max1237 },
1384 { "max1238", max1238 },
1385 { "max1239", max1239 },
1386 { "max11600", max11600 },
1387 { "max11601", max11601 },
1388 { "max11602", max11602 },
1389 { "max11603", max11603 },
1390 { "max11604", max11604 },
1391 { "max11605", max11605 },
1392 { "max11606", max11606 },
1393 { "max11607", max11607 },
1394 { "max11608", max11608 },
1395 { "max11609", max11609 },
1396 { "max11610", max11610 },
1397 { "max11611", max11611 },
1398 { "max11612", max11612 },
1399 { "max11613", max11613 },
1400 { "max11614", max11614 },
1401 { "max11615", max11615 },
1402 { "max11616", max11616 },
1403 { "max11617", max11617 },
1404 {}
1405 };
1406
1407 MODULE_DEVICE_TABLE(i2c, max1363_id);
1408
1409 static struct i2c_driver max1363_driver = {
1410 .driver = {
1411 .name = "max1363",
1412 },
1413 .probe = max1363_probe,
1414 .remove = max1363_remove,
1415 .id_table = max1363_id,
1416 };
1417
1418 static __init int max1363_init(void)
1419 {
1420 return i2c_add_driver(&max1363_driver);
1421 }
1422
1423 static __exit void max1363_exit(void)
1424 {
1425 i2c_del_driver(&max1363_driver);
1426 }
1427
1428 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
1429 MODULE_DESCRIPTION("Maxim 1363 ADC");
1430 MODULE_LICENSE("GPL v2");
1431
1432 module_init(max1363_init);
1433 module_exit(max1363_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree