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8139cp: properly config rx mode after resuming
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / realtek / 8139cp.c
blobcc6b391479ca62ff3aaaabbe3f2c6ec09a5740df
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
72 #include <linux/in.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/uaccess.h>
80
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
84
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
89
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
93
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
99
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
101 NETIF_MSG_PROBE | \
102 NETIF_MSG_LINK)
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
112 CP_STATS_SIZE)
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
119
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
122
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
128
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
131
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
135
136 enum {
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
169
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
191 RxProtoTCP = 1,
192 RxProtoUDP = 2,
193 RxProtoIP = 3,
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
206
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
209
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
219
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
235
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
239
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
244
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
252
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
256
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
260
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
264
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
269
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
274
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
278
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
289 };
290
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
294
295 struct cp_desc {
296 __le32 opts1;
297 __le32 opts2;
298 __le64 addr;
299 };
300
301 struct cp_dma_stats {
302 __le64 tx_ok;
303 __le64 rx_ok;
304 __le64 tx_err;
305 __le32 rx_err;
306 __le16 rx_fifo;
307 __le16 frame_align;
308 __le32 tx_ok_1col;
309 __le32 tx_ok_mcol;
310 __le64 rx_ok_phys;
311 __le64 rx_ok_bcast;
312 __le32 rx_ok_mcast;
313 __le16 tx_abort;
314 __le16 tx_underrun;
315 } __packed;
316
317 struct cp_extra_stats {
318 unsigned long rx_frags;
319 };
320
321 struct cp_private {
322 void __iomem *regs;
323 struct net_device *dev;
324 spinlock_t lock;
325 u32 msg_enable;
326
327 struct napi_struct napi;
328
329 struct pci_dev *pdev;
330 u32 rx_config;
331 u16 cpcmd;
332
333 struct cp_extra_stats cp_stats;
334
335 unsigned rx_head ____cacheline_aligned;
336 unsigned rx_tail;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
339
340 unsigned tx_head ____cacheline_aligned;
341 unsigned tx_tail;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
344
345 unsigned rx_buf_sz;
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
347
348 dma_addr_t ring_dma;
349
350 struct mii_if_info mii_if;
351 };
352
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
362 } while (0)
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
366 } while (0)
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
370 } while (0)
371
372
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
378 #endif
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
384
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
388 { },
389 };
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
391
392 static struct {
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
395 { "tx_ok" },
396 { "rx_ok" },
397 { "tx_err" },
398 { "rx_err" },
399 { "rx_fifo" },
400 { "frame_align" },
401 { "tx_ok_1col" },
402 { "tx_ok_mcol" },
403 { "rx_ok_phys" },
404 { "rx_ok_bcast" },
405 { "rx_ok_mcast" },
406 { "tx_abort" },
407 { "tx_underrun" },
408 { "rx_frags" },
409 };
410
411
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
413 {
414 unsigned int mtu = cp->dev->mtu;
415
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
419 else
420 cp->rx_buf_sz = PKT_BUF_SZ;
421 }
422
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
425 {
426 u32 opts2 = le32_to_cpu(desc->opts2);
427
428 skb->protocol = eth_type_trans (skb, cp->dev);
429
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
432
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
435
436 napi_gro_receive(&cp->napi, skb);
437 }
438
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
440 u32 status, u32 len)
441 {
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
455 }
456
457 static inline unsigned int cp_rx_csum_ok (u32 status)
458 {
459 unsigned int protocol = (status >> 16) & 0x3;
460
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
463 return 1;
464 else
465 return 0;
466 }
467
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
469 {
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
473 int rx;
474
475 rx_status_loop:
476 rx = 0;
477 cpw16(IntrStatus, cp_rx_intr_mask);
478
479 while (1) {
480 u32 status, len;
481 dma_addr_t mapping;
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
485
486 skb = cp->rx_skb[rx_tail];
487 BUG_ON(!skb);
488
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
492 break;
493
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
496
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
502 */
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
506 goto rx_next;
507 }
508
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
511 goto rx_next;
512 }
513
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
516
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
518 if (!new_skb) {
519 dev->stats.rx_dropped++;
520 goto rx_next;
521 }
522
523 dma_unmap_single(&cp->pdev->dev, mapping,
524 buflen, PCI_DMA_FROMDEVICE);
525
526 /* Handle checksum offloading for incoming packets. */
527 if (cp_rx_csum_ok(status))
528 skb->ip_summed = CHECKSUM_UNNECESSARY;
529 else
530 skb_checksum_none_assert(skb);
531
532 skb_put(skb, len);
533
534 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
535 PCI_DMA_FROMDEVICE);
536 cp->rx_skb[rx_tail] = new_skb;
537
538 cp_rx_skb(cp, skb, desc);
539 rx++;
540
541 rx_next:
542 cp->rx_ring[rx_tail].opts2 = 0;
543 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
544 if (rx_tail == (CP_RX_RING_SIZE - 1))
545 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
546 cp->rx_buf_sz);
547 else
548 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
549 rx_tail = NEXT_RX(rx_tail);
550
551 if (rx >= budget)
552 break;
553 }
554
555 cp->rx_tail = rx_tail;
556
557 /* if we did not reach work limit, then we're done with
558 * this round of polling
559 */
560 if (rx < budget) {
561 unsigned long flags;
562
563 if (cpr16(IntrStatus) & cp_rx_intr_mask)
564 goto rx_status_loop;
565
566 spin_lock_irqsave(&cp->lock, flags);
567 __napi_complete(napi);
568 cpw16_f(IntrMask, cp_intr_mask);
569 spin_unlock_irqrestore(&cp->lock, flags);
570 }
571
572 return rx;
573 }
574
575 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
576 {
577 struct net_device *dev = dev_instance;
578 struct cp_private *cp;
579 u16 status;
580
581 if (unlikely(dev == NULL))
582 return IRQ_NONE;
583 cp = netdev_priv(dev);
584
585 status = cpr16(IntrStatus);
586 if (!status || (status == 0xFFFF))
587 return IRQ_NONE;
588
589 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
590 status, cpr8(Cmd), cpr16(CpCmd));
591
592 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
593
594 spin_lock(&cp->lock);
595
596 /* close possible race's with dev_close */
597 if (unlikely(!netif_running(dev))) {
598 cpw16(IntrMask, 0);
599 spin_unlock(&cp->lock);
600 return IRQ_HANDLED;
601 }
602
603 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
604 if (napi_schedule_prep(&cp->napi)) {
605 cpw16_f(IntrMask, cp_norx_intr_mask);
606 __napi_schedule(&cp->napi);
607 }
608
609 if (status & (TxOK | TxErr | TxEmpty | SWInt))
610 cp_tx(cp);
611 if (status & LinkChg)
612 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
613
614 spin_unlock(&cp->lock);
615
616 if (status & PciErr) {
617 u16 pci_status;
618
619 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
620 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
621 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
622 status, pci_status);
623
624 /* TODO: reset hardware */
625 }
626
627 return IRQ_HANDLED;
628 }
629
630 #ifdef CONFIG_NET_POLL_CONTROLLER
631 /*
632 * Polling receive - used by netconsole and other diagnostic tools
633 * to allow network i/o with interrupts disabled.
634 */
635 static void cp_poll_controller(struct net_device *dev)
636 {
637 disable_irq(dev->irq);
638 cp_interrupt(dev->irq, dev);
639 enable_irq(dev->irq);
640 }
641 #endif
642
643 static void cp_tx (struct cp_private *cp)
644 {
645 unsigned tx_head = cp->tx_head;
646 unsigned tx_tail = cp->tx_tail;
647
648 while (tx_tail != tx_head) {
649 struct cp_desc *txd = cp->tx_ring + tx_tail;
650 struct sk_buff *skb;
651 u32 status;
652
653 rmb();
654 status = le32_to_cpu(txd->opts1);
655 if (status & DescOwn)
656 break;
657
658 skb = cp->tx_skb[tx_tail];
659 BUG_ON(!skb);
660
661 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
662 le32_to_cpu(txd->opts1) & 0xffff,
663 PCI_DMA_TODEVICE);
664
665 if (status & LastFrag) {
666 if (status & (TxError | TxFIFOUnder)) {
667 netif_dbg(cp, tx_err, cp->dev,
668 "tx err, status 0x%x\n", status);
669 cp->dev->stats.tx_errors++;
670 if (status & TxOWC)
671 cp->dev->stats.tx_window_errors++;
672 if (status & TxMaxCol)
673 cp->dev->stats.tx_aborted_errors++;
674 if (status & TxLinkFail)
675 cp->dev->stats.tx_carrier_errors++;
676 if (status & TxFIFOUnder)
677 cp->dev->stats.tx_fifo_errors++;
678 } else {
679 cp->dev->stats.collisions +=
680 ((status >> TxColCntShift) & TxColCntMask);
681 cp->dev->stats.tx_packets++;
682 cp->dev->stats.tx_bytes += skb->len;
683 netif_dbg(cp, tx_done, cp->dev,
684 "tx done, slot %d\n", tx_tail);
685 }
686 dev_kfree_skb_irq(skb);
687 }
688
689 cp->tx_skb[tx_tail] = NULL;
690
691 tx_tail = NEXT_TX(tx_tail);
692 }
693
694 cp->tx_tail = tx_tail;
695
696 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
697 netif_wake_queue(cp->dev);
698 }
699
700 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
701 {
702 return vlan_tx_tag_present(skb) ?
703 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
704 }
705
706 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
707 struct net_device *dev)
708 {
709 struct cp_private *cp = netdev_priv(dev);
710 unsigned entry;
711 u32 eor, flags;
712 unsigned long intr_flags;
713 __le32 opts2;
714 int mss = 0;
715
716 spin_lock_irqsave(&cp->lock, intr_flags);
717
718 /* This is a hard error, log it. */
719 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
720 netif_stop_queue(dev);
721 spin_unlock_irqrestore(&cp->lock, intr_flags);
722 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
723 return NETDEV_TX_BUSY;
724 }
725
726 entry = cp->tx_head;
727 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
728 mss = skb_shinfo(skb)->gso_size;
729
730 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
731
732 if (skb_shinfo(skb)->nr_frags == 0) {
733 struct cp_desc *txd = &cp->tx_ring[entry];
734 u32 len;
735 dma_addr_t mapping;
736
737 len = skb->len;
738 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
739 txd->opts2 = opts2;
740 txd->addr = cpu_to_le64(mapping);
741 wmb();
742
743 flags = eor | len | DescOwn | FirstFrag | LastFrag;
744
745 if (mss)
746 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
747 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
748 const struct iphdr *ip = ip_hdr(skb);
749 if (ip->protocol == IPPROTO_TCP)
750 flags |= IPCS | TCPCS;
751 else if (ip->protocol == IPPROTO_UDP)
752 flags |= IPCS | UDPCS;
753 else
754 WARN_ON(1); /* we need a WARN() */
755 }
756
757 txd->opts1 = cpu_to_le32(flags);
758 wmb();
759
760 cp->tx_skb[entry] = skb;
761 entry = NEXT_TX(entry);
762 } else {
763 struct cp_desc *txd;
764 u32 first_len, first_eor;
765 dma_addr_t first_mapping;
766 int frag, first_entry = entry;
767 const struct iphdr *ip = ip_hdr(skb);
768
769 /* We must give this initial chunk to the device last.
770 * Otherwise we could race with the device.
771 */
772 first_eor = eor;
773 first_len = skb_headlen(skb);
774 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
775 first_len, PCI_DMA_TODEVICE);
776 cp->tx_skb[entry] = skb;
777 entry = NEXT_TX(entry);
778
779 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
780 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
781 u32 len;
782 u32 ctrl;
783 dma_addr_t mapping;
784
785 len = skb_frag_size(this_frag);
786 mapping = dma_map_single(&cp->pdev->dev,
787 skb_frag_address(this_frag),
788 len, PCI_DMA_TODEVICE);
789 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
790
791 ctrl = eor | len | DescOwn;
792
793 if (mss)
794 ctrl |= LargeSend |
795 ((mss & MSSMask) << MSSShift);
796 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
797 if (ip->protocol == IPPROTO_TCP)
798 ctrl |= IPCS | TCPCS;
799 else if (ip->protocol == IPPROTO_UDP)
800 ctrl |= IPCS | UDPCS;
801 else
802 BUG();
803 }
804
805 if (frag == skb_shinfo(skb)->nr_frags - 1)
806 ctrl |= LastFrag;
807
808 txd = &cp->tx_ring[entry];
809 txd->opts2 = opts2;
810 txd->addr = cpu_to_le64(mapping);
811 wmb();
812
813 txd->opts1 = cpu_to_le32(ctrl);
814 wmb();
815
816 cp->tx_skb[entry] = skb;
817 entry = NEXT_TX(entry);
818 }
819
820 txd = &cp->tx_ring[first_entry];
821 txd->opts2 = opts2;
822 txd->addr = cpu_to_le64(first_mapping);
823 wmb();
824
825 if (skb->ip_summed == CHECKSUM_PARTIAL) {
826 if (ip->protocol == IPPROTO_TCP)
827 txd->opts1 = cpu_to_le32(first_eor | first_len |
828 FirstFrag | DescOwn |
829 IPCS | TCPCS);
830 else if (ip->protocol == IPPROTO_UDP)
831 txd->opts1 = cpu_to_le32(first_eor | first_len |
832 FirstFrag | DescOwn |
833 IPCS | UDPCS);
834 else
835 BUG();
836 } else
837 txd->opts1 = cpu_to_le32(first_eor | first_len |
838 FirstFrag | DescOwn);
839 wmb();
840 }
841 cp->tx_head = entry;
842 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
843 entry, skb->len);
844 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
845 netif_stop_queue(dev);
846
847 spin_unlock_irqrestore(&cp->lock, intr_flags);
848
849 cpw8(TxPoll, NormalTxPoll);
850
851 return NETDEV_TX_OK;
852 }
853
854 /* Set or clear the multicast filter for this adaptor.
855 This routine is not state sensitive and need not be SMP locked. */
856
857 static void __cp_set_rx_mode (struct net_device *dev)
858 {
859 struct cp_private *cp = netdev_priv(dev);
860 u32 mc_filter[2]; /* Multicast hash filter */
861 int rx_mode;
862
863 /* Note: do not reorder, GCC is clever about common statements. */
864 if (dev->flags & IFF_PROMISC) {
865 /* Unconditionally log net taps. */
866 rx_mode =
867 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
868 AcceptAllPhys;
869 mc_filter[1] = mc_filter[0] = 0xffffffff;
870 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
871 (dev->flags & IFF_ALLMULTI)) {
872 /* Too many to filter perfectly -- accept all multicasts. */
873 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
874 mc_filter[1] = mc_filter[0] = 0xffffffff;
875 } else {
876 struct netdev_hw_addr *ha;
877 rx_mode = AcceptBroadcast | AcceptMyPhys;
878 mc_filter[1] = mc_filter[0] = 0;
879 netdev_for_each_mc_addr(ha, dev) {
880 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
881
882 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
883 rx_mode |= AcceptMulticast;
884 }
885 }
886
887 /* We can safely update without stopping the chip. */
888 cp->rx_config = cp_rx_config | rx_mode;
889 cpw32_f(RxConfig, cp->rx_config);
890
891 cpw32_f (MAR0 + 0, mc_filter[0]);
892 cpw32_f (MAR0 + 4, mc_filter[1]);
893 }
894
895 static void cp_set_rx_mode (struct net_device *dev)
896 {
897 unsigned long flags;
898 struct cp_private *cp = netdev_priv(dev);
899
900 spin_lock_irqsave (&cp->lock, flags);
901 __cp_set_rx_mode(dev);
902 spin_unlock_irqrestore (&cp->lock, flags);
903 }
904
905 static void __cp_get_stats(struct cp_private *cp)
906 {
907 /* only lower 24 bits valid; write any value to clear */
908 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
909 cpw32 (RxMissed, 0);
910 }
911
912 static struct net_device_stats *cp_get_stats(struct net_device *dev)
913 {
914 struct cp_private *cp = netdev_priv(dev);
915 unsigned long flags;
916
917 /* The chip only need report frame silently dropped. */
918 spin_lock_irqsave(&cp->lock, flags);
919 if (netif_running(dev) && netif_device_present(dev))
920 __cp_get_stats(cp);
921 spin_unlock_irqrestore(&cp->lock, flags);
922
923 return &dev->stats;
924 }
925
926 static void cp_stop_hw (struct cp_private *cp)
927 {
928 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
929 cpw16_f(IntrMask, 0);
930 cpw8(Cmd, 0);
931 cpw16_f(CpCmd, 0);
932 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
933
934 cp->rx_tail = 0;
935 cp->tx_head = cp->tx_tail = 0;
936 }
937
938 static void cp_reset_hw (struct cp_private *cp)
939 {
940 unsigned work = 1000;
941
942 cpw8(Cmd, CmdReset);
943
944 while (work--) {
945 if (!(cpr8(Cmd) & CmdReset))
946 return;
947
948 schedule_timeout_uninterruptible(10);
949 }
950
951 netdev_err(cp->dev, "hardware reset timeout\n");
952 }
953
954 static inline void cp_start_hw (struct cp_private *cp)
955 {
956 cpw16(CpCmd, cp->cpcmd);
957 cpw8(Cmd, RxOn | TxOn);
958 }
959
960 static void cp_init_hw (struct cp_private *cp)
961 {
962 struct net_device *dev = cp->dev;
963 dma_addr_t ring_dma;
964
965 cp_reset_hw(cp);
966
967 cpw8_f (Cfg9346, Cfg9346_Unlock);
968
969 /* Restore our idea of the MAC address. */
970 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
971 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
972
973 cp_start_hw(cp);
974 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
975
976 __cp_set_rx_mode(dev);
977 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
978
979 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
980 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
981 cpw8(Config3, PARMEnable);
982 cp->wol_enabled = 0;
983
984 cpw8(Config5, cpr8(Config5) & PMEStatus);
985
986 cpw32_f(HiTxRingAddr, 0);
987 cpw32_f(HiTxRingAddr + 4, 0);
988
989 ring_dma = cp->ring_dma;
990 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
991 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
992
993 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
994 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
995 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
996
997 cpw16(MultiIntr, 0);
998
999 cpw16_f(IntrMask, cp_intr_mask);
1000
1001 cpw8_f(Cfg9346, Cfg9346_Lock);
1002 }
1003
1004 static int cp_refill_rx(struct cp_private *cp)
1005 {
1006 struct net_device *dev = cp->dev;
1007 unsigned i;
1008
1009 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1010 struct sk_buff *skb;
1011 dma_addr_t mapping;
1012
1013 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1014 if (!skb)
1015 goto err_out;
1016
1017 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1018 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1019 cp->rx_skb[i] = skb;
1020
1021 cp->rx_ring[i].opts2 = 0;
1022 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1023 if (i == (CP_RX_RING_SIZE - 1))
1024 cp->rx_ring[i].opts1 =
1025 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1026 else
1027 cp->rx_ring[i].opts1 =
1028 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1029 }
1030
1031 return 0;
1032
1033 err_out:
1034 cp_clean_rings(cp);
1035 return -ENOMEM;
1036 }
1037
1038 static void cp_init_rings_index (struct cp_private *cp)
1039 {
1040 cp->rx_tail = 0;
1041 cp->tx_head = cp->tx_tail = 0;
1042 }
1043
1044 static int cp_init_rings (struct cp_private *cp)
1045 {
1046 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1047 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1048
1049 cp_init_rings_index(cp);
1050
1051 return cp_refill_rx (cp);
1052 }
1053
1054 static int cp_alloc_rings (struct cp_private *cp)
1055 {
1056 void *mem;
1057
1058 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1059 &cp->ring_dma, GFP_KERNEL);
1060 if (!mem)
1061 return -ENOMEM;
1062
1063 cp->rx_ring = mem;
1064 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1065
1066 return cp_init_rings(cp);
1067 }
1068
1069 static void cp_clean_rings (struct cp_private *cp)
1070 {
1071 struct cp_desc *desc;
1072 unsigned i;
1073
1074 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1075 if (cp->rx_skb[i]) {
1076 desc = cp->rx_ring + i;
1077 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1078 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1079 dev_kfree_skb(cp->rx_skb[i]);
1080 }
1081 }
1082
1083 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1084 if (cp->tx_skb[i]) {
1085 struct sk_buff *skb = cp->tx_skb[i];
1086
1087 desc = cp->tx_ring + i;
1088 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1089 le32_to_cpu(desc->opts1) & 0xffff,
1090 PCI_DMA_TODEVICE);
1091 if (le32_to_cpu(desc->opts1) & LastFrag)
1092 dev_kfree_skb(skb);
1093 cp->dev->stats.tx_dropped++;
1094 }
1095 }
1096
1097 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1098 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1099
1100 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1101 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1102 }
1103
1104 static void cp_free_rings (struct cp_private *cp)
1105 {
1106 cp_clean_rings(cp);
1107 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1108 cp->ring_dma);
1109 cp->rx_ring = NULL;
1110 cp->tx_ring = NULL;
1111 }
1112
1113 static int cp_open (struct net_device *dev)
1114 {
1115 struct cp_private *cp = netdev_priv(dev);
1116 int rc;
1117
1118 netif_dbg(cp, ifup, dev, "enabling interface\n");
1119
1120 rc = cp_alloc_rings(cp);
1121 if (rc)
1122 return rc;
1123
1124 napi_enable(&cp->napi);
1125
1126 cp_init_hw(cp);
1127
1128 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1129 if (rc)
1130 goto err_out_hw;
1131
1132 netif_carrier_off(dev);
1133 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1134 netif_start_queue(dev);
1135
1136 return 0;
1137
1138 err_out_hw:
1139 napi_disable(&cp->napi);
1140 cp_stop_hw(cp);
1141 cp_free_rings(cp);
1142 return rc;
1143 }
1144
1145 static int cp_close (struct net_device *dev)
1146 {
1147 struct cp_private *cp = netdev_priv(dev);
1148 unsigned long flags;
1149
1150 napi_disable(&cp->napi);
1151
1152 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1153
1154 spin_lock_irqsave(&cp->lock, flags);
1155
1156 netif_stop_queue(dev);
1157 netif_carrier_off(dev);
1158
1159 cp_stop_hw(cp);
1160
1161 spin_unlock_irqrestore(&cp->lock, flags);
1162
1163 free_irq(dev->irq, dev);
1164
1165 cp_free_rings(cp);
1166 return 0;
1167 }
1168
1169 static void cp_tx_timeout(struct net_device *dev)
1170 {
1171 struct cp_private *cp = netdev_priv(dev);
1172 unsigned long flags;
1173 int rc;
1174
1175 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1176 cpr8(Cmd), cpr16(CpCmd),
1177 cpr16(IntrStatus), cpr16(IntrMask));
1178
1179 spin_lock_irqsave(&cp->lock, flags);
1180
1181 cp_stop_hw(cp);
1182 cp_clean_rings(cp);
1183 rc = cp_init_rings(cp);
1184 cp_start_hw(cp);
1185
1186 netif_wake_queue(dev);
1187
1188 spin_unlock_irqrestore(&cp->lock, flags);
1189 }
1190
1191 #ifdef BROKEN
1192 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1193 {
1194 struct cp_private *cp = netdev_priv(dev);
1195 int rc;
1196 unsigned long flags;
1197
1198 /* check for invalid MTU, according to hardware limits */
1199 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1200 return -EINVAL;
1201
1202 /* if network interface not up, no need for complexity */
1203 if (!netif_running(dev)) {
1204 dev->mtu = new_mtu;
1205 cp_set_rxbufsize(cp); /* set new rx buf size */
1206 return 0;
1207 }
1208
1209 spin_lock_irqsave(&cp->lock, flags);
1210
1211 cp_stop_hw(cp); /* stop h/w and free rings */
1212 cp_clean_rings(cp);
1213
1214 dev->mtu = new_mtu;
1215 cp_set_rxbufsize(cp); /* set new rx buf size */
1216
1217 rc = cp_init_rings(cp); /* realloc and restart h/w */
1218 cp_start_hw(cp);
1219
1220 spin_unlock_irqrestore(&cp->lock, flags);
1221
1222 return rc;
1223 }
1224 #endif /* BROKEN */
1225
1226 static const char mii_2_8139_map[8] = {
1227 BasicModeCtrl,
1228 BasicModeStatus,
1229 0,
1230 0,
1231 NWayAdvert,
1232 NWayLPAR,
1233 NWayExpansion,
1234 0
1235 };
1236
1237 static int mdio_read(struct net_device *dev, int phy_id, int location)
1238 {
1239 struct cp_private *cp = netdev_priv(dev);
1240
1241 return location < 8 && mii_2_8139_map[location] ?
1242 readw(cp->regs + mii_2_8139_map[location]) : 0;
1243 }
1244
1245
1246 static void mdio_write(struct net_device *dev, int phy_id, int location,
1247 int value)
1248 {
1249 struct cp_private *cp = netdev_priv(dev);
1250
1251 if (location == 0) {
1252 cpw8(Cfg9346, Cfg9346_Unlock);
1253 cpw16(BasicModeCtrl, value);
1254 cpw8(Cfg9346, Cfg9346_Lock);
1255 } else if (location < 8 && mii_2_8139_map[location])
1256 cpw16(mii_2_8139_map[location], value);
1257 }
1258
1259 /* Set the ethtool Wake-on-LAN settings */
1260 static int netdev_set_wol (struct cp_private *cp,
1261 const struct ethtool_wolinfo *wol)
1262 {
1263 u8 options;
1264
1265 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1266 /* If WOL is being disabled, no need for complexity */
1267 if (wol->wolopts) {
1268 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1269 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1270 }
1271
1272 cpw8 (Cfg9346, Cfg9346_Unlock);
1273 cpw8 (Config3, options);
1274 cpw8 (Cfg9346, Cfg9346_Lock);
1275
1276 options = 0; /* Paranoia setting */
1277 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1278 /* If WOL is being disabled, no need for complexity */
1279 if (wol->wolopts) {
1280 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1281 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1282 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1283 }
1284
1285 cpw8 (Config5, options);
1286
1287 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1288
1289 return 0;
1290 }
1291
1292 /* Get the ethtool Wake-on-LAN settings */
1293 static void netdev_get_wol (struct cp_private *cp,
1294 struct ethtool_wolinfo *wol)
1295 {
1296 u8 options;
1297
1298 wol->wolopts = 0; /* Start from scratch */
1299 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1300 WAKE_MCAST | WAKE_UCAST;
1301 /* We don't need to go on if WOL is disabled */
1302 if (!cp->wol_enabled) return;
1303
1304 options = cpr8 (Config3);
1305 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1306 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1307
1308 options = 0; /* Paranoia setting */
1309 options = cpr8 (Config5);
1310 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1311 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1312 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1313 }
1314
1315 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1316 {
1317 struct cp_private *cp = netdev_priv(dev);
1318
1319 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1320 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1321 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1322 }
1323
1324 static void cp_get_ringparam(struct net_device *dev,
1325 struct ethtool_ringparam *ring)
1326 {
1327 ring->rx_max_pending = CP_RX_RING_SIZE;
1328 ring->tx_max_pending = CP_TX_RING_SIZE;
1329 ring->rx_pending = CP_RX_RING_SIZE;
1330 ring->tx_pending = CP_TX_RING_SIZE;
1331 }
1332
1333 static int cp_get_regs_len(struct net_device *dev)
1334 {
1335 return CP_REGS_SIZE;
1336 }
1337
1338 static int cp_get_sset_count (struct net_device *dev, int sset)
1339 {
1340 switch (sset) {
1341 case ETH_SS_STATS:
1342 return CP_NUM_STATS;
1343 default:
1344 return -EOPNOTSUPP;
1345 }
1346 }
1347
1348 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1349 {
1350 struct cp_private *cp = netdev_priv(dev);
1351 int rc;
1352 unsigned long flags;
1353
1354 spin_lock_irqsave(&cp->lock, flags);
1355 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1356 spin_unlock_irqrestore(&cp->lock, flags);
1357
1358 return rc;
1359 }
1360
1361 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1362 {
1363 struct cp_private *cp = netdev_priv(dev);
1364 int rc;
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&cp->lock, flags);
1368 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1369 spin_unlock_irqrestore(&cp->lock, flags);
1370
1371 return rc;
1372 }
1373
1374 static int cp_nway_reset(struct net_device *dev)
1375 {
1376 struct cp_private *cp = netdev_priv(dev);
1377 return mii_nway_restart(&cp->mii_if);
1378 }
1379
1380 static u32 cp_get_msglevel(struct net_device *dev)
1381 {
1382 struct cp_private *cp = netdev_priv(dev);
1383 return cp->msg_enable;
1384 }
1385
1386 static void cp_set_msglevel(struct net_device *dev, u32 value)
1387 {
1388 struct cp_private *cp = netdev_priv(dev);
1389 cp->msg_enable = value;
1390 }
1391
1392 static int cp_set_features(struct net_device *dev, netdev_features_t features)
1393 {
1394 struct cp_private *cp = netdev_priv(dev);
1395 unsigned long flags;
1396
1397 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1398 return 0;
1399
1400 spin_lock_irqsave(&cp->lock, flags);
1401
1402 if (features & NETIF_F_RXCSUM)
1403 cp->cpcmd |= RxChkSum;
1404 else
1405 cp->cpcmd &= ~RxChkSum;
1406
1407 if (features & NETIF_F_HW_VLAN_RX)
1408 cp->cpcmd |= RxVlanOn;
1409 else
1410 cp->cpcmd &= ~RxVlanOn;
1411
1412 cpw16_f(CpCmd, cp->cpcmd);
1413 spin_unlock_irqrestore(&cp->lock, flags);
1414
1415 return 0;
1416 }
1417
1418 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1419 void *p)
1420 {
1421 struct cp_private *cp = netdev_priv(dev);
1422 unsigned long flags;
1423
1424 if (regs->len < CP_REGS_SIZE)
1425 return /* -EINVAL */;
1426
1427 regs->version = CP_REGS_VER;
1428
1429 spin_lock_irqsave(&cp->lock, flags);
1430 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1431 spin_unlock_irqrestore(&cp->lock, flags);
1432 }
1433
1434 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1435 {
1436 struct cp_private *cp = netdev_priv(dev);
1437 unsigned long flags;
1438
1439 spin_lock_irqsave (&cp->lock, flags);
1440 netdev_get_wol (cp, wol);
1441 spin_unlock_irqrestore (&cp->lock, flags);
1442 }
1443
1444 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1445 {
1446 struct cp_private *cp = netdev_priv(dev);
1447 unsigned long flags;
1448 int rc;
1449
1450 spin_lock_irqsave (&cp->lock, flags);
1451 rc = netdev_set_wol (cp, wol);
1452 spin_unlock_irqrestore (&cp->lock, flags);
1453
1454 return rc;
1455 }
1456
1457 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1458 {
1459 switch (stringset) {
1460 case ETH_SS_STATS:
1461 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1462 break;
1463 default:
1464 BUG();
1465 break;
1466 }
1467 }
1468
1469 static void cp_get_ethtool_stats (struct net_device *dev,
1470 struct ethtool_stats *estats, u64 *tmp_stats)
1471 {
1472 struct cp_private *cp = netdev_priv(dev);
1473 struct cp_dma_stats *nic_stats;
1474 dma_addr_t dma;
1475 int i;
1476
1477 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1478 &dma, GFP_KERNEL);
1479 if (!nic_stats)
1480 return;
1481
1482 /* begin NIC statistics dump */
1483 cpw32(StatsAddr + 4, (u64)dma >> 32);
1484 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1485 cpr32(StatsAddr);
1486
1487 for (i = 0; i < 1000; i++) {
1488 if ((cpr32(StatsAddr) & DumpStats) == 0)
1489 break;
1490 udelay(10);
1491 }
1492 cpw32(StatsAddr, 0);
1493 cpw32(StatsAddr + 4, 0);
1494 cpr32(StatsAddr);
1495
1496 i = 0;
1497 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1498 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1499 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1500 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1501 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1502 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1503 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1504 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1505 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1506 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1507 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1508 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1509 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1510 tmp_stats[i++] = cp->cp_stats.rx_frags;
1511 BUG_ON(i != CP_NUM_STATS);
1512
1513 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1514 }
1515
1516 static const struct ethtool_ops cp_ethtool_ops = {
1517 .get_drvinfo = cp_get_drvinfo,
1518 .get_regs_len = cp_get_regs_len,
1519 .get_sset_count = cp_get_sset_count,
1520 .get_settings = cp_get_settings,
1521 .set_settings = cp_set_settings,
1522 .nway_reset = cp_nway_reset,
1523 .get_link = ethtool_op_get_link,
1524 .get_msglevel = cp_get_msglevel,
1525 .set_msglevel = cp_set_msglevel,
1526 .get_regs = cp_get_regs,
1527 .get_wol = cp_get_wol,
1528 .set_wol = cp_set_wol,
1529 .get_strings = cp_get_strings,
1530 .get_ethtool_stats = cp_get_ethtool_stats,
1531 .get_eeprom_len = cp_get_eeprom_len,
1532 .get_eeprom = cp_get_eeprom,
1533 .set_eeprom = cp_set_eeprom,
1534 .get_ringparam = cp_get_ringparam,
1535 };
1536
1537 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1538 {
1539 struct cp_private *cp = netdev_priv(dev);
1540 int rc;
1541 unsigned long flags;
1542
1543 if (!netif_running(dev))
1544 return -EINVAL;
1545
1546 spin_lock_irqsave(&cp->lock, flags);
1547 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1548 spin_unlock_irqrestore(&cp->lock, flags);
1549 return rc;
1550 }
1551
1552 static int cp_set_mac_address(struct net_device *dev, void *p)
1553 {
1554 struct cp_private *cp = netdev_priv(dev);
1555 struct sockaddr *addr = p;
1556
1557 if (!is_valid_ether_addr(addr->sa_data))
1558 return -EADDRNOTAVAIL;
1559
1560 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1561
1562 spin_lock_irq(&cp->lock);
1563
1564 cpw8_f(Cfg9346, Cfg9346_Unlock);
1565 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1566 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1567 cpw8_f(Cfg9346, Cfg9346_Lock);
1568
1569 spin_unlock_irq(&cp->lock);
1570
1571 return 0;
1572 }
1573
1574 /* Serial EEPROM section. */
1575
1576 /* EEPROM_Ctrl bits. */
1577 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1578 #define EE_CS 0x08 /* EEPROM chip select. */
1579 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1580 #define EE_WRITE_0 0x00
1581 #define EE_WRITE_1 0x02
1582 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1583 #define EE_ENB (0x80 | EE_CS)
1584
1585 /* Delay between EEPROM clock transitions.
1586 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1587 */
1588
1589 #define eeprom_delay() readb(ee_addr)
1590
1591 /* The EEPROM commands include the alway-set leading bit. */
1592 #define EE_EXTEND_CMD (4)
1593 #define EE_WRITE_CMD (5)
1594 #define EE_READ_CMD (6)
1595 #define EE_ERASE_CMD (7)
1596
1597 #define EE_EWDS_ADDR (0)
1598 #define EE_WRAL_ADDR (1)
1599 #define EE_ERAL_ADDR (2)
1600 #define EE_EWEN_ADDR (3)
1601
1602 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1603
1604 static void eeprom_cmd_start(void __iomem *ee_addr)
1605 {
1606 writeb (EE_ENB & ~EE_CS, ee_addr);
1607 writeb (EE_ENB, ee_addr);
1608 eeprom_delay ();
1609 }
1610
1611 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1612 {
1613 int i;
1614
1615 /* Shift the command bits out. */
1616 for (i = cmd_len - 1; i >= 0; i--) {
1617 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1618 writeb (EE_ENB | dataval, ee_addr);
1619 eeprom_delay ();
1620 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1621 eeprom_delay ();
1622 }
1623 writeb (EE_ENB, ee_addr);
1624 eeprom_delay ();
1625 }
1626
1627 static void eeprom_cmd_end(void __iomem *ee_addr)
1628 {
1629 writeb (~EE_CS, ee_addr);
1630 eeprom_delay ();
1631 }
1632
1633 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1634 int addr_len)
1635 {
1636 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1637
1638 eeprom_cmd_start(ee_addr);
1639 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1640 eeprom_cmd_end(ee_addr);
1641 }
1642
1643 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1644 {
1645 int i;
1646 u16 retval = 0;
1647 void __iomem *ee_addr = ioaddr + Cfg9346;
1648 int read_cmd = location | (EE_READ_CMD << addr_len);
1649
1650 eeprom_cmd_start(ee_addr);
1651 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1652
1653 for (i = 16; i > 0; i--) {
1654 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1655 eeprom_delay ();
1656 retval =
1657 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1658 0);
1659 writeb (EE_ENB, ee_addr);
1660 eeprom_delay ();
1661 }
1662
1663 eeprom_cmd_end(ee_addr);
1664
1665 return retval;
1666 }
1667
1668 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1669 int addr_len)
1670 {
1671 int i;
1672 void __iomem *ee_addr = ioaddr + Cfg9346;
1673 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1674
1675 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1676
1677 eeprom_cmd_start(ee_addr);
1678 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1679 eeprom_cmd(ee_addr, val, 16);
1680 eeprom_cmd_end(ee_addr);
1681
1682 eeprom_cmd_start(ee_addr);
1683 for (i = 0; i < 20000; i++)
1684 if (readb(ee_addr) & EE_DATA_READ)
1685 break;
1686 eeprom_cmd_end(ee_addr);
1687
1688 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1689 }
1690
1691 static int cp_get_eeprom_len(struct net_device *dev)
1692 {
1693 struct cp_private *cp = netdev_priv(dev);
1694 int size;
1695
1696 spin_lock_irq(&cp->lock);
1697 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1698 spin_unlock_irq(&cp->lock);
1699
1700 return size;
1701 }
1702
1703 static int cp_get_eeprom(struct net_device *dev,
1704 struct ethtool_eeprom *eeprom, u8 *data)
1705 {
1706 struct cp_private *cp = netdev_priv(dev);
1707 unsigned int addr_len;
1708 u16 val;
1709 u32 offset = eeprom->offset >> 1;
1710 u32 len = eeprom->len;
1711 u32 i = 0;
1712
1713 eeprom->magic = CP_EEPROM_MAGIC;
1714
1715 spin_lock_irq(&cp->lock);
1716
1717 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1718
1719 if (eeprom->offset & 1) {
1720 val = read_eeprom(cp->regs, offset, addr_len);
1721 data[i++] = (u8)(val >> 8);
1722 offset++;
1723 }
1724
1725 while (i < len - 1) {
1726 val = read_eeprom(cp->regs, offset, addr_len);
1727 data[i++] = (u8)val;
1728 data[i++] = (u8)(val >> 8);
1729 offset++;
1730 }
1731
1732 if (i < len) {
1733 val = read_eeprom(cp->regs, offset, addr_len);
1734 data[i] = (u8)val;
1735 }
1736
1737 spin_unlock_irq(&cp->lock);
1738 return 0;
1739 }
1740
1741 static int cp_set_eeprom(struct net_device *dev,
1742 struct ethtool_eeprom *eeprom, u8 *data)
1743 {
1744 struct cp_private *cp = netdev_priv(dev);
1745 unsigned int addr_len;
1746 u16 val;
1747 u32 offset = eeprom->offset >> 1;
1748 u32 len = eeprom->len;
1749 u32 i = 0;
1750
1751 if (eeprom->magic != CP_EEPROM_MAGIC)
1752 return -EINVAL;
1753
1754 spin_lock_irq(&cp->lock);
1755
1756 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1757
1758 if (eeprom->offset & 1) {
1759 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1760 val |= (u16)data[i++] << 8;
1761 write_eeprom(cp->regs, offset, val, addr_len);
1762 offset++;
1763 }
1764
1765 while (i < len - 1) {
1766 val = (u16)data[i++];
1767 val |= (u16)data[i++] << 8;
1768 write_eeprom(cp->regs, offset, val, addr_len);
1769 offset++;
1770 }
1771
1772 if (i < len) {
1773 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1774 val |= (u16)data[i];
1775 write_eeprom(cp->regs, offset, val, addr_len);
1776 }
1777
1778 spin_unlock_irq(&cp->lock);
1779 return 0;
1780 }
1781
1782 /* Put the board into D3cold state and wait for WakeUp signal */
1783 static void cp_set_d3_state (struct cp_private *cp)
1784 {
1785 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1786 pci_set_power_state (cp->pdev, PCI_D3hot);
1787 }
1788
1789 static const struct net_device_ops cp_netdev_ops = {
1790 .ndo_open = cp_open,
1791 .ndo_stop = cp_close,
1792 .ndo_validate_addr = eth_validate_addr,
1793 .ndo_set_mac_address = cp_set_mac_address,
1794 .ndo_set_rx_mode = cp_set_rx_mode,
1795 .ndo_get_stats = cp_get_stats,
1796 .ndo_do_ioctl = cp_ioctl,
1797 .ndo_start_xmit = cp_start_xmit,
1798 .ndo_tx_timeout = cp_tx_timeout,
1799 .ndo_set_features = cp_set_features,
1800 #ifdef BROKEN
1801 .ndo_change_mtu = cp_change_mtu,
1802 #endif
1803
1804 #ifdef CONFIG_NET_POLL_CONTROLLER
1805 .ndo_poll_controller = cp_poll_controller,
1806 #endif
1807 };
1808
1809 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1810 {
1811 struct net_device *dev;
1812 struct cp_private *cp;
1813 int rc;
1814 void __iomem *regs;
1815 resource_size_t pciaddr;
1816 unsigned int addr_len, i, pci_using_dac;
1817
1818 #ifndef MODULE
1819 static int version_printed;
1820 if (version_printed++ == 0)
1821 pr_info("%s", version);
1822 #endif
1823
1824 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1825 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1826 dev_info(&pdev->dev,
1827 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1828 pdev->vendor, pdev->device, pdev->revision);
1829 return -ENODEV;
1830 }
1831
1832 dev = alloc_etherdev(sizeof(struct cp_private));
1833 if (!dev)
1834 return -ENOMEM;
1835 SET_NETDEV_DEV(dev, &pdev->dev);
1836
1837 cp = netdev_priv(dev);
1838 cp->pdev = pdev;
1839 cp->dev = dev;
1840 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1841 spin_lock_init (&cp->lock);
1842 cp->mii_if.dev = dev;
1843 cp->mii_if.mdio_read = mdio_read;
1844 cp->mii_if.mdio_write = mdio_write;
1845 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1846 cp->mii_if.phy_id_mask = 0x1f;
1847 cp->mii_if.reg_num_mask = 0x1f;
1848 cp_set_rxbufsize(cp);
1849
1850 rc = pci_enable_device(pdev);
1851 if (rc)
1852 goto err_out_free;
1853
1854 rc = pci_set_mwi(pdev);
1855 if (rc)
1856 goto err_out_disable;
1857
1858 rc = pci_request_regions(pdev, DRV_NAME);
1859 if (rc)
1860 goto err_out_mwi;
1861
1862 pciaddr = pci_resource_start(pdev, 1);
1863 if (!pciaddr) {
1864 rc = -EIO;
1865 dev_err(&pdev->dev, "no MMIO resource\n");
1866 goto err_out_res;
1867 }
1868 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1869 rc = -EIO;
1870 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1871 (unsigned long long)pci_resource_len(pdev, 1));
1872 goto err_out_res;
1873 }
1874
1875 /* Configure DMA attributes. */
1876 if ((sizeof(dma_addr_t) > 4) &&
1877 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1878 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1879 pci_using_dac = 1;
1880 } else {
1881 pci_using_dac = 0;
1882
1883 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1884 if (rc) {
1885 dev_err(&pdev->dev,
1886 "No usable DMA configuration, aborting\n");
1887 goto err_out_res;
1888 }
1889 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1890 if (rc) {
1891 dev_err(&pdev->dev,
1892 "No usable consistent DMA configuration, aborting\n");
1893 goto err_out_res;
1894 }
1895 }
1896
1897 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1898 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1899
1900 dev->features |= NETIF_F_RXCSUM;
1901 dev->hw_features |= NETIF_F_RXCSUM;
1902
1903 regs = ioremap(pciaddr, CP_REGS_SIZE);
1904 if (!regs) {
1905 rc = -EIO;
1906 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1907 (unsigned long long)pci_resource_len(pdev, 1),
1908 (unsigned long long)pciaddr);
1909 goto err_out_res;
1910 }
1911 dev->base_addr = (unsigned long) regs;
1912 cp->regs = regs;
1913
1914 cp_stop_hw(cp);
1915
1916 /* read MAC address from EEPROM */
1917 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1918 for (i = 0; i < 3; i++)
1919 ((__le16 *) (dev->dev_addr))[i] =
1920 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1921 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1922
1923 dev->netdev_ops = &cp_netdev_ops;
1924 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1925 dev->ethtool_ops = &cp_ethtool_ops;
1926 dev->watchdog_timeo = TX_TIMEOUT;
1927
1928 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1929
1930 if (pci_using_dac)
1931 dev->features |= NETIF_F_HIGHDMA;
1932
1933 /* disabled by default until verified */
1934 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1935 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1936 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1937 NETIF_F_HIGHDMA;
1938
1939 dev->irq = pdev->irq;
1940
1941 rc = register_netdev(dev);
1942 if (rc)
1943 goto err_out_iomap;
1944
1945 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1946 dev->base_addr, dev->dev_addr, dev->irq);
1947
1948 pci_set_drvdata(pdev, dev);
1949
1950 /* enable busmastering and memory-write-invalidate */
1951 pci_set_master(pdev);
1952
1953 if (cp->wol_enabled)
1954 cp_set_d3_state (cp);
1955
1956 return 0;
1957
1958 err_out_iomap:
1959 iounmap(regs);
1960 err_out_res:
1961 pci_release_regions(pdev);
1962 err_out_mwi:
1963 pci_clear_mwi(pdev);
1964 err_out_disable:
1965 pci_disable_device(pdev);
1966 err_out_free:
1967 free_netdev(dev);
1968 return rc;
1969 }
1970
1971 static void cp_remove_one (struct pci_dev *pdev)
1972 {
1973 struct net_device *dev = pci_get_drvdata(pdev);
1974 struct cp_private *cp = netdev_priv(dev);
1975
1976 unregister_netdev(dev);
1977 iounmap(cp->regs);
1978 if (cp->wol_enabled)
1979 pci_set_power_state (pdev, PCI_D0);
1980 pci_release_regions(pdev);
1981 pci_clear_mwi(pdev);
1982 pci_disable_device(pdev);
1983 pci_set_drvdata(pdev, NULL);
1984 free_netdev(dev);
1985 }
1986
1987 #ifdef CONFIG_PM
1988 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1989 {
1990 struct net_device *dev = pci_get_drvdata(pdev);
1991 struct cp_private *cp = netdev_priv(dev);
1992 unsigned long flags;
1993
1994 if (!netif_running(dev))
1995 return 0;
1996
1997 netif_device_detach (dev);
1998 netif_stop_queue (dev);
1999
2000 spin_lock_irqsave (&cp->lock, flags);
2001
2002 /* Disable Rx and Tx */
2003 cpw16 (IntrMask, 0);
2004 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2005
2006 spin_unlock_irqrestore (&cp->lock, flags);
2007
2008 pci_save_state(pdev);
2009 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2010 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2011
2012 return 0;
2013 }
2014
2015 static int cp_resume (struct pci_dev *pdev)
2016 {
2017 struct net_device *dev = pci_get_drvdata (pdev);
2018 struct cp_private *cp = netdev_priv(dev);
2019 unsigned long flags;
2020
2021 if (!netif_running(dev))
2022 return 0;
2023
2024 netif_device_attach (dev);
2025
2026 pci_set_power_state(pdev, PCI_D0);
2027 pci_restore_state(pdev);
2028 pci_enable_wake(pdev, PCI_D0, 0);
2029
2030 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2031 cp_init_rings_index (cp);
2032 cp_init_hw (cp);
2033 netif_start_queue (dev);
2034
2035 spin_lock_irqsave (&cp->lock, flags);
2036
2037 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2038
2039 spin_unlock_irqrestore (&cp->lock, flags);
2040
2041 return 0;
2042 }
2043 #endif /* CONFIG_PM */
2044
2045 static struct pci_driver cp_driver = {
2046 .name = DRV_NAME,
2047 .id_table = cp_pci_tbl,
2048 .probe = cp_init_one,
2049 .remove = cp_remove_one,
2050 #ifdef CONFIG_PM
2051 .resume = cp_resume,
2052 .suspend = cp_suspend,
2053 #endif
2054 };
2055
2056 static int __init cp_init (void)
2057 {
2058 #ifdef MODULE
2059 pr_info("%s", version);
2060 #endif
2061 return pci_register_driver(&cp_driver);
2062 }
2063
2064 static void __exit cp_exit (void)
2065 {
2066 pci_unregister_driver (&cp_driver);
2067 }
2068
2069 module_init(cp_init);
2070 module_exit(cp_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree