arch/arm/mach-shmobile/smp-sh73a0.c

   1 /*
   2  * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2010  Takashi Yoshii
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/smp.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <mach/common.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/smp_twd.h>
  28 #include <asm/hardware/gic.h>
  29
  30 #define WUPCR           0xe6151010
  31 #define SRESCR          0xe6151018
  32 #define PSTR            0xe6151040
  33 #define SBAR            0xe6180020
  34 #define APARMBAREA      0xe6f10020
  35
  36 static void __iomem *scu_base_addr(void)
  37 {
  38         return (void __iomem *)0xf0000000;
  39 }
  40
  41 static DEFINE_SPINLOCK(scu_lock);
  42 static unsigned long tmp;
  43
  44 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
  45 {
  46         void __iomem *scu_base = scu_base_addr();
  47
  48         spin_lock(&scu_lock);
  49         tmp = __raw_readl(scu_base + 8);
  50         tmp &= ~clr;
  51         tmp |= set;
  52         spin_unlock(&scu_lock);
  53
  54         /* disable cache coherency after releasing the lock */
  55         __raw_writel(tmp, scu_base + 8);
  56 }
  57
  58 unsigned int __init sh73a0_get_core_count(void)
  59 {
  60         void __iomem *scu_base = scu_base_addr();
  61
  62 #ifdef CONFIG_HAVE_ARM_TWD
  63         /* twd_base needs to be initialized before percpu_timer_setup() */
  64         twd_base = (void __iomem *)0xf0000600;
  65 #endif
  66
  67         return scu_get_core_count(scu_base);
  68 }
  69
  70 void __cpuinit sh73a0_secondary_init(unsigned int cpu)
  71 {
  72         gic_secondary_init(0);
  73 }
  74
  75 int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
  76 {
  77         cpu = cpu_logical_map(cpu);
  78
  79         /* enable cache coherency */
  80         modify_scu_cpu_psr(0, 3 << (cpu * 8));
  81
  82         if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
  83                 __raw_writel(1 << cpu, __io(WUPCR));    /* wake up */
  84         else
  85                 __raw_writel(1 << cpu, __io(SRESCR));   /* reset */
  86
  87         return 0;
  88 }
  89
  90 void __init sh73a0_smp_prepare_cpus(void)
  91 {
  92         int cpu = cpu_logical_map(0);
  93
  94         scu_enable(scu_base_addr());
  95
  96         /* Map the reset vector (in headsmp.S) */
  97         __raw_writel(0, __io(APARMBAREA));      /* 4k */
  98         __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
  99
 100         /* enable cache coherency on CPU0 */
 101         modify_scu_cpu_psr(0, 3 << (cpu * 8));
 102 }