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usb: musb: pass platform_ops via platform_data
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / watchdog / iTCO_wdt.c
blobf7e90fe47b71fb823620ed06496370cfcf6b3c30
1 /*
2 * intel TCO Watchdog Driver
3 *
4 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 313056-003, 313057-017: 82801H (ICH8)
30 * document number 316972-004, 316973-012: 82801I (ICH9)
31 * document number 319973-002, 319974-002: 82801J (ICH10)
32 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
33 * document number 320066-003, 320257-008: EP80597 (IICH)
34 * document number TBD : Cougar Point (CPT)
35 */
36
37 /*
38 * Includes, defines, variables, module parameters, ...
39 */
40
41 /* Module and version information */
42 #define DRV_NAME "iTCO_wdt"
43 #define DRV_VERSION "1.06"
44 #define PFX DRV_NAME ": "
45
46 /* Includes */
47 #include <linux/module.h> /* For module specific items */
48 #include <linux/moduleparam.h> /* For new moduleparam's */
49 #include <linux/types.h> /* For standard types (like size_t) */
50 #include <linux/errno.h> /* For the -ENODEV/... values */
51 #include <linux/kernel.h> /* For printk/panic/... */
52 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
53 (WATCHDOG_MINOR) */
54 #include <linux/watchdog.h> /* For the watchdog specific items */
55 #include <linux/init.h> /* For __init/__exit/... */
56 #include <linux/fs.h> /* For file operations */
57 #include <linux/platform_device.h> /* For platform_driver framework */
58 #include <linux/pci.h> /* For pci functions */
59 #include <linux/ioport.h> /* For io-port access */
60 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
61 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
62 #include <linux/io.h> /* For inb/outb/... */
63
64 #include "iTCO_vendor.h"
65
66 /* TCO related info */
67 enum iTCO_chipsets {
68 TCO_ICH = 0, /* ICH */
69 TCO_ICH0, /* ICH0 */
70 TCO_ICH2, /* ICH2 */
71 TCO_ICH2M, /* ICH2-M */
72 TCO_ICH3, /* ICH3-S */
73 TCO_ICH3M, /* ICH3-M */
74 TCO_ICH4, /* ICH4 */
75 TCO_ICH4M, /* ICH4-M */
76 TCO_CICH, /* C-ICH */
77 TCO_ICH5, /* ICH5 & ICH5R */
78 TCO_6300ESB, /* 6300ESB */
79 TCO_ICH6, /* ICH6 & ICH6R */
80 TCO_ICH6M, /* ICH6-M */
81 TCO_ICH6W, /* ICH6W & ICH6RW */
82 TCO_631XESB, /* 631xESB/632xESB */
83 TCO_ICH7, /* ICH7 & ICH7R */
84 TCO_ICH7DH, /* ICH7DH */
85 TCO_ICH7M, /* ICH7-M & ICH7-U */
86 TCO_ICH7MDH, /* ICH7-M DH */
87 TCO_ICH8, /* ICH8 & ICH8R */
88 TCO_ICH8DH, /* ICH8DH */
89 TCO_ICH8DO, /* ICH8DO */
90 TCO_ICH8M, /* ICH8M */
91 TCO_ICH8ME, /* ICH8M-E */
92 TCO_ICH9, /* ICH9 */
93 TCO_ICH9R, /* ICH9R */
94 TCO_ICH9DH, /* ICH9DH */
95 TCO_ICH9DO, /* ICH9DO */
96 TCO_ICH9M, /* ICH9M */
97 TCO_ICH9ME, /* ICH9M-E */
98 TCO_ICH10, /* ICH10 */
99 TCO_ICH10R, /* ICH10R */
100 TCO_ICH10D, /* ICH10D */
101 TCO_ICH10DO, /* ICH10DO */
102 TCO_PCH, /* PCH Desktop Full Featured */
103 TCO_PCHM, /* PCH Mobile Full Featured */
104 TCO_P55, /* P55 */
105 TCO_PM55, /* PM55 */
106 TCO_H55, /* H55 */
107 TCO_QM57, /* QM57 */
108 TCO_H57, /* H57 */
109 TCO_HM55, /* HM55 */
110 TCO_Q57, /* Q57 */
111 TCO_HM57, /* HM57 */
112 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */
113 TCO_QS57, /* QS57 */
114 TCO_3400, /* 3400 */
115 TCO_3420, /* 3420 */
116 TCO_3450, /* 3450 */
117 TCO_EP80579, /* EP80579 */
118 TCO_CPT1, /* Cougar Point */
119 TCO_CPT2, /* Cougar Point Desktop */
120 TCO_CPT3, /* Cougar Point Mobile */
121 TCO_CPT4, /* Cougar Point */
122 TCO_CPT5, /* Cougar Point */
123 TCO_CPT6, /* Cougar Point */
124 TCO_CPT7, /* Cougar Point */
125 TCO_CPT8, /* Cougar Point */
126 TCO_CPT9, /* Cougar Point */
127 TCO_CPT10, /* Cougar Point */
128 TCO_CPT11, /* Cougar Point */
129 TCO_CPT12, /* Cougar Point */
130 TCO_CPT13, /* Cougar Point */
131 TCO_CPT14, /* Cougar Point */
132 TCO_CPT15, /* Cougar Point */
133 TCO_CPT16, /* Cougar Point */
134 TCO_CPT17, /* Cougar Point */
135 TCO_CPT18, /* Cougar Point */
136 TCO_CPT19, /* Cougar Point */
137 TCO_CPT20, /* Cougar Point */
138 TCO_CPT21, /* Cougar Point */
139 TCO_CPT22, /* Cougar Point */
140 TCO_CPT23, /* Cougar Point */
141 TCO_CPT24, /* Cougar Point */
142 TCO_CPT25, /* Cougar Point */
143 TCO_CPT26, /* Cougar Point */
144 TCO_CPT27, /* Cougar Point */
145 TCO_CPT28, /* Cougar Point */
146 TCO_CPT29, /* Cougar Point */
147 TCO_CPT30, /* Cougar Point */
148 TCO_CPT31, /* Cougar Point */
149 TCO_PBG, /* Patsburg */
150 };
151
152 static struct {
153 char *name;
154 unsigned int iTCO_version;
155 } iTCO_chipset_info[] __devinitdata = {
156 {"ICH", 1},
157 {"ICH0", 1},
158 {"ICH2", 1},
159 {"ICH2-M", 1},
160 {"ICH3-S", 1},
161 {"ICH3-M", 1},
162 {"ICH4", 1},
163 {"ICH4-M", 1},
164 {"C-ICH", 1},
165 {"ICH5 or ICH5R", 1},
166 {"6300ESB", 1},
167 {"ICH6 or ICH6R", 2},
168 {"ICH6-M", 2},
169 {"ICH6W or ICH6RW", 2},
170 {"631xESB/632xESB", 2},
171 {"ICH7 or ICH7R", 2},
172 {"ICH7DH", 2},
173 {"ICH7-M or ICH7-U", 2},
174 {"ICH7-M DH", 2},
175 {"ICH8 or ICH8R", 2},
176 {"ICH8DH", 2},
177 {"ICH8DO", 2},
178 {"ICH8M", 2},
179 {"ICH8M-E", 2},
180 {"ICH9", 2},
181 {"ICH9R", 2},
182 {"ICH9DH", 2},
183 {"ICH9DO", 2},
184 {"ICH9M", 2},
185 {"ICH9M-E", 2},
186 {"ICH10", 2},
187 {"ICH10R", 2},
188 {"ICH10D", 2},
189 {"ICH10DO", 2},
190 {"PCH Desktop Full Featured", 2},
191 {"PCH Mobile Full Featured", 2},
192 {"P55", 2},
193 {"PM55", 2},
194 {"H55", 2},
195 {"QM57", 2},
196 {"H57", 2},
197 {"HM55", 2},
198 {"Q57", 2},
199 {"HM57", 2},
200 {"PCH Mobile SFF Full Featured", 2},
201 {"QS57", 2},
202 {"3400", 2},
203 {"3420", 2},
204 {"3450", 2},
205 {"EP80579", 2},
206 {"Cougar Point", 2},
207 {"Cougar Point", 2},
208 {"Cougar Point", 2},
209 {"Cougar Point", 2},
210 {"Cougar Point", 2},
211 {"Cougar Point", 2},
212 {"Cougar Point", 2},
213 {"Cougar Point", 2},
214 {"Cougar Point", 2},
215 {"Cougar Point", 2},
216 {"Cougar Point", 2},
217 {"Cougar Point", 2},
218 {"Cougar Point", 2},
219 {"Cougar Point", 2},
220 {"Cougar Point", 2},
221 {"Cougar Point", 2},
222 {"Cougar Point", 2},
223 {"Cougar Point", 2},
224 {"Cougar Point", 2},
225 {"Cougar Point", 2},
226 {"Cougar Point", 2},
227 {"Cougar Point", 2},
228 {"Cougar Point", 2},
229 {"Cougar Point", 2},
230 {"Cougar Point", 2},
231 {"Cougar Point", 2},
232 {"Cougar Point", 2},
233 {"Cougar Point", 2},
234 {"Cougar Point", 2},
235 {"Cougar Point", 2},
236 {"Cougar Point", 2},
237 {"Patsburg", 2},
238 {NULL, 0}
239 };
240
241 #define ITCO_PCI_DEVICE(dev, data) \
242 .vendor = PCI_VENDOR_ID_INTEL, \
243 .device = dev, \
244 .subvendor = PCI_ANY_ID, \
245 .subdevice = PCI_ANY_ID, \
246 .class = 0, \
247 .class_mask = 0, \
248 .driver_data = data
249
250 /*
251 * This data only exists for exporting the supported PCI ids
252 * via MODULE_DEVICE_TABLE. We do not actually register a
253 * pci_driver, because the I/O Controller Hub has also other
254 * functions that probably will be registered by other drivers.
255 */
256 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
257 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)},
258 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)},
259 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)},
260 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)},
261 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)},
262 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)},
263 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)},
264 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)},
265 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)},
266 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)},
267 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
268 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)},
269 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)},
270 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)},
271 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
272 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
273 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
274 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
275 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
276 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
277 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
278 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
279 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
280 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
281 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
282 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
283 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
284 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
285 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
286 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
287 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)},
288 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30, TCO_ICH7DH)},
289 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)},
290 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
291 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)},
292 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)},
293 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)},
294 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)},
295 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)},
296 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)},
297 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)},
298 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)},
299 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)},
300 { ITCO_PCI_DEVICE(0x2919, TCO_ICH9M)},
301 { ITCO_PCI_DEVICE(0x2917, TCO_ICH9ME)},
302 { ITCO_PCI_DEVICE(0x3a18, TCO_ICH10)},
303 { ITCO_PCI_DEVICE(0x3a16, TCO_ICH10R)},
304 { ITCO_PCI_DEVICE(0x3a1a, TCO_ICH10D)},
305 { ITCO_PCI_DEVICE(0x3a14, TCO_ICH10DO)},
306 { ITCO_PCI_DEVICE(0x3b00, TCO_PCH)},
307 { ITCO_PCI_DEVICE(0x3b01, TCO_PCHM)},
308 { ITCO_PCI_DEVICE(0x3b02, TCO_P55)},
309 { ITCO_PCI_DEVICE(0x3b03, TCO_PM55)},
310 { ITCO_PCI_DEVICE(0x3b06, TCO_H55)},
311 { ITCO_PCI_DEVICE(0x3b07, TCO_QM57)},
312 { ITCO_PCI_DEVICE(0x3b08, TCO_H57)},
313 { ITCO_PCI_DEVICE(0x3b09, TCO_HM55)},
314 { ITCO_PCI_DEVICE(0x3b0a, TCO_Q57)},
315 { ITCO_PCI_DEVICE(0x3b0b, TCO_HM57)},
316 { ITCO_PCI_DEVICE(0x3b0d, TCO_PCHMSFF)},
317 { ITCO_PCI_DEVICE(0x3b0f, TCO_QS57)},
318 { ITCO_PCI_DEVICE(0x3b12, TCO_3400)},
319 { ITCO_PCI_DEVICE(0x3b14, TCO_3420)},
320 { ITCO_PCI_DEVICE(0x3b16, TCO_3450)},
321 { ITCO_PCI_DEVICE(0x5031, TCO_EP80579)},
322 { ITCO_PCI_DEVICE(0x1c41, TCO_CPT1)},
323 { ITCO_PCI_DEVICE(0x1c42, TCO_CPT2)},
324 { ITCO_PCI_DEVICE(0x1c43, TCO_CPT3)},
325 { ITCO_PCI_DEVICE(0x1c44, TCO_CPT4)},
326 { ITCO_PCI_DEVICE(0x1c45, TCO_CPT5)},
327 { ITCO_PCI_DEVICE(0x1c46, TCO_CPT6)},
328 { ITCO_PCI_DEVICE(0x1c47, TCO_CPT7)},
329 { ITCO_PCI_DEVICE(0x1c48, TCO_CPT8)},
330 { ITCO_PCI_DEVICE(0x1c49, TCO_CPT9)},
331 { ITCO_PCI_DEVICE(0x1c4a, TCO_CPT10)},
332 { ITCO_PCI_DEVICE(0x1c4b, TCO_CPT11)},
333 { ITCO_PCI_DEVICE(0x1c4c, TCO_CPT12)},
334 { ITCO_PCI_DEVICE(0x1c4d, TCO_CPT13)},
335 { ITCO_PCI_DEVICE(0x1c4e, TCO_CPT14)},
336 { ITCO_PCI_DEVICE(0x1c4f, TCO_CPT15)},
337 { ITCO_PCI_DEVICE(0x1c50, TCO_CPT16)},
338 { ITCO_PCI_DEVICE(0x1c51, TCO_CPT17)},
339 { ITCO_PCI_DEVICE(0x1c52, TCO_CPT18)},
340 { ITCO_PCI_DEVICE(0x1c53, TCO_CPT19)},
341 { ITCO_PCI_DEVICE(0x1c54, TCO_CPT20)},
342 { ITCO_PCI_DEVICE(0x1c55, TCO_CPT21)},
343 { ITCO_PCI_DEVICE(0x1c56, TCO_CPT22)},
344 { ITCO_PCI_DEVICE(0x1c57, TCO_CPT23)},
345 { ITCO_PCI_DEVICE(0x1c58, TCO_CPT24)},
346 { ITCO_PCI_DEVICE(0x1c59, TCO_CPT25)},
347 { ITCO_PCI_DEVICE(0x1c5a, TCO_CPT26)},
348 { ITCO_PCI_DEVICE(0x1c5b, TCO_CPT27)},
349 { ITCO_PCI_DEVICE(0x1c5c, TCO_CPT28)},
350 { ITCO_PCI_DEVICE(0x1c5d, TCO_CPT29)},
351 { ITCO_PCI_DEVICE(0x1c5e, TCO_CPT30)},
352 { ITCO_PCI_DEVICE(0x1c5f, TCO_CPT31)},
353 { ITCO_PCI_DEVICE(0x1d40, TCO_PBG)},
354 { 0, }, /* End of list */
355 };
356 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
357
358 /* Address definitions for the TCO */
359 /* TCO base address */
360 #define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
361 /* SMI Control and Enable Register */
362 #define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
363
364 #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
365 #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
366 #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
367 #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
368 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
369 #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
370 #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
371 #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
372 #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
373
374 /* internal variables */
375 static unsigned long is_active;
376 static char expect_release;
377 static struct { /* this is private data for the iTCO_wdt device */
378 /* TCO version/generation */
379 unsigned int iTCO_version;
380 /* The device's ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
381 unsigned long ACPIBASE;
382 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
383 unsigned long __iomem *gcs;
384 /* the lock for io operations */
385 spinlock_t io_lock;
386 /* the PCI-device */
387 struct pci_dev *pdev;
388 } iTCO_wdt_private;
389
390 /* the watchdog platform device */
391 static struct platform_device *iTCO_wdt_platform_device;
392
393 /* module parameters */
394 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
395 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
396 module_param(heartbeat, int, 0);
397 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
398 "5..76 (TCO v1) or 3..614 (TCO v2), default="
399 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
400
401 static int nowayout = WATCHDOG_NOWAYOUT;
402 module_param(nowayout, int, 0);
403 MODULE_PARM_DESC(nowayout,
404 "Watchdog cannot be stopped once started (default="
405 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
406
407 /*
408 * Some TCO specific functions
409 */
410
411 static inline unsigned int seconds_to_ticks(int seconds)
412 {
413 /* the internal timer is stored as ticks which decrement
414 * every 0.6 seconds */
415 return (seconds * 10) / 6;
416 }
417
418 static void iTCO_wdt_set_NO_REBOOT_bit(void)
419 {
420 u32 val32;
421
422 /* Set the NO_REBOOT bit: this disables reboots */
423 if (iTCO_wdt_private.iTCO_version == 2) {
424 val32 = readl(iTCO_wdt_private.gcs);
425 val32 |= 0x00000020;
426 writel(val32, iTCO_wdt_private.gcs);
427 } else if (iTCO_wdt_private.iTCO_version == 1) {
428 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
429 val32 |= 0x00000002;
430 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
431 }
432 }
433
434 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
435 {
436 int ret = 0;
437 u32 val32;
438
439 /* Unset the NO_REBOOT bit: this enables reboots */
440 if (iTCO_wdt_private.iTCO_version == 2) {
441 val32 = readl(iTCO_wdt_private.gcs);
442 val32 &= 0xffffffdf;
443 writel(val32, iTCO_wdt_private.gcs);
444
445 val32 = readl(iTCO_wdt_private.gcs);
446 if (val32 & 0x00000020)
447 ret = -EIO;
448 } else if (iTCO_wdt_private.iTCO_version == 1) {
449 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
450 val32 &= 0xfffffffd;
451 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
452
453 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
454 if (val32 & 0x00000002)
455 ret = -EIO;
456 }
457
458 return ret; /* returns: 0 = OK, -EIO = Error */
459 }
460
461 static int iTCO_wdt_start(void)
462 {
463 unsigned int val;
464
465 spin_lock(&iTCO_wdt_private.io_lock);
466
467 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
468
469 /* disable chipset's NO_REBOOT bit */
470 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
471 spin_unlock(&iTCO_wdt_private.io_lock);
472 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
473 "reboot disabled by hardware/BIOS\n");
474 return -EIO;
475 }
476
477 /* Force the timer to its reload value by writing to the TCO_RLD
478 register */
479 if (iTCO_wdt_private.iTCO_version == 2)
480 outw(0x01, TCO_RLD);
481 else if (iTCO_wdt_private.iTCO_version == 1)
482 outb(0x01, TCO_RLD);
483
484 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
485 val = inw(TCO1_CNT);
486 val &= 0xf7ff;
487 outw(val, TCO1_CNT);
488 val = inw(TCO1_CNT);
489 spin_unlock(&iTCO_wdt_private.io_lock);
490
491 if (val & 0x0800)
492 return -1;
493 return 0;
494 }
495
496 static int iTCO_wdt_stop(void)
497 {
498 unsigned int val;
499
500 spin_lock(&iTCO_wdt_private.io_lock);
501
502 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
503
504 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
505 val = inw(TCO1_CNT);
506 val |= 0x0800;
507 outw(val, TCO1_CNT);
508 val = inw(TCO1_CNT);
509
510 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
511 iTCO_wdt_set_NO_REBOOT_bit();
512
513 spin_unlock(&iTCO_wdt_private.io_lock);
514
515 if ((val & 0x0800) == 0)
516 return -1;
517 return 0;
518 }
519
520 static int iTCO_wdt_keepalive(void)
521 {
522 spin_lock(&iTCO_wdt_private.io_lock);
523
524 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
525
526 /* Reload the timer by writing to the TCO Timer Counter register */
527 if (iTCO_wdt_private.iTCO_version == 2)
528 outw(0x01, TCO_RLD);
529 else if (iTCO_wdt_private.iTCO_version == 1) {
530 /* Reset the timeout status bit so that the timer
531 * needs to count down twice again before rebooting */
532 outw(0x0008, TCO1_STS); /* write 1 to clear bit */
533
534 outb(0x01, TCO_RLD);
535 }
536
537 spin_unlock(&iTCO_wdt_private.io_lock);
538 return 0;
539 }
540
541 static int iTCO_wdt_set_heartbeat(int t)
542 {
543 unsigned int val16;
544 unsigned char val8;
545 unsigned int tmrval;
546
547 tmrval = seconds_to_ticks(t);
548
549 /* For TCO v1 the timer counts down twice before rebooting */
550 if (iTCO_wdt_private.iTCO_version == 1)
551 tmrval /= 2;
552
553 /* from the specs: */
554 /* "Values of 0h-3h are ignored and should not be attempted" */
555 if (tmrval < 0x04)
556 return -EINVAL;
557 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
558 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
559 return -EINVAL;
560
561 iTCO_vendor_pre_set_heartbeat(tmrval);
562
563 /* Write new heartbeat to watchdog */
564 if (iTCO_wdt_private.iTCO_version == 2) {
565 spin_lock(&iTCO_wdt_private.io_lock);
566 val16 = inw(TCOv2_TMR);
567 val16 &= 0xfc00;
568 val16 |= tmrval;
569 outw(val16, TCOv2_TMR);
570 val16 = inw(TCOv2_TMR);
571 spin_unlock(&iTCO_wdt_private.io_lock);
572
573 if ((val16 & 0x3ff) != tmrval)
574 return -EINVAL;
575 } else if (iTCO_wdt_private.iTCO_version == 1) {
576 spin_lock(&iTCO_wdt_private.io_lock);
577 val8 = inb(TCOv1_TMR);
578 val8 &= 0xc0;
579 val8 |= (tmrval & 0xff);
580 outb(val8, TCOv1_TMR);
581 val8 = inb(TCOv1_TMR);
582 spin_unlock(&iTCO_wdt_private.io_lock);
583
584 if ((val8 & 0x3f) != tmrval)
585 return -EINVAL;
586 }
587
588 heartbeat = t;
589 return 0;
590 }
591
592 static int iTCO_wdt_get_timeleft(int *time_left)
593 {
594 unsigned int val16;
595 unsigned char val8;
596
597 /* read the TCO Timer */
598 if (iTCO_wdt_private.iTCO_version == 2) {
599 spin_lock(&iTCO_wdt_private.io_lock);
600 val16 = inw(TCO_RLD);
601 val16 &= 0x3ff;
602 spin_unlock(&iTCO_wdt_private.io_lock);
603
604 *time_left = (val16 * 6) / 10;
605 } else if (iTCO_wdt_private.iTCO_version == 1) {
606 spin_lock(&iTCO_wdt_private.io_lock);
607 val8 = inb(TCO_RLD);
608 val8 &= 0x3f;
609 if (!(inw(TCO1_STS) & 0x0008))
610 val8 += (inb(TCOv1_TMR) & 0x3f);
611 spin_unlock(&iTCO_wdt_private.io_lock);
612
613 *time_left = (val8 * 6) / 10;
614 } else
615 return -EINVAL;
616 return 0;
617 }
618
619 /*
620 * /dev/watchdog handling
621 */
622
623 static int iTCO_wdt_open(struct inode *inode, struct file *file)
624 {
625 /* /dev/watchdog can only be opened once */
626 if (test_and_set_bit(0, &is_active))
627 return -EBUSY;
628
629 /*
630 * Reload and activate timer
631 */
632 iTCO_wdt_start();
633 return nonseekable_open(inode, file);
634 }
635
636 static int iTCO_wdt_release(struct inode *inode, struct file *file)
637 {
638 /*
639 * Shut off the timer.
640 */
641 if (expect_release == 42) {
642 iTCO_wdt_stop();
643 } else {
644 printk(KERN_CRIT PFX
645 "Unexpected close, not stopping watchdog!\n");
646 iTCO_wdt_keepalive();
647 }
648 clear_bit(0, &is_active);
649 expect_release = 0;
650 return 0;
651 }
652
653 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
654 size_t len, loff_t *ppos)
655 {
656 /* See if we got the magic character 'V' and reload the timer */
657 if (len) {
658 if (!nowayout) {
659 size_t i;
660
661 /* note: just in case someone wrote the magic
662 character five months ago... */
663 expect_release = 0;
664
665 /* scan to see whether or not we got the
666 magic character */
667 for (i = 0; i != len; i++) {
668 char c;
669 if (get_user(c, data + i))
670 return -EFAULT;
671 if (c == 'V')
672 expect_release = 42;
673 }
674 }
675
676 /* someone wrote to us, we should reload the timer */
677 iTCO_wdt_keepalive();
678 }
679 return len;
680 }
681
682 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
683 unsigned long arg)
684 {
685 int new_options, retval = -EINVAL;
686 int new_heartbeat;
687 void __user *argp = (void __user *)arg;
688 int __user *p = argp;
689 static const struct watchdog_info ident = {
690 .options = WDIOF_SETTIMEOUT |
691 WDIOF_KEEPALIVEPING |
692 WDIOF_MAGICCLOSE,
693 .firmware_version = 0,
694 .identity = DRV_NAME,
695 };
696
697 switch (cmd) {
698 case WDIOC_GETSUPPORT:
699 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
700 case WDIOC_GETSTATUS:
701 case WDIOC_GETBOOTSTATUS:
702 return put_user(0, p);
703
704 case WDIOC_SETOPTIONS:
705 {
706 if (get_user(new_options, p))
707 return -EFAULT;
708
709 if (new_options & WDIOS_DISABLECARD) {
710 iTCO_wdt_stop();
711 retval = 0;
712 }
713 if (new_options & WDIOS_ENABLECARD) {
714 iTCO_wdt_keepalive();
715 iTCO_wdt_start();
716 retval = 0;
717 }
718 return retval;
719 }
720 case WDIOC_KEEPALIVE:
721 iTCO_wdt_keepalive();
722 return 0;
723
724 case WDIOC_SETTIMEOUT:
725 {
726 if (get_user(new_heartbeat, p))
727 return -EFAULT;
728 if (iTCO_wdt_set_heartbeat(new_heartbeat))
729 return -EINVAL;
730 iTCO_wdt_keepalive();
731 /* Fall */
732 }
733 case WDIOC_GETTIMEOUT:
734 return put_user(heartbeat, p);
735 case WDIOC_GETTIMELEFT:
736 {
737 int time_left;
738 if (iTCO_wdt_get_timeleft(&time_left))
739 return -EINVAL;
740 return put_user(time_left, p);
741 }
742 default:
743 return -ENOTTY;
744 }
745 }
746
747 /*
748 * Kernel Interfaces
749 */
750
751 static const struct file_operations iTCO_wdt_fops = {
752 .owner = THIS_MODULE,
753 .llseek = no_llseek,
754 .write = iTCO_wdt_write,
755 .unlocked_ioctl = iTCO_wdt_ioctl,
756 .open = iTCO_wdt_open,
757 .release = iTCO_wdt_release,
758 };
759
760 static struct miscdevice iTCO_wdt_miscdev = {
761 .minor = WATCHDOG_MINOR,
762 .name = "watchdog",
763 .fops = &iTCO_wdt_fops,
764 };
765
766 /*
767 * Init & exit routines
768 */
769
770 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
771 const struct pci_device_id *ent, struct platform_device *dev)
772 {
773 int ret;
774 u32 base_address;
775 unsigned long RCBA;
776 unsigned long val32;
777
778 /*
779 * Find the ACPI/PM base I/O address which is the base
780 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
781 * ACPIBASE is bits [15:7] from 0x40-0x43
782 */
783 pci_read_config_dword(pdev, 0x40, &base_address);
784 base_address &= 0x0000ff80;
785 if (base_address == 0x00000000) {
786 /* Something's wrong here, ACPIBASE has to be set */
787 printk(KERN_ERR PFX "failed to get TCOBASE address, "
788 "device disabled by hardware/BIOS\n");
789 return -ENODEV;
790 }
791 iTCO_wdt_private.iTCO_version =
792 iTCO_chipset_info[ent->driver_data].iTCO_version;
793 iTCO_wdt_private.ACPIBASE = base_address;
794 iTCO_wdt_private.pdev = pdev;
795
796 /* Get the Memory-Mapped GCS register, we need it for the
797 NO_REBOOT flag (TCO v2). To get access to it you have to
798 read RCBA from PCI Config space 0xf0 and use it as base.
799 GCS = RCBA + ICH6_GCS(0x3410). */
800 if (iTCO_wdt_private.iTCO_version == 2) {
801 pci_read_config_dword(pdev, 0xf0, &base_address);
802 if ((base_address & 1) == 0) {
803 printk(KERN_ERR PFX "RCBA is disabled by hardware"
804 "/BIOS, device disabled\n");
805 ret = -ENODEV;
806 goto out;
807 }
808 RCBA = base_address & 0xffffc000;
809 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
810 }
811
812 /* Check chipset's NO_REBOOT bit */
813 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
814 printk(KERN_INFO PFX "unable to reset NO_REBOOT flag, "
815 "device disabled by hardware/BIOS\n");
816 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
817 goto out_unmap;
818 }
819
820 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
821 iTCO_wdt_set_NO_REBOOT_bit();
822
823 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
824 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
825 printk(KERN_ERR PFX
826 "I/O address 0x%04lx already in use, "
827 "device disabled\n", SMI_EN);
828 ret = -EIO;
829 goto out_unmap;
830 }
831 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
832 val32 = inl(SMI_EN);
833 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
834 outl(val32, SMI_EN);
835
836 /* The TCO I/O registers reside in a 32-byte range pointed to
837 by the TCOBASE value */
838 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
839 printk(KERN_ERR PFX "I/O address 0x%04lx already in use "
840 "device disabled\n", TCOBASE);
841 ret = -EIO;
842 goto unreg_smi_en;
843 }
844
845 printk(KERN_INFO PFX
846 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
847 iTCO_chipset_info[ent->driver_data].name,
848 iTCO_chipset_info[ent->driver_data].iTCO_version,
849 TCOBASE);
850
851 /* Clear out the (probably old) status */
852 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
853 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
854 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
855
856 /* Make sure the watchdog is not running */
857 iTCO_wdt_stop();
858
859 /* Check that the heartbeat value is within it's range;
860 if not reset to the default */
861 if (iTCO_wdt_set_heartbeat(heartbeat)) {
862 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
863 printk(KERN_INFO PFX
864 "timeout value out of range, using %d\n", heartbeat);
865 }
866
867 ret = misc_register(&iTCO_wdt_miscdev);
868 if (ret != 0) {
869 printk(KERN_ERR PFX
870 "cannot register miscdev on minor=%d (err=%d)\n",
871 WATCHDOG_MINOR, ret);
872 goto unreg_region;
873 }
874
875 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
876 heartbeat, nowayout);
877
878 return 0;
879
880 unreg_region:
881 release_region(TCOBASE, 0x20);
882 unreg_smi_en:
883 release_region(SMI_EN, 4);
884 out_unmap:
885 if (iTCO_wdt_private.iTCO_version == 2)
886 iounmap(iTCO_wdt_private.gcs);
887 out:
888 iTCO_wdt_private.ACPIBASE = 0;
889 return ret;
890 }
891
892 static void __devexit iTCO_wdt_cleanup(void)
893 {
894 /* Stop the timer before we leave */
895 if (!nowayout)
896 iTCO_wdt_stop();
897
898 /* Deregister */
899 misc_deregister(&iTCO_wdt_miscdev);
900 release_region(TCOBASE, 0x20);
901 release_region(SMI_EN, 4);
902 if (iTCO_wdt_private.iTCO_version == 2)
903 iounmap(iTCO_wdt_private.gcs);
904 pci_dev_put(iTCO_wdt_private.pdev);
905 iTCO_wdt_private.ACPIBASE = 0;
906 }
907
908 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
909 {
910 int ret = -ENODEV;
911 int found = 0;
912 struct pci_dev *pdev = NULL;
913 const struct pci_device_id *ent;
914
915 spin_lock_init(&iTCO_wdt_private.io_lock);
916
917 for_each_pci_dev(pdev) {
918 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
919 if (ent) {
920 found++;
921 ret = iTCO_wdt_init(pdev, ent, dev);
922 if (!ret)
923 break;
924 }
925 }
926
927 if (!found)
928 printk(KERN_INFO PFX "No device detected.\n");
929
930 return ret;
931 }
932
933 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
934 {
935 if (iTCO_wdt_private.ACPIBASE)
936 iTCO_wdt_cleanup();
937
938 return 0;
939 }
940
941 static void iTCO_wdt_shutdown(struct platform_device *dev)
942 {
943 iTCO_wdt_stop();
944 }
945
946 #define iTCO_wdt_suspend NULL
947 #define iTCO_wdt_resume NULL
948
949 static struct platform_driver iTCO_wdt_driver = {
950 .probe = iTCO_wdt_probe,
951 .remove = __devexit_p(iTCO_wdt_remove),
952 .shutdown = iTCO_wdt_shutdown,
953 .suspend = iTCO_wdt_suspend,
954 .resume = iTCO_wdt_resume,
955 .driver = {
956 .owner = THIS_MODULE,
957 .name = DRV_NAME,
958 },
959 };
960
961 static int __init iTCO_wdt_init_module(void)
962 {
963 int err;
964
965 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
966 DRV_VERSION);
967
968 err = platform_driver_register(&iTCO_wdt_driver);
969 if (err)
970 return err;
971
972 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
973 -1, NULL, 0);
974 if (IS_ERR(iTCO_wdt_platform_device)) {
975 err = PTR_ERR(iTCO_wdt_platform_device);
976 goto unreg_platform_driver;
977 }
978
979 return 0;
980
981 unreg_platform_driver:
982 platform_driver_unregister(&iTCO_wdt_driver);
983 return err;
984 }
985
986 static void __exit iTCO_wdt_cleanup_module(void)
987 {
988 platform_device_unregister(iTCO_wdt_platform_device);
989 platform_driver_unregister(&iTCO_wdt_driver);
990 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
991 }
992
993 module_init(iTCO_wdt_init_module);
994 module_exit(iTCO_wdt_cleanup_module);
995
996 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
997 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
998 MODULE_VERSION(DRV_VERSION);
999 MODULE_LICENSE("GPL");
1000 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree