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OMAP: GPIO: fix _set_gpio_triggering() for OMAP2+
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / plat-omap / gpio.c
blob60631f227797cc3a8ca5ec29c84daffd8521b7df
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
26
27 #include <mach/hardware.h>
28 #include <asm/irq.h>
29 #include <mach/irqs.h>
30 #include <mach/gpio.h>
31 #include <asm/mach/irq.h>
32
33 /*
34 * OMAP1510 GPIO registers
35 */
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44 #define OMAP1510_IH_GPIO_BASE 64
45
46 /*
47 * OMAP1610 specific GPIO registers
48 */
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67 /*
68 * OMAP7XX specific GPIO registers
69 */
70 #define OMAP7XX_GPIO_DATA_INPUT 0x00
71 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
72 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
73 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
74 #define OMAP7XX_GPIO_INT_MASK 0x10
75 #define OMAP7XX_GPIO_INT_STATUS 0x14
76
77 /*
78 * omap2+ specific GPIO registers
79 */
80 #define OMAP24XX_GPIO_REVISION 0x0000
81 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
82 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
84 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
85 #define OMAP24XX_GPIO_WAKE_EN 0x0020
86 #define OMAP24XX_GPIO_CTRL 0x0030
87 #define OMAP24XX_GPIO_OE 0x0034
88 #define OMAP24XX_GPIO_DATAIN 0x0038
89 #define OMAP24XX_GPIO_DATAOUT 0x003c
90 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
91 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
92 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
93 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
94 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
95 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
96 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
98 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
99 #define OMAP24XX_GPIO_SETWKUENA 0x0084
100 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
101 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
102
103 #define OMAP4_GPIO_REVISION 0x0000
104 #define OMAP4_GPIO_EOI 0x0020
105 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
106 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
107 #define OMAP4_GPIO_IRQSTATUS0 0x002c
108 #define OMAP4_GPIO_IRQSTATUS1 0x0030
109 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
110 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
111 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
113 #define OMAP4_GPIO_IRQWAKEN0 0x0044
114 #define OMAP4_GPIO_IRQWAKEN1 0x0048
115 #define OMAP4_GPIO_IRQENABLE1 0x011c
116 #define OMAP4_GPIO_WAKE_EN 0x0120
117 #define OMAP4_GPIO_IRQSTATUS2 0x0128
118 #define OMAP4_GPIO_IRQENABLE2 0x012c
119 #define OMAP4_GPIO_CTRL 0x0130
120 #define OMAP4_GPIO_OE 0x0134
121 #define OMAP4_GPIO_DATAIN 0x0138
122 #define OMAP4_GPIO_DATAOUT 0x013c
123 #define OMAP4_GPIO_LEVELDETECT0 0x0140
124 #define OMAP4_GPIO_LEVELDETECT1 0x0144
125 #define OMAP4_GPIO_RISINGDETECT 0x0148
126 #define OMAP4_GPIO_FALLINGDETECT 0x014c
127 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
129 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
131 #define OMAP4_GPIO_CLEARWKUENA 0x0180
132 #define OMAP4_GPIO_SETWKUENA 0x0184
133 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
134 #define OMAP4_GPIO_SETDATAOUT 0x0194
135
136 struct gpio_bank {
137 unsigned long pbase;
138 void __iomem *base;
139 u16 irq;
140 u16 virtual_irq_start;
141 int method;
142 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
143 u32 suspend_wakeup;
144 u32 saved_wakeup;
145 #endif
146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
148
149 u32 saved_datain;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
152 u32 level_mask;
153 u32 toggle_mask;
154 spinlock_t lock;
155 struct gpio_chip chip;
156 struct clk *dbck;
157 u32 mod_usage;
158 u32 dbck_enable_mask;
159 struct device *dev;
160 bool dbck_flag;
161 int stride;
162 };
163
164 #ifdef CONFIG_ARCH_OMAP3
165 struct omap3_gpio_regs {
166 u32 irqenable1;
167 u32 irqenable2;
168 u32 wake_en;
169 u32 ctrl;
170 u32 oe;
171 u32 leveldetect0;
172 u32 leveldetect1;
173 u32 risingdetect;
174 u32 fallingdetect;
175 u32 dataout;
176 };
177
178 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
179 #endif
180
181 /*
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
184 */
185 static struct gpio_bank *gpio_bank;
186
187 static int bank_width;
188
189 /* TODO: Analyze removing gpio_bank_count usage from driver code */
190 int gpio_bank_count;
191
192 static inline struct gpio_bank *get_gpio_bank(int gpio)
193 {
194 if (cpu_is_omap15xx()) {
195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
198 }
199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
203 }
204 if (cpu_is_omap7xx()) {
205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
208 }
209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
212 return &gpio_bank[gpio >> 5];
213 BUG();
214 return NULL;
215 }
216
217 static inline int get_gpio_index(int gpio)
218 {
219 if (cpu_is_omap7xx())
220 return gpio & 0x1f;
221 if (cpu_is_omap24xx())
222 return gpio & 0x1f;
223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
224 return gpio & 0x1f;
225 return gpio & 0x0f;
226 }
227
228 static inline int gpio_valid(int gpio)
229 {
230 if (gpio < 0)
231 return -1;
232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
234 return -1;
235 return 0;
236 }
237 if (cpu_is_omap15xx() && gpio < 16)
238 return 0;
239 if ((cpu_is_omap16xx()) && gpio < 64)
240 return 0;
241 if (cpu_is_omap7xx() && gpio < 192)
242 return 0;
243 if (cpu_is_omap2420() && gpio < 128)
244 return 0;
245 if (cpu_is_omap2430() && gpio < 160)
246 return 0;
247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
248 return 0;
249 return -1;
250 }
251
252 static int check_gpio(int gpio)
253 {
254 if (unlikely(gpio_valid(gpio) < 0)) {
255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
256 dump_stack();
257 return -1;
258 }
259 return 0;
260 }
261
262 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
263 {
264 void __iomem *reg = bank->base;
265 u32 l;
266
267 switch (bank->method) {
268 #ifdef CONFIG_ARCH_OMAP1
269 case METHOD_MPUIO:
270 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
271 break;
272 #endif
273 #ifdef CONFIG_ARCH_OMAP15XX
274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
276 break;
277 #endif
278 #ifdef CONFIG_ARCH_OMAP16XX
279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
281 break;
282 #endif
283 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
286 break;
287 #endif
288 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
291 break;
292 #endif
293 #if defined(CONFIG_ARCH_OMAP4)
294 case METHOD_GPIO_44XX:
295 reg += OMAP4_GPIO_OE;
296 break;
297 #endif
298 default:
299 WARN_ON(1);
300 return;
301 }
302 l = __raw_readl(reg);
303 if (is_input)
304 l |= 1 << gpio;
305 else
306 l &= ~(1 << gpio);
307 __raw_writel(l, reg);
308 }
309
310 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
311 {
312 void __iomem *reg = bank->base;
313 u32 l = 0;
314
315 switch (bank->method) {
316 #ifdef CONFIG_ARCH_OMAP1
317 case METHOD_MPUIO:
318 reg += OMAP_MPUIO_OUTPUT / bank->stride;
319 l = __raw_readl(reg);
320 if (enable)
321 l |= 1 << gpio;
322 else
323 l &= ~(1 << gpio);
324 break;
325 #endif
326 #ifdef CONFIG_ARCH_OMAP15XX
327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
330 if (enable)
331 l |= 1 << gpio;
332 else
333 l &= ~(1 << gpio);
334 break;
335 #endif
336 #ifdef CONFIG_ARCH_OMAP16XX
337 case METHOD_GPIO_1610:
338 if (enable)
339 reg += OMAP1610_GPIO_SET_DATAOUT;
340 else
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
342 l = 1 << gpio;
343 break;
344 #endif
345 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
348 l = __raw_readl(reg);
349 if (enable)
350 l |= 1 << gpio;
351 else
352 l &= ~(1 << gpio);
353 break;
354 #endif
355 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
356 case METHOD_GPIO_24XX:
357 if (enable)
358 reg += OMAP24XX_GPIO_SETDATAOUT;
359 else
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
361 l = 1 << gpio;
362 break;
363 #endif
364 #ifdef CONFIG_ARCH_OMAP4
365 case METHOD_GPIO_44XX:
366 if (enable)
367 reg += OMAP4_GPIO_SETDATAOUT;
368 else
369 reg += OMAP4_GPIO_CLEARDATAOUT;
370 l = 1 << gpio;
371 break;
372 #endif
373 default:
374 WARN_ON(1);
375 return;
376 }
377 __raw_writel(l, reg);
378 }
379
380 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
381 {
382 void __iomem *reg;
383
384 if (check_gpio(gpio) < 0)
385 return -EINVAL;
386 reg = bank->base;
387 switch (bank->method) {
388 #ifdef CONFIG_ARCH_OMAP1
389 case METHOD_MPUIO:
390 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
391 break;
392 #endif
393 #ifdef CONFIG_ARCH_OMAP15XX
394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
396 break;
397 #endif
398 #ifdef CONFIG_ARCH_OMAP16XX
399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
401 break;
402 #endif
403 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
406 break;
407 #endif
408 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
411 break;
412 #endif
413 #ifdef CONFIG_ARCH_OMAP4
414 case METHOD_GPIO_44XX:
415 reg += OMAP4_GPIO_DATAIN;
416 break;
417 #endif
418 default:
419 return -EINVAL;
420 }
421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
423 }
424
425 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
426 {
427 void __iomem *reg;
428
429 if (check_gpio(gpio) < 0)
430 return -EINVAL;
431 reg = bank->base;
432
433 switch (bank->method) {
434 #ifdef CONFIG_ARCH_OMAP1
435 case METHOD_MPUIO:
436 reg += OMAP_MPUIO_OUTPUT / bank->stride;
437 break;
438 #endif
439 #ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
442 break;
443 #endif
444 #ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
447 break;
448 #endif
449 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
452 break;
453 #endif
454 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
457 break;
458 #endif
459 #ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
462 break;
463 #endif
464 default:
465 return -EINVAL;
466 }
467
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
469 }
470
471 #define MOD_REG_BIT(reg, bit_mask, set) \
472 do { \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
477 } while(0)
478
479 /**
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
484 *
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
487 */
488 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
489 unsigned debounce)
490 {
491 void __iomem *reg = bank->base;
492 u32 val;
493 u32 l;
494
495 if (!bank->dbck_flag)
496 return;
497
498 if (debounce < 32)
499 debounce = 0x01;
500 else if (debounce > 7936)
501 debounce = 0xff;
502 else
503 debounce = (debounce / 0x1f) - 1;
504
505 l = 1 << get_gpio_index(gpio);
506
507 if (bank->method == METHOD_GPIO_44XX)
508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
509 else
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
511
512 __raw_writel(debounce, reg);
513
514 reg = bank->base;
515 if (bank->method == METHOD_GPIO_44XX)
516 reg += OMAP4_GPIO_DEBOUNCENABLE;
517 else
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
519
520 val = __raw_readl(reg);
521
522 if (debounce) {
523 val |= l;
524 clk_enable(bank->dbck);
525 } else {
526 val &= ~l;
527 clk_disable(bank->dbck);
528 }
529 bank->dbck_enable_mask = val;
530
531 __raw_writel(val, reg);
532 }
533
534 #ifdef CONFIG_ARCH_OMAP2PLUS
535 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
536 int trigger)
537 {
538 void __iomem *base = bank->base;
539 u32 gpio_bit = 1 << gpio;
540 u32 val;
541
542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
551 } else {
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
560 }
561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
562 if (cpu_is_omap44xx()) {
563 if (trigger != 0)
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
566 else {
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
571 }
572 } else {
573 /*
574 * GPIO wakeup request can only be generated on edge
575 * transitions
576 */
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
578 __raw_writel(1 << gpio, bank->base
579 + OMAP24XX_GPIO_SETWKUENA);
580 else
581 __raw_writel(1 << gpio, bank->base
582 + OMAP24XX_GPIO_CLEARWKUENA);
583 }
584 }
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
587 /*
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
592 */
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
594 bank->enabled_non_wakeup_gpios |= gpio_bit;
595 else
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
597 }
598
599 if (cpu_is_omap44xx()) {
600 bank->level_mask =
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
603 } else {
604 bank->level_mask =
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
607 }
608 }
609 #endif
610
611 #ifdef CONFIG_ARCH_OMAP1
612 /*
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
615 */
616 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
617 {
618 void __iomem *reg = bank->base;
619 u32 l = 0;
620
621 switch (bank->method) {
622 case METHOD_MPUIO:
623 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
624 break;
625 #ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
628 break;
629 #endif
630 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
633 break;
634 #endif
635 default:
636 return;
637 }
638
639 l = __raw_readl(reg);
640 if ((l >> gpio) & 1)
641 l &= ~(1 << gpio);
642 else
643 l |= 1 << gpio;
644
645 __raw_writel(l, reg);
646 }
647 #endif
648
649 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
650 {
651 void __iomem *reg = bank->base;
652 u32 l = 0;
653
654 switch (bank->method) {
655 #ifdef CONFIG_ARCH_OMAP1
656 case METHOD_MPUIO:
657 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
658 l = __raw_readl(reg);
659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
660 bank->toggle_mask |= 1 << gpio;
661 if (trigger & IRQ_TYPE_EDGE_RISING)
662 l |= 1 << gpio;
663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
664 l &= ~(1 << gpio);
665 else
666 goto bad;
667 break;
668 #endif
669 #ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
674 bank->toggle_mask |= 1 << gpio;
675 if (trigger & IRQ_TYPE_EDGE_RISING)
676 l |= 1 << gpio;
677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
678 l &= ~(1 << gpio);
679 else
680 goto bad;
681 break;
682 #endif
683 #ifdef CONFIG_ARCH_OMAP16XX
684 case METHOD_GPIO_1610:
685 if (gpio & 0x08)
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
687 else
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
689 gpio &= 0x07;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
692 if (trigger & IRQ_TYPE_EDGE_RISING)
693 l |= 2 << (gpio << 1);
694 if (trigger & IRQ_TYPE_EDGE_FALLING)
695 l |= 1 << (gpio << 1);
696 if (trigger)
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
699 else
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
701 break;
702 #endif
703 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
706 l = __raw_readl(reg);
707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
708 bank->toggle_mask |= 1 << gpio;
709 if (trigger & IRQ_TYPE_EDGE_RISING)
710 l |= 1 << gpio;
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
712 l &= ~(1 << gpio);
713 else
714 goto bad;
715 break;
716 #endif
717 #ifdef CONFIG_ARCH_OMAP2PLUS
718 case METHOD_GPIO_24XX:
719 case METHOD_GPIO_44XX:
720 set_24xx_gpio_triggering(bank, gpio, trigger);
721 return 0;
722 #endif
723 default:
724 goto bad;
725 }
726 __raw_writel(l, reg);
727 return 0;
728 bad:
729 return -EINVAL;
730 }
731
732 static int gpio_irq_type(unsigned irq, unsigned type)
733 {
734 struct gpio_bank *bank;
735 unsigned gpio;
736 int retval;
737 unsigned long flags;
738
739 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
740 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
741 else
742 gpio = irq - IH_GPIO_BASE;
743
744 if (check_gpio(gpio) < 0)
745 return -EINVAL;
746
747 if (type & ~IRQ_TYPE_SENSE_MASK)
748 return -EINVAL;
749
750 /* OMAP1 allows only only edge triggering */
751 if (!cpu_class_is_omap2()
752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
753 return -EINVAL;
754
755 bank = get_irq_chip_data(irq);
756 spin_lock_irqsave(&bank->lock, flags);
757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
758 if (retval == 0) {
759 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
760 irq_desc[irq].status |= type;
761 }
762 spin_unlock_irqrestore(&bank->lock, flags);
763
764 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
765 __set_irq_handler_unlocked(irq, handle_level_irq);
766 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
767 __set_irq_handler_unlocked(irq, handle_edge_irq);
768
769 return retval;
770 }
771
772 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
773 {
774 void __iomem *reg = bank->base;
775
776 switch (bank->method) {
777 #ifdef CONFIG_ARCH_OMAP1
778 case METHOD_MPUIO:
779 /* MPUIO irqstatus is reset by reading the status register,
780 * so do nothing here */
781 return;
782 #endif
783 #ifdef CONFIG_ARCH_OMAP15XX
784 case METHOD_GPIO_1510:
785 reg += OMAP1510_GPIO_INT_STATUS;
786 break;
787 #endif
788 #ifdef CONFIG_ARCH_OMAP16XX
789 case METHOD_GPIO_1610:
790 reg += OMAP1610_GPIO_IRQSTATUS1;
791 break;
792 #endif
793 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
794 case METHOD_GPIO_7XX:
795 reg += OMAP7XX_GPIO_INT_STATUS;
796 break;
797 #endif
798 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
799 case METHOD_GPIO_24XX:
800 reg += OMAP24XX_GPIO_IRQSTATUS1;
801 break;
802 #endif
803 #if defined(CONFIG_ARCH_OMAP4)
804 case METHOD_GPIO_44XX:
805 reg += OMAP4_GPIO_IRQSTATUS0;
806 break;
807 #endif
808 default:
809 WARN_ON(1);
810 return;
811 }
812 __raw_writel(gpio_mask, reg);
813
814 /* Workaround for clearing DSP GPIO interrupts to allow retention */
815 if (cpu_is_omap24xx() || cpu_is_omap34xx())
816 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
817 else if (cpu_is_omap44xx())
818 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
819
820 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
821 __raw_writel(gpio_mask, reg);
822
823 /* Flush posted write for the irq status to avoid spurious interrupts */
824 __raw_readl(reg);
825 }
826 }
827
828 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
829 {
830 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
831 }
832
833 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
834 {
835 void __iomem *reg = bank->base;
836 int inv = 0;
837 u32 l;
838 u32 mask;
839
840 switch (bank->method) {
841 #ifdef CONFIG_ARCH_OMAP1
842 case METHOD_MPUIO:
843 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
844 mask = 0xffff;
845 inv = 1;
846 break;
847 #endif
848 #ifdef CONFIG_ARCH_OMAP15XX
849 case METHOD_GPIO_1510:
850 reg += OMAP1510_GPIO_INT_MASK;
851 mask = 0xffff;
852 inv = 1;
853 break;
854 #endif
855 #ifdef CONFIG_ARCH_OMAP16XX
856 case METHOD_GPIO_1610:
857 reg += OMAP1610_GPIO_IRQENABLE1;
858 mask = 0xffff;
859 break;
860 #endif
861 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
862 case METHOD_GPIO_7XX:
863 reg += OMAP7XX_GPIO_INT_MASK;
864 mask = 0xffffffff;
865 inv = 1;
866 break;
867 #endif
868 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
869 case METHOD_GPIO_24XX:
870 reg += OMAP24XX_GPIO_IRQENABLE1;
871 mask = 0xffffffff;
872 break;
873 #endif
874 #if defined(CONFIG_ARCH_OMAP4)
875 case METHOD_GPIO_44XX:
876 reg += OMAP4_GPIO_IRQSTATUSSET0;
877 mask = 0xffffffff;
878 break;
879 #endif
880 default:
881 WARN_ON(1);
882 return 0;
883 }
884
885 l = __raw_readl(reg);
886 if (inv)
887 l = ~l;
888 l &= mask;
889 return l;
890 }
891
892 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
893 {
894 void __iomem *reg = bank->base;
895 u32 l;
896
897 switch (bank->method) {
898 #ifdef CONFIG_ARCH_OMAP1
899 case METHOD_MPUIO:
900 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
901 l = __raw_readl(reg);
902 if (enable)
903 l &= ~(gpio_mask);
904 else
905 l |= gpio_mask;
906 break;
907 #endif
908 #ifdef CONFIG_ARCH_OMAP15XX
909 case METHOD_GPIO_1510:
910 reg += OMAP1510_GPIO_INT_MASK;
911 l = __raw_readl(reg);
912 if (enable)
913 l &= ~(gpio_mask);
914 else
915 l |= gpio_mask;
916 break;
917 #endif
918 #ifdef CONFIG_ARCH_OMAP16XX
919 case METHOD_GPIO_1610:
920 if (enable)
921 reg += OMAP1610_GPIO_SET_IRQENABLE1;
922 else
923 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
924 l = gpio_mask;
925 break;
926 #endif
927 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
928 case METHOD_GPIO_7XX:
929 reg += OMAP7XX_GPIO_INT_MASK;
930 l = __raw_readl(reg);
931 if (enable)
932 l &= ~(gpio_mask);
933 else
934 l |= gpio_mask;
935 break;
936 #endif
937 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
938 case METHOD_GPIO_24XX:
939 if (enable)
940 reg += OMAP24XX_GPIO_SETIRQENABLE1;
941 else
942 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
943 l = gpio_mask;
944 break;
945 #endif
946 #ifdef CONFIG_ARCH_OMAP4
947 case METHOD_GPIO_44XX:
948 if (enable)
949 reg += OMAP4_GPIO_IRQSTATUSSET0;
950 else
951 reg += OMAP4_GPIO_IRQSTATUSCLR0;
952 l = gpio_mask;
953 break;
954 #endif
955 default:
956 WARN_ON(1);
957 return;
958 }
959 __raw_writel(l, reg);
960 }
961
962 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
963 {
964 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
965 }
966
967 /*
968 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
969 * 1510 does not seem to have a wake-up register. If JTAG is connected
970 * to the target, system will wake up always on GPIO events. While
971 * system is running all registered GPIO interrupts need to have wake-up
972 * enabled. When system is suspended, only selected GPIO interrupts need
973 * to have wake-up enabled.
974 */
975 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
976 {
977 unsigned long uninitialized_var(flags);
978
979 switch (bank->method) {
980 #ifdef CONFIG_ARCH_OMAP16XX
981 case METHOD_MPUIO:
982 case METHOD_GPIO_1610:
983 spin_lock_irqsave(&bank->lock, flags);
984 if (enable)
985 bank->suspend_wakeup |= (1 << gpio);
986 else
987 bank->suspend_wakeup &= ~(1 << gpio);
988 spin_unlock_irqrestore(&bank->lock, flags);
989 return 0;
990 #endif
991 #ifdef CONFIG_ARCH_OMAP2PLUS
992 case METHOD_GPIO_24XX:
993 case METHOD_GPIO_44XX:
994 if (bank->non_wakeup_gpios & (1 << gpio)) {
995 printk(KERN_ERR "Unable to modify wakeup on "
996 "non-wakeup GPIO%d\n",
997 (bank - gpio_bank) * 32 + gpio);
998 return -EINVAL;
999 }
1000 spin_lock_irqsave(&bank->lock, flags);
1001 if (enable)
1002 bank->suspend_wakeup |= (1 << gpio);
1003 else
1004 bank->suspend_wakeup &= ~(1 << gpio);
1005 spin_unlock_irqrestore(&bank->lock, flags);
1006 return 0;
1007 #endif
1008 default:
1009 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1010 bank->method);
1011 return -EINVAL;
1012 }
1013 }
1014
1015 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1016 {
1017 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1018 _set_gpio_irqenable(bank, gpio, 0);
1019 _clear_gpio_irqstatus(bank, gpio);
1020 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1021 }
1022
1023 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1024 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1025 {
1026 unsigned int gpio = irq - IH_GPIO_BASE;
1027 struct gpio_bank *bank;
1028 int retval;
1029
1030 if (check_gpio(gpio) < 0)
1031 return -ENODEV;
1032 bank = get_irq_chip_data(irq);
1033 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1034
1035 return retval;
1036 }
1037
1038 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1039 {
1040 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1041 unsigned long flags;
1042
1043 spin_lock_irqsave(&bank->lock, flags);
1044
1045 /* Set trigger to none. You need to enable the desired trigger with
1046 * request_irq() or set_irq_type().
1047 */
1048 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1049
1050 #ifdef CONFIG_ARCH_OMAP15XX
1051 if (bank->method == METHOD_GPIO_1510) {
1052 void __iomem *reg;
1053
1054 /* Claim the pin for MPU */
1055 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1056 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1057 }
1058 #endif
1059 if (!cpu_class_is_omap1()) {
1060 if (!bank->mod_usage) {
1061 void __iomem *reg = bank->base;
1062 u32 ctrl;
1063
1064 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1065 reg += OMAP24XX_GPIO_CTRL;
1066 else if (cpu_is_omap44xx())
1067 reg += OMAP4_GPIO_CTRL;
1068 ctrl = __raw_readl(reg);
1069 /* Module is enabled, clocks are not gated */
1070 ctrl &= 0xFFFFFFFE;
1071 __raw_writel(ctrl, reg);
1072 }
1073 bank->mod_usage |= 1 << offset;
1074 }
1075 spin_unlock_irqrestore(&bank->lock, flags);
1076
1077 return 0;
1078 }
1079
1080 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1081 {
1082 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1083 unsigned long flags;
1084
1085 spin_lock_irqsave(&bank->lock, flags);
1086 #ifdef CONFIG_ARCH_OMAP16XX
1087 if (bank->method == METHOD_GPIO_1610) {
1088 /* Disable wake-up during idle for dynamic tick */
1089 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1090 __raw_writel(1 << offset, reg);
1091 }
1092 #endif
1093 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1094 if (bank->method == METHOD_GPIO_24XX) {
1095 /* Disable wake-up during idle for dynamic tick */
1096 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1097 __raw_writel(1 << offset, reg);
1098 }
1099 #endif
1100 #ifdef CONFIG_ARCH_OMAP4
1101 if (bank->method == METHOD_GPIO_44XX) {
1102 /* Disable wake-up during idle for dynamic tick */
1103 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1104 __raw_writel(1 << offset, reg);
1105 }
1106 #endif
1107 if (!cpu_class_is_omap1()) {
1108 bank->mod_usage &= ~(1 << offset);
1109 if (!bank->mod_usage) {
1110 void __iomem *reg = bank->base;
1111 u32 ctrl;
1112
1113 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1114 reg += OMAP24XX_GPIO_CTRL;
1115 else if (cpu_is_omap44xx())
1116 reg += OMAP4_GPIO_CTRL;
1117 ctrl = __raw_readl(reg);
1118 /* Module is disabled, clocks are gated */
1119 ctrl |= 1;
1120 __raw_writel(ctrl, reg);
1121 }
1122 }
1123 _reset_gpio(bank, bank->chip.base + offset);
1124 spin_unlock_irqrestore(&bank->lock, flags);
1125 }
1126
1127 /*
1128 * We need to unmask the GPIO bank interrupt as soon as possible to
1129 * avoid missing GPIO interrupts for other lines in the bank.
1130 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1131 * in the bank to avoid missing nested interrupts for a GPIO line.
1132 * If we wait to unmask individual GPIO lines in the bank after the
1133 * line's interrupt handler has been run, we may miss some nested
1134 * interrupts.
1135 */
1136 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1137 {
1138 void __iomem *isr_reg = NULL;
1139 u32 isr;
1140 unsigned int gpio_irq, gpio_index;
1141 struct gpio_bank *bank;
1142 u32 retrigger = 0;
1143 int unmasked = 0;
1144
1145 desc->chip->ack(irq);
1146
1147 bank = get_irq_data(irq);
1148 #ifdef CONFIG_ARCH_OMAP1
1149 if (bank->method == METHOD_MPUIO)
1150 isr_reg = bank->base +
1151 OMAP_MPUIO_GPIO_INT / bank->stride;
1152 #endif
1153 #ifdef CONFIG_ARCH_OMAP15XX
1154 if (bank->method == METHOD_GPIO_1510)
1155 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1156 #endif
1157 #if defined(CONFIG_ARCH_OMAP16XX)
1158 if (bank->method == METHOD_GPIO_1610)
1159 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1160 #endif
1161 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1162 if (bank->method == METHOD_GPIO_7XX)
1163 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1164 #endif
1165 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1166 if (bank->method == METHOD_GPIO_24XX)
1167 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1168 #endif
1169 #if defined(CONFIG_ARCH_OMAP4)
1170 if (bank->method == METHOD_GPIO_44XX)
1171 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1172 #endif
1173
1174 if (WARN_ON(!isr_reg))
1175 goto exit;
1176
1177 while(1) {
1178 u32 isr_saved, level_mask = 0;
1179 u32 enabled;
1180
1181 enabled = _get_gpio_irqbank_mask(bank);
1182 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1183
1184 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1185 isr &= 0x0000ffff;
1186
1187 if (cpu_class_is_omap2()) {
1188 level_mask = bank->level_mask & enabled;
1189 }
1190
1191 /* clear edge sensitive interrupts before handler(s) are
1192 called so that we don't miss any interrupt occurred while
1193 executing them */
1194 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1195 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1196 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1197
1198 /* if there is only edge sensitive GPIO pin interrupts
1199 configured, we could unmask GPIO bank interrupt immediately */
1200 if (!level_mask && !unmasked) {
1201 unmasked = 1;
1202 desc->chip->unmask(irq);
1203 }
1204
1205 isr |= retrigger;
1206 retrigger = 0;
1207 if (!isr)
1208 break;
1209
1210 gpio_irq = bank->virtual_irq_start;
1211 for (; isr != 0; isr >>= 1, gpio_irq++) {
1212 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1213
1214 if (!(isr & 1))
1215 continue;
1216
1217 #ifdef CONFIG_ARCH_OMAP1
1218 /*
1219 * Some chips can't respond to both rising and falling
1220 * at the same time. If this irq was requested with
1221 * both flags, we need to flip the ICR data for the IRQ
1222 * to respond to the IRQ for the opposite direction.
1223 * This will be indicated in the bank toggle_mask.
1224 */
1225 if (bank->toggle_mask & (1 << gpio_index))
1226 _toggle_gpio_edge_triggering(bank, gpio_index);
1227 #endif
1228
1229 generic_handle_irq(gpio_irq);
1230 }
1231 }
1232 /* if bank has any level sensitive GPIO pin interrupt
1233 configured, we must unmask the bank interrupt only after
1234 handler(s) are executed in order to avoid spurious bank
1235 interrupt */
1236 exit:
1237 if (!unmasked)
1238 desc->chip->unmask(irq);
1239
1240 }
1241
1242 static void gpio_irq_shutdown(unsigned int irq)
1243 {
1244 unsigned int gpio = irq - IH_GPIO_BASE;
1245 struct gpio_bank *bank = get_irq_chip_data(irq);
1246
1247 _reset_gpio(bank, gpio);
1248 }
1249
1250 static void gpio_ack_irq(unsigned int irq)
1251 {
1252 unsigned int gpio = irq - IH_GPIO_BASE;
1253 struct gpio_bank *bank = get_irq_chip_data(irq);
1254
1255 _clear_gpio_irqstatus(bank, gpio);
1256 }
1257
1258 static void gpio_mask_irq(unsigned int irq)
1259 {
1260 unsigned int gpio = irq - IH_GPIO_BASE;
1261 struct gpio_bank *bank = get_irq_chip_data(irq);
1262
1263 _set_gpio_irqenable(bank, gpio, 0);
1264 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1265 }
1266
1267 static void gpio_unmask_irq(unsigned int irq)
1268 {
1269 unsigned int gpio = irq - IH_GPIO_BASE;
1270 struct gpio_bank *bank = get_irq_chip_data(irq);
1271 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1272 struct irq_desc *desc = irq_to_desc(irq);
1273 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1274
1275 if (trigger)
1276 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1277
1278 /* For level-triggered GPIOs, the clearing must be done after
1279 * the HW source is cleared, thus after the handler has run */
1280 if (bank->level_mask & irq_mask) {
1281 _set_gpio_irqenable(bank, gpio, 0);
1282 _clear_gpio_irqstatus(bank, gpio);
1283 }
1284
1285 _set_gpio_irqenable(bank, gpio, 1);
1286 }
1287
1288 static struct irq_chip gpio_irq_chip = {
1289 .name = "GPIO",
1290 .shutdown = gpio_irq_shutdown,
1291 .ack = gpio_ack_irq,
1292 .mask = gpio_mask_irq,
1293 .unmask = gpio_unmask_irq,
1294 .set_type = gpio_irq_type,
1295 .set_wake = gpio_wake_enable,
1296 };
1297
1298 /*---------------------------------------------------------------------*/
1299
1300 #ifdef CONFIG_ARCH_OMAP1
1301
1302 /* MPUIO uses the always-on 32k clock */
1303
1304 static void mpuio_ack_irq(unsigned int irq)
1305 {
1306 /* The ISR is reset automatically, so do nothing here. */
1307 }
1308
1309 static void mpuio_mask_irq(unsigned int irq)
1310 {
1311 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1312 struct gpio_bank *bank = get_irq_chip_data(irq);
1313
1314 _set_gpio_irqenable(bank, gpio, 0);
1315 }
1316
1317 static void mpuio_unmask_irq(unsigned int irq)
1318 {
1319 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1320 struct gpio_bank *bank = get_irq_chip_data(irq);
1321
1322 _set_gpio_irqenable(bank, gpio, 1);
1323 }
1324
1325 static struct irq_chip mpuio_irq_chip = {
1326 .name = "MPUIO",
1327 .ack = mpuio_ack_irq,
1328 .mask = mpuio_mask_irq,
1329 .unmask = mpuio_unmask_irq,
1330 .set_type = gpio_irq_type,
1331 #ifdef CONFIG_ARCH_OMAP16XX
1332 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1333 .set_wake = gpio_wake_enable,
1334 #endif
1335 };
1336
1337
1338 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1339
1340
1341 #ifdef CONFIG_ARCH_OMAP16XX
1342
1343 #include <linux/platform_device.h>
1344
1345 static int omap_mpuio_suspend_noirq(struct device *dev)
1346 {
1347 struct platform_device *pdev = to_platform_device(dev);
1348 struct gpio_bank *bank = platform_get_drvdata(pdev);
1349 void __iomem *mask_reg = bank->base +
1350 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1351 unsigned long flags;
1352
1353 spin_lock_irqsave(&bank->lock, flags);
1354 bank->saved_wakeup = __raw_readl(mask_reg);
1355 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1356 spin_unlock_irqrestore(&bank->lock, flags);
1357
1358 return 0;
1359 }
1360
1361 static int omap_mpuio_resume_noirq(struct device *dev)
1362 {
1363 struct platform_device *pdev = to_platform_device(dev);
1364 struct gpio_bank *bank = platform_get_drvdata(pdev);
1365 void __iomem *mask_reg = bank->base +
1366 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1367 unsigned long flags;
1368
1369 spin_lock_irqsave(&bank->lock, flags);
1370 __raw_writel(bank->saved_wakeup, mask_reg);
1371 spin_unlock_irqrestore(&bank->lock, flags);
1372
1373 return 0;
1374 }
1375
1376 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1377 .suspend_noirq = omap_mpuio_suspend_noirq,
1378 .resume_noirq = omap_mpuio_resume_noirq,
1379 };
1380
1381 /* use platform_driver for this, now that there's no longer any
1382 * point to sys_device (other than not disturbing old code).
1383 */
1384 static struct platform_driver omap_mpuio_driver = {
1385 .driver = {
1386 .name = "mpuio",
1387 .pm = &omap_mpuio_dev_pm_ops,
1388 },
1389 };
1390
1391 static struct platform_device omap_mpuio_device = {
1392 .name = "mpuio",
1393 .id = -1,
1394 .dev = {
1395 .driver = &omap_mpuio_driver.driver,
1396 }
1397 /* could list the /proc/iomem resources */
1398 };
1399
1400 static inline void mpuio_init(void)
1401 {
1402 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1403 platform_set_drvdata(&omap_mpuio_device, bank);
1404
1405 if (platform_driver_register(&omap_mpuio_driver) == 0)
1406 (void) platform_device_register(&omap_mpuio_device);
1407 }
1408
1409 #else
1410 static inline void mpuio_init(void) {}
1411 #endif /* 16xx */
1412
1413 #else
1414
1415 extern struct irq_chip mpuio_irq_chip;
1416
1417 #define bank_is_mpuio(bank) 0
1418 static inline void mpuio_init(void) {}
1419
1420 #endif
1421
1422 /*---------------------------------------------------------------------*/
1423
1424 /* REVISIT these are stupid implementations! replace by ones that
1425 * don't switch on METHOD_* and which mostly avoid spinlocks
1426 */
1427
1428 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1429 {
1430 struct gpio_bank *bank;
1431 unsigned long flags;
1432
1433 bank = container_of(chip, struct gpio_bank, chip);
1434 spin_lock_irqsave(&bank->lock, flags);
1435 _set_gpio_direction(bank, offset, 1);
1436 spin_unlock_irqrestore(&bank->lock, flags);
1437 return 0;
1438 }
1439
1440 static int gpio_is_input(struct gpio_bank *bank, int mask)
1441 {
1442 void __iomem *reg = bank->base;
1443
1444 switch (bank->method) {
1445 case METHOD_MPUIO:
1446 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1447 break;
1448 case METHOD_GPIO_1510:
1449 reg += OMAP1510_GPIO_DIR_CONTROL;
1450 break;
1451 case METHOD_GPIO_1610:
1452 reg += OMAP1610_GPIO_DIRECTION;
1453 break;
1454 case METHOD_GPIO_7XX:
1455 reg += OMAP7XX_GPIO_DIR_CONTROL;
1456 break;
1457 case METHOD_GPIO_24XX:
1458 reg += OMAP24XX_GPIO_OE;
1459 break;
1460 case METHOD_GPIO_44XX:
1461 reg += OMAP4_GPIO_OE;
1462 break;
1463 default:
1464 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1465 return -EINVAL;
1466 }
1467 return __raw_readl(reg) & mask;
1468 }
1469
1470 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1471 {
1472 struct gpio_bank *bank;
1473 void __iomem *reg;
1474 int gpio;
1475 u32 mask;
1476
1477 gpio = chip->base + offset;
1478 bank = get_gpio_bank(gpio);
1479 reg = bank->base;
1480 mask = 1 << get_gpio_index(gpio);
1481
1482 if (gpio_is_input(bank, mask))
1483 return _get_gpio_datain(bank, gpio);
1484 else
1485 return _get_gpio_dataout(bank, gpio);
1486 }
1487
1488 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1489 {
1490 struct gpio_bank *bank;
1491 unsigned long flags;
1492
1493 bank = container_of(chip, struct gpio_bank, chip);
1494 spin_lock_irqsave(&bank->lock, flags);
1495 _set_gpio_dataout(bank, offset, value);
1496 _set_gpio_direction(bank, offset, 0);
1497 spin_unlock_irqrestore(&bank->lock, flags);
1498 return 0;
1499 }
1500
1501 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1502 unsigned debounce)
1503 {
1504 struct gpio_bank *bank;
1505 unsigned long flags;
1506
1507 bank = container_of(chip, struct gpio_bank, chip);
1508
1509 if (!bank->dbck) {
1510 bank->dbck = clk_get(bank->dev, "dbclk");
1511 if (IS_ERR(bank->dbck))
1512 dev_err(bank->dev, "Could not get gpio dbck\n");
1513 }
1514
1515 spin_lock_irqsave(&bank->lock, flags);
1516 _set_gpio_debounce(bank, offset, debounce);
1517 spin_unlock_irqrestore(&bank->lock, flags);
1518
1519 return 0;
1520 }
1521
1522 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1523 {
1524 struct gpio_bank *bank;
1525 unsigned long flags;
1526
1527 bank = container_of(chip, struct gpio_bank, chip);
1528 spin_lock_irqsave(&bank->lock, flags);
1529 _set_gpio_dataout(bank, offset, value);
1530 spin_unlock_irqrestore(&bank->lock, flags);
1531 }
1532
1533 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1534 {
1535 struct gpio_bank *bank;
1536
1537 bank = container_of(chip, struct gpio_bank, chip);
1538 return bank->virtual_irq_start + offset;
1539 }
1540
1541 /*---------------------------------------------------------------------*/
1542
1543 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1544 {
1545 u32 rev;
1546
1547 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1548 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1549 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1550 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1551 else if (cpu_is_omap44xx())
1552 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1553 else
1554 return;
1555
1556 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1557 (rev >> 4) & 0x0f, rev & 0x0f);
1558 }
1559
1560 /* This lock class tells lockdep that GPIO irqs are in a different
1561 * category than their parents, so it won't report false recursion.
1562 */
1563 static struct lock_class_key gpio_lock_class;
1564
1565 static inline int init_gpio_info(struct platform_device *pdev)
1566 {
1567 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1568 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1569 GFP_KERNEL);
1570 if (!gpio_bank) {
1571 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1572 return -ENOMEM;
1573 }
1574 return 0;
1575 }
1576
1577 /* TODO: Cleanup cpu_is_* checks */
1578 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1579 {
1580 if (cpu_class_is_omap2()) {
1581 if (cpu_is_omap44xx()) {
1582 __raw_writel(0xffffffff, bank->base +
1583 OMAP4_GPIO_IRQSTATUSCLR0);
1584 __raw_writel(0x00000000, bank->base +
1585 OMAP4_GPIO_DEBOUNCENABLE);
1586 /* Initialize interface clk ungated, module enabled */
1587 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1588 } else if (cpu_is_omap34xx()) {
1589 __raw_writel(0x00000000, bank->base +
1590 OMAP24XX_GPIO_IRQENABLE1);
1591 __raw_writel(0xffffffff, bank->base +
1592 OMAP24XX_GPIO_IRQSTATUS1);
1593 __raw_writel(0x00000000, bank->base +
1594 OMAP24XX_GPIO_DEBOUNCE_EN);
1595
1596 /* Initialize interface clk ungated, module enabled */
1597 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1598 } else if (cpu_is_omap24xx()) {
1599 static const u32 non_wakeup_gpios[] = {
1600 0xe203ffc0, 0x08700040
1601 };
1602 if (id < ARRAY_SIZE(non_wakeup_gpios))
1603 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1604 }
1605 } else if (cpu_class_is_omap1()) {
1606 if (bank_is_mpuio(bank))
1607 __raw_writew(0xffff, bank->base +
1608 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1609 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1610 __raw_writew(0xffff, bank->base
1611 + OMAP1510_GPIO_INT_MASK);
1612 __raw_writew(0x0000, bank->base
1613 + OMAP1510_GPIO_INT_STATUS);
1614 }
1615 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1616 __raw_writew(0x0000, bank->base
1617 + OMAP1610_GPIO_IRQENABLE1);
1618 __raw_writew(0xffff, bank->base
1619 + OMAP1610_GPIO_IRQSTATUS1);
1620 __raw_writew(0x0014, bank->base
1621 + OMAP1610_GPIO_SYSCONFIG);
1622
1623 /*
1624 * Enable system clock for GPIO module.
1625 * The CAM_CLK_CTRL *is* really the right place.
1626 */
1627 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1628 ULPD_CAM_CLK_CTRL);
1629 }
1630 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1631 __raw_writel(0xffffffff, bank->base
1632 + OMAP7XX_GPIO_INT_MASK);
1633 __raw_writel(0x00000000, bank->base
1634 + OMAP7XX_GPIO_INT_STATUS);
1635 }
1636 }
1637 }
1638
1639 static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1640 {
1641 int j;
1642 static int gpio;
1643
1644 bank->mod_usage = 0;
1645 /*
1646 * REVISIT eventually switch from OMAP-specific gpio structs
1647 * over to the generic ones
1648 */
1649 bank->chip.request = omap_gpio_request;
1650 bank->chip.free = omap_gpio_free;
1651 bank->chip.direction_input = gpio_input;
1652 bank->chip.get = gpio_get;
1653 bank->chip.direction_output = gpio_output;
1654 bank->chip.set_debounce = gpio_debounce;
1655 bank->chip.set = gpio_set;
1656 bank->chip.to_irq = gpio_2irq;
1657 if (bank_is_mpuio(bank)) {
1658 bank->chip.label = "mpuio";
1659 #ifdef CONFIG_ARCH_OMAP16XX
1660 bank->chip.dev = &omap_mpuio_device.dev;
1661 #endif
1662 bank->chip.base = OMAP_MPUIO(0);
1663 } else {
1664 bank->chip.label = "gpio";
1665 bank->chip.base = gpio;
1666 gpio += bank_width;
1667 }
1668 bank->chip.ngpio = bank_width;
1669
1670 gpiochip_add(&bank->chip);
1671
1672 for (j = bank->virtual_irq_start;
1673 j < bank->virtual_irq_start + bank_width; j++) {
1674 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1675 set_irq_chip_data(j, bank);
1676 if (bank_is_mpuio(bank))
1677 set_irq_chip(j, &mpuio_irq_chip);
1678 else
1679 set_irq_chip(j, &gpio_irq_chip);
1680 set_irq_handler(j, handle_simple_irq);
1681 set_irq_flags(j, IRQF_VALID);
1682 }
1683 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1684 set_irq_data(bank->irq, bank);
1685 }
1686
1687 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1688 {
1689 static int gpio_init_done;
1690 struct omap_gpio_platform_data *pdata;
1691 struct resource *res;
1692 int id;
1693 struct gpio_bank *bank;
1694
1695 if (!pdev->dev.platform_data)
1696 return -EINVAL;
1697
1698 pdata = pdev->dev.platform_data;
1699
1700 if (!gpio_init_done) {
1701 int ret;
1702
1703 ret = init_gpio_info(pdev);
1704 if (ret)
1705 return ret;
1706 }
1707
1708 id = pdev->id;
1709 bank = &gpio_bank[id];
1710
1711 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1712 if (unlikely(!res)) {
1713 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1714 return -ENODEV;
1715 }
1716
1717 bank->irq = res->start;
1718 bank->virtual_irq_start = pdata->virtual_irq_start;
1719 bank->method = pdata->bank_type;
1720 bank->dev = &pdev->dev;
1721 bank->dbck_flag = pdata->dbck_flag;
1722 bank->stride = pdata->bank_stride;
1723 bank_width = pdata->bank_width;
1724
1725 spin_lock_init(&bank->lock);
1726
1727 /* Static mapping, never released */
1728 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1729 if (unlikely(!res)) {
1730 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1731 return -ENODEV;
1732 }
1733
1734 bank->base = ioremap(res->start, resource_size(res));
1735 if (!bank->base) {
1736 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1737 return -ENOMEM;
1738 }
1739
1740 pm_runtime_enable(bank->dev);
1741 pm_runtime_get_sync(bank->dev);
1742
1743 omap_gpio_mod_init(bank, id);
1744 omap_gpio_chip_init(bank);
1745 omap_gpio_show_rev(bank);
1746
1747 if (!gpio_init_done)
1748 gpio_init_done = 1;
1749
1750 return 0;
1751 }
1752
1753 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1754 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1755 {
1756 int i;
1757
1758 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1759 return 0;
1760
1761 for (i = 0; i < gpio_bank_count; i++) {
1762 struct gpio_bank *bank = &gpio_bank[i];
1763 void __iomem *wake_status;
1764 void __iomem *wake_clear;
1765 void __iomem *wake_set;
1766 unsigned long flags;
1767
1768 switch (bank->method) {
1769 #ifdef CONFIG_ARCH_OMAP16XX
1770 case METHOD_GPIO_1610:
1771 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1772 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1773 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1774 break;
1775 #endif
1776 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1777 case METHOD_GPIO_24XX:
1778 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1779 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1780 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1781 break;
1782 #endif
1783 #ifdef CONFIG_ARCH_OMAP4
1784 case METHOD_GPIO_44XX:
1785 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1786 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1787 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1788 break;
1789 #endif
1790 default:
1791 continue;
1792 }
1793
1794 spin_lock_irqsave(&bank->lock, flags);
1795 bank->saved_wakeup = __raw_readl(wake_status);
1796 __raw_writel(0xffffffff, wake_clear);
1797 __raw_writel(bank->suspend_wakeup, wake_set);
1798 spin_unlock_irqrestore(&bank->lock, flags);
1799 }
1800
1801 return 0;
1802 }
1803
1804 static int omap_gpio_resume(struct sys_device *dev)
1805 {
1806 int i;
1807
1808 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1809 return 0;
1810
1811 for (i = 0; i < gpio_bank_count; i++) {
1812 struct gpio_bank *bank = &gpio_bank[i];
1813 void __iomem *wake_clear;
1814 void __iomem *wake_set;
1815 unsigned long flags;
1816
1817 switch (bank->method) {
1818 #ifdef CONFIG_ARCH_OMAP16XX
1819 case METHOD_GPIO_1610:
1820 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1821 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1822 break;
1823 #endif
1824 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1825 case METHOD_GPIO_24XX:
1826 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1827 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1828 break;
1829 #endif
1830 #ifdef CONFIG_ARCH_OMAP4
1831 case METHOD_GPIO_44XX:
1832 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1833 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1834 break;
1835 #endif
1836 default:
1837 continue;
1838 }
1839
1840 spin_lock_irqsave(&bank->lock, flags);
1841 __raw_writel(0xffffffff, wake_clear);
1842 __raw_writel(bank->saved_wakeup, wake_set);
1843 spin_unlock_irqrestore(&bank->lock, flags);
1844 }
1845
1846 return 0;
1847 }
1848
1849 static struct sysdev_class omap_gpio_sysclass = {
1850 .name = "gpio",
1851 .suspend = omap_gpio_suspend,
1852 .resume = omap_gpio_resume,
1853 };
1854
1855 static struct sys_device omap_gpio_device = {
1856 .id = 0,
1857 .cls = &omap_gpio_sysclass,
1858 };
1859
1860 #endif
1861
1862 #ifdef CONFIG_ARCH_OMAP2PLUS
1863
1864 static int workaround_enabled;
1865
1866 void omap2_gpio_prepare_for_idle(int off_mode)
1867 {
1868 int i, c = 0;
1869 int min = 0;
1870
1871 if (cpu_is_omap34xx())
1872 min = 1;
1873
1874 for (i = min; i < gpio_bank_count; i++) {
1875 struct gpio_bank *bank = &gpio_bank[i];
1876 u32 l1 = 0, l2 = 0;
1877 int j;
1878
1879 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1880 clk_disable(bank->dbck);
1881
1882 if (!off_mode)
1883 continue;
1884
1885 /* If going to OFF, remove triggering for all
1886 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1887 * generated. See OMAP2420 Errata item 1.101. */
1888 if (!(bank->enabled_non_wakeup_gpios))
1889 continue;
1890
1891 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1892 bank->saved_datain = __raw_readl(bank->base +
1893 OMAP24XX_GPIO_DATAIN);
1894 l1 = __raw_readl(bank->base +
1895 OMAP24XX_GPIO_FALLINGDETECT);
1896 l2 = __raw_readl(bank->base +
1897 OMAP24XX_GPIO_RISINGDETECT);
1898 }
1899
1900 if (cpu_is_omap44xx()) {
1901 bank->saved_datain = __raw_readl(bank->base +
1902 OMAP4_GPIO_DATAIN);
1903 l1 = __raw_readl(bank->base +
1904 OMAP4_GPIO_FALLINGDETECT);
1905 l2 = __raw_readl(bank->base +
1906 OMAP4_GPIO_RISINGDETECT);
1907 }
1908
1909 bank->saved_fallingdetect = l1;
1910 bank->saved_risingdetect = l2;
1911 l1 &= ~bank->enabled_non_wakeup_gpios;
1912 l2 &= ~bank->enabled_non_wakeup_gpios;
1913
1914 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1915 __raw_writel(l1, bank->base +
1916 OMAP24XX_GPIO_FALLINGDETECT);
1917 __raw_writel(l2, bank->base +
1918 OMAP24XX_GPIO_RISINGDETECT);
1919 }
1920
1921 if (cpu_is_omap44xx()) {
1922 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1923 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1924 }
1925
1926 c++;
1927 }
1928 if (!c) {
1929 workaround_enabled = 0;
1930 return;
1931 }
1932 workaround_enabled = 1;
1933 }
1934
1935 void omap2_gpio_resume_after_idle(void)
1936 {
1937 int i;
1938 int min = 0;
1939
1940 if (cpu_is_omap34xx())
1941 min = 1;
1942 for (i = min; i < gpio_bank_count; i++) {
1943 struct gpio_bank *bank = &gpio_bank[i];
1944 u32 l = 0, gen, gen0, gen1;
1945 int j;
1946
1947 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1948 clk_enable(bank->dbck);
1949
1950 if (!workaround_enabled)
1951 continue;
1952
1953 if (!(bank->enabled_non_wakeup_gpios))
1954 continue;
1955
1956 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1957 __raw_writel(bank->saved_fallingdetect,
1958 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1959 __raw_writel(bank->saved_risingdetect,
1960 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1961 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1962 }
1963
1964 if (cpu_is_omap44xx()) {
1965 __raw_writel(bank->saved_fallingdetect,
1966 bank->base + OMAP4_GPIO_FALLINGDETECT);
1967 __raw_writel(bank->saved_risingdetect,
1968 bank->base + OMAP4_GPIO_RISINGDETECT);
1969 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1970 }
1971
1972 /* Check if any of the non-wakeup interrupt GPIOs have changed
1973 * state. If so, generate an IRQ by software. This is
1974 * horribly racy, but it's the best we can do to work around
1975 * this silicon bug. */
1976 l ^= bank->saved_datain;
1977 l &= bank->enabled_non_wakeup_gpios;
1978
1979 /*
1980 * No need to generate IRQs for the rising edge for gpio IRQs
1981 * configured with falling edge only; and vice versa.
1982 */
1983 gen0 = l & bank->saved_fallingdetect;
1984 gen0 &= bank->saved_datain;
1985
1986 gen1 = l & bank->saved_risingdetect;
1987 gen1 &= ~(bank->saved_datain);
1988
1989 /* FIXME: Consider GPIO IRQs with level detections properly! */
1990 gen = l & (~(bank->saved_fallingdetect) &
1991 ~(bank->saved_risingdetect));
1992 /* Consider all GPIO IRQs needed to be updated */
1993 gen |= gen0 | gen1;
1994
1995 if (gen) {
1996 u32 old0, old1;
1997
1998 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1999 old0 = __raw_readl(bank->base +
2000 OMAP24XX_GPIO_LEVELDETECT0);
2001 old1 = __raw_readl(bank->base +
2002 OMAP24XX_GPIO_LEVELDETECT1);
2003 __raw_writel(old0 | gen, bank->base +
2004 OMAP24XX_GPIO_LEVELDETECT0);
2005 __raw_writel(old1 | gen, bank->base +
2006 OMAP24XX_GPIO_LEVELDETECT1);
2007 __raw_writel(old0, bank->base +
2008 OMAP24XX_GPIO_LEVELDETECT0);
2009 __raw_writel(old1, bank->base +
2010 OMAP24XX_GPIO_LEVELDETECT1);
2011 }
2012
2013 if (cpu_is_omap44xx()) {
2014 old0 = __raw_readl(bank->base +
2015 OMAP4_GPIO_LEVELDETECT0);
2016 old1 = __raw_readl(bank->base +
2017 OMAP4_GPIO_LEVELDETECT1);
2018 __raw_writel(old0 | l, bank->base +
2019 OMAP4_GPIO_LEVELDETECT0);
2020 __raw_writel(old1 | l, bank->base +
2021 OMAP4_GPIO_LEVELDETECT1);
2022 __raw_writel(old0, bank->base +
2023 OMAP4_GPIO_LEVELDETECT0);
2024 __raw_writel(old1, bank->base +
2025 OMAP4_GPIO_LEVELDETECT1);
2026 }
2027 }
2028 }
2029
2030 }
2031
2032 #endif
2033
2034 #ifdef CONFIG_ARCH_OMAP3
2035 /* save the registers of bank 2-6 */
2036 void omap_gpio_save_context(void)
2037 {
2038 int i;
2039
2040 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2041 for (i = 1; i < gpio_bank_count; i++) {
2042 struct gpio_bank *bank = &gpio_bank[i];
2043 gpio_context[i].irqenable1 =
2044 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2045 gpio_context[i].irqenable2 =
2046 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2047 gpio_context[i].wake_en =
2048 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2049 gpio_context[i].ctrl =
2050 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2051 gpio_context[i].oe =
2052 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2053 gpio_context[i].leveldetect0 =
2054 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2055 gpio_context[i].leveldetect1 =
2056 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2057 gpio_context[i].risingdetect =
2058 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2059 gpio_context[i].fallingdetect =
2060 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2061 gpio_context[i].dataout =
2062 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2063 }
2064 }
2065
2066 /* restore the required registers of bank 2-6 */
2067 void omap_gpio_restore_context(void)
2068 {
2069 int i;
2070
2071 for (i = 1; i < gpio_bank_count; i++) {
2072 struct gpio_bank *bank = &gpio_bank[i];
2073 __raw_writel(gpio_context[i].irqenable1,
2074 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2075 __raw_writel(gpio_context[i].irqenable2,
2076 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2077 __raw_writel(gpio_context[i].wake_en,
2078 bank->base + OMAP24XX_GPIO_WAKE_EN);
2079 __raw_writel(gpio_context[i].ctrl,
2080 bank->base + OMAP24XX_GPIO_CTRL);
2081 __raw_writel(gpio_context[i].oe,
2082 bank->base + OMAP24XX_GPIO_OE);
2083 __raw_writel(gpio_context[i].leveldetect0,
2084 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2085 __raw_writel(gpio_context[i].leveldetect1,
2086 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2087 __raw_writel(gpio_context[i].risingdetect,
2088 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2089 __raw_writel(gpio_context[i].fallingdetect,
2090 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2091 __raw_writel(gpio_context[i].dataout,
2092 bank->base + OMAP24XX_GPIO_DATAOUT);
2093 }
2094 }
2095 #endif
2096
2097 static struct platform_driver omap_gpio_driver = {
2098 .probe = omap_gpio_probe,
2099 .driver = {
2100 .name = "omap_gpio",
2101 },
2102 };
2103
2104 /*
2105 * gpio driver register needs to be done before
2106 * machine_init functions access gpio APIs.
2107 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2108 */
2109 static int __init omap_gpio_drv_reg(void)
2110 {
2111 return platform_driver_register(&omap_gpio_driver);
2112 }
2113 postcore_initcall(omap_gpio_drv_reg);
2114
2115 static int __init omap_gpio_sysinit(void)
2116 {
2117 int ret = 0;
2118
2119 mpuio_init();
2120
2121 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2122 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2123 if (ret == 0) {
2124 ret = sysdev_class_register(&omap_gpio_sysclass);
2125 if (ret == 0)
2126 ret = sysdev_register(&omap_gpio_device);
2127 }
2128 }
2129 #endif
2130
2131 return ret;
2132 }
2133
2134 arch_initcall(omap_gpio_sysinit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree