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serial: fix rs485 for atmel_serial on avr32
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / spi_mpc8xxx.c
blob97ab0a81338adf036bea9e706dbcbe552b6d607c
1 /*
2 * MPC8xxx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/bug.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/irq.h>
29 #include <linux/device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/platform_device.h>
33 #include <linux/fsl_devices.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/mm.h>
36 #include <linux/mutex.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
41 #include <linux/of_spi.h>
42 #include <linux/slab.h>
43
44 #include <sysdev/fsl_soc.h>
45 #include <asm/cpm.h>
46 #include <asm/qe.h>
47 #include <asm/irq.h>
48
49 /* CPM1 and CPM2 are mutually exclusive. */
50 #ifdef CONFIG_CPM1
51 #include <asm/cpm1.h>
52 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
53 #else
54 #include <asm/cpm2.h>
55 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
56 #endif
57
58 /* SPI Controller registers */
59 struct mpc8xxx_spi_reg {
60 u8 res1[0x20];
61 __be32 mode;
62 __be32 event;
63 __be32 mask;
64 __be32 command;
65 __be32 transmit;
66 __be32 receive;
67 };
68
69 /* SPI Controller mode register definitions */
70 #define SPMODE_LOOP (1 << 30)
71 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
72 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
73 #define SPMODE_DIV16 (1 << 27)
74 #define SPMODE_REV (1 << 26)
75 #define SPMODE_MS (1 << 25)
76 #define SPMODE_ENABLE (1 << 24)
77 #define SPMODE_LEN(x) ((x) << 20)
78 #define SPMODE_PM(x) ((x) << 16)
79 #define SPMODE_OP (1 << 14)
80 #define SPMODE_CG(x) ((x) << 7)
81
82 /*
83 * Default for SPI Mode:
84 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
85 */
86 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
87 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
88
89 /* SPIE register values */
90 #define SPIE_NE 0x00000200 /* Not empty */
91 #define SPIE_NF 0x00000100 /* Not full */
92
93 /* SPIM register values */
94 #define SPIM_NE 0x00000200 /* Not empty */
95 #define SPIM_NF 0x00000100 /* Not full */
96
97 #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
98 #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
99
100 /* SPCOM register values */
101 #define SPCOM_STR (1 << 23) /* Start transmit */
102
103 #define SPI_PRAM_SIZE 0x100
104 #define SPI_MRBLR ((unsigned int)PAGE_SIZE)
105
106 /* SPI Controller driver's private data. */
107 struct mpc8xxx_spi {
108 struct device *dev;
109 struct mpc8xxx_spi_reg __iomem *base;
110
111 /* rx & tx bufs from the spi_transfer */
112 const void *tx;
113 void *rx;
114
115 int subblock;
116 struct spi_pram __iomem *pram;
117 struct cpm_buf_desc __iomem *tx_bd;
118 struct cpm_buf_desc __iomem *rx_bd;
119
120 struct spi_transfer *xfer_in_progress;
121
122 /* dma addresses for CPM transfers */
123 dma_addr_t tx_dma;
124 dma_addr_t rx_dma;
125 bool map_tx_dma;
126 bool map_rx_dma;
127
128 dma_addr_t dma_dummy_tx;
129 dma_addr_t dma_dummy_rx;
130
131 /* functions to deal with different sized buffers */
132 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
133 u32(*get_tx) (struct mpc8xxx_spi *);
134
135 unsigned int count;
136 unsigned int irq;
137
138 unsigned nsecs; /* (clock cycle time)/2 */
139
140 u32 spibrg; /* SPIBRG input clock */
141 u32 rx_shift; /* RX data reg shift when in qe mode */
142 u32 tx_shift; /* TX data reg shift when in qe mode */
143
144 unsigned int flags;
145
146 struct workqueue_struct *workqueue;
147 struct work_struct work;
148
149 struct list_head queue;
150 spinlock_t lock;
151
152 struct completion done;
153 };
154
155 static void *mpc8xxx_dummy_rx;
156 static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
157 static int mpc8xxx_dummy_rx_refcnt;
158
159 struct spi_mpc8xxx_cs {
160 /* functions to deal with different sized buffers */
161 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
162 u32 (*get_tx) (struct mpc8xxx_spi *);
163 u32 rx_shift; /* RX data reg shift when in qe mode */
164 u32 tx_shift; /* TX data reg shift when in qe mode */
165 u32 hw_mode; /* Holds HW mode register settings */
166 };
167
168 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
169 {
170 out_be32(reg, val);
171 }
172
173 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
174 {
175 return in_be32(reg);
176 }
177
178 #define MPC83XX_SPI_RX_BUF(type) \
179 static \
180 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
181 { \
182 type *rx = mpc8xxx_spi->rx; \
183 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
184 mpc8xxx_spi->rx = rx; \
185 }
186
187 #define MPC83XX_SPI_TX_BUF(type) \
188 static \
189 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
190 { \
191 u32 data; \
192 const type *tx = mpc8xxx_spi->tx; \
193 if (!tx) \
194 return 0; \
195 data = *tx++ << mpc8xxx_spi->tx_shift; \
196 mpc8xxx_spi->tx = tx; \
197 return data; \
198 }
199
200 MPC83XX_SPI_RX_BUF(u8)
201 MPC83XX_SPI_RX_BUF(u16)
202 MPC83XX_SPI_RX_BUF(u32)
203 MPC83XX_SPI_TX_BUF(u8)
204 MPC83XX_SPI_TX_BUF(u16)
205 MPC83XX_SPI_TX_BUF(u32)
206
207 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
208 {
209 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
210 struct spi_mpc8xxx_cs *cs = spi->controller_state;
211 __be32 __iomem *mode = &mspi->base->mode;
212 unsigned long flags;
213
214 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
215 return;
216
217 /* Turn off IRQs locally to minimize time that SPI is disabled. */
218 local_irq_save(flags);
219
220 /* Turn off SPI unit prior changing mode */
221 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
222
223 /* When in CPM mode, we need to reinit tx and rx. */
224 if (mspi->flags & SPI_CPM_MODE) {
225 if (mspi->flags & SPI_QE) {
226 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
227 QE_CR_PROTOCOL_UNSPECIFIED, 0);
228 } else {
229 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
230 if (mspi->flags & SPI_CPM1) {
231 out_be16(&mspi->pram->rbptr,
232 in_be16(&mspi->pram->rbase));
233 out_be16(&mspi->pram->tbptr,
234 in_be16(&mspi->pram->tbase));
235 }
236 }
237 }
238 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
239 local_irq_restore(flags);
240 }
241
242 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
243 {
244 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
245 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
246 bool pol = spi->mode & SPI_CS_HIGH;
247 struct spi_mpc8xxx_cs *cs = spi->controller_state;
248
249 if (value == BITBANG_CS_INACTIVE) {
250 if (pdata->cs_control)
251 pdata->cs_control(spi, !pol);
252 }
253
254 if (value == BITBANG_CS_ACTIVE) {
255 mpc8xxx_spi->rx_shift = cs->rx_shift;
256 mpc8xxx_spi->tx_shift = cs->tx_shift;
257 mpc8xxx_spi->get_rx = cs->get_rx;
258 mpc8xxx_spi->get_tx = cs->get_tx;
259
260 mpc8xxx_spi_change_mode(spi);
261
262 if (pdata->cs_control)
263 pdata->cs_control(spi, pol);
264 }
265 }
266
267 static int
268 mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
269 struct spi_device *spi,
270 struct mpc8xxx_spi *mpc8xxx_spi,
271 int bits_per_word)
272 {
273 cs->rx_shift = 0;
274 cs->tx_shift = 0;
275 if (bits_per_word <= 8) {
276 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
277 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
278 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
279 cs->rx_shift = 16;
280 cs->tx_shift = 24;
281 }
282 } else if (bits_per_word <= 16) {
283 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
284 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
285 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
286 cs->rx_shift = 16;
287 cs->tx_shift = 16;
288 }
289 } else if (bits_per_word <= 32) {
290 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
291 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
292 } else
293 return -EINVAL;
294
295 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
296 spi->mode & SPI_LSB_FIRST) {
297 cs->tx_shift = 0;
298 if (bits_per_word <= 8)
299 cs->rx_shift = 8;
300 else
301 cs->rx_shift = 0;
302 }
303 mpc8xxx_spi->rx_shift = cs->rx_shift;
304 mpc8xxx_spi->tx_shift = cs->tx_shift;
305 mpc8xxx_spi->get_rx = cs->get_rx;
306 mpc8xxx_spi->get_tx = cs->get_tx;
307
308 return bits_per_word;
309 }
310
311 static int
312 mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
313 struct spi_device *spi,
314 int bits_per_word)
315 {
316 /* QE uses Little Endian for words > 8
317 * so transform all words > 8 into 8 bits
318 * Unfortnatly that doesn't work for LSB so
319 * reject these for now */
320 /* Note: 32 bits word, LSB works iff
321 * tfcr/rfcr is set to CPMFCR_GBL */
322 if (spi->mode & SPI_LSB_FIRST &&
323 bits_per_word > 8)
324 return -EINVAL;
325 if (bits_per_word > 8)
326 return 8; /* pretend its 8 bits */
327 return bits_per_word;
328 }
329
330 static
331 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
332 {
333 struct mpc8xxx_spi *mpc8xxx_spi;
334 int bits_per_word;
335 u8 pm;
336 u32 hz;
337 struct spi_mpc8xxx_cs *cs = spi->controller_state;
338
339 mpc8xxx_spi = spi_master_get_devdata(spi->master);
340
341 if (t) {
342 bits_per_word = t->bits_per_word;
343 hz = t->speed_hz;
344 } else {
345 bits_per_word = 0;
346 hz = 0;
347 }
348
349 /* spi_transfer level calls that work per-word */
350 if (!bits_per_word)
351 bits_per_word = spi->bits_per_word;
352
353 /* Make sure its a bit width we support [4..16, 32] */
354 if ((bits_per_word < 4)
355 || ((bits_per_word > 16) && (bits_per_word != 32)))
356 return -EINVAL;
357
358 if (!hz)
359 hz = spi->max_speed_hz;
360
361 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
362 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
363 mpc8xxx_spi,
364 bits_per_word);
365 else if (mpc8xxx_spi->flags & SPI_QE)
366 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
367 bits_per_word);
368
369 if (bits_per_word < 0)
370 return bits_per_word;
371
372 if (bits_per_word == 32)
373 bits_per_word = 0;
374 else
375 bits_per_word = bits_per_word - 1;
376
377 /* mask out bits we are going to set */
378 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
379 | SPMODE_PM(0xF));
380
381 cs->hw_mode |= SPMODE_LEN(bits_per_word);
382
383 if ((mpc8xxx_spi->spibrg / hz) > 64) {
384 cs->hw_mode |= SPMODE_DIV16;
385 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
386
387 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
388 "Will use %d Hz instead.\n", dev_name(&spi->dev),
389 hz, mpc8xxx_spi->spibrg / 1024);
390 if (pm > 16)
391 pm = 16;
392 } else
393 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
394 if (pm)
395 pm--;
396
397 cs->hw_mode |= SPMODE_PM(pm);
398
399 mpc8xxx_spi_change_mode(spi);
400 return 0;
401 }
402
403 static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
404 {
405 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
406 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
407 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
408 unsigned int xfer_ofs;
409
410 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
411
412 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
413 out_be16(&rx_bd->cbd_datlen, 0);
414 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
415
416 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
417 out_be16(&tx_bd->cbd_datlen, xfer_len);
418 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
419 BD_SC_LAST);
420
421 /* start transfer */
422 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
423 }
424
425 static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
426 struct spi_transfer *t, bool is_dma_mapped)
427 {
428 struct device *dev = mspi->dev;
429
430 if (is_dma_mapped) {
431 mspi->map_tx_dma = 0;
432 mspi->map_rx_dma = 0;
433 } else {
434 mspi->map_tx_dma = 1;
435 mspi->map_rx_dma = 1;
436 }
437
438 if (!t->tx_buf) {
439 mspi->tx_dma = mspi->dma_dummy_tx;
440 mspi->map_tx_dma = 0;
441 }
442
443 if (!t->rx_buf) {
444 mspi->rx_dma = mspi->dma_dummy_rx;
445 mspi->map_rx_dma = 0;
446 }
447
448 if (mspi->map_tx_dma) {
449 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
450
451 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
452 DMA_TO_DEVICE);
453 if (dma_mapping_error(dev, mspi->tx_dma)) {
454 dev_err(dev, "unable to map tx dma\n");
455 return -ENOMEM;
456 }
457 } else if (t->tx_buf) {
458 mspi->tx_dma = t->tx_dma;
459 }
460
461 if (mspi->map_rx_dma) {
462 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
463 DMA_FROM_DEVICE);
464 if (dma_mapping_error(dev, mspi->rx_dma)) {
465 dev_err(dev, "unable to map rx dma\n");
466 goto err_rx_dma;
467 }
468 } else if (t->rx_buf) {
469 mspi->rx_dma = t->rx_dma;
470 }
471
472 /* enable rx ints */
473 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
474
475 mspi->xfer_in_progress = t;
476 mspi->count = t->len;
477
478 /* start CPM transfers */
479 mpc8xxx_spi_cpm_bufs_start(mspi);
480
481 return 0;
482
483 err_rx_dma:
484 if (mspi->map_tx_dma)
485 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
486 return -ENOMEM;
487 }
488
489 static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
490 {
491 struct device *dev = mspi->dev;
492 struct spi_transfer *t = mspi->xfer_in_progress;
493
494 if (mspi->map_tx_dma)
495 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
496 if (mspi->map_rx_dma)
497 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
498 mspi->xfer_in_progress = NULL;
499 }
500
501 static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
502 struct spi_transfer *t, unsigned int len)
503 {
504 u32 word;
505
506 mspi->count = len;
507
508 /* enable rx ints */
509 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
510
511 /* transmit word */
512 word = mspi->get_tx(mspi);
513 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
514
515 return 0;
516 }
517
518 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
519 bool is_dma_mapped)
520 {
521 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
522 unsigned int len = t->len;
523 u8 bits_per_word;
524 int ret;
525
526 bits_per_word = spi->bits_per_word;
527 if (t->bits_per_word)
528 bits_per_word = t->bits_per_word;
529
530 if (bits_per_word > 8) {
531 /* invalid length? */
532 if (len & 1)
533 return -EINVAL;
534 len /= 2;
535 }
536 if (bits_per_word > 16) {
537 /* invalid length? */
538 if (len & 1)
539 return -EINVAL;
540 len /= 2;
541 }
542
543 mpc8xxx_spi->tx = t->tx_buf;
544 mpc8xxx_spi->rx = t->rx_buf;
545
546 INIT_COMPLETION(mpc8xxx_spi->done);
547
548 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
549 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
550 else
551 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
552 if (ret)
553 return ret;
554
555 wait_for_completion(&mpc8xxx_spi->done);
556
557 /* disable rx ints */
558 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
559
560 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
561 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
562
563 return mpc8xxx_spi->count;
564 }
565
566 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
567 {
568 struct spi_device *spi = m->spi;
569 struct spi_transfer *t;
570 unsigned int cs_change;
571 const int nsecs = 50;
572 int status;
573
574 cs_change = 1;
575 status = 0;
576 list_for_each_entry(t, &m->transfers, transfer_list) {
577 if (t->bits_per_word || t->speed_hz) {
578 /* Don't allow changes if CS is active */
579 status = -EINVAL;
580
581 if (cs_change)
582 status = mpc8xxx_spi_setup_transfer(spi, t);
583 if (status < 0)
584 break;
585 }
586
587 if (cs_change) {
588 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
589 ndelay(nsecs);
590 }
591 cs_change = t->cs_change;
592 if (t->len)
593 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
594 if (status) {
595 status = -EMSGSIZE;
596 break;
597 }
598 m->actual_length += t->len;
599
600 if (t->delay_usecs)
601 udelay(t->delay_usecs);
602
603 if (cs_change) {
604 ndelay(nsecs);
605 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
606 ndelay(nsecs);
607 }
608 }
609
610 m->status = status;
611 m->complete(m->context);
612
613 if (status || !cs_change) {
614 ndelay(nsecs);
615 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
616 }
617
618 mpc8xxx_spi_setup_transfer(spi, NULL);
619 }
620
621 static void mpc8xxx_spi_work(struct work_struct *work)
622 {
623 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
624 work);
625
626 spin_lock_irq(&mpc8xxx_spi->lock);
627 while (!list_empty(&mpc8xxx_spi->queue)) {
628 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
629 struct spi_message, queue);
630
631 list_del_init(&m->queue);
632 spin_unlock_irq(&mpc8xxx_spi->lock);
633
634 mpc8xxx_spi_do_one_msg(m);
635
636 spin_lock_irq(&mpc8xxx_spi->lock);
637 }
638 spin_unlock_irq(&mpc8xxx_spi->lock);
639 }
640
641 static int mpc8xxx_spi_setup(struct spi_device *spi)
642 {
643 struct mpc8xxx_spi *mpc8xxx_spi;
644 int retval;
645 u32 hw_mode;
646 struct spi_mpc8xxx_cs *cs = spi->controller_state;
647
648 if (!spi->max_speed_hz)
649 return -EINVAL;
650
651 if (!cs) {
652 cs = kzalloc(sizeof *cs, GFP_KERNEL);
653 if (!cs)
654 return -ENOMEM;
655 spi->controller_state = cs;
656 }
657 mpc8xxx_spi = spi_master_get_devdata(spi->master);
658
659 hw_mode = cs->hw_mode; /* Save original settings */
660 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
661 /* mask out bits we are going to set */
662 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
663 | SPMODE_REV | SPMODE_LOOP);
664
665 if (spi->mode & SPI_CPHA)
666 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
667 if (spi->mode & SPI_CPOL)
668 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
669 if (!(spi->mode & SPI_LSB_FIRST))
670 cs->hw_mode |= SPMODE_REV;
671 if (spi->mode & SPI_LOOP)
672 cs->hw_mode |= SPMODE_LOOP;
673
674 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
675 if (retval < 0) {
676 cs->hw_mode = hw_mode; /* Restore settings */
677 return retval;
678 }
679 return 0;
680 }
681
682 static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
683 {
684 u16 len;
685
686 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
687 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
688
689 len = in_be16(&mspi->rx_bd->cbd_datlen);
690 if (len > mspi->count) {
691 WARN_ON(1);
692 len = mspi->count;
693 }
694
695 /* Clear the events */
696 mpc8xxx_spi_write_reg(&mspi->base->event, events);
697
698 mspi->count -= len;
699 if (mspi->count)
700 mpc8xxx_spi_cpm_bufs_start(mspi);
701 else
702 complete(&mspi->done);
703 }
704
705 static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
706 {
707 /* We need handle RX first */
708 if (events & SPIE_NE) {
709 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
710
711 if (mspi->rx)
712 mspi->get_rx(rx_data, mspi);
713 }
714
715 if ((events & SPIE_NF) == 0)
716 /* spin until TX is done */
717 while (((events =
718 mpc8xxx_spi_read_reg(&mspi->base->event)) &
719 SPIE_NF) == 0)
720 cpu_relax();
721
722 /* Clear the events */
723 mpc8xxx_spi_write_reg(&mspi->base->event, events);
724
725 mspi->count -= 1;
726 if (mspi->count) {
727 u32 word = mspi->get_tx(mspi);
728
729 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
730 } else {
731 complete(&mspi->done);
732 }
733 }
734
735 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
736 {
737 struct mpc8xxx_spi *mspi = context_data;
738 irqreturn_t ret = IRQ_NONE;
739 u32 events;
740
741 /* Get interrupt events(tx/rx) */
742 events = mpc8xxx_spi_read_reg(&mspi->base->event);
743 if (events)
744 ret = IRQ_HANDLED;
745
746 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
747
748 if (mspi->flags & SPI_CPM_MODE)
749 mpc8xxx_spi_cpm_irq(mspi, events);
750 else
751 mpc8xxx_spi_cpu_irq(mspi, events);
752
753 return ret;
754 }
755
756 static int mpc8xxx_spi_transfer(struct spi_device *spi,
757 struct spi_message *m)
758 {
759 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
760 unsigned long flags;
761
762 m->actual_length = 0;
763 m->status = -EINPROGRESS;
764
765 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
766 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
767 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
768 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
769
770 return 0;
771 }
772
773
774 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
775 {
776 kfree(spi->controller_state);
777 }
778
779 static void *mpc8xxx_spi_alloc_dummy_rx(void)
780 {
781 mutex_lock(&mpc8xxx_dummy_rx_lock);
782
783 if (!mpc8xxx_dummy_rx)
784 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
785 if (mpc8xxx_dummy_rx)
786 mpc8xxx_dummy_rx_refcnt++;
787
788 mutex_unlock(&mpc8xxx_dummy_rx_lock);
789
790 return mpc8xxx_dummy_rx;
791 }
792
793 static void mpc8xxx_spi_free_dummy_rx(void)
794 {
795 mutex_lock(&mpc8xxx_dummy_rx_lock);
796
797 switch (mpc8xxx_dummy_rx_refcnt) {
798 case 0:
799 WARN_ON(1);
800 break;
801 case 1:
802 kfree(mpc8xxx_dummy_rx);
803 mpc8xxx_dummy_rx = NULL;
804 /* fall through */
805 default:
806 mpc8xxx_dummy_rx_refcnt--;
807 break;
808 }
809
810 mutex_unlock(&mpc8xxx_dummy_rx_lock);
811 }
812
813 static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
814 {
815 struct device *dev = mspi->dev;
816 struct device_node *np = dev->of_node;
817 const u32 *iprop;
818 int size;
819 unsigned long spi_base_ofs;
820 unsigned long pram_ofs = -ENOMEM;
821
822 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
823 iprop = of_get_property(np, "reg", &size);
824
825 /* QE with a fixed pram location? */
826 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
827 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
828
829 /* QE but with a dynamic pram location? */
830 if (mspi->flags & SPI_QE) {
831 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
832 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
833 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
834 return pram_ofs;
835 }
836
837 /* CPM1 and CPM2 pram must be at a fixed addr. */
838 if (!iprop || size != sizeof(*iprop) * 4)
839 return -ENOMEM;
840
841 spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
842 if (IS_ERR_VALUE(spi_base_ofs))
843 return -ENOMEM;
844
845 if (mspi->flags & SPI_CPM2) {
846 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
847 if (!IS_ERR_VALUE(pram_ofs)) {
848 u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
849
850 out_be16(spi_base, pram_ofs);
851 }
852 } else {
853 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
854 u16 rpbase = in_be16(&pram->rpbase);
855
856 /* Microcode relocation patch applied? */
857 if (rpbase)
858 pram_ofs = rpbase;
859 else
860 return spi_base_ofs;
861 }
862
863 cpm_muram_free(spi_base_ofs);
864 return pram_ofs;
865 }
866
867 static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
868 {
869 struct device *dev = mspi->dev;
870 struct device_node *np = dev->of_node;
871 const u32 *iprop;
872 int size;
873 unsigned long pram_ofs;
874 unsigned long bds_ofs;
875
876 if (!(mspi->flags & SPI_CPM_MODE))
877 return 0;
878
879 if (!mpc8xxx_spi_alloc_dummy_rx())
880 return -ENOMEM;
881
882 if (mspi->flags & SPI_QE) {
883 iprop = of_get_property(np, "cell-index", &size);
884 if (iprop && size == sizeof(*iprop))
885 mspi->subblock = *iprop;
886
887 switch (mspi->subblock) {
888 default:
889 dev_warn(dev, "cell-index unspecified, assuming SPI1");
890 /* fall through */
891 case 0:
892 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
893 break;
894 case 1:
895 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
896 break;
897 }
898 }
899
900 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
901 if (IS_ERR_VALUE(pram_ofs)) {
902 dev_err(dev, "can't allocate spi parameter ram\n");
903 goto err_pram;
904 }
905
906 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
907 sizeof(*mspi->rx_bd), 8);
908 if (IS_ERR_VALUE(bds_ofs)) {
909 dev_err(dev, "can't allocate bds\n");
910 goto err_bds;
911 }
912
913 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
914 DMA_TO_DEVICE);
915 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
916 dev_err(dev, "unable to map dummy tx buffer\n");
917 goto err_dummy_tx;
918 }
919
920 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
921 DMA_FROM_DEVICE);
922 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
923 dev_err(dev, "unable to map dummy rx buffer\n");
924 goto err_dummy_rx;
925 }
926
927 mspi->pram = cpm_muram_addr(pram_ofs);
928
929 mspi->tx_bd = cpm_muram_addr(bds_ofs);
930 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
931
932 /* Initialize parameter ram. */
933 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
934 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
935 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
936 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
937 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
938 out_be32(&mspi->pram->rstate, 0);
939 out_be32(&mspi->pram->rdp, 0);
940 out_be16(&mspi->pram->rbptr, 0);
941 out_be16(&mspi->pram->rbc, 0);
942 out_be32(&mspi->pram->rxtmp, 0);
943 out_be32(&mspi->pram->tstate, 0);
944 out_be32(&mspi->pram->tdp, 0);
945 out_be16(&mspi->pram->tbptr, 0);
946 out_be16(&mspi->pram->tbc, 0);
947 out_be32(&mspi->pram->txtmp, 0);
948
949 return 0;
950
951 err_dummy_rx:
952 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
953 err_dummy_tx:
954 cpm_muram_free(bds_ofs);
955 err_bds:
956 cpm_muram_free(pram_ofs);
957 err_pram:
958 mpc8xxx_spi_free_dummy_rx();
959 return -ENOMEM;
960 }
961
962 static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
963 {
964 struct device *dev = mspi->dev;
965
966 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
967 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
968 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
969 cpm_muram_free(cpm_muram_offset(mspi->pram));
970 mpc8xxx_spi_free_dummy_rx();
971 }
972
973 static const char *mpc8xxx_spi_strmode(unsigned int flags)
974 {
975 if (flags & SPI_QE_CPU_MODE) {
976 return "QE CPU";
977 } else if (flags & SPI_CPM_MODE) {
978 if (flags & SPI_QE)
979 return "QE";
980 else if (flags & SPI_CPM2)
981 return "CPM2";
982 else
983 return "CPM1";
984 }
985 return "CPU";
986 }
987
988 static struct spi_master * __devinit
989 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
990 {
991 struct fsl_spi_platform_data *pdata = dev->platform_data;
992 struct spi_master *master;
993 struct mpc8xxx_spi *mpc8xxx_spi;
994 u32 regval;
995 int ret = 0;
996
997 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
998 if (master == NULL) {
999 ret = -ENOMEM;
1000 goto err;
1001 }
1002
1003 dev_set_drvdata(dev, master);
1004
1005 /* the spi->mode bits understood by this driver: */
1006 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
1007 | SPI_LSB_FIRST | SPI_LOOP;
1008
1009 master->setup = mpc8xxx_spi_setup;
1010 master->transfer = mpc8xxx_spi_transfer;
1011 master->cleanup = mpc8xxx_spi_cleanup;
1012
1013 mpc8xxx_spi = spi_master_get_devdata(master);
1014 mpc8xxx_spi->dev = dev;
1015 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
1016 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
1017 mpc8xxx_spi->flags = pdata->flags;
1018 mpc8xxx_spi->spibrg = pdata->sysclk;
1019
1020 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1021 if (ret)
1022 goto err_cpm_init;
1023
1024 mpc8xxx_spi->rx_shift = 0;
1025 mpc8xxx_spi->tx_shift = 0;
1026 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1027 mpc8xxx_spi->rx_shift = 16;
1028 mpc8xxx_spi->tx_shift = 24;
1029 }
1030
1031 init_completion(&mpc8xxx_spi->done);
1032
1033 mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
1034 if (mpc8xxx_spi->base == NULL) {
1035 ret = -ENOMEM;
1036 goto err_ioremap;
1037 }
1038
1039 mpc8xxx_spi->irq = irq;
1040
1041 /* Register for SPI Interrupt */
1042 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1043 0, "mpc8xxx_spi", mpc8xxx_spi);
1044
1045 if (ret != 0)
1046 goto unmap_io;
1047
1048 master->bus_num = pdata->bus_num;
1049 master->num_chipselect = pdata->max_chipselect;
1050
1051 /* SPI controller initializations */
1052 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1053 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1054 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1055 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
1056
1057 /* Enable SPI interface */
1058 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1059 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1060 regval |= SPMODE_OP;
1061
1062 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1063 spin_lock_init(&mpc8xxx_spi->lock);
1064 init_completion(&mpc8xxx_spi->done);
1065 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1066 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1067
1068 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1069 dev_name(master->dev.parent));
1070 if (mpc8xxx_spi->workqueue == NULL) {
1071 ret = -EBUSY;
1072 goto free_irq;
1073 }
1074
1075 ret = spi_register_master(master);
1076 if (ret < 0)
1077 goto unreg_master;
1078
1079 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1080 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1081
1082 return master;
1083
1084 unreg_master:
1085 destroy_workqueue(mpc8xxx_spi->workqueue);
1086 free_irq:
1087 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1088 unmap_io:
1089 iounmap(mpc8xxx_spi->base);
1090 err_ioremap:
1091 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1092 err_cpm_init:
1093 spi_master_put(master);
1094 err:
1095 return ERR_PTR(ret);
1096 }
1097
1098 static int __devexit mpc8xxx_spi_remove(struct device *dev)
1099 {
1100 struct mpc8xxx_spi *mpc8xxx_spi;
1101 struct spi_master *master;
1102
1103 master = dev_get_drvdata(dev);
1104 mpc8xxx_spi = spi_master_get_devdata(master);
1105
1106 flush_workqueue(mpc8xxx_spi->workqueue);
1107 destroy_workqueue(mpc8xxx_spi->workqueue);
1108 spi_unregister_master(master);
1109
1110 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1111 iounmap(mpc8xxx_spi->base);
1112 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1113
1114 return 0;
1115 }
1116
1117 struct mpc8xxx_spi_probe_info {
1118 struct fsl_spi_platform_data pdata;
1119 int *gpios;
1120 bool *alow_flags;
1121 };
1122
1123 static struct mpc8xxx_spi_probe_info *
1124 to_of_pinfo(struct fsl_spi_platform_data *pdata)
1125 {
1126 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1127 }
1128
1129 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1130 {
1131 struct device *dev = spi->dev.parent;
1132 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
1133 u16 cs = spi->chip_select;
1134 int gpio = pinfo->gpios[cs];
1135 bool alow = pinfo->alow_flags[cs];
1136
1137 gpio_set_value(gpio, on ^ alow);
1138 }
1139
1140 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1141 {
1142 struct device_node *np = dev->of_node;
1143 struct fsl_spi_platform_data *pdata = dev->platform_data;
1144 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1145 unsigned int ngpios;
1146 int i = 0;
1147 int ret;
1148
1149 ngpios = of_gpio_count(np);
1150 if (!ngpios) {
1151 /*
1152 * SPI w/o chip-select line. One SPI device is still permitted
1153 * though.
1154 */
1155 pdata->max_chipselect = 1;
1156 return 0;
1157 }
1158
1159 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
1160 if (!pinfo->gpios)
1161 return -ENOMEM;
1162 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
1163
1164 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
1165 GFP_KERNEL);
1166 if (!pinfo->alow_flags) {
1167 ret = -ENOMEM;
1168 goto err_alloc_flags;
1169 }
1170
1171 for (; i < ngpios; i++) {
1172 int gpio;
1173 enum of_gpio_flags flags;
1174
1175 gpio = of_get_gpio_flags(np, i, &flags);
1176 if (!gpio_is_valid(gpio)) {
1177 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
1178 ret = gpio;
1179 goto err_loop;
1180 }
1181
1182 ret = gpio_request(gpio, dev_name(dev));
1183 if (ret) {
1184 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1185 goto err_loop;
1186 }
1187
1188 pinfo->gpios[i] = gpio;
1189 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1190
1191 ret = gpio_direction_output(pinfo->gpios[i],
1192 pinfo->alow_flags[i]);
1193 if (ret) {
1194 dev_err(dev, "can't set output direction for gpio "
1195 "#%d: %d\n", i, ret);
1196 goto err_loop;
1197 }
1198 }
1199
1200 pdata->max_chipselect = ngpios;
1201 pdata->cs_control = mpc8xxx_spi_cs_control;
1202
1203 return 0;
1204
1205 err_loop:
1206 while (i >= 0) {
1207 if (gpio_is_valid(pinfo->gpios[i]))
1208 gpio_free(pinfo->gpios[i]);
1209 i--;
1210 }
1211
1212 kfree(pinfo->alow_flags);
1213 pinfo->alow_flags = NULL;
1214 err_alloc_flags:
1215 kfree(pinfo->gpios);
1216 pinfo->gpios = NULL;
1217 return ret;
1218 }
1219
1220 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1221 {
1222 struct fsl_spi_platform_data *pdata = dev->platform_data;
1223 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1224 int i;
1225
1226 if (!pinfo->gpios)
1227 return 0;
1228
1229 for (i = 0; i < pdata->max_chipselect; i++) {
1230 if (gpio_is_valid(pinfo->gpios[i]))
1231 gpio_free(pinfo->gpios[i]);
1232 }
1233
1234 kfree(pinfo->gpios);
1235 kfree(pinfo->alow_flags);
1236 return 0;
1237 }
1238
1239 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
1240 const struct of_device_id *ofid)
1241 {
1242 struct device *dev = &ofdev->dev;
1243 struct device_node *np = ofdev->dev.of_node;
1244 struct mpc8xxx_spi_probe_info *pinfo;
1245 struct fsl_spi_platform_data *pdata;
1246 struct spi_master *master;
1247 struct resource mem;
1248 struct resource irq;
1249 const void *prop;
1250 int ret = -ENOMEM;
1251
1252 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1253 if (!pinfo)
1254 return -ENOMEM;
1255
1256 pdata = &pinfo->pdata;
1257 dev->platform_data = pdata;
1258
1259 /* Allocate bus num dynamically. */
1260 pdata->bus_num = -1;
1261
1262 /* SPI controller is either clocked from QE or SoC clock. */
1263 pdata->sysclk = get_brgfreq();
1264 if (pdata->sysclk == -1) {
1265 pdata->sysclk = fsl_get_sys_freq();
1266 if (pdata->sysclk == -1) {
1267 ret = -ENODEV;
1268 goto err_clk;
1269 }
1270 }
1271
1272 prop = of_get_property(np, "mode", NULL);
1273 if (prop && !strcmp(prop, "cpu-qe"))
1274 pdata->flags = SPI_QE_CPU_MODE;
1275 else if (prop && !strcmp(prop, "qe"))
1276 pdata->flags = SPI_CPM_MODE | SPI_QE;
1277 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1278 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1279 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1280 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1281
1282 ret = of_mpc8xxx_spi_get_chipselects(dev);
1283 if (ret)
1284 goto err;
1285
1286 ret = of_address_to_resource(np, 0, &mem);
1287 if (ret)
1288 goto err;
1289
1290 ret = of_irq_to_resource(np, 0, &irq);
1291 if (!ret) {
1292 ret = -EINVAL;
1293 goto err;
1294 }
1295
1296 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1297 if (IS_ERR(master)) {
1298 ret = PTR_ERR(master);
1299 goto err;
1300 }
1301
1302 of_register_spi_devices(master, np);
1303
1304 return 0;
1305
1306 err:
1307 of_mpc8xxx_spi_free_chipselects(dev);
1308 err_clk:
1309 kfree(pinfo);
1310 return ret;
1311 }
1312
1313 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
1314 {
1315 int ret;
1316
1317 ret = mpc8xxx_spi_remove(&ofdev->dev);
1318 if (ret)
1319 return ret;
1320 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1321 return 0;
1322 }
1323
1324 static const struct of_device_id of_mpc8xxx_spi_match[] = {
1325 { .compatible = "fsl,spi" },
1326 {},
1327 };
1328 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1329
1330 static struct of_platform_driver of_mpc8xxx_spi_driver = {
1331 .driver = {
1332 .name = "mpc8xxx_spi",
1333 .owner = THIS_MODULE,
1334 .of_match_table = of_mpc8xxx_spi_match,
1335 },
1336 .probe = of_mpc8xxx_spi_probe,
1337 .remove = __devexit_p(of_mpc8xxx_spi_remove),
1338 };
1339
1340 #ifdef CONFIG_MPC832x_RDB
1341 /*
1342 * XXX XXX XXX
1343 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1344 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1345 * tree can work with OpenFirmware driver. But for now we support old trees
1346 * as well.
1347 */
1348 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1349 {
1350 struct resource *mem;
1351 int irq;
1352 struct spi_master *master;
1353
1354 if (!pdev->dev.platform_data)
1355 return -EINVAL;
1356
1357 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358 if (!mem)
1359 return -EINVAL;
1360
1361 irq = platform_get_irq(pdev, 0);
1362 if (irq <= 0)
1363 return -EINVAL;
1364
1365 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1366 if (IS_ERR(master))
1367 return PTR_ERR(master);
1368 return 0;
1369 }
1370
1371 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1372 {
1373 return mpc8xxx_spi_remove(&pdev->dev);
1374 }
1375
1376 MODULE_ALIAS("platform:mpc8xxx_spi");
1377 static struct platform_driver mpc8xxx_spi_driver = {
1378 .probe = plat_mpc8xxx_spi_probe,
1379 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
1380 .driver = {
1381 .name = "mpc8xxx_spi",
1382 .owner = THIS_MODULE,
1383 },
1384 };
1385
1386 static bool legacy_driver_failed;
1387
1388 static void __init legacy_driver_register(void)
1389 {
1390 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1391 }
1392
1393 static void __exit legacy_driver_unregister(void)
1394 {
1395 if (legacy_driver_failed)
1396 return;
1397 platform_driver_unregister(&mpc8xxx_spi_driver);
1398 }
1399 #else
1400 static void __init legacy_driver_register(void) {}
1401 static void __exit legacy_driver_unregister(void) {}
1402 #endif /* CONFIG_MPC832x_RDB */
1403
1404 static int __init mpc8xxx_spi_init(void)
1405 {
1406 legacy_driver_register();
1407 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1408 }
1409
1410 static void __exit mpc8xxx_spi_exit(void)
1411 {
1412 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1413 legacy_driver_unregister();
1414 }
1415
1416 module_init(mpc8xxx_spi_init);
1417 module_exit(mpc8xxx_spi_exit);
1418
1419 MODULE_AUTHOR("Kumar Gala");
1420 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1421 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree